Method and device for solving function optimization problem based on parallel processor

Abstract

The invention relates to a function optimization problem solving method and device based on a parallel processor, and is particularly suitable for the field of data processing. The invention provides a parallel processor M, and provides a method for executing parallel instructions on the basis of the parallel processor M, so that the parallel processor can execute serial instructions and parallel instructions at the same time. Based on the parallel processor, the invention provides a method for solving a function optimization problem, and the maximum / minimum value can be calculated in constant time complexity under the specific function optimization problem and input scale. According to the method, the global optimal solution of the function optimization problem is solved within the constant time through the specific parallel computing strategy, and compared with the prior art, the data processing time is effectively shortened, and the solving efficiency of the function optimization problem is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a method and device for solving function optimization problems based on parallel processors. Background Art

[0002] Function optimization problems play a vital role in the fields of mathematics and computer science. The core goal is to find the input value that can make the objective function reach the optimal value under given constraints. The "optimal value" here usually refers to the maximum or minimum value that the objective function can achieve within the problem definition domain.

[0003] Function optimization problems are widely involved and applied in the fields of production and life. For example, in the field of engineering design, function optimization is used to minimize costs, maximize performance, or find a balance between multiple objectives; in the financial field, function optimization is used to help users optimize their portfolios, that is, to find a set of asset weights to maximize the expected return of the portfolio or minimize investment risks; in the manufacturing industry, function optimization can be used to optimize the scheduling and resource allocation of production lines to maximize production efficiency, reduce production costs, or minimize production time. In addition to the above applications, function optimization problems also play an important role in high-tech fields such as scientific research and aerospace, and solving function optimization problems has practical research significance.

[0004] As an important optimization problem in theoretical mathematics, there are currently many solutions to function optimization problems. For general functions, mathematical tools such as calculus and linear algebra can be used to analyze the objective function and obtain the optimal value of the function. In this regard, there are classic algorithms such as gradient descent and Newton's method. However, they also have certain limitations. The gradient descent method is an iterative optimization method based on the gradient information of the function. It depends on the selection of the initial point and may fall into the problem of local optimal solution; the Newton method needs to calculate the second-order derivative of the function, and its use conditions and computational cost are higher. For complex search spaces and multimodal problems, heuristic algorithms represented by genetic algorithms perform well, but they cannot guarantee that the optimal solution can be found, and there is a possibility of falling into local optimality.

[0005] Based on the above situation, the present invention provides a method and device for solving function optimization problems, which can effectively reduce the time of data processing while ensuring that the global optimal value is obtained. Summary of the invention

[0006] The present invention provides a method and device for solving function optimization problems based on parallel processors, for problem of function optimization that existing algorithms have too high processing complexity or cannot calculate the global optimal solution.

[0007] In a first aspect, the present invention provides a parallel processor M, the processing core of which is used to process and decode parallel instructions and track their execution status, and the processing core can also execute serial instructions, the processing core comprising: a memory, an instruction decoding unit, an instruction execution unit, a register unit, a parallel instruction decoding unit, a parallel address decoding unit, a register array, and a calculation array;

[0008] The memory is used to store data and instructions involved in the operation;

[0009] The instruction decoding unit is used to obtain serial instructions or parallel instructions from the memory, and decode the operation to be performed and the parameters corresponding to the operation from the instruction; the serial instruction is opposite to the parallel instruction, and represents the instruction to operate on a single data;

[0010] The instruction execution unit is used to obtain data involved in the operation from the register unit according to the instruction decoded by the instruction decoding unit, perform operations on serial instructions and store the operation results in the register unit, and dispatch the operations to the parallel instruction decoding unit for execution for parallel instructions;

[0011] The register unit is used to store data involved in the execution of serial instructions;

[0012] The parallel instruction decoding unit is used to obtain parallel instructions from the instruction execution unit, and decode the operations to be performed and the parameters and addresses corresponding to the operations from the instructions;

[0013] The parallel address decoding unit is used to obtain the address that needs to perform the corresponding operation from the parallel instruction decoding unit, and select the unit in the corresponding register array and calculation array, and only the selected unit will perform the corresponding operation;

[0014] The register array is used to store data involved in parallel computing instructions;

[0015] The calculation array is used to obtain data involved in the operation from the register array according to the instructions parsed by the instruction decoding unit, and all units selected by the address decoding perform the operation and save the operation results to the register array, and at the same time notify the instruction execution unit that the parallel instruction has been executed.

[0016] In a second aspect, the present invention provides a method for executing parallel instructions, based on the parallel processor M described in the first aspect, comprising:

[0017] Step S01: the parallel processor M obtains the parallel instruction I from the memory and decodes it;

[0018] Step S02: the vector instruction enters the parallel instruction decoding unit, performs the second step of decoding, and selects all register units and computing units that need to be executed;

[0019] Step S03: fetching corresponding data from all selected register units of the register array and transmitting them to the calculation array;

[0020] Step S04: Wait until all selected computing units in the computing array are completed;

[0021] Step S05: writing the calculation result of the calculation array back to the register array;

[0022] Step S06: Notify the instruction execution unit of the result that the parallel instruction has been completed.

[0023] In a third aspect, the present invention provides a method for solving a function optimization problem, based on the parallel processor M of the first aspect, comprising:

[0024] Step S01: set initial values ​​for all units in the register array, and write 0 to N-1 into different operation units in parallel, where N is the number of parallel units;

[0025] Step S02: Map the [0, N-1] interval in all operation units to the specified interval through arithmetic operation;

[0026] Step S03: Calculate the values ​​of all cells according to the function to be calculated;

[0027] Step S04: perform an OR operation on the highest bit of all cells. If the result is 1, exclude all cells whose highest bit is 0.

[0028] Step S05: Repeat step S04, perform an OR operation on the next bit, and determine whether the result is 1, until the last bit is executed;

[0029] Step S06: Read the remaining cells that have not been excluded from the register array, and the remaining cells are the maximum values ​​of the function;

[0030] For the search of the minimum value, the principle is similar. You only need to change the OR operation to an AND operation, and exclude the cells with a bit of 1 each time.

[0031] It can be seen that through the parallel processor provided by the present invention, the maximum / minimum value of the function optimization problem can be calculated with a time complexity of O(1), thereby effectively reducing the data processing time while ensuring that the global optimal value is obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. The objects and features of the present invention will become more apparent in view of the following description in conjunction with the accompanying drawings, in which:

[0033] Figure 1 A schematic diagram of the structure of a parallel processor provided by the present invention

[0034] Figure 2 A schematic diagram of the structure of a parallel address decoding unit, a register array, and a calculation array in a parallel processor provided by the present invention

[0035] Figure 3 The present invention provides a flow chart of a method for executing parallel instructions.

[0036] Figure 4 A flowchart of a method for solving function optimization problems provided by the present invention DETAILED DESCRIPTION

[0037] In order to make the present invention more clearly understandable for its invention points, the present invention will be further described below in conjunction with the accompanying drawings and examples. In the following description, many details and specific examples are set forth, and these examples are provided in order to enable a more thorough understanding of the present invention and to be able to convey the present invention to those skilled in the art in a complete and vivid manner. Although the present invention can be implemented in many other ways different from the description hereof, those skilled in the art can make corresponding generalizations without violating the connotation of the present invention, so the present invention is not limited by the specific examples and specific drawings disclosed below.

[0038] Although the present invention has been described with reference to specific illustrative embodiments, it is not limited to these embodiments but only to the appended claims. It should be understood by those skilled in the art that the embodiments of the present invention can be changed and modified without departing from the scope and spirit of the present invention.

[0039] like Figure 1 FIG. 1 is a schematic diagram of the structure of a parallel processor M provided by the present invention, comprising:

[0040] An instruction decoding unit is used to obtain a serial instruction or a parallel instruction from a memory, and decode the operation to be performed and the parameters corresponding to the operation from the instruction; the serial instruction is opposite to the parallel instruction, and represents an instruction for operating on a single data;

[0041] An instruction execution unit is used to obtain data involved in the operation from the register unit according to the instruction decoded by the instruction decoding unit, perform operations on serial instructions, and store the operation results in the register unit; for parallel instructions, the operation is dispatched to the parallel instruction decoding unit for execution;

[0042] Register unit, used to store data involved in serial instruction execution.

[0043] The parallel instruction decoding unit is used to obtain parallel instructions from the instruction execution unit, and decode the operations to be executed and the parameters and addresses corresponding to the operations from the instructions.

[0044] The parallel address decoding unit is used to obtain the address that needs to perform the corresponding operation from the parallel instruction decoding unit, and select the unit in the corresponding register array and calculation array. Only the selected unit will perform the corresponding operation.

[0045] A register array for storing data involved in parallel computing instructions;

[0046] The calculation array is used to obtain data involved in the operation from the register array according to the instructions parsed by the instruction decoding unit, and all units selected by the address decoding perform the operation and save the operation results to the register array, and at the same time notify the instruction execution unit that the parallel instruction has been executed.

[0047] On the basis of the above-mentioned embodiments, in order to reduce the address lines required for selecting the register array and the calculation array, the present invention uses a multi-valued logical address as the address of the parallel array, and a 2n-bit address unit can be used to select 2 n units. Compared with the address decoder in which each address bit has only two states, namely 0 or 1, this paper uses two bits to represent each address bit, resulting in four states: 00, 01, 10, and 11. This paper only uses three of them: 01, 10, and 11; 00 is an empty state and has no practical meaning. The remaining three states correspond to the three situations {0, 1, *}, namely all 0, all 1, and superposition state. All 0 and all 1 correspond to the original 0 and 1, respectively, indicating that the bit address can only be 0 or 1; and the superposition state indicates that the bit address can be either 0 or 1;

[0048] For example, in Figure 2 In the illustrated architecture, the multi-address converter used in the present invention can be implemented by 6-bit address lines when processing a parallel array of 8 units in total. For example, the address 100111, i.e., {10*}, can select both units 100 and 101 at the same time. This reduces the consumption of address lines when selecting units.

[0049] like Figure 3The figure shows a flow chart of a method for executing parallel instructions provided by the present invention. The specific instruction executed is vand{01010*}v3,v2,23, which specifically means performing an AND operation on the v2 register of each unit in the register array that meets the address requirement and 23, and saving the result to the v3 register. It should be understood by those skilled in the art that the execution flow of other vector instructions is similar to Figure 3 The flowchart in is similar to that in the previous section, except that the specific operations performed and the length of the operation elements are somewhat different. Figure 3 As shown, the method includes:

[0050] Step S01, obtaining parallel instructions from a memory and decoding them;

[0051] Step S02, the parallel instruction enters the instruction execution unit and is ready to start execution;

[0052] Step S03, the parallel instruction enters the parallel instruction decoding unit, is decoded, and the units that need to be calculated are parsed. For the example here, the units that need to be calculated are 010100 and 010101;

[0053] Step S04, reading the value of the source register of the corresponding unit from the register array;

[0054] Step S05, performing an operation. For the example here, the actual operation performed is to perform an AND operation on each element and 23;

[0055] Step S06, write the calculation result into the destination register of the selected unit

[0056] Step S07, notifying the instruction execution unit that the parallel instruction has been executed.

[0057] like Figure 4 The figure shows a flow chart of a method for solving a function optimization problem provided by the present invention. The problem to be solved is to find the minimum value of f(x)=xsin(3x), x∈[0,1), wherein both the register array and the operation array have 64 units, and the method comprises:

[0058] Step S01: set initial values ​​for all units in the register array, and write 0 to 63 into different operation units in parallel;

[0059] Step S02: All operation units are divided by 64, and [0,63] is mapped to [0,1);

[0060] Step S03: Calculate the values ​​of all cells according to the function to be calculated. For the example here, the function to be calculated is xsin(3x);

[0061] Step S04: perform an OR operation on the highest bit of all cells. If the result is 1, exclude all cells whose highest bit is 0.

[0062] Step S05: Repeat step S04, perform an OR operation on the next bit, and determine whether the result is 1, until the last bit is executed;

[0063] Step S06: Read the remaining cells that have not been excluded from the register array, and the remaining cells are the maximum values ​​of the function;

[0064] For the search of the minimum value, the principle is similar. You only need to change the OR operation to an AND operation, and exclude the cells with a bit of 1 each time.

Claims

1. The present invention provides a parallel processor M, characterized in that: include: A memory for storing data and instructions involved in the operation; An instruction decoding unit, used to obtain a scalar instruction or a parallel instruction from the memory, and decode the operation to be performed and the parameters corresponding to the operation from the instruction; the scalar instruction is opposite to the parallel instruction, and represents an instruction for operating on a single data; an instruction execution unit, for obtaining data involved in operation from the register unit according to the instruction decoded by the instruction decoding unit, performing operation on scalar instructions and storing the operation result in the register unit, and dispatching the operation to the parallel instruction decoding unit for execution for parallel instructions; A register unit for storing data involved in the execution of scalar instructions; A parallel instruction decoding unit, used for obtaining parallel instructions from the instruction execution unit, and decoding the operations to be performed and the parameters and addresses corresponding to the operations from the instructions; A parallel address decoding unit, used to obtain the address of the corresponding operation to be performed from the parallel instruction decoding unit, and select the corresponding unit in the register array and the calculation array, and only the selected unit will perform the corresponding operation; A register array for storing data involved in parallel computation instructions; A calculation array is used to obtain the data involved in the operation from the register array according to the instructions parsed by the instruction decoding unit. All units selected by the address decoding perform the operation and save the operation results to the register array. At the same time, the instruction execution unit is notified that the parallel instruction has been executed.

2. A method for executing parallel instructions, based on the vector processor according to claim 1, characterized in that: include: Step S01: the parallel processor M obtains the parallel instruction I from the memory and decodes it; Step S02: the vector instruction enters the parallel instruction decoding unit, performs the second step of decoding, and selects all register units and computing units that need to be executed; Step S03: fetching corresponding data from all selected register units of the register array and transmitting them to the calculation array; Step S04: Wait until all selected computing units in the computing array are completed; Step S05: writing the calculation result of the calculation array back to the register array; Step S06: Notify the instruction execution unit of the result that the parallel instruction has been completed.

3. A method for solving a function optimization problem, based on the vector processor of claim 1, characterized in that: include: Step S01: set initial values ​​for all units in the register array, and write 0 to N-1 into different operation units in parallel, where N is the number of parallel units; Step S02: Map the [0, N-1] interval in all operation units to the specified interval through arithmetic operation; Step S03: Calculate the values ​​of all cells according to the function to be calculated; Step S04: perform an OR operation on the highest bit of all cells. If the result is 1, exclude all cells whose highest bit is 0. Step S05: Repeat step S04, perform an OR operation on the next bit, and determine whether the result is 1, until the last bit is executed; Step S06: Read the remaining cells that have not been excluded from the register array, and the remaining cells are the maximum values ​​of the function.

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