Method and apparatus for automating testing of i2c peripherals

Abstract

The application relates to a method and device for automatically testing I2c peripherals, and the above-mentioned testing method can test the functions and fault points of all I2c peripherals in a very short time period, can greatly save the time of a chip testing and verifying stage, shorten the chip research and development period, and can also perform stress testing in this way to measure the operation of the I2c peripheral module under extreme conditions, test the pressure resistance and robustness of the I2c peripheral module. In addition, compared with a traditional testing method, the method is simpler to use, and the transplantation between different types of chips is simple; when the I2c peripherals in the chips are tested, the testing time, receiving manpower and physical cost expenditure can be greatly shortened.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of peripheral testing, and relates to a method and device for automatically testing I2c peripherals. BACKGROUND

[0002] With the increase in the number of vehicle-mounted sensors and the improvement in the requirement for testing accuracy, a more convenient, reliable and economical vehicle-mounted data communication solution is needed. I2c (Inter-Integrated Circuit) is a serial communication bus protocol that is widely used in short-distance, low-speed data transmission occasions, such as communication between a microcontroller and a sensor. The testing of I2c peripherals is crucial to the reliability of their application in vehicle-mounted data communication. At present, the traditional testing method for I2c peripherals is as follows: one testing method is to take the I2c (sensor) peripheral as a test input. However, the sensor can only cover one scenario, while as a peripheral for testing, it needs to cover various I2c functions, modes and test various I2c faults that may occur. Therefore, this testing method cannot meet the actual testing requirements and can only be used as a sampling test. Another testing method is to build a test platform, constantly modify test codes and artificially create communication faults to verify various functions, modes and faults of I2c. Although this testing method can cover the functions, modes and various faults of I2c, it needs to rebuild the test platform and artificially reproduce the faults each time, which requires a large amount of manpower and material resources and is time-consuming and laborious. SUMMARY

[0003] In view of the problems in the above-mentioned traditional technology, the present application provides a method and device for automatically testing I2c peripherals, which can efficiently and automatically test I2c peripherals.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0005] On the one hand, a method for automatically testing I2c peripherals is provided, which includes the following steps:

[0006] The host computer sends a test instruction for this test to the slave computer from the serial port; each test instruction is used to test a function point or a fault point of the I2c peripheral to be tested;

[0007] The MCU of the slave computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction to send test data to the I2c peripheral to be tested in the I2c protocol; the first GPIO pin is connected to the data line of the I2c peripheral to be tested, and the second GPIO pin is connected to the clock line of the I2c peripheral to be tested;

[0008] The I2c peripheral to be tested re-establishes the communication connection with the lower computer after reading the test data, and sends the read test data to the lower computer;

[0009] The lower computer compares the test data sent by the I2c peripheral to be tested with the test data sent by the lower computer for consistency, and determines whether the addresses of the I2c peripheral to be tested before receiving data and when sending data are consistent;

[0010] When the consistency comparison result is consistent and the addresses are consistent, the lower computer determines that the I2c peripheral to be tested passes the test in this test, and uploads the test pass as the test result of this test to the upper computer.

[0011] On the other hand, an apparatus for automatically testing an I2c peripheral is also provided, comprising an upper computer, a lower computer and an I2c peripheral to be tested, the upper computer is connected to the lower computer through a serial port, a first GPIO pin of the MCU in the lower computer is connected to a data line of the I2c peripheral to be tested, and a second GPIO pin is connected to a clock line of the I2c peripheral to be tested;

[0012] The upper computer sends a test instruction of this test to the lower computer through the serial port; each test instruction is used to test a corresponding function point or fault point of the I2c peripheral to be tested;

[0013] The MCU of the lower computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction to send test data to the I2c peripheral to be tested in the I2c protocol;

[0014] The I2c peripheral to be tested re-establishes the communication connection with the lower computer after reading the test data, and sends the read test data to the lower computer;

[0015] The lower computer compares the test data sent by the I2c peripheral to be tested with the test data sent by the lower computer for consistency, and determines whether the addresses of the I2c peripheral to be tested before receiving data and when sending data are consistent;

[0016] When the consistency comparison result is consistent and the addresses are consistent, the lower computer determines that the I2c peripheral to be tested passes the test in this test, and uploads the test pass as the test result of this test to the upper computer.

[0017] One of the above technical solutions has the following advantages and beneficial effects:

[0018] The method and device for automatically testing the I2c peripheral device are based on a test platform composed of an upper computer, a lower computer and an I2c peripheral device to be tested, and the MCU chip of the lower computer simulates the level signal change of the data line and the clock line in the I2c protocol through the control of the GPIO interface, thereby communicating with the I2c peripheral device to be tested to complete the automatic testing of the I2c peripheral device. Only by issuing test instructions to the lower computer through the unified upper computer, the functions and fault points of all I2c peripheral devices can be tested in a very short time period, which can greatly save the time of the chip testing and verification stage, shorten the chip development cycle, and also can perform stress testing by this way to measure the running condition of the I2c peripheral module under extreme conditions, test its pressure resistance and robustness. In addition, compared with the traditional testing method, the use is simpler, the transplantation between different types of chips is also simple, and the testing time, labor and physical cost of the I2c peripheral device in the chip can be greatly shortened. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 The flowchart of the method for automatically testing the I2c peripheral device in an embodiment;

[0021] Figure 2 The block diagram of the overall automatic test platform in an embodiment;

[0022] Figure 3 The instruction and result transmission flowchart of the function point test in an embodiment;

[0023] Figure 4 The schematic diagram of the test receiving process in an embodiment;

[0024] Figure 5 The schematic diagram of the test sending process in an embodiment;

[0025] Figure 6 The module structure schematic diagram of the device for automatically testing the I2c peripheral device in an embodiment. DETAILED DESCRIPTION

[0026] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0027] It should be noted that the term "embodiment" mentioned herein means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the present application. The phrase is shown at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the specification and the appended claims means one or more of the associated listed terms in any combination and all possible combinations, and includes these combinations.

[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings of the embodiments of the present application.

[0029] In one embodiment, as shown in Figure 1 A method for automatically testing an I2c peripheral device can include the following processing steps S10-S18:

[0030] S10, sending a test instruction for this test from the host computer to the slave computer through the serial port; each test instruction is used to test a function point or a fault point of the I2c peripheral device to be tested;

[0031] S12, setting the level signals of the first GPIO pin and the second GPIO pin according to the test instruction by the MCU of the slave computer to send test data to the I2c peripheral device to be tested in the I2c protocol; the first GPIO pin is connected to the data line of the I2c peripheral device to be tested, and the second GPIO pin is connected to the clock line of the I2c peripheral device to be tested;

[0032] S14, after the I2c peripheral device to be tested reads the test data sent by the slave computer, re-establishes the communication connection with the slave computer, and sends the read test data to the slave computer;

[0033] S16, after the slave computer reads the test data sent by the I2c peripheral device to be tested from the first GPIO pin, the consistency of the test data sent by the slave computer and the test data is compared, and whether the address of the I2c peripheral device to be tested is consistent before receiving data and when sending data is determined;

[0034] S18, when the result of the consistency comparison is consistent and the addresses are consistent, the lower machine determines that the I2c peripheral to be tested passes the test in this test, and uploads the test pass as the test result of this test to the upper machine.

[0035] It can be understood that the I2c protocol is a synchronous, half-duplex serial low-speed protocol. In the I2c protocol, only two signal lines are needed to link multiple slave devices to one or more master devices; the two signal lines are SDA (data line, used to transmit data) and SCL (clock line, provides a synchronous clock signal). The MCU chip simulates the level signal change of the data line and the clock line in the I2c protocol by controlling the GPIO interface, thereby communicating with the I2c peripheral to be tested to complete the automatic test of the I2c peripheral, and the overall automatic test platform block diagram is as shown in Figure 2

[0036] When the lower machine receives the instruction of the upper machine, the MCU chip of the lower machine will control the GPIO interface of itself to simulate the corresponding I2c signal; the corresponding I2c peripheral reads the test data sent in the I2c signal; and then uploads the obtained test data to the lower machine after the test data is received, for confirming the accuracy of the test data.

[0037] Specifically, the upper machine can set various test instructions, and each test instruction corresponds to a test point (i.e. a function or fault point) of I2c; when the upper machine sends information to the lower machine through the serial port, the MCU chip of the lower machine will read the level signal on the GPIO interface of itself, or control the GPIO interface of itself to simulate the I2c signal to send corresponding test data to the I2c peripheral to be tested. When the lower machine completes the test of the function point in this test, it will upload the corresponding test result to the upper machine, and the specific flow chart can be as shown in Figure 3

[0038] ​​The method for automatically testing the I2c peripheral device is based on a test platform composed of an upper computer, a lower computer and an I2c peripheral device to be tested, and the MCU chip of the lower computer simulates the level signal change of the data line and the clock line in the I2c protocol to communicate with the I2c peripheral device to be tested, thereby completing the automatic testing of the I2c peripheral device. Only by sending test instructions to the lower computer through the unified upper computer, the functions and fault points of all I2c peripheral devices can be tested in a very short time period, thereby greatly saving the time of the chip testing and verification stage, shortening the chip development cycle, and also enabling the stress test to be performed in this way to measure the running condition of the I2c peripheral module under extreme conditions, test the pressure resistance and robustness thereof. In addition, compared with the traditional testing method, the method is simpler to use and simpler to transplant between different types of chips, and the testing time, labor and physical cost of the I2c peripheral device in the chip can be greatly shortened.

[0039] In one embodiment, the present test is to test the seven-address mode I2c host communication of the I2c peripheral device to be tested, and the I2c peripheral device to be tested first sends an address and a read information request to the lower computer;

[0040] The lower computer reads the level signals of the first GPIO pin and the second GPIO pin to determine whether the I2c peripheral device to be tested correctly sends a start signal; the first GPIO pin and the second GPIO pin are configured as clock line falling edge interrupts;

[0041] When the clock line has a rising edge, the lower computer reads the level in the data line and records the read level in the MCU of the lower computer, obtains the eight-bit data sent by the I2c peripheral device to be tested, and judges whether the eighth-bit data is 0;

[0042] If the eighth-bit data is 0, the lower computer pulls up the level signal of the data line through the first GPIO pin;

[0043] The MCU of the lower computer randomly selects test data and uses the first GPIO pin to simulate the I2c protocol to send to the I2c peripheral device to be tested.

[0044] Specifically, the working principle of the lower computer is that after the serial port of the lower computer receives a test instruction from the upper computer, the test instruction is automatically parsed and the GPIO interface of the lower computer is controlled to respond. For example, when the I2c peripheral device needs to be tested for seven-address mode I2c host communication, two GPIO pins (such as GPIO1 and GPIO2) of the MCU chip of the lower computer are connected to two pins (i.e. data line and clock line) of the I2c peripheral device; the lower computer prepares 0~0xFF total 256 data as test data.

[0045] When the test starts, the I2c peripheral first sends a request for address and read information; the lower computer first reads the level signals on the GPIO1 interface and the GPIO2 interface, and when the start signal in the I2c protocol is met (that is, when the data line is at a high level, the clock line has a falling edge), the lower computer judges whether the data line is still at a high level at this time, and if so, the I2c peripheral correctly sends the start signal at this time.

[0046] After the start signal occurs, the lower computer continuously reads the level signal of the clock line and continues to read the level signal in the I2c bus. When the clock line has a rising edge, the lower computer reads the level in the data line and records the level (high level is 1 and low level is 0) in the MCU chip of the lower computer at this time. At this time, the first bit of the address sent by the I2c peripheral is obtained, and the eighth bit of data is read in total and it is judged whether the eighth bit of data is 0. If the eighth bit of data is 0, it indicates that the read command sent by the I2c peripheral is normally received, and then the lower computer pulls the level signal of the data line high through the GPIO to indicate that the communication is normally established.

[0047] At this time, the MCU chip of the lower computer randomly selects a data from 256 data according to the change of time and uses the GPIO interface to simulate the I2c protocol to send to the I2c peripheral; that is, when the clock line has a rising edge change, the level signal of the first GPIO (data line) is pulled low or high according to the 8 bits of data. When the 8 bits of data are sent, it is necessary to judge whether the data line is pulled low after the clock line rises for a period of time, and if so, it indicates that the I2c peripheral is normally received, otherwise it indicates that a stop signal is generated and the reception is stopped. When the I2c peripheral reads all the data, the I2c peripheral will re-establish the communication connection with the lower computer to send the data just received to the lower computer; at this time, the lower computer compares whether the data read from the GPIO interface is consistent with the data sent by itself, and compares whether the addresses read from the GPIO interface in two communications are consistent, and if so, it indicates that the communication passes and the test result is uploaded to the upper computer through the serial port, otherwise the test result that the communication does not pass is reported to the upper computer through the serial port. As shown in Figure 4 As shown in Figure 5 As shown in

[0048] In one fault embodiment, the function point is the deadlock release function, and after the lower computer establishes communication with the I2c peripheral to be tested, the level signal of the data line is pulled low through the first GPIO pin to create a deadlock for the I2c peripheral to be tested.

[0049] It can be understood that using the GPIO interface to simulate I2c is more friendly to test the fault point of the I2c peripheral, for example, when testing the I2c deadlock release function, it is necessary to make a deadlock in advance; usually, it is necessary to reset to make a deadlock phenomenon, which is more troublesome; but using the GPIO interface simulation, as long as the GPIO interface directly pulls down the data line corresponding pin level after the communication connection is established, the deadlock phenomenon can be made to test the I2c peripheral deadlock release function.

[0050] In one embodiment, the MCU of the lower computer outputs an error level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the I2c peripheral to be tested.

[0051] Specifically, the working principle of the chip where the I2c peripheral to be tested is located: the I2c peripheral has high multiplicity, and only one code needs to be prepared for the test function point; a normal I2c module in the chip where the I2c peripheral is located is prepared as a host to receive and send codes with the slave. Then the correct and fault codes are obtained in the code, and the next function point is run when the current function point is correctly run; when testing the fault feedback mechanism, only the I2c peripheral works normally, and the MCU chip of the lower computer can make an error level signal.

[0052] In one embodiment, the logic analyzer is used to read the level signals on the data line and the clock line and then analyze the waveforms; the I2c protocol waveform obtained after waveform analysis is used to monitor the test error of the I2c peripheral to be tested.

[0053] It can be understood that in order to enhance the reliability of the system, the overall automatic test platform can also include a logic analyzer (such as an oscilloscope or other types of digital signal waveform analyzer) to read the level signals on the data line and the clock line to more accurately verify the integrity of the test, thereby increasing the reliability of the system.

[0054] Specifically, the test pins (i.e. data line and clock line) can be connected to the oscilloscope in the peripheral circuit of the overall automatic test platform, as shown in Figure 2 , the analyzed waveform in the oscilloscope can be observed each time a function point is tested, and the waveform of the test site fault can be retained when a test error occurs, so that the tester can quickly locate the problem, thereby improving the test efficiency.

[0055] It should be understood that although each step in Figure 1 is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1At least one of the steps can include a plurality of sub-steps or a plurality of stages, which are not necessarily performed at the same time, but can be performed at different times, and the order of the execution of the sub-steps or stages is not necessarily sequential, but can be performed alternately or in rotation with at least one of the other steps or sub-steps or stages of the other steps.

[0056] In one embodiment, as shown in FIG. 1, an apparatus 100 for automatically testing an I2c peripheral device can include a host computer, a slave computer, and an I2c peripheral device to be tested. The host computer is connected to the slave computer through a serial port. A first GPIO pin of an MCU in the slave computer is connected to a data line of the I2c peripheral device to be tested, and a second GPIO pin of the MCU is connected to a clock line of the I2c peripheral device to be tested. The host computer sends a test instruction for this test to the slave computer from the serial port. Each test instruction is used to test a corresponding function point or fault point of the I2c peripheral device to be tested. Figure 6

[0057] The MCU of the slave computer sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction to send test data to the I2c peripheral device to be tested in the I2c protocol. After the I2c peripheral device to be tested reads the test data, it re-establishes the communication connection with the slave computer and sends the read test data to the slave computer. The slave computer reads the test data sent by the I2c peripheral device to be tested from the first GPIO pin and compares the test data with the test data sent by the slave computer for consistency, and determines whether the address of the I2c peripheral device to be tested is consistent before receiving data and when sending data. When the consistency comparison result is consistent and the address is consistent, the slave computer determines that the I2c peripheral device to be tested passes the test in this test, and uploads the test pass as the test result of this test to the host computer.

[0058] The apparatus 100 for automatically testing an I2c peripheral device described above, based on a test platform composed of a host computer, a slave computer, and an I2c peripheral device to be tested, uses the MCU chip of the slave computer to simulate the level signal changes of the data line and the clock line in the I2c protocol through the control of the GPIO interface, thereby communicating with the I2c peripheral device to be tested to complete the automatic testing of the I2c peripheral device. Only by sending various test instructions to the slave computer through a unified host computer, all function points and fault points of the I2c peripheral device can be tested in a very short time period, which can greatly save the time of the chip testing and verification stage, shorten the chip development cycle, and also can perform stress testing in this way to measure the running condition of the I2c peripheral device module under extreme conditions, test its pressure resistance and robustness. In addition, compared with the traditional testing method, it is simpler to use, and it is also simple to transplant between different types of chips. When testing the I2c peripheral device in the chip, the test time, the receiving manpower, and the physical cost can be greatly reduced.

[0059] ​In one embodiment, when the host communication of the seven-bit addressing mode I2c of the to-be-tested I2c peripheral is tested, the to-be-tested I2c peripheral first sends a request for address and read information to the lower computer. The lower computer reads the level signals of the first GPIO pin and the second GPIO pin to determine whether the to-be-tested I2c peripheral correctly sends a start signal; the first GPIO pin and the second GPIO pin are configured as clock line falling edge interrupts. When the clock line has a rising edge, the lower computer reads the level in the data line and records the read level in the MCU of the lower computer, obtains the eight-bit data sent by the to-be-tested I2c peripheral and judges whether the eighth-bit data is 0. If the eighth-bit data is 0, the lower computer pulls up the level signal of the data line through the first GPIO pin. The MCU of the lower computer randomly selects test data and sends the test data to the to-be-tested I2c peripheral through the first GPIO pin in the form of I2c protocol.

[0060] In one embodiment, when the function point is the deadlock release function, the lower computer establishes communication with the to-be-tested I2c peripheral and then pulls down the level signal of the data line through the first GPIO pin to create a deadlock for the to-be-tested I2c peripheral.

[0061] In one embodiment, the MCU of the lower computer outputs an error level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the to-be-tested I2c peripheral.

[0062] In one embodiment, the above-mentioned device 100 for automatically testing I2c peripherals can further include a logic analyzer, which is used to read the level signals on the data line and the clock line and then perform waveform analysis; the I2c protocol waveform obtained after the waveform analysis is used to monitor test errors of the to-be-tested I2c peripheral.

[0063] It can be understood that the specific limitations of the device 100 for automatically testing I2c peripherals can refer to the corresponding limitations of the method for automatically testing I2c peripherals in the above, which will not be described here again.

[0064] Each module in the above-mentioned device 100 for automatically testing I2c peripherals can be realized by software, hardware and a combination thereof in whole or in part. The above-mentioned modules can be embedded in or independent of a device with a data processing function in a hardware form, or can be stored in a memory of the aforementioned device in a software form, so as to call and execute the operations corresponding to the above-mentioned modules by the processor. The aforementioned device can be, but is not limited to, various types of computing terminals in the prior art.

[0065] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiment methods can be included. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, RDRAM for short) and interface dynamic random access memory (DRDRAM).

[0066] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0067] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for automating the testing of I2C peripherals, characterized in that, Including the following steps: The host computer sends the test command for this test to the slave computer via the serial port; each test command is used to test a function point or fault point corresponding to the I2C peripheral under test. The lower-level MCU sets the level signals of the first GPIO pin and the second GPIO pin according to the test instructions and sends test data to the I2C peripheral under test via the I2C protocol; the first GPIO pin is connected to the data line of the I2C peripheral under test, and the second GPIO pin is connected to the clock line of the I2C peripheral under test. After the I2C peripheral under test reads the test data, it re-establishes the communication connection with the lower-level machine and sends the read test data to the lower-level machine. The lower-level machine reads the test data sent by the I2C peripheral under test from the first GPIO pin and compares it with the test data sent by the lower-level machine to determine whether the address of the I2C peripheral under test is the same before receiving the data and when sending the data. When the consistency comparison result is consistent and the address is consistent, the lower-level machine determines that the I2C peripheral under test has passed the test in this test, and uploads the test pass as the test result of this test to the upper-level machine; This test is to test the host communication of the I2C peripheral under test in the seven-bit addressing mode. The I2C peripheral under test first sends an address and read information request to the lower-level machine. The lower-level machine reads the level signals of the first GPIO pin and the second GPIO pin to determine that the I2C peripheral under test has correctly issued the start signal; the first GPIO pin and the second GPIO pin are configured to interrupt on the falling edge of the clock line; When the clock line has a rising edge, the lower-level machine reads the level in the data line and records the read level in the MCU of the lower-level machine, obtains the eight-bit data sent by the I2C peripheral under test and determines whether the eighth bit data is 0. If the eighth bit is 0, the lower-level machine pulls the level signal of the data line high through the first GPIO pin; The lower-level MCU randomly selects test data and sends it to the I2C peripheral under test using the first GPIO pin to simulate the I2C protocol.

2. The method for automated testing of I2C peripherals according to claim 1, characterized in that, When the function is to resolve deadlock, the lower-level machine establishes communication with the I2C peripheral under test and then pulls the level signal of the data line low through the first GPIO pin to create a deadlock for the I2C peripheral under test.

3. The method for automated testing of I2C peripherals according to claim 1, characterized in that, The lower-level MCU outputs an error level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the I2C peripheral under test.

4. The method for automated testing of I2C peripherals according to claim 1, characterized in that, The waveform is analyzed by reading the level signals on the data line and the clock line using a logic analyzer. The I2C protocol waveform obtained after waveform analysis is used to monitor test errors of the I2C peripheral under test.

5. A device for automatically testing I2C peripherals, characterized in that, The device includes a host computer, a slave computer, and an I2C peripheral under test. The host computer is connected to the slave computer via a serial port. The first GPIO pin of the MCU in the slave computer is connected to the data line of the I2C peripheral under test, and the second GPIO pin is connected to the clock line of the I2C peripheral under test. The host computer sends the test command for this test to the slave computer from the serial port; each test command is used to test a function point or fault point corresponding to the I2C peripheral under test. The lower-level MCU sets the level signals of the first GPIO pin and the second GPIO pin according to the test instruction and sends test data to the I2C peripheral under test via the I2C protocol. After the I2C peripheral under test reads the test data, it re-establishes the communication connection with the lower-level machine and sends the read test data to the lower-level machine. The lower-level machine reads the test data sent by the I2C peripheral under test from the first GPIO pin and compares it with the test data sent by the lower-level machine to determine whether the address of the I2C peripheral under test is the same before receiving the data and when sending the data. When the consistency comparison result is consistent and the address is consistent, the lower-level machine determines that the I2C peripheral under test has passed the test in this test, and uploads the test pass as the test result of this test to the upper-level machine; This test is to test the host communication of the I2C peripheral under test in the seven-bit addressing mode. The I2C peripheral under test first sends an address and read information request to the lower-level machine. The lower-level machine reads the level signals of the first GPIO pin and the second GPIO pin to determine that the I2C peripheral under test has correctly issued the start signal; the first GPIO pin and the second GPIO pin are configured to interrupt on the falling edge of the clock line; When the clock line has a rising edge, the lower-level machine reads the level in the data line and records the read level in the MCU of the lower-level machine, obtains the eight-bit data sent by the I2C peripheral under test and determines whether the eighth bit data is 0. If the eighth bit is 0, the lower-level machine pulls the level signal of the data line high through the first GPIO pin; The lower-level MCU randomly selects test data and sends it to the I2C peripheral under test using the first GPIO pin to simulate the I2C protocol.

6. The apparatus for automated testing of I2C peripherals according to claim 5, characterized in that, When the function is to resolve deadlock, the lower-level machine establishes communication with the I2C peripheral under test and then pulls the level signal of the data line low through the first GPIO pin to create a deadlock for the I2C peripheral under test.

7. The apparatus for automated testing of I2C peripherals according to claim 5, characterized in that, The lower-level MCU outputs an error level signal to the data line through the first GPIO pin to test the fault feedback mechanism of the I2C peripheral under test.

8. The apparatus for automatically testing I2C peripherals according to claim 5, characterized in that, It also includes a logic analyzer, which is used to read the level signals on the data line and the clock line and then perform waveform analysis; the I2C protocol waveform obtained after waveform analysis is used to monitor the test errors of the I2C peripheral under test.

Images