PCIe switch delay test device and method

Abstract

The present invention provides a PCIe exchange delay test device and method, which relates to the field of PCIe exchange delay technology. The test device mainly includes a CPU module, a NOC module, a first bridge module, a second bridge module, a memory module, a local time module, a first timestamp adding module, a first calculation module, a second timestamp adding module, a second calculation module, an RC controller module and an EP controller module. The scheme has a simple structure and is easy to operate. After connecting the PCIe exchange chip to be tested, it only needs to write data to the specified address and then read the address to obtain the accurate delay information of the PCIe exchange chip to be tested; the scheme can support the exchange delay measurement of the PCIe exchange chip from the UP port to the DP port or from the DP port to the UP port in two directions; the scheme can also further improve the measurement accuracy by increasing the clock frequency of the counter in the local time module.

Description

Technical Field

[0001] The present invention relates to the technical field of PCIe exchange delay, and in particular to a PCIe exchange delay testing device and method. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) switch chip is a core component of a high-speed serial bus standard and a bridge connecting various hardware devices (motherboards, graphics cards, storage devices, etc.). In the development or selection process of PCIe switch chips, switching delay is a key parameter.

[0003] Currently, there is no reliable device in the industry that can efficiently measure the switching delay. Therefore, how to efficiently, reliably and simply measure the PCIe switching delay has become a major issue that needs to be solved in the industry. Summary of the invention

[0004] The object of the present invention is to provide a PCIe switch delay testing device and method to solve at least one of the above-mentioned technical problems existing in the prior art.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides a PCIe switching delay test device, including a CPU module, a NOC module, a first bridge module, a second bridge module, a memory module, a local time (Time_Counter) module, a first timestamp adding (Add_Timestamp) module, a first calculation (Calc_Delay) module, a second timestamp adding module, a second calculation module, an RC (Root Complex) controller module and an EP (Endpoint) controller module;

[0006] The CPU module includes a first MA (Master) port and a first SLA (Slave) port of the AXI protocol; the first MA port is used to initiate access from the CPU module to the PCIe side; the first SLA port is used to receive access from the PCIe side to the CPU module;

[0007] The first bridge module includes a second MA port and a second SLA port on the AXI side; includes a third MA port and a third SLA port on the PCIe side; the second SLA port is connected to the third MA port, and is used to receive an AXI data packet, convert it into a PCIe data packet, and then send it to the PCIe side; the third SLA port is connected to the second SLA port, and is used to receive a PCIe data packet, convert it into an AXI data packet, and then send it to the AXI side;

[0008] The second bridge module includes a fourth MA port and a fourth SLA port on the AXI side; includes a fifth MA port and a fifth SLA port on the PCIe side; the fourth SLA port is connected to the fifth MA port, and is used to receive an AXI data packet, convert it into a PCIe data packet, and then send it to the PCIe side; the fifth SLA port is connected to the fourth SLA port, and is used to receive a PCIe data packet, convert it into an AXI data packet, and then send it to the AXI side;

[0009] The memory module is interconnected with the NOC module and is used for storing data in the CPU module and the PCIe-side EP controller module;

[0010] The NOC (Net On Chip) module interconnects the CPU module, the memory module, the port of the first bridge module on the AXI side, and the port of the second bridge module on the AXI side based on the AXI protocol; thus, all MA ports connected to the NOC module can flexibly access all SLA ports connected to the NOC module;

[0011] The local time module is used to output a timestamp counting reference to the first calculation module, the second calculation module, the first timestamp adding module and the second timestamp adding module based on the clock frequency;

[0012] The sixth SLA port of the first timestamp adding module is connected to the third MA port, and the sixth MA port is connected to the RC controller module on the PCIe side, and is used to add instant timestamp information at the specified position of the payload length (Payload) in the preset PCIeMWr (Memory Write) packet message, and synchronously update the verification information and send it to the RC controller module to ensure that the data packet is correctly transmitted to the PCIe side;

[0013] The seventh SLA port of the first calculation module is connected to the RC controller module on the PCIe side, and the seventh MA port is connected to the third SLA port, and is used to retrieve a preset PCIeMWr packet message, take out the sending timestamp value at the specified position of the Payload, and then subtract the sending timestamp value from the instant time counter value to obtain the transmission delay value of the PCIe MWr packet message; attach the transmission delay value to the specified position of the Payload of the PCIe MWr packet message;

[0014] The eighth SLA port of the second timestamp adding module is connected to the fifth MA port, and the eighth MA port is connected to the EP controller module on the PCIe side, and is used to add instant timestamp information at the specified position of Payload in the preset PCIe MWr packet message, and synchronously update the verification information and send it to the EP controller module, so as to ensure that the data packet is correctly transmitted to the PCIe side;

[0015] The ninth SLA port of the second calculation module is connected to the EP controller module on the PCIe side, and the ninth MA port is connected to the fifth SLA port, and is used to retrieve a preset PCIe MWr packet message, take out the sending timestamp value at the specified position of the Payload, and then subtract the sending timestamp value from the instant time counter value to obtain the transmission delay value of the PCIe MWr packet message; and attach the transmission delay value to the specified position of the Payload of the PCIe MWr packet message.

[0016] Through the above test device, it is only necessary to connect the UP (Upstream) port and the DP (Downstream) port of the tested PCIe switch chip to the RC controller module and the EP controller module respectively, and then write data to the specified address through the CPU, and then read the address, so as to automatically obtain the transmission delay value of the tested PCIe switch chip;

[0017] The measurement accuracy of the test device can also be improved by adjusting the clock frequency of the local time module.

[0018] In a feasible implementation manner, the test device may be implemented by means of FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

[0019] In a feasible implementation, the CPU module can be implemented by integrating an ARM core in an FPGA or by a logic code soft core (such as Microblaze from Xilinx) to run the driver of the test device to implement functions such as PCIe enumeration, PCIe message sending, and system configuration.

[0020] In a feasible implementation manner, the verification information refers to a verification field added to the Payload, such as a CRC (cyclic redundancy check), so that by verifying the CRC value, it can be determined whether the content of the data packet has been changed during the transmission process;

[0021] And by recalculating the CRC value, the check information is updated, that is, the original CRC value is overwritten, thereby reflecting that the data packet content has changed.

[0022] In a feasible implementation manner, the configuration information of the calculation module and the timestamp adding module includes:

[0023] The address information of the PCIe MWr packet message is used to match the message used for PCIe switch delay measurement;

[0024] The location information of adding timestamp in Payload is used to describe the offset location of adding timestamp information in Payload;

[0025] The conversion address of the PCIe MWr packet message is used to replace the original address in the returned PCIe MWr packet message, so that the timestamp information and transmission delay value can be written to the specified location of the memory module.

[0026] In a feasible implementation, the RC controller module and the EP controller module include a Serdes high-speed channel; the Serdes high-speed channel is located at the physical layer (Physical Layer) of each device, and is used to convert multiple low-speed parallel data into high-speed serial data at the transmitting end, and convert high-speed serial data into multiple low-speed parallel data at the receiving end, so as to improve the transmission stability between the device and the PCIe switching chip.

[0027] In a feasible implementation manner, an electronic switching device is further provided between the RC controller module and the EP controller module, for directly connecting or disconnecting the RC controller module and the EP controller module through program control.

[0028] On the second aspect, based on the same inventive concept, the present application also provides a testing method using the above-mentioned PCIe switch delay testing device, including a testing method from the RC controller module to the EP controller module and a testing method from the EP controller module to the RC controller module.

[0029] In a feasible implementation manner, the test method from the RC controller module to the EP controller module specifically includes the following steps:

[0030] Step a1: interconnect the PCIe switch chip under test with the test device, and the CPU module sends a data packet to the RC controller module to obtain the transmission delay T1 of the PCIe switch chip under test.

[0031] Preferably, the step a1 specifically includes:

[0032] Step a11, the RC controller module in the test device is connected to the UP port of the PCIe switch chip under test; the EP controller module in the test device is connected to the DP port of the PCIe switch chip under test;

[0033] Step a12: After the test device is powered on, the CPU module executes the PCIe enumeration program, allocates EP memory space to the EP controller module in the memory module, and implements cache mapping between the CPU module and the EP memory space for reading delay information;

[0034] Step a13, after the CPU module completes the PCIe enumeration procedure, it selects an address in the EP memory space as the storage address Delay_Info_Addr of the delay information, and configures the address to the first timestamp adding module and the second calculation module, so as to add the timestamp information to a preset DW (double word) position of the preset PCIe MWr packet message (replacing the original data at the position), and add the calculated delay information to another preset DW position (replacing the original data at the position);

[0035] Step a14, the CPU module initiates a write operation to Delay_Info_Addr, and outputs an AXI data packet through the first MA port. The Payload of the AXI data packet is greater than Dw_Offset+2 DWs; Dw_Offset represents a configuration parameter; thus, the configuration parameter Dw_Offset can be used for flexible configuration, and one DW can store the calculated transmission delay, and the other can store the verification information;

[0036] Step a15, the AXI data packet enters the first bridge module from the second SLA port through the NOC module and is converted into a PCIe MWr packet; enters the sixth SLA port of the first timestamping module through the third MA port, and replaces the timestamp position information with the time count value provided by the local time module; the position information may be the offset position of the Dw_Offsetth DW, and the offset position is configured to the first timestamping module and the second calculation module through the CPU module;

[0037] Step a16, the PCIe MWr packet enters the RC controller module via the sixth MA port, and then is sent to the UP port of the PCIe switch chip; the PCIe switch chip forwards the packet to the DP port connected to the EP controller module according to the storage address Delay_Info_Addr assigned during PCIe enumeration, and then enters the EP controller module;

[0038] Step a17: The PCIe MWr packet enters the second computing module through the ninth SLA port; the second computing module identifies the address information in the PCIe MWr packet and makes a judgment:

[0039] If the address information in the PCIe MWr packet is equal to the storage address Delay_Info_Addr, the data at the offset position of the Dw_Offsetth DW is used as the initial counting node, and then the current time count value provided by the local time module is subtracted from the initial counting node to obtain the transmission delay T1; T1 is added to the offset position of the Dw_Offset+1th DW of the PCIe MWr packet;

[0040] If the address information in the PCIe MWr packet is not equal to the storage address Delay_Info_Addr, it means that the PCIe MWr packet does not carry timestamp information, and the transmission delay T1 is not calculated;

[0041] If the address information in the PCIe MWr packet is not within the management range of the CPU module, the CPU module issues an address within the management range as the conversion address Trans_Addr, which is configured to the second computing module, replaces the address field in the PCIe MWr packet header, writes the timestamp information to the address of Trans_Addr+Dw_Offset*4 bytes, and writes the delay information to the address of Trans_Addr+(Dw_Offset+1)*4 bytes; the address field in the PCIe MWr packet header is located at Byte0 (0 byte) of the first DW in the Payload;

[0042] If the address information in the PCIe MWr packet is within the management range of the CPU module, the timestamp information is specifically written to the address of Delay_Info_Addr+Dw_Offset*4 bytes, and the delay information is specifically written to the address of Delay_Info_Addr+(Dw_Offset+1)*4 bytes;

[0043] Step a18, the PCIe MWr packet message enters the second bridge module through the fifth SLA port and is converted into an AXI data packet; then enters the NOC module through the fourth MA port and is sent to the specified address of the memory module;

[0044] Step a19: The CPU module accesses the specified address in the memory module to obtain the transmission delay T1.

[0045] Step a2: directly connect the RC controller module of the test device to the EP controller module, and the CPU module sends a data packet to the RC controller module to obtain the transmission delay T2 introduced by the test device.

[0046] Preferably, the step a2 specifically comprises the following steps:

[0047] Step a21, directly connecting the RC controller module and the EP controller module of the test device;

[0048] Step a22, based on the preset working rate and channel width, perform the test in the manner of steps a11-a19 to obtain the transmission delay T2; the working rate can be set through the Max Link Speed ​​field in the Link Capabilities Register in the PCIe protocol space; the channel width can be set through the Maximum LinkWidth field in the Link Capabilities Register in the PCIe protocol space; in this way, the transmission delay T2 under various conditions can be obtained by performing a combined traversal test on the working rate and channel width.

[0049] Step a3: Calculate the transmission delay T of the tested PCIe switch chip from the RC controller module to the EP controller module. The specific formula may be: T=T1-T2.

[0050] Through the above steps, the transmission delay introduced by the test device can be easily eliminated, so as to accurately obtain the transmission delay of the tested PCIe switch chip from the RC controller module to the EP controller module.

[0051] In a feasible implementation manner, the test method from the EP controller module to the RC controller module specifically includes the following steps:

[0052] Step b1: interconnect the PCIe switch chip under test with the test device, and the CPU module sends a data packet to the EP controller module to obtain the transmission delay T1' of the PCIe switch chip under test.

[0053] Preferably, the step b1 specifically includes:

[0054] Step b11, the RC controller module in the test device is connected to the UP port of the PCIe switch chip under test; the EP controller module in the test device is connected to the DP port of the PCIe switch chip under test;

[0055] Step b12: After the test device is powered on, the CPU module executes the PCIe enumeration program, allocates RC memory space to the RC controller module in the memory module, and implements cache mapping between the CPU module and the RC memory space for reading delay information;

[0056] Step b13, after the CPU module completes the PCIe enumeration procedure, it selects an address in the RC memory space as the storage address Delay_Info_Addr of the delay information, and configures the address to the second timestamp adding module, which is used to add the timestamp information to a preset DW position of the preset PCIe MWr packet message (replacing the original data at the position), and add the calculated delay information to another preset DW position (replacing the original data at the position);

[0057] Step b14, the CPU module initiates a write operation to Delay_Info_Addr, and outputs an AXI data packet through the first MA port. The payload length of the AXI data packet is greater than Dw_Offset+2 DWs; Dw_Offset indicates a configuration parameter;

[0058] Step b15, the AXI data packet enters the second bridge module from the fourth SLA port through the NOC module and is converted into a PCIe MWr packet; enters the eighth SLA port of the second timestamping module through the fifth MA port, and replaces the timestamp position information with the time count value provided by the local time module; the position information may be the offset position of the Dw_Offsetth DW, and the offset position is configured to the second timestamping module and the first calculation module through the CPU module;

[0059] Step b16, the PCIe MWr packet enters the EP controller module via the eighth MA port, and then is sent to the DP port of the PCIe switch chip; the PCIe switch chip forwards the packet to the UP port connected to the RC controller module according to the storage address Delay_Info_Addr assigned during PCIe enumeration, and then enters the RC controller module;

[0060] Step b17: The PCIe MWr packet enters the first computing module through the seventh SLA port; the first computing module identifies the address information in the PCIe MWr packet and makes a judgment:

[0061] If the address information in the PCIe MWr packet is equal to the storage address Delay_Info_Addr, the data at the offset position of the Dw_Offsetth DW is used as the initial counting node, and then the current time count value provided by the local time module is subtracted from the initial counting node to obtain the transmission delay T1'; T1' is added to the offset position of the Dw_Offset+1th DW of the PCIe MWr packet;

[0062] If the address information in the PCIe MWr packet is not equal to the storage address Delay_Info_Addr, it means that the PCIe MWr packet does not carry timestamp information, and the transmission delay T1' is not calculated;

[0063] If the address information in the PCIe MWr packet is not within the management range of the CPU module, the CPU module issues an address within the management range as the conversion address Trans_Addr, which is configured to the first computing module, replaces the address field in the PCIe MWr packet header, writes the timestamp information to the address of Trans_Addr+Dw_Offset*4 bytes, and writes the delay information to the address of Trans_Addr+(Dw_Offset+1)*4 bytes; the address field in the PCIe MWr packet header is located at Byte0 of the first DW in the Payload;

[0064] If the address information in the PCIe MWr packet is within the management range of the CPU module, the timestamp information is specifically written to the address of Delay_Info_Addr+Dw_Offset*4 bytes, and the delay information is specifically written to the address of Delay_Info_Addr+(Dw_Offset+1)*4 bytes;

[0065] Step b18, the PCIe MWr packet message enters the first bridge module through the third SLA port and is converted into an AXI data packet; then enters the NOC module through the second MA port and is sent to the specified address of the memory module;

[0066] Step b19: The CPU module accesses the designated address in the memory module to obtain the transmission delay T1'.

[0067] Step b2: directly connect the RC controller module of the test device to the EP controller module, and the CPU module sends a data packet to the EP controller module to obtain the transmission delay T2' introduced by the test device.

[0068] Preferably, the step b2 specifically comprises the following steps:

[0069] Step b21, directly connecting the RC controller module and the EP controller module of the test device;

[0070] Step b22, based on the preset working rate and channel width, perform the test in the manner of steps b11-b19 to obtain the transmission delay T2'; the working rate can be set by the Max Link Speed ​​field in the Link Capabilities Register in the PCIe protocol space; the channel width can be set by the Maximum LinkWidth field in the Link Capabilities Register in the PCIe protocol space; in this way, the transmission delay T2' under various conditions can be obtained by performing a combined traversal test on the working rate and channel width.

[0071] Step b3: Calculate the transmission delay T' of the tested PCIe switch chip from the EP controller module to the RC controller module. The specific formula may be: T'=T1'-T2'.

[0072] Through the above steps, the transmission delay introduced by the test device can be easily eliminated, so as to accurately obtain the transmission delay of the tested PCIe switch chip from the EP controller module to the RC controller module.

[0073] By adopting the above technical solution, the present invention has the following beneficial effects:

[0074] A PCIe exchange delay test device and method provided by the present invention have a simple structure and are easy to operate. After connecting the PCIe switch chip under test, it is only necessary to write data to a specified address and then read the address to obtain accurate delay information of the PCIe switch chip under test. The scheme can support exchange delay measurement of the PCIe switch chip in two directions, from the UP port to the DP port (i.e., from the RC controller module to the EP controller module) or from the DP port to the UP port (i.e., from the EP controller module to the RC controller module). The scheme can also further improve the measurement accuracy by increasing the clock frequency of the counter in the local time module. In particular, when a high-performance FPGA is used, the measurement accuracy of the test device can reach 1ns. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0076] Figure 1An architectural layout diagram of a PCIe switching delay test device provided by an embodiment of the present invention;

[0077] Figure 2 An operation roadmap of a PCIe exchange delay test method provided by an embodiment of the present invention;

[0078] Figure 3 A schematic diagram of adding timestamp information provided by an embodiment of the present invention;

[0079] Figure 4 A schematic diagram of adding delay information provided by an embodiment of the present invention;

[0080] Figure 5 A schematic diagram of a RC controller module and an EP controller module directly connected to each other according to an embodiment of the present invention;

[0081] Figure 6 An operation roadmap of another PCIe exchange delay testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0082] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0083] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0084] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0085] The present invention is further explained below in conjunction with specific implementation modes.

[0086] It should also be noted that the following specific embodiments or specific implementations are a series of optimized settings listed in the present invention to further explain the specific content of the invention, and these settings can be used in combination or in association with each other. Embodiment 1:

[0087] like Figure 1 As shown, a PCIe switching delay test device provided by this embodiment includes a CPU module, a NOC module, a first bridge module, a second bridge module, a memory module, a local time (Time_Counter) module, a first timestamp adding (Add_Timestamp) module, a first calculation (Calc_Delay) module, a second timestamp adding module, a second calculation module, an RC controller module and an EP controller module;

[0088] The CPU module includes a first MA (Master) port and a first SLA (Slave) port of the AXI protocol; the first MA port is used to initiate access from the CPU module to the PCIe side; the first SLA port is used to receive access from the PCIe side to the CPU module;

[0089] The first bridge module includes a second MA port and a second SLA port on the AXI side; includes a third MA port and a third SLA port on the PCIe side; the second SLA port is connected to the third MA port, and is used to receive an AXI data packet, convert it into a PCIe data packet, and then send it to the PCIe side; the third SLA port is connected to the second SLA port, and is used to receive a PCIe data packet, convert it into an AXI data packet, and then send it to the AXI side;

[0090] The second bridge module includes a fourth MA port and a fourth SLA port on the AXI side; includes a fifth MA port and a fifth SLA port on the PCIe side; the fourth SLA port is connected to the fifth MA port, and is used to receive an AXI data packet, convert it into a PCIe data packet, and then send it to the PCIe side; the fifth SLA port is connected to the fourth SLA port, and is used to receive a PCIe data packet, convert it into an AXI data packet, and then send it to the AXI side;

[0091] The memory module is interconnected with the NOC module and is used for storing data in the CPU module and the PCIe-side EP controller module;

[0092] The NOC (Net On Chip) module interconnects the CPU module, the memory module, the port of the first bridge module on the AXI side, and the port of the second bridge module on the AXI side based on the AXI protocol;

[0093] The local time module is used to output a timestamp counting reference to the first calculation module, the second calculation module, the first timestamp adding module and the second timestamp adding module based on the clock frequency;

[0094] The sixth SLA port of the first timestamp adding module is connected to the third MA port, and the sixth MA port is connected to the RC controller module on the PCIe side, and is used to add instant timestamp information at the Payload specified position in the preset PCIe MWr (Memory Write) packet message, and synchronously update the verification information and send it to the RC controller module, so as to ensure that the data packet is correctly transmitted to the PCIe side;

[0095] The seventh SLA port of the first calculation module is connected to the RC controller module on the PCIe side, and the seventh MA port is connected to the third SLA port, and is used to retrieve a preset PCIe MWr packet message, take out the sending timestamp value at the specified position of the Payload, and then subtract the sending timestamp value from the instant time counter value to obtain the transmission delay value of the PCIe MWr packet message; attach the transmission delay value to the specified position of the Payload of the PCIe MWr packet message;

[0096] The eighth SLA port of the second timestamp adding module is connected to the fifth MA port, and the eighth MA port is connected to the EP controller module on the PCIe side, and is used to add instant timestamp information at the specified position of Payload in the preset PCIe MWr packet message, and synchronously update the verification information and send it to the EP controller module, so as to ensure that the data packet is correctly transmitted to the PCIe side;

[0097] The ninth SLA port of the second calculation module is connected to the EP controller module on the PCIe side, and the ninth MA port is connected to the fifth SLA port, and is used to retrieve a preset PCIe MWr packet message, take out the sending timestamp value at the specified position of the Payload, and then subtract the sending timestamp value from the instant time counter value to obtain the transmission delay value of the PCIe MWr packet message; and attach the transmission delay value to the specified position of the Payload of the PCIe MWr packet message.

[0098] Through the above test device, it is only necessary to connect the UP (Upstream) port and the DP (Downstream) port of the tested PCIe switch chip to the RC controller module and the EP controller module respectively, and then write data to the specified address through the CPU, and then read the address, so as to automatically obtain the transmission delay value of the tested PCIe switch chip;

[0099] The measurement accuracy of the test device can also be improved by adjusting the clock frequency of the local time module;

[0100] For example, when the clock frequency is 100Mhz and the period is 10ns, the transmission delay value can only be an integer multiple of 10ns; when the clock frequency is 500Mhz and the period is 2ns, the transmission delay value can be an integer multiple of 2ns, thereby improving the measurement accuracy by 5 times.

[0101] Furthermore, the test device can be implemented by FPGA, thereby significantly reducing hardware costs.

[0102] Furthermore, the CPU module can be implemented by integrating an ARM core in an FPGA or by a logic code soft core (such as Microblaze from Xilinx) to run the driver of the test device to implement functions such as PCIe enumeration, PCIe message sending, and system configuration.

[0103] Furthermore, the verification information refers to a verification field added to the Payload, such as a 32-bit CRC (cyclic redundancy check), so that by verifying the CRC value, it can be determined whether the data packet content has been changed during the transmission process;

[0104] And by recalculating the CRC value, the check information is updated, that is, the original CRC value is overwritten, thereby reflecting that the data packet content has changed.

[0105] Furthermore, the bit width of the counting reference in the local time module is 1DW (double word, occupying 4 byte units, ie 32 bits).

[0106] Furthermore, the configuration information of the calculation module and the timestamp adding module includes:

[0107] The address information of the PCIe MWr packet message is used to match the message used for PCIe switch delay measurement;

[0108] The location information of adding timestamp in Payload is used to describe the offset location of adding timestamp information in Payload, the unit is 4DW;

[0109] The conversion address of the PCIe MWr packet message is used to replace the original address in the returned PCIe MWr packet message, so that the timestamp information and transmission delay value can be written to the specified location of the memory module.

[0110] Furthermore, the RC controller module and the EP controller module include a Serdes high-speed channel, which is located at the physical layer (Physical Layer) of each device and is used to convert multiple low-speed parallel data into high-speed serial data at the transmitting end, and convert high-speed serial data into multiple low-speed parallel data at the receiving end, so as to improve the transmission stability between the device and the PCIe switching chip.

[0111] Furthermore, an electronic switching device is provided between the RC controller module and the EP controller module, for directly connecting or disconnecting the RC controller module and the EP controller module through program control. Embodiment 2:

[0112] This embodiment provides a testing method using the above-mentioned PCIe exchange delay testing device, including a testing method from the RC controller module to the EP controller module and a testing method from the EP controller module to the RC controller module.

[0113] Further, the test method from the RC controller module to the EP controller module is as follows: Figure 2 As shown, the specific steps include:

[0114] Step a1: interconnect the PCIe switch chip under test with the test device, and the CPU module sends a data packet to the RC controller module to obtain the transmission delay T1 of the PCIe switch chip under test.

[0115] Preferably, the step a1 specifically includes:

[0116] Step a11, the RC controller module in the test device is connected to the UP port of the PCIe switch chip under test; the EP controller module in the test device is connected to the DP port of the PCIe switch chip under test;

[0117] Step a12: After the test device is powered on, the CPU module executes the PCIe enumeration program, allocates EP memory space to the EP controller module in the memory module, and implements cache mapping between the CPU module and the EP memory space for reading delay information;

[0118] Step a13, after the CPU module completes the PCIe enumeration procedure, it selects an address in the EP memory space as the storage address Delay_Info_Addr of the delay information, and configures the address to the first timestamp adding module and the second calculation module, so as to add the timestamp information to a (for example, the first) preset DW position of the preset PCIe MWr packet message (replacing the original data at the position), and add the calculated delay information to another (for example, the second) preset DW position (replacing the original data at the position);

[0119] Step a14, the CPU module initiates a write operation to Delay_Info_Addr, outputs an AXI data packet through the first MA port, and the payload length of the AXI data packet is greater than Dw_Offset+2 DWs;

[0120] Step a15, the AXI data packet enters the first bridge module from the second SLA port through the NOC module and is converted into a PCIe MWr packet; enters the sixth SLA port of the first timestamping module through the third MA port, and replaces the timestamp position information with the time count value provided by the local time module; the position information may be the offset position of the Dw_Offsetth DW, and the offset position is configured to the first timestamping module and the second calculation module through the CPU module; Figure 3 As shown;

[0121] Step a16, the PCIe MWr packet enters the RC controller module via the sixth MA port, and then is sent to the UP port of the PCIe switch chip; the PCIe switch chip forwards the packet to the DP port connected to the EP controller module according to the storage address Delay_Info_Addr assigned during PCIe enumeration, and then enters the EP controller module;

[0122] Step a17, the PCIe MWr packet enters the second computing module through the ninth SLA port; the second computing module identifies the address information in the PCIe MWr packet and makes a judgment, such as Figure 4 As shown:

[0123] If the address information in the PCIe MWr packet is equal to the storage address Delay_Info_Addr, the data at the offset position of the Dw_Offsetth DW is used as the initial counting node, and then the current time count value provided by the local time module is subtracted from the initial counting node to obtain the transmission delay T1; T1 is added to the offset position of the Dw_Offset+1th DW of the PCIe MWr packet;

[0124] If the address information in the PCIe MWr packet is not equal to the storage address Delay_Info_Addr, it means that the PCIe MWr packet does not carry timestamp information, and the transmission delay T1 is not calculated;

[0125] If the address information in the PCIe MWr packet is not within the management range of the CPU module, the CPU module issues an address within the management range as the conversion address Trans_Addr, which is configured to the second computing module, replaces the address field in the PCIe MWr packet header, writes the timestamp information to the address of Trans_Addr+Dw_Offset*4 bytes, and writes the delay information to the address of Trans_Addr+(Dw_Offset+1)*4 bytes; the address field in the PCIe MWr packet header is located at Byte0 of the first DW in the Payload;

[0126] If the address information in the PCIe MWr packet is within the management range of the CPU module, the timestamp information is specifically written to the address of Delay_Info_Addr+Dw_Offset*4 bytes, and the delay information is specifically written to the address of Delay_Info_Addr+(Dw_Offset+1)*4 bytes;

[0127] Step a18, the PCIe MWr packet message enters the second bridge module through the fifth SLA port and is converted into an AXI data packet; then enters the NOC module through the fourth MA port and is sent to the specified address of the memory module;

[0128] Step a19: The CPU module accesses the specified address in the memory module to obtain the transmission delay T1.

[0129] Step a2: directly connect the RC controller module of the test device to the EP controller module, and the CPU module sends a data packet to the RC controller module to obtain the transmission delay T2 introduced by the test device.

[0130] Preferably, the step a2 specifically comprises the following steps:

[0131] Step a21, directly connect the RC controller module of the test device to the EP controller module, such as Figure 5 As shown;

[0132] Step a22, based on the preset working rate and channel width, perform the test in the manner of steps a11-a19 to obtain the transmission delay T2; the working rate can be set through the Max Link Speed ​​field in the Link Capabilities Register in the PCIe protocol space; the channel width can be set through the Maximum LinkWidth field in the Link Capabilities Register in the PCIe protocol space; in this way, the transmission delay T2 under various conditions can be obtained by performing a combined traversal test on the working rate and channel width.

[0133] Step a3: Calculate the transmission delay T of the tested PCIe switch chip from the RC controller module to the EP controller module. The specific formula may be: T=T1-T2.

[0134] Through the above steps, the transmission delay introduced by the test device can be easily eliminated, so as to accurately obtain the transmission delay of the tested PCIe switch chip from the RC controller module to the EP controller module.

[0135] Further, the test method from the EP controller module to the RC controller module is as follows: Figure 6 As shown, the specific steps include:

[0136] Step b1: interconnect the PCIe switch chip under test with the test device, and the CPU module sends a data packet to the EP controller module to obtain the transmission delay T1' of the PCIe switch chip under test.

[0137] Preferably, the step b1 specifically includes:

[0138] Step b11, the RC controller module in the test device is connected to the UP port of the PCIe switch chip under test; the EP controller module in the test device is connected to the DP port of the PCIe switch chip under test;

[0139] Step b12: After the test device is powered on, the CPU module executes the PCIe enumeration program, allocates RC memory space to the RC controller module in the memory module, and implements cache mapping between the CPU module and the RC memory space for reading delay information;

[0140] Step b13, after the CPU module completes the PCIe enumeration procedure, it selects an address in the RC memory space as the storage address Delay_Info_Addr of the delay information, and configures the address to the second timestamp adding module, which is used to add the timestamp information to a (for example, the first) preset DW position of the preset PCIe MWr packet message (replacing the original data at the position), and add the calculated delay information to another (for example, the second) preset DW position (replacing the original data at the position);

[0141] Step b14, the CPU module initiates a write operation to Delay_Info_Addr, outputs an AXI data packet through the first MA port, and the payload length of the AXI data packet is greater than Dw_Offset + 2 DWs;

[0142] Step b15, the AXI data packet enters the second bridge module from the fourth SLA port through the NOC module and is converted into a PCIe MWr packet; enters the eighth SLA port of the second timestamping module through the fifth MA port, and replaces the timestamp position information with the time count value provided by the local time module; the position information may be the offset position of the Dw_Offsetth DW, and the offset position is configured to the second timestamping module and the first calculation module through the CPU module;

[0143] Step b16, the PCIe MWr packet enters the EP controller module via the eighth MA port, and then is sent to the DP port of the PCIe switch chip; the PCIe switch chip forwards the packet to the UP port connected to the RC controller module according to the storage address Delay_Info_Addr assigned during PCIe enumeration, and then enters the RC controller module;

[0144] Step b17: The PCIe MWr packet enters the first computing module through the seventh SLA port; the first computing module identifies the address information in the PCIe MWr packet and makes a judgment:

[0145] If the address information in the PCIe MWr packet is equal to the storage address Delay_Info_Addr, the data at the offset position of the Dw_Offsetth DW is used as the initial counting node, and then the current time count value provided by the local time module is subtracted from the initial counting node to obtain the transmission delay T1'; T1' is added to the offset position of the Dw_Offset+1th DW of the PCIe MWr packet;

[0146] If the address information in the PCIe MWr packet is not equal to the storage address Delay_Info_Addr, it means that the PCIe MWr packet does not carry timestamp information, and the transmission delay T1' is not calculated;

[0147] If the address information in the PCIe MWr packet is not within the management range of the CPU module, the CPU module issues an address within the management range as the conversion address Trans_Addr, which is configured to the first computing module, replaces the address field in the PCIe MWr packet header, writes the timestamp information to the address of Trans_Addr+Dw_Offset*4 bytes, and writes the delay information to the address of Trans_Addr+(Dw_Offset+1)*4 bytes; the address field in the PCIe MWr packet header is located at Byte0 of the first DW in the Payload;

[0148] If the address information in the PCIe MWr packet is within the management range of the CPU module, the timestamp information is specifically written to the address of Delay_Info_Addr+Dw_Offset*4 bytes, and the delay information is specifically written to the address of Delay_Info_Addr+(Dw_Offset+1)*4 bytes;

[0149] Step b18, the PCIe MWr packet message enters the first bridge module through the third SLA port and is converted into an AXI data packet; then enters the NOC module through the second MA port and is sent to the specified address of the memory module;

[0150] Step b19: The CPU module accesses the designated address in the memory module to obtain the transmission delay T1'.

[0151] Step b2: directly connect the RC controller module of the test device to the EP controller module, and the CPU module sends a data packet to the EP controller module to obtain the transmission delay T2' introduced by the test device.

[0152] Preferably, the step b2 specifically comprises the following steps:

[0153] Step b21, directly connecting the RC controller module and the EP controller module of the test device;

[0154] Step b22, based on the preset working rate and channel width, perform the test in the manner of steps b11-b19 to obtain the transmission delay T2'; the working rate can be set by the Max Link Speed ​​field in the Link Capabilities Register in the PCIe protocol space; the channel width can be set by the Maximum LinkWidth field in the Link Capabilities Register in the PCIe protocol space; in this way, the transmission delay T2' under various conditions can be obtained by performing a combined traversal test on the working rate and channel width.

[0155] Step b3: Calculate the transmission delay T' of the tested PCIe switch chip from the EP controller module to the RC controller module. The specific formula may be: T'=T1'-T2'.

[0156] Through the above steps, the transmission delay introduced by the test device can be easily eliminated, so as to accurately obtain the transmission delay of the tested PCIe switch chip from the EP controller module to the RC controller module.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PCIe switch delay test device, characterized in that: It includes a CPU module, a NOC module, a first bridge module, a second bridge module, a memory module, a local time module, a first timestamp adding module, a first calculation module, a second timestamp adding module, a second calculation module, an RC controller module and an EP controller module; The CPU module includes a first MA port and a first SLA port of the AXI protocol; the first MA port is used to initiate access from the CPU module to the PCIe side; the first SLA port is used to receive access from the PCIe side to the CPU module; The first bridge module includes a second MA port and a second SLA port on the AXI side; includes a third MA port and a third SLA port on the PCIe side; the second SLA port is connected to the third MA port, and is used to receive an AXI data packet, convert it into a PCIe data packet, and then send it to the PCIe side; the third SLA port is connected to the second SLA port, and is used to receive a PCIe data packet, convert it into an AXI data packet, and then send it to the AXI side; The second bridge module includes a fourth MA port and a fourth SLA port on the AXI side; includes a fifth MA port and a fifth SLA port on the PCIe side; the fourth SLA port is connected to the fifth MA port, and is used to receive an AXI data packet, convert it into a PCIe data packet, and then send it to the PCIe side; the fifth SLA port is connected to the fourth SLA port, and is used to receive a PCIe data packet, convert it into an AXI data packet, and then send it to the AXI side; The memory module is interconnected with the NOC module and is used for storing data in the CPU module and the PCIe-side EP controller module; The NOC module interconnects the CPU module, the memory module, the port of the first bridge module on the AXI side, and the port of the second bridge module on the AXI side based on the AXI protocol; The local time module is used to output a timestamp counting reference to the first calculation module, the second calculation module, the first timestamp adding module and the second timestamp adding module based on the clock frequency; The sixth SLA port of the first timestamp adding module is connected to the third MA port, and the sixth MA port is connected to the RC controller module on the PCIe side, and is used to add instant timestamp information at the specified position of the payload length in the preset PCIe MWr packet message, and synchronously update the verification information and send it to the RC controller module; The seventh SLA port of the first calculation module is connected to the RC controller module on the PCIe side, and the seventh MA port is connected to the third SLA port, and is used to retrieve the preset PCIe MWr packet message, take out the sending timestamp value at the specified position of the payload length, and then subtract the sending timestamp value from the instant time counter value to obtain the transmission delay value of the PCIe MWr packet message; Attach the transmission delay value to the specified position of the payload length of the PCIe MWr packet message; The eighth SLA port of the second timestamp adding module is connected to the fifth MA port, and the eighth MA port is connected to the EP controller module on the PCIe side, and is used to add instant timestamp information at the specified position of the payload length in the preset PCIe MWr packet message, and send it to the EP controller module after synchronously updating the verification information; The ninth SLA port of the second calculation module is connected to the EP controller module on the PCIe side, and the ninth MA port is connected to the fifth SLA port, and is used to retrieve a preset PCIe MWr packet message, take out the sending timestamp value at the specified position of the payload length, and then subtract the sending timestamp value from the instant time counter value to obtain the transmission delay value of the PCIe MWr packet message; The transmission delay value is attached to the specified position of the payload length of the PCIe MWr packet message.

2. The testing device according to claim 1, characterized in that: The check information refers to a check field added to the payload length, and the check field includes a CRC value.

3. The testing device according to claim 1, characterized in that: The configuration information of the calculation module and the timestamp adding module includes: The address information of the PCIe MWr packet message is used to match the message used for PCIe switch delay measurement; The position information of adding the timestamp in the payload length is used to describe the offset position of adding the timestamp information in the payload length; The conversion address of the PCIe MWr packet message is used to replace the native address in the returned PCIe MWr packet message.

4. The testing device according to claim 1, characterized in that: The RC controller module and the EP controller module include Serdes high-speed channels.

5. A testing method using the testing device as claimed in any one of claims 1 to 4, characterized in that: It includes a test method from the RC controller module to the EP controller module and a test method from the EP controller module to the RC controller module.

6. The testing method according to claim 5, characterized in that: The test method from the RC controller module to the EP controller module includes: Step a1, interconnecting the PCIe switch chip under test with the test device, and the CPU module sends a data packet to the RC controller module to obtain the transmission delay T1 of the PCIe switch chip under test; Step a2, directly connecting the RC controller module of the test device to the EP controller module, and the CPU module sends a data packet to the RC controller module to obtain the transmission delay T2 introduced by the test device; Step a3: Calculate the transmission delay T of the tested PCIe switch chip from the RC controller module to the EP controller module. The specific formula is: T=T1-T2.

7. The testing method according to claim 6, characterized in that: The step a1 specifically includes: Step a11, connect the RC controller module in the test device to the UP port of the PCIe switch chip under test; connect the EP controller module in the test device to the DP port of the PCIe switch chip under test; the UP port is the Upstream port; the DP port is the Downstream port; Step a12: After the test device is powered on, the CPU module executes the PCIe enumeration program, allocates EP memory space to the EP controller module in the memory module, and implements cache mapping between the CPU module and the EP memory space for reading delay information; Step a13, after the CPU module completes the PCIe enumeration procedure, it selects an address in the EP memory space as the storage address Delay_Info_Addr of the delay information, and configures the address to the first timestamp adding module and the second calculation module, so as to add the timestamp information to a preset DW position of the preset PCIe MWr packet message, and add the calculated delay information to another preset DW position; Step a14, the CPU module initiates a write operation to Delay_Info_Addr, and outputs an AXI data packet through the first MA port. The payload length of the AXI data packet is greater than Dw_Offset+2 DWs; Dw_Offset represents a configuration parameter; Step a15, the AXI data packet enters the first bridge module from the second SLA port through the NOC module and is converted into a PCIeMWr packet; enters the sixth SLA port of the first timestamping module through the third MA port, and replaces the timestamp position information with the time count value provided by the local time module; the position information is the offset position of the Dw_Offsetth DW, and the offset position is configured to the first timestamping module and the second calculation module through the CPU module; Step a16, the PCIe MWr packet enters the RC controller module via the sixth MA port, and then is sent to the UP port of the PCIe switch chip; the PCIe switch chip forwards the packet to the DP port connected to the EP controller module according to the storage address Delay_Info_Addr assigned during PCIe enumeration, and then enters the EP controller module; Step a17, the PCIe MWr packet enters the second computing module through the ninth SLA port; the second computing module identifies the address information in the PCIe MWr packet and makes a judgment: If the address information in the PCIe MWr packet is equal to the storage address Delay_Info_Addr, the data at the offset position of the Dw_Offsetth DW is used as the initial counting node, and then the current time count value provided by the local time module is subtracted from the initial counting node to obtain the transmission delay T1; T1 is added to the offset position of the Dw_Offset+1th DW of the PCIe MWr packet; If the address information in the PCIe MWr packet is not equal to the storage address Delay_Info_Addr, it means that the PCIe MWr packet does not carry timestamp information, and the transmission delay T1 is not calculated; If the address information in the PCIe MWr packet is not within the management range of the CPU module, the CPU module issues an address within the management range as the conversion address Trans_Addr, which is configured to the second computing module, replaces the address field in the PCIe MWr packet header, writes the timestamp information to the address of Trans_Addr+Dw_Offset*4 bytes, and writes the delay information to the address of Trans_Addr+(Dw_Offset+1)*4 bytes; the address field in the PCIe MWr packet header is located at the 0th byte of the first DW in the payload length; If the address information in the PCIe MWr packet is within the management range of the CPU module, the timestamp information is specifically written to the address of Delay_Info_Addr+Dw_Offset*4 bytes, and the delay information is specifically written to the address of Delay_Info_Addr+(Dw_Offset+1)*4 bytes; Step a18, the PCIe MWr packet message enters the second bridge module through the fifth SLA port and is converted into an AXI data packet; then enters the NOC module through the fourth MA port and is sent to the specified address of the memory module; Step a19: The CPU module accesses the specified address in the memory module to obtain the transmission delay T1.

8. The testing method according to claim 7, characterized in that: The step a2 specifically includes: Step a21, directly connecting the RC controller module and the EP controller module of the test device; Step a22: Based on the preset working rate and channel width, perform the test in the manner of steps a12-a19 to obtain the transmission delay T2; and replace step a16 with: the PCIeMWr packet enters the RC controller module via the sixth MA port and then directly enters the EP controller module.

9. The testing method according to claim 5, characterized in that: The test method from the EP controller module to the RC controller module includes: Step b1, the tested PCIe switch chip is interconnected with the test device, the CPU module sends a data packet to the EP controller module to obtain the transmission delay T1 'of the tested PCIe switch chip; Step b2, the RC controller module of the test device is directly connected to the EP controller module, the CPU module sends a data packet to the EP controller module to obtain the transmission delay T2 'introduced by the test device; Step b3: Calculate the transmission delay T' of the tested PCIe switch chip from the EP controller module to the RC controller module. The specific formula is: T'=T1'-T2'.

10. The testing method according to claim 9, characterized in that: The step b1 specifically includes: Step b11, connect the RC controller module in the test device to the UP port of the PCIe switch chip under test; connect the EP controller module in the test device to the DP port of the PCIe switch chip under test; the UP port is the Upstream port; the DP port is the Downstream port; Step b12: After the test device is powered on, the CPU module executes the PCIe enumeration program, allocates RC memory space to the RC controller module in the memory module, and implements cache mapping between the CPU module and the RC memory space for reading delay information; Step b13, after the CPU module completes the PCIe enumeration procedure, it selects an address in the RC memory space as the storage address Delay_Info_Addr of the delay information, and configures the address to the second timestamp adding module, which is used to add the timestamp information to a preset DW position of the preset PCIe MWr packet message in a subsequent sequence, and add the calculated delay information to another preset DW position; Step b14, the CPU module initiates a write operation to Delay_Info_Addr, and outputs an AXI data packet through the first MA port. The payload length of the AXI data packet is greater than Dw_Offset+2 DWs; Dw_Offset indicates a configuration parameter; Step b15, the AXI data packet enters the second bridge module from the fourth SLA port through the NOC module and is converted into a PCIeMWr packet; enters the eighth SLA port of the second timestamping module through the fifth MA port, and replaces the timestamp position information with the time count value provided by the local time module; the position information is the offset position of the Dw_Offsetth DW, and the offset position is configured to the second timestamping module and the first calculation module through the CPU module; Step b16, the PCIe MWr packet enters the EP controller module via the eighth MA port, and then is sent to the DP port of the PCIe switch chip; the PCIe switch chip forwards the packet to the UP port connected to the RC controller module according to the storage address Delay_Info_Addr assigned during PCIe enumeration, and then enters the RC controller module; Step b17: The PCIe MWr packet enters the first computing module through the seventh SLA port; the first computing module identifies the address information in the PCIe MWr packet and makes a judgment: If the address information in the PCIe MWr packet is equal to the storage address Delay_Info_Addr, the data at the offset position of the Dw_Offsetth DW is used as the initial counting node, and then the current time count value provided by the local time module is subtracted from the initial counting node to obtain the transmission delay T1'; T1' is added to the offset position of the Dw_Offset+1th DW of the PCIe MWr packet; If the address information in the PCIe MWr packet is not equal to the storage address Delay_Info_Addr, it means that the PCIe MWr packet does not carry timestamp information, and the transmission delay T1' is not calculated; If the address information in the PCIe MWr packet is not within the management range of the CPU module, the CPU module issues an address within the management range as the conversion address Trans_Addr, which is configured to the first computing module, replaces the address field in the PCIe MWr packet header, writes the timestamp information to the address of Trans_Addr+Dw_Offset*4 bytes, and writes the delay information to the address of Trans_Addr+(Dw_Offset+1)*4 bytes; the address field in the PCIe MWr packet header is located at the 0th byte of the first DW in the payload length; If the address information in the PCIe MWr packet is within the management range of the CPU module, the timestamp information is specifically written to the address of Delay_Info_Addr+Dw_Offset*4 bytes, and the delay information is specifically written to the address of Delay_Info_Addr+(Dw_Offset+1)*4 bytes; Step b18, the PCIe MWr packet message enters the first bridge module through the third SLA port and is converted into an AXI data packet; then enters the NOC module through the second MA port and is sent to the specified address of the memory module; Step b19: The CPU module accesses the designated address in the memory module to obtain the transmission delay T1'.

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