UART module verification system and method based on DMA communication of UVM

Abstract

The invention relates to a UVM-based DMA communication UART module verification system and method, an advanced UVM verification platform integrating data sending, processing and checking is established, each integrated AHB and UART protocol component has good transportability, and an integrated UART configuration component is used for randomizing data and configuration and is matched with various test cases, so that the verification efficiency of the UART module is improved. The UART module verification supporting DMA communication based on the UVM verification methodology is realized, the verification completeness and accuracy are ensured, the verification flexibility is improved, the synchronization of the verification environment and the to-be-tested module is realized with relatively low configuration cost, and the verification efficiency is improved; meanwhile, the degree of freedom of the configuration options also improves the randomness of verification, so that the verification is more complete.

Description

Technical Field

[0001] The invention belongs to the technical field of chip verification, and relates to a UART module verification system and method for DMA communication based on UVM. Background Art

[0002] Universal Asynchronous Receiver-Transmitter (UART) is a hardware device for serial communication. In recent years, UART has gradually become one of the most commonly used communication protocols in computers and embedded systems. Previously, UART was mainly used for data transmission between computers and external devices (such as modems). With the popularization of microcontrollers and single-chip microcomputers, UART is increasingly used in embedded systems. The working principle of UART is to convert parallel data into serial data for transmission on a signal line. This design makes UART simple and efficient in hardware implementation and suitable for low-speed data transmission scenarios. However, with the rapid development of intelligent technology, the speed of UART has been continuously improved, and more features have been added, such as error detection, baud rate adaptation, and support for direct memory access (DMA) communication. The addition of DMA makes UART data transmission more efficient, but also puts forward more complex requirements for verification.

[0003] However, compared with the independent verification of the mature UART module, the UART module that supports DMA communication needs to be implemented in the system verification scenario, which makes it more complicated than the module verification scenario, consumes more resources, has a longer verification cycle, and currently lacks a systematic verification solution. Therefore, how to build a complete and adaptive system verification platform including UART and DMA, accurately simulate the UART data interaction process that supports DMA communication and perform detailed and sufficient verification on it, is a technical problem that urgently needs to be solved in the current verification technology. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a UART module verification system for DMA communication based on UVM and a UART module verification method for DMA communication based on UVM, builds a complete and adaptive system verification platform including UART and DMA, which can accurately simulate the UART data interaction process supporting DMA communication and perform detailed and sufficient verification on it.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a UART module verification system for DMA communication based on UVM is provided, comprising a top-level file, the top-level file comprising a test case base class, an instantiated AHB bus, an instantiated UART bus and a DUT to be tested, wherein the DUT to be tested comprises a UART unit, a DMA unit and a storage unit; Verification environment and test cases are deployed based on the test case base class. The verification environment includes AHB system environment components and UART environment components. The AHB system environment components include component system environment configuration and AHB host agent components. The AHB host agent component includes a sequence generator, an AHB driver, and an AHB bus monitor. The sequence generator is used to generate a sequence when the test case is called and pass it to the AHB driver, and then send it to the DUT through the AHB bus. The AHB bus monitor continuously monitors whether the access initiated by the DUT complies with the AHB protocol during the data transmission process through the AHB bus; the instantiated AHB bus and UART bus are used to connect the DUT and the verification environment respectively; The UART environment components include a UART data sending component, a UART data receiving component, a UART configuration component, a UART frame format component and a UART data comparator. The sequence generator in the UART data sending component generates data through the UART frame format component, and the data is sent to the DUT via the UART bus by the UART_ driver in the UART data sending component. The UART monitor in the UART data receiving component collects the data sent from the UART bus and sends it to the UART data comparator for comparison between the expected result and the actual result. The UART configuration component is used to generate configuration information for each component and the DUT, and is used to randomly generate frame format configurations of different lengths and different verification methods and send them to the UART frame format component.

[0006] On the other hand, a UART module verification method based on DMA communication of UVM is also provided, which is applied to the above-mentioned UART module verification system based on DMA communication of UVM. The UART module verification method based on DMA communication of UVM comprises the steps of: Power on and initialize the UART module verification system; The UART environment component is called through the test case to generate receiving data and send it to the UART unit through the UART bus, and the receiving data is taken as the expected result of receiving; The UART unit continuously receives the received data. When the amount of data in the received data FIFO buffer is higher than the set watermark, a DMA read request is sent to the DMA unit. The DMA unit reads the received data from the UART unit and writes it into the storage unit. The received data is read out from the storage unit through the AHB bus as the actual reception result, and the expected reception result and the actual reception result are compared. If the comparison fails, the simulation ends after the simulation log of failed reception data comparison is printed; if the comparison passes, the simulation ends after the simulation log of successful reception comparison is output.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned UVM-based DMA communication UART module verification system and method builds an advanced UVM verification platform integrating data transmission, processing and inspection through SystemVerilog language. The integrated components of each AHB and UART protocol have good portability, and the integrated UART configuration component uart_cfg is used to randomize data and configuration. In conjunction with a variety of test cases, the UVM verification methodology-based UART module verification supporting DMA communication is realized, and the completeness and accuracy of the verification are guaranteed. Compared with traditional technologies, not only a systematic verification solution for the UART module of DMA communication is provided, but also the flexibility of verification is improved by adopting the UVM verification environment, and the synchronization of the verification environment and the module to be tested is achieved with a lower configuration cost, thereby improving the efficiency of verification; at the same time, the degree of freedom of configuration options also improves the randomness of verification, making the verification more complete. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 It is a structural block diagram of a UART module verification system for DMA communication based on UVM in one embodiment; Figure 2 A schematic flow diagram of a UART module verification method for DMA communication based on UVM in one embodiment; Figure 3 The figure is a flow chart of a UART module verification method for DMA communication based on UVM in another embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] In one embodiment, Figure 1 As shown, a UART module verification system for DMA communication based on UVM is provided, including a top-level file, the top-level file includes a test case base class, an instantiated AHB bus, an instantiated UART bus and a DUT to be tested, and the DUT to be tested includes a UART unit, a DMA unit and a storage unit. A verification environment and a test case are deployed based on the test case base class, and the verification environment includes an AHB system environment component and a UART environment component, and the AHB system environment component includes a component system environment configuration and an AHB host agent component. Among them, the AHB host agent component includes a sequence generator, an AHB driver and an AHB bus monitor, the sequence generator is used to generate a sequence when the test case is called and pass it to the AHB driver, and then send it to the DUT through the AHB bus, and the AHB bus monitor continuously monitors whether the access initiated by the DUT complies with the AHB protocol during the data transmission process through the AHB bus; the instantiated AHB bus and the UART bus are used to connect the DUT and the verification environment respectively.

[0014] The UART environment components include a UART data sending component, a UART data receiving component, a UART configuration component, a UART frame format component and a UART data comparator. The sequence generator in the UART data sending component generates data through the UART frame format component, and the data is sent to the DUT via the UART bus by the UART_ driver in the UART data sending component. The UART monitor in the UART data receiving component collects the data sent from the UART bus and sends it to the UART data comparator for comparison between the expected result and the actual result. The UART configuration component is used to generate configuration information for each component and the DUT, and is used to randomly generate frame format configurations of different lengths and different verification methods and send them to the UART frame format component.

[0015] It can be understood that the design of each component in the above-mentioned UART module verification system based on UVM DMA communication follows the existing UVM verification methodology. According to the verification of the UART module to be verified with integrated DMA, it is necessary to configure the components of the corresponding functions based on the UVM verification platform and complete the connection between the components, connectivity testing and other basic operations to ensure that the data flow between the components during the verification process is normal.

[0016] The top-level file (testbench) of the entire verification environment of the above-mentioned UVM-based DMA communication UART module verification system includes a test case base class (base_test), an instantiated AHB bus (which can be recorded as ahb_if), an instantiated UART bus (which can be recorded as uart_if) and a DUT to be tested. The DUT to be tested includes a UART unit, a DMA unit and a storage unit.

[0017] Based on the test case base class (base_test), multiple test cases (testcase) are derived and a verification environment (env) is created. The verification environment (env) includes the AHB system environment component (which can be recorded as ahb_system_env) and the UART environment component (which can be recorded as uart_subenv). The AHB system environment component includes the component system environment configuration (which can be recorded as ahb_cfg) and the AHB host agent component (which can be recorded as master_agent). Each AHB host agent component includes a sequencer (sequencer), an AHB driver (ahb_driver) and an AHB bus monitor (ahb_monitor). The sequencer will be called by the test case, and after generating the sequence, it will be passed to the AHB driver and sent to the DUT module through the AHB bus to simulate the actual data transmission. The AHB bus monitor will continuously monitor whether the access initiated by the DUT module complies with the AHB protocol during the data transmission process through the AHB bus. The instantiated AHB bus and UART bus are used to connect the DUT to be tested and the verification environment (env) respectively.

[0018] The UART environment component uart_subenv includes the UART data transmission component (which can be recorded as the transmission agent tx_agent), the UART data receiving component (which can be recorded as the receiving agent rx_agent), the UART configuration component (which can be recorded as uart_cfg), the UART frame format component (which can be recorded as uart_frame) and the UART data comparator (which can be recorded as uart_scb). After the sequencer in the UART data transmission component generates data through the UART frame format component (i.e. uart_frame), the UART driver (uart_driver) in the UART data transmission component sends it to the DUT via the UART bus uart_if.

[0019] In the UART data receiving component, the internal UART monitor (which can be recorded as uart_monitor) collects the data sent by the UART bus uart_if and sends it to the UART data comparator uart_scb. The UART data comparator uart_scb is used to compare the expected result with the actual result. Since UART is a full-duplex communication mode, the input and output data will be compared at the same time. If the comparison is wrong, an error message will be output. The UART configuration component uart_cfg is used to generate the configuration information of the above components and DUT, such as clock frequency, baud rate, parity check, stop bit length, and FIFO water level line; at the same time, the UART configuration component uart_cfg is also used to randomly generate frame format configurations of different lengths and different check methods and send them to the UART frame format component uart_frame. The communication direction between the above components is indicated by arrows, and double arrows indicate that bidirectional communication is possible.

[0020] The above-mentioned UVM-based DMA communication UART module verification system has built an advanced UVM verification platform integrating data transmission, processing and inspection through SystemVerilog language. The integrated components of various AHB and UART protocols have good portability, and the integrated UART configuration component uart_cfg is used to randomize data and configuration. With a variety of test cases, the UVM verification methodology-based UART module verification supporting DMA communication is realized, and the completeness and accuracy of the verification are guaranteed. Compared with traditional technologies, it not only provides a systematic verification solution for the UART module of DMA communication, but also improves the flexibility of verification by adopting the UVM verification environment, realizes the synchronization of the verification environment and the module to be tested with a lower configuration cost, and improves the efficiency of verification; at the same time, the degree of freedom of configuration options also improves the randomness of verification, making the verification more complete.

[0021] More specifically, for the verification task of the UART module of DMA communication, first, a top-level simulation file can be created for the UART module of DMA communication, which is used to initialize the verification platform testbench (top-level file), start the test case, and instantiate the AHB bus ahb_if and UART bus uart_if. Then, a basic test component base_test (i.e., the test case base class) is created to create a verification environment (env), declare environment variables, configuration information, and construct various functions for test case calls, such as system configuration functions and DUT access functions.

[0022] Based on the test case base class (base_test), multiple test cases are derived to generate random configuration information, configure the DUT and verify the synchronization of environment configuration by calling the above functions. At the same time, the test case can also be used to call the UART frame format component uart_frame to generate stimulus and read the data of the DUT. Among them, when the UART unit initiates a DMA read request, the DMA unit will read data from the UART unit and write it to the storage unit; when the UART unit initiates a DMA transfer request, the DMA unit will read data from the storage unit and write it to the UART unit.

[0023] In order to verify the UART and DMA communication of the DUT under test, it is necessary to configure the water level of the internal receive data FIFO (First in first out) cache of the UART unit. Specifically, when the UART unit receives data, the data will be stored in the receive data FIFO cache. If the amount of data stored in the receive data FIFO cache reaches the configured water level, a DMA read request will be issued, and the DMA unit will read the data from the receive data FIFO cache in the UART unit, and the amount of data will decrease accordingly. When the amount of data is lower than the water level, the DMA read request will no longer be issued.

[0024] Correspondingly, the water level of the transmit data FIFO buffer also needs to be configured. Specifically, when the amount of data in the transmit data FIFO buffer inside the UART unit is lower than the water level, the UART unit will issue a DMA transfer request, and the DMA unit will transfer the data into the transmit data FIFO buffer inside the UART unit, and the amount of data in the transmit data FIFO buffer will increase. When the amount of data is higher than the water level, the DMA transfer request will no longer be issued.

[0025] After completing the creation of each component, the components are connected to each other for communication. The data of each component in the verification environment (env) is transmitted using TLM (Transaction Level Modeling). Each component interacts with data through the port and export port in UVM. These data include a 5-bit to 8-bit payload (communication transaction), any parity bit, and a 1-bit to 2-bit stop bit, which is determined by the UART configuration component uart_cfg and generated by the UART frame format component uart_frame.

[0026] In one embodiment, the baud rate clock of the DUT is kept consistent with the sampling frequency of the UART environment components.

[0027] It can be understood that since the communication connection protocol between the UART unit in the DUT and the verification environment (env) is the UART communication protocol, the baud rate clock of the DUT needs to be consistent with the sampling frequency of the UART environment component uart_subenv. If the baud rate clock of the DUT changes, the sampling frequency of the UART environment component uart_subenv also needs to be changed according to the register configuration to avoid distortion of the sampled data, etc. The random baud rate clock configuration is determined by the UART configuration component uart_cfg.

[0028] In one embodiment, the UART configuration component is also used to randomly configure the watermarks of the receive data FIFO buffer and the transmit data FIFO buffer in the UART unit.

[0029] It can be understood that the UART configuration component uart_cfg is used to randomly cover all frame formats of the UART unit, and at the same time, different water levels of the receive data FIFO cache and the transmit data FIFO cache in the UART unit are configured to achieve random DMA data transfer. After the UART configuration component uart_cfg is configured, the configuration synchronization of the DUT and the verification environment will be achieved through the AHB bus. The test case generates pre-stored data (which can be recorded as TXDATA) by calling the UART frame format component uart_frame, and writes it to the storage unit through the AHB bus. At the same time, the pre-stored data generated will also be sent to the UART data comparator of the UART environment component uart_subenv for data comparison. The pre-stored data sent to the UART data comparator can be called the expected result tx_exp_data.

[0030] After the UART unit is started, the test case calls the UART environment component uart_subenv to generate received data (which can be recorded as RXDATA) and sends it to the UART unit through the UART bus uart_if, and uses the generated received data as the expected reception result rx_exp_data. Since UART is full-duplex communication, the UART unit will enter the data reception (RX) and data transmission (TX) processing flow at the same time.

[0031] In one embodiment, the processing flow of data transmission (TX) of the system is as follows: when the amount of data cached in the transmission data FIFO is lower than the set water level, a DMA transfer request is issued, and the DMA unit reads the pre-stored data TXDATA from the storage unit and writes it into the UART unit. After the pre-stored data TXDATA enters the UART unit, it will be sent to the UART environment component uart_subenv through the UART bus uart_if in the form of the UART communication protocol. The pre-stored data sent out can be called the sending real result tx_act_data. The UART data comparator uart_scb will compare the sending expected result tx_exp_data and the sending real result tx_act_data. If the comparison fails (such as inconsistency), the sending data comparison failure simulation log is printed and the simulation ends. If the comparison passes (such as consistency), the sending comparison success simulation log is output and the simulation ends.

[0032] In one embodiment, the processing flow of data reception (RX) of the system is as follows: the UART unit continuously receives the received data RXDATA. When the amount of data in the received data FIFO buffer is higher than the set watermark, a DMA read request is issued to the DMA unit. The DMA unit reads the received data RXDATA from the UART unit and writes it into the storage unit. The test case reads the received data RXDATA from the storage unit through the AHB bus. At this time, the read received data RXDATA can be called the received real result rx_act_data. The test case will compare the received expected result rx_exp_data with the received real result rx_act_data. If the comparison fails (such as inconsistency), the received data comparison failure simulation log is printed and the simulation ends. If the comparison passes (such as consistency), the received comparison success simulation log is output and the simulation ends.

[0033] In some implementations, a makefile file can also be written, a compilation tool can be selected, the file list flielist of the DUT and the file list filelist of the verification environment can be connected, compilation macros can be added, etc. Through the makefile file script, the test case can be automatically run a specified number of times. Specifically, the makefile file script can be used to set the number of runs and then start the system to automatically execute the simulation verification for the corresponding number of runs.

[0034] Each component in the above-mentioned UVM-based DMA communication UART module verification system can be fully or partially implemented by software, hardware and a combination thereof. The above-mentioned components can be embedded in or independent of a device with a data processing function in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules. The aforementioned device can be, but is not limited to, various types of chip verification computers already available in the art.

[0035] In one embodiment, a UART module verification method for DMA communication based on UVM is provided, which is applied to the UART module verification system for DMA communication based on UVM, such as Figure 2 As shown, the UART module verification method based on UVM DMA communication includes the following steps S10 to S16: S10, power on and initialize the UART module verification system; S12, calling the UART environment component through the test case to generate receiving data and sending it to the UART unit through the UART bus, and taking the receiving data as the expected result of receiving; S14, receiving the received data uninterruptedly through the UART unit, when the amount of data cached in the received data FIFO is higher than the set watermark, a DMA read request is issued to the DMA unit, and the DMA unit reads the received data from the UART unit and writes it into the storage unit; S16, read the received data from the storage unit through the AHB bus as the actual reception result, compare the expected reception result with the actual reception result, if the comparison fails, print the simulation log of the failed reception data comparison and end the simulation, if the comparison passes, output the simulation log of the successful reception comparison and end the simulation.

[0036] The above-mentioned UVM-based DMA communication UART module verification method builds an advanced UVM verification platform integrating data transmission, processing and inspection through SystemVerilog language. The integrated components of each AHB and UART protocol have good portability, and the integrated UART configuration component uart_cfg is used to randomize data and configuration. With a variety of test cases, the UVM verification methodology-based UART module verification supporting DMA communication is realized, and the completeness and accuracy of the verification are guaranteed. Compared with traditional technologies, not only a systematic verification solution for the UART module of DMA communication is provided, but also the flexibility of verification is improved by using the UVM verification environment, and the synchronization of the verification environment and the module to be tested is achieved with a lower configuration cost, which improves the efficiency of verification; at the same time, the degree of freedom of configuration options also improves the randomness of verification, making the verification more complete.

[0037] In one embodiment, Figure 3 As shown, the above-mentioned UART module verification method based on UVM DMA communication may also include the following steps S21 to S25: S21, generating pre-stored data through the UART frame format component and writing it into the storage unit through the AHB bus, and sending the generated pre-stored data to the UART data comparator as the expected result of sending; S23, when the amount of data in the transmit data FIFO buffer is lower than the set water level, a DMA transfer request is issued to the DMA unit, and the DMA unit reads the pre-stored data from the storage unit and writes it into the UART unit; after the pre-stored data enters the UART unit, it is sent to the UART environment component via the UART bus in the form of the UART communication protocol as the real result of the transmission; S25, compare the expected result and the actual result through the UART data comparator. If the comparison fails, the simulation ends after printing the simulation log of the failed comparison of the sent data. If the comparison passes, the simulation ends after outputting the simulation log of the successful comparison of the sent data.

[0038] Regarding the specific limitations of the UART module verification method for DMA communication based on UVM, please refer to the corresponding limitations of the UART module verification system for DMA communication based on UVM above, which will not be repeated here.

[0039] It should be understood that although Figure 2 and Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 2 and Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0040] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0041] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A UART module verification system for DMA communication based on UVM, characterized in that, The method comprises a top-level file, wherein the top-level file comprises a test case base class, an instantiated AHB bus, an instantiated UART bus and a DUT to be tested, wherein the DUT to be tested comprises a UART unit, a DMA unit and a storage unit; A verification environment and a test case are deployed based on the test case base class, wherein the verification environment includes an AHB system environment component and a UART environment component, wherein the AHB system environment component includes a component system environment configuration and an AHB host agent component, wherein the AHB host agent component includes a sequence generator, an AHB driver, and an AHB bus monitor, wherein the sequence generator is used to generate a sequence when the test case is called and pass it to the AHB driver, and then send it to the DUT via the AHB bus, and the AHB bus monitor continuously monitors whether the access initiated by the DUT complies with the AHB protocol during the data transmission process via the AHB bus; the instantiated AHB bus and the UART bus are used to connect the DUT and the verification environment respectively; The UART environment component includes a UART data sending component, a UART data receiving component, a UART configuration component, a UART frame format component and a UART data comparator. The sequence generator in the UART data sending component generates data through the UART frame format component and then sends the data to the DUT via the UART bus by the UART_ driver in the UART data sending component. The UART monitor in the UART data receiving component collects the data sent from the UART bus and sends it to the UART data comparator for comparison between expected results and actual results. The UART configuration component is used to generate configuration information of each component and the DUT, and is used to randomly generate frame format configurations of different lengths and different verification methods and send them to the UART frame format component.

2. The UART module verification system of the DMA communication based on UVM according to claim 1, characterized in that, The baud rate clock of the DUT is consistent with the sampling frequency of the UART environment component; the baud rate clock of the DUT is randomly determined by the UART configuration component.

3. The UART module verification system of the DMA communication based on UVM according to claim 1 or 2, characterized in that, The UART configuration component is also used to randomly configure the watermarks of the receive data FIFO buffer and the transmit data FIFO buffer in the UART unit.

4. The UART module verification system of the DMA communication based on UVM according to claim 3, characterized in that, The test case calls the UART environment component to generate received data and sends it to the UART unit via the UART bus, and uses the received data as the expected result of reception; The UART unit continuously receives the received data, and when the amount of data in the received data FIFO buffer is higher than the set watermark, a DMA read request is issued to the DMA unit, and the DMA unit reads the received data from the UART unit and writes it into the storage unit; The test case reads the received data from the storage unit through the AHB bus as the actual reception result, and compares the expected reception result with the actual reception result. If the comparison fails, the simulation ends after printing the simulation log of failed reception data comparison; if the comparison passes, the simulation ends after outputting the simulation log of successful reception comparison.

5. The UART module verification system of the DMA communication based on UVM according to claim 3, characterized in that, The test case generates pre-stored data through the UART frame format component and writes it into the storage unit through the AHB bus, and sends the generated pre-stored data to the UART data comparator as the expected result of sending; When the amount of data in the transmit data FIFO buffer is lower than the set water level, a DMA transfer request is issued to the DMA unit, and the DMA unit reads the pre-stored data from the storage unit and writes it into the UART unit. After the pre-stored data enters the UART unit, it is sent to the UART environment component through the UART bus in the form of the UART communication protocol as a real sending result; The UART data comparator compares the expected sending result with the actual sending result. If the comparison fails, the simulation ends after printing a simulation log of failed sending data comparison. If the comparison passes, the simulation ends after outputting a simulation log of successful sending comparison.

6. The UART module verification system of the DMA communication based on UVM according to claim 3, characterized in that, It also includes a written makefile file and a selected compilation tool, wherein the makefile file is used to connect the file list of the DUT and the file list of the verification environment, and add compilation macros.

7. A UART module verification method for DMA communication based on UVM, characterized in that, The UART module verification system for DMA communication based on UVM according to any one of claims 1 to 6, wherein the UART module verification method for DMA communication based on UVM comprises the steps of: Power on and initialize the UART module verification system; Calling the UART environment component through the test case generates receiving data and sends it to the UART unit through the UART bus, and taking the receiving data as the expected result of receiving; The received data is continuously received through the UART unit, and when the amount of data in the received data FIFO buffer is higher than the set watermark, a DMA read request is issued to the DMA unit, and the DMA unit reads the received data from the UART unit and writes it into the storage unit; The received data is read out from the storage unit through the AHB bus as the actual reception result, and the expected reception result and the actual reception result are compared. If the comparison fails, the simulation ends after printing the simulation log of failed reception data comparison; if the comparison passes, the simulation ends after outputting the simulation log of successful reception comparison.

8. The UART module verification method of the DMA communication based on UVM according to claim 7, characterized in that, Also includes the steps: Generate pre-stored data through the UART frame format component and write it into the storage unit through the AHB bus, and send the generated pre-stored data to the UART data comparator as the expected result of sending; When the amount of data in the transmit data FIFO buffer is lower than the set water level, a DMA transfer request is issued to the DMA unit, and the DMA unit reads the pre-stored data from the storage unit and writes it into the UART unit; after the pre-stored data enters the UART unit, it is sent to the UART environment component through the UART bus in the form of the UART communication protocol as a real sending result; The expected sending result and the actual sending result are compared by the UART data comparator. If the comparison fails, the simulation ends after printing the simulation log of sending data comparison failure. If the comparison passes, the simulation ends after outputting the simulation log of sending data comparison success.

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