A circuit board communication address allocation system, method, device and storage medium

Abstract

The application discloses a circuit board communication address allocation system, method and device and a storage medium. The system comprises a main circuit board and multiple sub-circuit boards, wherein the main circuit board is electrically connected with the input end of a resistor in an adjacent sub-circuit board through a voltage dividing power supply wire; the main circuit board and the resistor in the sub-circuit board form a series loop through a field effect transistor in the sub-circuit board; and the MCU of the main circuit board is in communication connection with the MCU of the sub-circuit board. The technical scheme of the embodiment of the application can quickly and accurately realize allocation of the communication address of the sub-circuit board, and solves the problems of low efficiency and large workload of the sub-circuit board communication address allocation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a circuit board communication address allocation system, method, device and storage medium. BACKGROUND

[0002] In the development process of a device, a master board and multiple sub-boards are usually connected in series to form a complete device. The master board and the sub-boards can exchange data through a communication interface such as RS485, I2C or CAN.

[0003] Currently, in such a device series structure, each sub-board needs to be assigned a unique communication address, so that the sub-board can stably exchange data with the master board or other sub-boards. The existing sub-board communication address allocation methods mainly include: 1) writing the communication address in the software code; 2) setting the communication address through a hardware dial switch; and 3) developing a host computer tool to set the communication address of each sub-board through the host computer tool.

[0004] However, the first method requires each sub-board to be configured with corresponding firmware, which can cause difficulty in firmware management when the number of sub-boards is large. The disadvantage of the second method is that each series-connected sub-board needs to be manually dialed before the device is powered on, which affects work efficiency. The disadvantage of the third method is that the development of the host computer tool requires a certain amount of work, and setting the communication address of each sub-board on site using the host computer tool also affects work efficiency. The existing sub-board communication address allocation methods have problems such as low efficiency or large configuration workload. SUMMARY

[0005] The present application provides a circuit board communication address allocation system, method, device and storage medium to solve the problems of low efficiency and large workload in sub-board communication address allocation.

[0006] In a first aspect, the present application provides a circuit board communication address allocation system, which comprises a master circuit board and multiple sub-circuit boards, wherein:

[0007] The master circuit board is electrically connected to the input end of the resistor in the adjacent sub-circuit board through a voltage dividing power supply wire; the master circuit board and the resistor in the sub-circuit board form a series loop through a field effect transistor in the sub-circuit board; and the MCU of the master circuit board is in communication connection with the MCU of the sub-circuit board.

[0008] In a second aspect, the present application provides a circuit board communication address allocation method applied to the master circuit board of the circuit board communication address allocation system of the first aspect, and the method comprises:

[0009] The information acquisition unit module is used for acquiring the residual voltage and the chip identifier of the built-in chip of each sub-circuit board through the acquisition port, wherein the residual voltage is the residual loop voltage measured at the position of the current sub-circuit board in the serial loop, and the residual voltages sent by different sub-circuit boards are different.

[0010] The communication address configuration module is used for configuring the communication address of the sub-circuit board according to the residual voltage and the chip identifier.

[0011] In a third aspect, the application provides a circuit board communication address allocation device applied to the main circuit board of the circuit board communication address allocation system in the first aspect, and the device comprises:

[0012] The information acquisition unit module is used for acquiring the residual voltage and the chip identifier of the built-in chip of each sub-circuit board through the acquisition port, wherein the residual voltage is the residual loop voltage measured at the position of the current sub-circuit board in the serial loop, and the residual voltages sent by different sub-circuit boards are different.

[0013] The communication address configuration module is used for configuring the communication address of the sub-circuit board according to the residual voltage and the chip identifier.

[0014] In a fourth aspect, the application provides a computer readable storage medium, which stores computer instructions for making a processor execute the circuit board communication address allocation method in the second aspect.

[0015] The circuit board communication address allocation system provided by the application comprises a main circuit board and a plurality of sub-circuit boards, wherein the main circuit board is electrically connected with the input end of the resistor in the adjacent sub-circuit board through the voltage dividing power supply wire, the main circuit board and the resistor in the sub-circuit board form a serial loop through the field effect tube in the sub-circuit board, and the MCU of the main circuit board is in communication connection with the MCU of the sub-circuit board. The system uses the resistance series voltage division mode, does not need to increase the firmware or hardware dial switch, and can quickly and accurately realize the allocation of the communication address of the sub-circuit board by the main circuit board, thereby solving the problems of low efficiency and large workload in the allocation of the communication address of the sub-circuit board.

[0016] The circuit board communication address allocation scheme provided by the application obtains the residual voltage and the chip identification of the built-in chip of each sub-circuit board sent by the acquisition port, wherein the residual voltage is the residual loop voltage measured by the current sub-circuit board in the serial loop, and the residual voltage sent by different sub-circuit boards is different, and the communication address of the sub-circuit board is configured according to the residual voltage and the chip identification. By using the above technical scheme, the different residual voltage values and the corresponding chip identifications collected by each sub-circuit board are used to quickly and accurately realize the allocation of the communication address of the sub-circuit board, and the problems of low efficiency and large workload of sub-circuit board communication address allocation are solved.

[0017] It should be understood that the content described in this part is not intended to identify the key or important features of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 It is an architecture schematic diagram of a circuit board communication address allocation system provided by the first embodiment of the application;

[0020] Figure 2 It is a circuit connection diagram of a circuit board communication address allocation system provided by the second embodiment of the application;

[0021] Figure 3 It is a flow chart of a circuit board communication address allocation method provided by the third embodiment of the application;

[0022] Figure 4 It is a flow chart of a circuit board communication address allocation method provided by the fourth embodiment of the application;

[0023] Figure 5 It is a structure schematic diagram of a circuit board communication address allocation device provided by the fifth embodiment of the application. DETAILED DESCRIPTION

[0024] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort should belong to the protection scope of the present application.

[0025] It should be noted that the terms "first", "second" and the like in the description of the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In the description of the present application, "a plurality of" means two or more, unless otherwise specified. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] Embodiment one

[0027] Figure 1 The schematic diagram of the architecture of a circuit board communication address allocation system provided by the first embodiment of the present application can be applied to the allocation of sub-circuit board communication addresses.

[0028] The circuit board communication address allocation system includes a main circuit board and a plurality of sub-circuit boards, wherein: the main circuit board is electrically connected to the input end of the resistor in the adjacent sub-circuit board through the voltage dividing power supply wire; the main circuit board and the resistor in the sub-circuit board form a series loop through the field effect tube in the sub-circuit board; and the MCU of the main circuit board is in communication connection with the MCU of the sub-circuit board.

[0029] For example, Figure 1As shown in the figure, the circuit board communication address allocation system comprises a main circuit board 101 and four sub-circuit boards 102, wherein: the main circuit board 101 is electrically connected to the input end of the resistor in the adjacent sub-circuit board 102 through the voltage dividing power supply wire 103; the main circuit board 101 forms a series loop with the resistor 105 in the sub-circuit board 102 through the field effect tube 104 in the sub-circuit board 102; the MCU 106 of the main circuit board 101 is in communication connection with the MCU 107 of the sub-circuit board 102. The field effect tube of only the last sub-circuit board (i.e. the circuit board 4) in the four sub-circuit boards is turned on to ground, so that the output end of the resistor is connected to the ground, forming a series loop of the resistors of the four sub-circuit boards.

[0030] In the embodiment, the MCU of the main circuit board and the MCU of the sub-circuit board can form a communication connection in a wired or wireless manner. The MCU of the main circuit board can be used to receive the information sent by the MCU of the sub-circuit board, and allocate a communication address to the sub-circuit board according to the information. The MCU of the sub-circuit board can be used to receive the information and send the information to the main circuit board. The information comprises a residual voltage, which is a residual loop voltage measured at the position of the current sub-circuit board in the series loop, i.e. a residual loop voltage measured at the position of the resistor in the current sub-circuit board in the series loop formed by the main circuit board and the resistors in the sub-circuit boards through the field effect tubes in the sub-circuit boards.

[0031] The circuit board communication address allocation system provided by the embodiment of the application comprises a main circuit board and four sub-circuit boards. The main circuit board forms a series loop with the resistors in the sub-circuit boards through the field effect tubes in the sub-circuit boards. Without increasing firmware or hardware dial switch, the MCU of the main circuit board can quickly and accurately allocate a communication address to the sub-circuit board according to the information sent by the sub-circuit board through the series voltage division of the resistors, thereby solving the problems of low efficiency and large workload in the allocation of the communication address of the sub-circuit board.

[0032] Embodiment two

[0033] Figure 2 The circuit connection diagram of the circuit board communication address allocation system provided by the embodiment two of the application. The system of the embodiment of the application is further optimized on the basis of the above system, and specific details of the circuit board communication address allocation system are given.

[0034] Optionally, the main circuit board supplies power to the adjacent sub-circuit board; the sub-circuit board supplies power to the adjacent next-level sub-circuit board; the output end of the resistor in the sub-circuit board is electrically connected to the input end of the resistor of the adjacent next-level sub-circuit, the acquisition port of the MCU built-in in the sub-circuit board and the source stage of the field effect tube built-in in the sub-circuit board; the acquisition port comprises an analog-digital converter acquisition port.

[0035] Furthermore, the drain of the field-effect transistor is grounded, and the gate of the field-effect transistor is electrically connected to the power supply output terminal of the adjacent next-level sub-circuit board; the source and drain of the last-level sub-circuit board are connected.

[0036] Optionally, the field-effect transistor includes a PMOS transistor or an NMOS transistor.

[0037] For example, such as Figure 2 As shown, assume there are currently 5 boards connected in series: 1 main (circuit) board and 4 sub- (circuit) boards. The main board's power output supplies power to sub-board 1, sub-board 1's power output supplies power to sub-board 2, and so on, with each sub-board powered by the preceding sub-board. A voltage divider power line is led out from the main board and connected to the resistor input terminal of sub-board 1. The output terminal of the resistor in sub-board 1 is connected to the input terminal of the resistor in sub-board 2, the output terminal of the resistor in sub-board 2 is connected to the input terminal of the resistor in sub-board 3, and the output terminal of the resistor in sub-board 3 is connected to the input terminal of the resistor in sub-board 4, thus this voltage divider power line is connected in series through the resistors of each sub-board. The output terminal of the resistor in each sub-board is connected to the ADC (analog-to-digital converter) acquisition port of the sub-board MCU to acquire residual voltage. Each sub-board can contain one PMOS transistor. The source of the PMOS transistor is connected to the output terminal of the resistor in the sub-board, the drain is grounded, and the gate is connected to the power output terminal of the next sub-board. If the current sub-board is an intermediate sub-board, the PMOS transistor is not turned on because the power supply output of the next sub-board is to the gate of the current sub-board. The gate of the PMOS transistor of the penultimate sub-board is connected to the power input terminal of the next sub-board. If the current sub-board is the last sub-board, the PMOS transistor is turned on because there is no power input from the next sub-board to its gate, thus connecting the resistor output terminal to ground, forming a loop.

[0038] The circuit board communication address allocation system provided in this invention can automatically determine whether the current sub-board is the last sub-board by supplying power to the gate of the PMOS transistor of the previous sub-board from the next sub-board. If it is not the last sub-board, the next sub-board will supply power to the gate of the PMOS transistor, causing the PMOS transistor to open and the voltage divider circuit to not form a loop. If it is the last sub-board, the PMOS transistor has no voltage, causing it to close and the voltage divider circuit to form a loop. The motherboard can quickly identify the position of the sub-board based on the collected residual voltage sent by the sub-board, and achieve fast and accurate allocation of communication addresses to the sub-board based on the position, solving the problems of low efficiency and large workload in sub-board communication address allocation.

[0039] Example 3

[0040] Figure 3A flowchart of a circuit board communication address allocation method provided by the third embodiment of the present application is provided, and the embodiment can be applied to the allocation of circuit board communication addresses and is applied to the main circuit board in the circuit board communication address allocation system described in the above embodiments. The method can be executed by a circuit board communication address allocation device, which can be realized in the form of hardware and / or software.

[0041] As shown in Figure 3 The circuit board communication address allocation method provided by the third embodiment of the present application specifically includes the following steps:

[0042] S301, acquiring the residual voltage sent by each sub-circuit board and the chip identifier of the built-in chip of the sub-circuit board through a collection port, wherein the residual voltage is the residual loop voltage measured at the position of the current sub-circuit board in the series loop, and the residual voltage sent by different sub-circuit boards is different.

[0043] S302, configuring the communication address of the sub-circuit board according to the residual voltage and the chip identifier.

[0044] In the embodiment, the main circuit board can acquire the residual voltage sent by the sub-circuit board and the chip identifier of the built-in chip. Since the main circuit board and the resistors in the sub-circuit board form a series voltage division circuit, the residual voltage sent by the sub-circuit board at different series positions is different. According to the residual voltage, the series position of the sub-circuit board can be determined, different communication addresses can be allocated according to the distance of the position, and the communication address can be issued to the corresponding sub-circuit board according to the chip identifier, so as to complete the configuration of the communication address of the sub-circuit board.

[0045] The circuit board communication address allocation method provided by the embodiment of the present application acquires the residual voltage sent by each sub-circuit board and the chip identifier of the built-in chip of the sub-circuit board through a collection port, wherein the residual voltage is the residual loop voltage measured at the position of the current sub-circuit board in the series loop, and the residual voltage sent by different sub-circuit boards is different, and the communication address of the sub-circuit board is configured according to the residual voltage and the chip identifier. The technical scheme of the embodiment of the present application quickly and accurately realizes the allocation of the communication address of the sub-circuit board through the different residual voltage values and the corresponding chip identifiers collected by each sub-circuit board, and solves the problems of low efficiency and large workload in the allocation of the communication address of the sub-circuit board.

[0046] Embodiment four

[0047] Figure 4 A flowchart of a circuit board communication address allocation method provided by the fourth embodiment of the present application is provided, and the technical scheme of the embodiment of the present application is further optimized on the basis of the above optional technical schemes, and a specific way of allocating the communication address of the circuit board is given.

[0048] Optionally, the communication address of the sub-circuit board is configured according to the residual voltage and the chip identifier, including: sorting the values of the residual voltages to obtain a sorting result; generating the communication address of the sub-circuit board according to the sorting result, and sending the communication address and the corresponding chip identifier to the sub-circuit board, so that the sub-circuit board acquires the corresponding communication address according to the chip identifier, to complete the configuration of the communication address of the sub-circuit board. In this way, the position of the corresponding sub-circuit board in series can be quickly determined by sorting the values of the residual voltages, so that the main board can reasonably allocate the communication address according to the position.

[0049] As shown in Figure 4 The circuit board communication address allocation method provided by the fourth embodiment of the present application specifically includes the following steps:

[0050] S401, the residual voltage and the chip identifier of the built-in chip of each sub-circuit board are acquired through the acquisition port, wherein the residual voltage is the residual loop voltage measured by the current sub-circuit board in the series loop, and the residual voltages sent by different sub-circuit boards are different.

[0051] S402, the values of the residual voltages are sorted to obtain a sorting result.

[0052] S403, the communication address of the sub-circuit board is generated according to the sorting result, and the communication address and the corresponding chip identifier are sent to the sub-circuit board, so that the sub-circuit board acquires the corresponding communication address according to the chip identifier, to complete the configuration of the communication address of the sub-circuit board.

[0053] Optionally, when the communication address is a number, the communication address and the residual voltage have a negative correlation or a positive correlation.

[0054] Optionally, the closer the series position of the sub-circuit board to the main circuit board, the greater the residual voltage sent by the sub-circuit board.

[0055] Specifically, the sub-circuit board can send the residual voltage value collected by itself and the chip identifier of the chip in the MCU configured by itself to the MCU of the main circuit board through the communication interface. The main circuit board sorts the residual voltage values reported by each sub-circuit board. For example, the sub-circuit board corresponding to the maximum residual voltage can be determined as 1, the sub-circuit board corresponding to the second maximum residual voltage can be determined as 2, the sub-circuit board corresponding to the third maximum residual voltage can be determined as 3, and so on. The communication address allocated in this way matches the serial position of the sub-circuit board in the serial circuit. After sorting, the main circuit board can send the allocated communication address and the corresponding chip identifier to the sub-circuit board through the communication interface of the MCU of the main circuit board. The sub-circuit board matches the corresponding communication address according to the chip identifier of the MCU of the sub-circuit board to realize the configuration of the communication address of the sub-circuit board.

[0056] The circuit board communication address allocation method provided by the embodiment of the application can quickly determine the serial position of the corresponding sub-circuit board by sorting the residual voltage values, so that the main board can reasonably allocate the communication address according to the position, quickly and accurately realize the allocation of the communication address of the sub-circuit board, and solve the problems of low efficiency and large workload in the allocation of the communication address of the sub-circuit board.

[0057] Embodiment five

[0058] Figure 5 A structural schematic diagram of a circuit board communication address allocation device provided by the embodiment five of the application is shown in the figure. Figure 5 As shown in the figure, the device comprises an information acquisition unit module 501 and a communication address configuration module 502, wherein:

[0059] The information acquisition unit module is configured to acquire the residual voltage and the chip identifier of the built-in chip of each sub-circuit board sent by the sub-circuit board through the acquisition port, wherein the residual voltage is the residual circuit voltage measured by the current sub-circuit board in the serial circuit, and the residual voltage sent by different sub-circuit boards is different.

[0060] The communication address configuration module is configured to configure the communication address of the sub-circuit board according to the residual voltage and the chip identifier.

[0061] The circuit board communication address allocation device provided by the embodiment of the application can quickly and accurately realize the allocation of the communication address of the sub-circuit board by the different residual voltage values and the corresponding chip identifiers collected by each sub-circuit board, and solve the problems of low efficiency and large workload in the allocation of the communication address of the sub-circuit board.

[0062] Optionally, the communication address configuration module comprises:

[0063] a sorting unit configured to sort the values of the residual voltages to obtain a sorting result;

[0064] a communication address configuration unit configured to generate a communication address of the sub-circuit board according to the sorting result, and send the communication address and a corresponding chip identifier to the sub-circuit board, so that the sub-circuit board acquires the corresponding communication address according to the chip identifier to complete the configuration of the communication address of the sub-circuit board.

[0065] Optionally, when the communication address is a number, the communication address and the residual voltage have a negative correlation or a positive correlation.

[0066] Optionally, the closer the series position of the sub-circuit board to the main circuit board, the greater the residual voltage sent by the sub-circuit board.

[0067] The circuit board communication address allocation device provided by the embodiments of the present application can perform the circuit board communication address allocation method provided by any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method.

[0068] Embodiment six

[0069] In the context of the present application, the computer-readable storage medium can be a tangible medium, and the computer-executable instructions, when executed by a computer processor, are used to perform a circuit board communication address allocation method, which comprises:

[0070] obtaining, through an acquisition port, a residual voltage and a chip identifier of an inbuilt chip of each sub-circuit board, wherein the residual voltage is a residual loop voltage measured at the position of the current sub-circuit board in a series loop, and the residual voltages sent by different sub-circuit boards are different;

[0071] configuring a communication address of the sub-circuit board according to the residual voltage and the chip identifier.

[0072] In the context of the present application, a computer readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer readable storage medium can be a machine readable signal medium. More specific examples of a machine readable storage medium will include one or more lines of a program of instructions in a transitory signal form, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0073] The computer device provided above can be used to execute the circuit board communication address allocation method provided by any of the embodiments above, and has the corresponding functions and advantages.

[0074] It is worth noting that the embodiments of the circuit board communication address allocation device above include various units and modules only according to the logical division of functions, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of each functional unit are only for easy mutual distinction, and do not limit the protection scope of the present application.

[0075] Note that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A circuit board communication address allocation system, characterized in that, The system includes a main circuit board and multiple sub-circuit boards, wherein: The main circuit board is electrically connected to the input terminals of resistors in adjacent sub-circuits via voltage divider power supply wires; the main circuit board forms a series circuit with resistors in all sub-circuits via field-effect transistors in the sub-circuits; the MCU of the main circuit board is communicatively connected to the MCU of the sub-circuits. The output terminal of the resistor in the sub-circuit board is electrically connected to the input terminal of the resistor in the adjacent next-level sub-circuit; the drain of the field-effect transistor is grounded, and the gate of the field-effect transistor is electrically connected to the power supply output terminal of the adjacent next-level sub-circuit board; the source and drain in the last sub-circuit board are connected.

2. The system according to claim 1, characterized in that, The main circuit board supplies power to the adjacent sub-circuit board; the sub-circuit board supplies power to the adjacent next-level sub-circuit board; the output terminals of the resistors in the sub-circuit board are also electrically connected to the acquisition port of its built-in MCU and the source terminal of its built-in field-effect transistor; the acquisition port includes an analog-to-digital converter acquisition port.

3. The system according to claim 1, characterized in that, The field-effect transistor includes a PMOS transistor or an NMOS transistor.

4. A circuit board communication address allocation method, applied to the main circuit board of the circuit board communication address allocation system according to any one of claims 1-3, characterized in that, The method includes: The remaining voltage and chip identifier of the built-in chip of each sub-circuit board are obtained through the acquisition port. The remaining voltage is the remaining circuit voltage measured at the position of the current sub-circuit board in the series circuit. The remaining voltages sent by different sub-circuit boards are different. Configure the communication address of the sub-circuit board based on the remaining voltage and the chip identifier.

5. The method according to claim 4, characterized in that, The step of configuring the communication address of the sub-circuit board based on the remaining voltage and the chip identifier includes: The remaining voltage values ​​are sorted to obtain a sorting result; The communication address of the sub-circuit board is generated based on the sorting result, and the communication address and the corresponding chip identifier are sent to the sub-circuit board so that the sub-circuit board can obtain the corresponding communication address based on the chip identifier, thereby completing the configuration of the communication address of the sub-circuit board.

6. The method according to claim 5, characterized in that, When the communication address is a number, the communication address and the remaining voltage are either negatively or positively correlated.

7. The method according to claim 4, characterized in that, The closer the sub-circuit board is to the main circuit board in series, the greater the residual voltage transmitted by the sub-circuit board.

8. A circuit board communication address allocation device, applied to the main circuit board of the circuit board communication address allocation system according to any one of claims 1-3, characterized in that, The device includes: The information acquisition unit module is used to acquire the remaining voltage and chip identifier of the built-in chip of each sub-circuit board through the acquisition port. The remaining voltage is the remaining circuit voltage measured by the position of the current sub-circuit board in the series circuit. The remaining voltages sent by different sub-circuit boards are different. The communication address configuration module is used to configure the communication address of the sub-circuit board according to the remaining voltage and the chip identifier.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the circuit board communication address allocation method according to any one of claims 4-7.

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