Repair method and device for keeping time sequence violation in chip, equipment and storage medium

Abstract

The invention provides a repairing method and device for keeping time sequence violation in a chip, equipment and a storage medium, and relates to the technical field of chips. The method comprises the following steps: determining the repair type of each to-be-repaired path according to the establishment time margin of each to-be-repaired path; according to the repair type of each to-be-repaired path, determining a time sequence repair strategy corresponding to each to-be-repaired path; and repairing the time sequence keeping violation of each to-be-repaired path according to the time sequence repairing strategy corresponding to each to-be-repaired path. According to the method, the set-up time margin of the unit in the path can be utilized to the maximum extent, and set-up time sequence violation caused by repairing the set-up time sequence violation can be reduced while the set-up time sequence violation is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device, equipment and storage medium for repairing timing violations in a chip. Background Art

[0002] With the development of integrated circuits, the chip scale is getting larger and larger. For high-frequency and high-performance chips, the timing requirements are very strict. In physical design, more attention is paid to the setup timing, which makes it difficult to converge the hold timing violation in the later stage. Therefore, it takes a lot of time to fix the hold timing violation.

[0003] Currently, the commonly used method to repair hold violations is to add delay units before units with sufficient setup margins or to change the number of winding layers, increase the winding length, etc.

[0004] However, for high-frequency chips, it is difficult to maximize the use of setup margin using the above method, and the setup timing may be deteriorated due to slight changes in winding or movement of unit positions. Summary of the invention

[0005] The purpose of the present application is to provide a method, device, equipment and storage medium for repairing hold time timing violations in a chip in order to improve the repair efficiency of hold time timing violations and reduce the setup time timing violations caused by repairing hold time timing violations.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a method for repairing a timing violation in a chip, comprising:

[0008] Determine the repair type of each path to be repaired according to the establishment time margin of each path to be repaired; the repair type includes: a first type and a second type, the first type is used to indicate that the establishment time margin of the path to be repaired is less than a first preset threshold; the second type is used to indicate that the establishment time margin of the path to be repaired is greater than or equal to a second preset threshold;

[0009] Determine, according to the repair type of each path to be repaired, a timing repair strategy corresponding to each path to be repaired, wherein the timing repair strategy includes: a first strategy and a second strategy, wherein the first strategy is used to instruct to insert a delay unit into a designated area corresponding to each unit in the path to be repaired to perform path repair; and the second strategy is used to instruct to perform step-by-step repair on each unit in the path to be repaired according to set constraints, and to insert a delay unit into a designated area corresponding to each unit in the path to be repaired to perform path repair;

[0010] According to the timing repair strategy corresponding to each path to be repaired, the hold timing violation of each path to be repaired is repaired.

[0011] Optionally, determining the repair type of each path to be repaired according to the establishment time margin of each path to be repaired includes:

[0012] Determine the setup time margin of the path to be repaired according to setup time margin information of the path end point of the path to be repaired under each process angle;

[0013] If the establishment time margin is less than the first preset threshold, determining that the repair type of the path to be repaired is the first type;

[0014] If the establishment time margin is greater than or equal to the second preset threshold, it is determined that the repair type of the path to be repaired is the second type.

[0015] Optionally, determining the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired includes:

[0016] If the repair type of the path to be repaired is the first type, determining that the timing repair strategy corresponding to the path to be repaired is the first strategy;

[0017] If the repair type of the path to be repaired is the second type, it is determined that the timing repair strategy corresponding to the path to be repaired is the second strategy.

[0018] Optionally, the repairing the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired includes:

[0019] If the timing repair strategy corresponding to the path to be repaired is the first strategy, the following loop steps are performed:

[0020] A1. Establish a first sequence of units to be processed according to the establishment time margin of each unit in the path to be repaired, and use the first unit to be processed in the first sequence of units to be processed as the initial current unit to be processed;

[0021] B1. Determine whether to perform setup time timing repair on a target path according to the setup time margin of the current unit to be processed, wherein the current unit to be processed is located in the target path, and the setup time margin of the current unit to be processed is output through the target path;

[0022] C1. If yes, then repair the target path to establish the time sequence and re-execute step A1;

[0023] D1, if not, determining the insertion position and delay parameter of the target delay unit to be inserted according to the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired, and inserting the target delay unit into the path to be repaired according to the insertion position and the delay parameter;

[0024] E1. Determine the current total delay time of the path to be repaired according to the delay parameter of the target delay unit and the newly added line delay related to the target delay unit in the path to be repaired, determine the new current hold timing violation value of the path to be repaired according to the current total delay time and the current hold timing violation value, and determine the new setup time margin of the current unit to be processed according to the current total delay time and the setup time margin of the current unit to be processed;

[0025] F1, if the new setup time margin of the current unit to be processed is less than the new current hold timing violation value, a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as a new current unit to be processed, and step B1 is executed again;

[0026] G1, if the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is less than the new setup time margin, then a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as the new current unit to be processed, and step B1 is re-executed, or step D1 is re-executed; wherein the current estimated total delay time is determined according to the new setup time margin of the current unit to be processed and the new current hold timing violation value of the path to be repaired;

[0027] H1. If the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is greater than or equal to the new setup time margin, then the loop ends.

[0028] Optionally, the performing time timing repair on the target path includes:

[0029] At least one of the following establishment time timing repair operations is performed on the target path: crosstalk resolution, fan-out division, correction of signal transition time, delayed capture clock, and shortening of transmission time.

[0030] Optionally, determining an insertion position and a delay parameter of a target delay unit to be inserted according to a setup time margin of a current unit to be processed and a current hold timing violation value of the path to be repaired, and inserting the target delay unit into the path to be repaired according to the insertion position and the delay parameter comprises:

[0031] Determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius;

[0032] The target delay unit is inserted into the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area.

[0033] Optionally, inserting the target delay unit in the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the idle position information in the delay unit placement area includes:

[0034] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area meets the condition, then determine a first position that meets a first distance from the current unit to be processed and a first delay parameter that is equal to the current hold timing violation value in the delay unit placement area, and insert a first target delay unit having the first delay parameter at the first position;

[0035] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area does not meet the condition, then determine a second position in the delay unit placement area that meets a second distance from the current unit to be processed, and determine a third position according to the second position and the position of the current unit to be processed, and insert a second target delay unit with a first preset delay parameter in the second position and insert a third target delay unit with a second preset delay parameter in the second position; the second preset delay parameter is a preset multiple of the first preset delay parameter;

[0036] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area meets the condition, then determine a second delay parameter equal to the setup time margin of the current unit to be processed, and insert a fourth target delay unit with the second delay parameter at the first position;

[0037] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area does not meet the conditions, a fifth target delay unit with the first preset delay parameter is inserted into the second position; the target delay unit is one or more of the first target delay unit, the second target delay unit, the third target delay unit, the fourth target delay unit and the fifth target delay unit.

[0038] Optionally, determining a new current hold timing violation value of the path to be repaired according to the current total delay time and the current hold timing violation value, and determining a new setup time margin of the current unit to be processed according to the current total delay time and the setup time margin of the current unit to be processed, comprises:

[0039] Determine a first difference between the current total delay time and the current hold timing violation value, and use the first difference as a new current hold timing violation value of the path to be repaired;

[0040] A second difference between the current total delay time and the setup time margin of the current unit to be processed is determined, and the second difference is determined as a new setup time margin of the current unit to be processed.

[0041] Optionally, the repairing the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired includes:

[0042] If the timing repair strategy corresponding to the path to be repaired is the second strategy, determining initial current congestion constraint information and initial current signal transition time constraint information;

[0043] Determine parameter information of each unit in the path to be repaired, wherein the parameter information includes: setup time margin, congestion degree, and signal transition time;

[0044] A2. Establish a second sequence of units to be processed according to the establishment time margin of each unit, and use the first unit to be processed in the second sequence of units to be processed as the initial current unit to be processed;

[0045] B2. Determine whether to insert a delay unit into the current unit to be processed according to the parameter information of the current unit to be processed, the current congestion constraint information and the current signal jump time constraint information;

[0046] C2, if yes, insert a delay unit into the current unit to be processed, update the parameter information of the current unit to be processed, and execute step E2;

[0047] D2. If not, update the current congestion constraint information and the current signal transition time constraint information, and re-execute step A2;

[0048] E2. Determine whether to end the loop based on the current timing violation information of the path to be repaired and the updated parameter information of the current unit to be processed. If so, end the loop; otherwise, take a unit to be processed in the second unit to be processed sequence that is located after the current unit to be processed as a new current unit to be processed, and re-execute step B2.

[0049] Optionally, determining whether to insert a delay unit into the current unit to be processed according to parameter information of the current unit to be processed, current congestion constraint information, and current signal transition time constraint information includes:

[0050] If the congestion degree of the current unit to be processed satisfies the current congestion constraint information, and the signal transition time of the current unit to be processed satisfies the current signal transition time constraint information, it is determined to insert a delay unit into the current unit to be processed.

[0051] Optionally, inserting a delay unit into the current unit to be processed includes:

[0052] Determine the number of target delay units currently allowed to be inserted and the total delay of the target delay units allowed to be inserted according to the pre-estimated congestion margin and the pre-estimated signal transition time margin;

[0053] The insertion position and delay parameter of each target delay unit are determined according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, and the target delay unit is inserted into the path to be repaired according to the insertion position and delay parameter of each target delay unit.

[0054] Optionally, determining the insertion position and delay parameter of each target delay unit according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, and inserting the target delay unit into the path to be repaired according to the insertion position and delay parameter of each target delay unit, comprises:

[0055] Determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius;

[0056] The target delay unit is inserted into the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the idle position information in the delay unit placement area.

[0057] Optionally, inserting the target delay unit in the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the idle position information in the delay unit placement area includes:

[0058] If the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is greater than 0, and the free positions in the delay unit placement area meet the conditions, inserting at least one target delay unit in the delay unit placement area according to the number of the target delay units allowed to be inserted and the total delay of the target delay units allowed to be inserted;

[0059] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is greater than 0, and the idle position in the delay unit placement area does not meet the condition, a fourth position that meets the third distance from the current unit to be processed is determined in the delay unit placement area, and a fifth position is determined according to the fourth position and the position of the current unit to be processed, and a sixth target delay unit with a first preset delay parameter is inserted in the fourth position, and a seventh target delay unit with a second preset delay parameter is inserted in the fifth position;

[0060] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and the free position in the delay unit placement area meets the condition, then determine the delay parameter of the target delay unit to be inserted according to the setup time margin of the current unit to be processed, and insert at least one target delay unit with the delay parameter in the delay unit placement area;

[0061] If the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is less than 0, and the idle positions in the delay unit placement area do not meet the conditions, an eighth target delay unit with the first preset delay parameter is inserted at the fourth position.

[0062] In a second aspect, an embodiment of the present application further provides a device for repairing a timing violation in a chip, comprising: a determination module and a processing module;

[0063] The determination module is used to determine the repair type of each path to be repaired according to the establishment time margin of each path to be repaired; the repair type includes: a first type and a second type, the first type is used to indicate that the establishment time margin of the path to be repaired is less than a first preset threshold; the second type is used to indicate that the establishment time margin of the path to be repaired is greater than or equal to a second preset threshold;

[0064] The determination module is used to determine the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired, and the timing repair strategy includes: a first strategy and a second strategy, the first strategy is used to instruct to insert a delay unit into the specified area corresponding to each unit in the path to be repaired to perform path repair; the second strategy is used to instruct to perform step-by-step repair on each unit in the path to be repaired according to the set constraint conditions, and insert a delay unit into the specified area corresponding to each unit in the path to be repaired to perform path repair;

[0065] The processing module is used to repair the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired.

[0066] Optionally, the determination module is specifically used to determine the setup time margin of the path to be repaired according to the setup time margin information of the path end point of the path to be repaired under each process angle;

[0067] If the establishment time margin is less than the first preset threshold, determining that the repair type of the path to be repaired is the first type;

[0068] If the establishment time margin is greater than or equal to the second preset threshold, it is determined that the repair type of the path to be repaired is the second type.

[0069] Optionally, the determining module is specifically configured to determine that the timing repair strategy corresponding to the path to be repaired is the first strategy if the repair type of the path to be repaired is the first type;

[0070] If the repair type of the path to be repaired is the second type, it is determined that the timing repair strategy corresponding to the path to be repaired is the second strategy.

[0071] Optionally, the processing module is specifically configured to execute the following loop steps if the timing repair strategy corresponding to the path to be repaired is the first strategy:

[0072] A1. Establish a first sequence of units to be processed according to the establishment time margin of each unit in the path to be repaired, and use the first unit to be processed in the first sequence of units to be processed as the initial current unit to be processed;

[0073] B1. Determine whether to perform setup time timing repair on a target path according to the setup time margin of the current unit to be processed, wherein the current unit to be processed is located in the target path, and the setup time margin of the current unit to be processed is output through the target path;

[0074] C1. If yes, then repair the target path to establish the time sequence and re-execute step A1;

[0075] D1, if not, determining the insertion position and delay parameter of the target delay unit to be inserted according to the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired, and inserting the target delay unit into the path to be repaired according to the insertion position and the delay parameter;

[0076] E1. Determine the current total delay time of the path to be repaired according to the delay parameter of the target delay unit and the newly added line delay related to the target delay unit in the path to be repaired, determine the new current hold timing violation value of the path to be repaired according to the current total delay time and the current hold timing violation value, and determine the new setup time margin of the current unit to be processed according to the current total delay time and the setup time margin of the current unit to be processed;

[0077] F1, if the new setup time margin of the current unit to be processed is less than the new current hold timing violation value, a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as a new current unit to be processed, and step B1 is executed again;

[0078] G1, if the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is less than the new setup time margin, then a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as the new current unit to be processed, and step B1 is re-executed, or step D1 is re-executed; wherein the current estimated total delay time is determined according to the new setup time margin of the current unit to be processed and the new current hold timing violation value of the path to be repaired;

[0079] H1. If the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is greater than or equal to the new setup time margin, then the loop ends.

[0080] Optionally, the processing module is specifically used to perform at least one of the following establishment time timing repair operations on the target path: crosstalk resolution, fan-out division, correction of signal jump time, delayed capture clock, and shortening of transmission time.

[0081] Optionally, the processing module is specifically used to determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius;

[0082] The target delay unit is inserted into the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area.

[0083] Optionally, the processing module is specifically configured to determine a first position that meets a first distance from the current unit to be processed and a first delay parameter that is equal to the current hold timing violation value in the delay unit placement area if the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area meets a condition, and insert a first target delay unit having the first delay parameter in the first position;

[0084] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area does not meet the condition, then determine a second position in the delay unit placement area that meets a second distance from the current unit to be processed, and determine a third position according to the second position and the position of the current unit to be processed, and insert a second target delay unit with a first preset delay parameter in the second position and insert a third target delay unit with a second preset delay parameter in the second position; the second preset delay parameter is a preset multiple of the first preset delay parameter;

[0085] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area meets the condition, then determine a second delay parameter equal to the setup time margin of the current unit to be processed, and insert a fourth target delay unit with the second delay parameter at the first position;

[0086] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area does not meet the conditions, a fifth target delay unit with the first preset delay parameter is inserted into the second position; the target delay unit is one or more of the first target delay unit, the second target delay unit, the third target delay unit, the fourth target delay unit and the fifth target delay unit.

[0087] Optionally, the processing module is specifically configured to determine a first difference between the current total delay time and the current hold timing violation value, and use the first difference as a new current hold timing violation value of the path to be repaired;

[0088] A second difference between the current total delay time and the setup time margin of the current unit to be processed is determined, and the second difference is determined as a new setup time margin of the current unit to be processed.

[0089] Optionally, the processing module is specifically configured to determine initial current congestion constraint information and initial current signal transition time constraint information if the timing repair strategy corresponding to the path to be repaired is the second strategy;

[0090] Determine parameter information of each unit in the path to be repaired, wherein the parameter information includes: setup time margin, congestion degree, and signal transition time;

[0091] A2. Establish a second sequence of units to be processed according to the establishment time margin of each unit, and use the first unit to be processed in the second sequence of units to be processed as the initial current unit to be processed;

[0092] B2. Determine whether to insert a delay unit into the current unit to be processed according to the parameter information of the current unit to be processed, the current congestion constraint information and the current signal jump time constraint information;

[0093] C2, if yes, insert a delay unit into the current unit to be processed, update the parameter information of the current unit to be processed, and execute step E2;

[0094] D2. If not, update the current congestion constraint information and the current signal transition time constraint information, and re-execute step A2;

[0095] E2. Determine whether to end the loop based on the current timing violation information of the path to be repaired and the updated parameter information of the current unit to be processed. If so, end the loop; otherwise, take a unit to be processed in the second unit to be processed sequence that is located after the current unit to be processed as a new current unit to be processed, and re-execute step B2.

[0096] Optionally, the processing module is specifically used to determine to insert a delay unit for the current unit to be processed if the congestion degree of the current unit to be processed meets the current congestion constraint information and the signal jump time of the current unit to be processed meets the current signal jump time constraint information.

[0097] Optionally, the processing module is specifically used to determine the number of target delay units currently allowed to be inserted and the total delay of the target delay units allowed to be inserted according to the pre-estimated congestion margin and the pre-estimated signal transition time margin;

[0098] The insertion position and delay parameter of each target delay unit are determined according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, and the target delay unit is inserted into the path to be repaired according to the insertion position and delay parameter of each target delay unit.

[0099] Optionally, the processing module is specifically used to determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius;

[0100] The target delay unit is inserted into the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the idle position information in the delay unit placement area.

[0101] Optionally, the processing module is specifically configured to insert at least one target delay unit in the delay unit placement area according to the number of target delay units allowed to be inserted and the total delay of target delay units allowed to be inserted, if the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is greater than 0, and the free positions in the delay unit placement area meet the conditions;

[0102] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is greater than 0, and the idle position in the delay unit placement area does not meet the condition, a fourth position that meets the third distance from the current unit to be processed is determined in the delay unit placement area, and a fifth position is determined according to the fourth position and the position of the current unit to be processed, and a sixth target delay unit with a first preset delay parameter is inserted in the fourth position, and a seventh target delay unit with a second preset delay parameter is inserted in the fifth position;

[0103] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and the free position in the delay unit placement area meets the condition, then determine the delay parameter of the target delay unit to be inserted according to the setup time margin of the current unit to be processed, and insert at least one target delay unit with the delay parameter in the delay unit placement area;

[0104] If the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is less than 0, and the idle positions in the delay unit placement area do not meet the conditions, an eighth target delay unit with the first preset delay parameter is inserted at the fourth position.

[0105] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to implement a method for repairing timing violations in a chip as provided in the first aspect.

[0106] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for repairing timing violations in a chip as provided in the first aspect is executed.

[0107] The beneficial effects of this application are:

[0108] The present application provides a method, device, equipment and storage medium for repairing timing violations in a chip, including: determining the repair type of each path to be repaired according to the setup time margin of each path to be repaired; determining the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired; and repairing the timing violations of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired. The method can divide the repair type of the path to be repaired into two categories according to the setup time margin of the path to be repaired. For the category with a smaller setup time margin, without setting any constraints, a delay unit is inserted in a specified area of ​​a unit in the path to be repaired, so as to repair the path to be repaired by the delay generated by the insertion of the delay unit, thereby ensuring sufficient space and winding resources; for the category with sufficient setup time margin, based on the set constraints and the gradual relaxation of the constraints, the path to be repaired is repaired round by round, and in each round of repair, a delay unit is also inserted in a specified area of ​​a unit in the path to be repaired, so as to repair the path to be repaired by the delay generated by the insertion of the delay unit. The method can maximize the use of the setup time margin of the cells in the path, and can reduce the setup time timing violation caused by repairing the hold timing violation while improving the hold timing violation. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0110] Figure 1 A flowchart of a method for repairing a timing violation in a chip provided in an embodiment of the present application;

[0111] Figure 2 A flowchart of another method for repairing timing violation in a chip provided in an embodiment of the present application;

[0112] Figure 3 A flowchart of another method for repairing a timing violation in a chip provided in an embodiment of the present application;

[0113] Figure 4 A flowchart of another method for repairing timing violation in a chip provided in an embodiment of the present application;

[0114] Figure 5 A flowchart of another method for repairing a timing violation in a chip provided in an embodiment of the present application;

[0115] Figure 6 A flowchart of another method for repairing timing violation in a chip provided in an embodiment of the present application;

[0116] Figure 7 A flowchart of another method for repairing a timing violation in a chip provided in an embodiment of the present application;

[0117] Figure 8 A flowchart of another method for repairing timing violation in a chip provided in an embodiment of the present application;

[0118] Fig. 9 A schematic diagram of a device for repairing timing violations in a chip provided by an embodiment of the present application;

[0119] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0120] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0121] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0122] With the development of integrated circuits, the chip scale is getting larger and larger. For high-frequency and high-performance chips, the timing requirements are very strict. In physical design, designers pay more attention to the setup timing during the Place & Route process, which makes it difficult to converge the hold timing violations in the later stage. Therefore, a lot of time is needed to repair the hold violations in the later stage, and the setup timing may be destroyed again in the process.

[0123] Currently, the main method to repair hold timing is to add delay cells before cells with sufficient setup margins, change the number of winding layers, increase the winding length, etc. However, for high-frequency chips, it is difficult to maximize the use of setup margins by using this method for all hold violations, and setup timing may be deteriorated due to slight changes in winding or movement of cell positions.

[0124] To address this problem, this solution provides a method for repairing hold timing violations in a chip. The hold violations are mainly divided into two categories through static timing analysis. The category with smaller setup margin is repaired first without setting any constraints to ensure sufficient space and winding resources; the category with sufficient setup margin is repaired by adding congestion (congestion) and transition (signal jump time) constraints to avoid DRV violations (Design Rule Violations) or mutual setup violations caused by delay units inserted to repair hold violations. If the path (the transmission path of the signal from the source to the destination in the circuit) that causes hold violations due to congestion or transition constraints has setup margin but is not repaired, these points will be processed separately after this round of hold repair, that is, the constraints are gradually relaxed until there is sufficient margin to repair the hold. This method can effectively improve the efficiency of hold repair and reduce setup timing violations caused by hold repair.

[0125] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0126] Figure 1 A flowchart of a method for repairing a timing violation in a chip provided in an embodiment of the present application is provided; the execution subject of the method may be a computer device, such as Figure 1 As shown, the method may include:

[0127] S101: Determine the repair type of each path to be repaired according to the establishment time margin of each path to be repaired.

[0128] The repair type includes: a first type and a second type, the first type is used to indicate that the establishment time margin of the path to be repaired is less than a first preset threshold; the second type is used to indicate that the establishment time margin of the path to be repaired is greater than or equal to a second preset threshold.

[0129] In this embodiment, the path to be repaired may refer to a path with a hold time violation (hereinafter collectively referred to as a hold timing violation), where the hold time refers to the minimum time interval during which the trigger input signal must remain stable after the clock valid edge arrives. If the input signal changes during this period, a hold timing violation occurs.

[0130] Optionally, the setup time margin (hereinafter referred to as the setup margin) of the path to be repaired can be calculated; the setup margin refers to the amount of time remaining when the data demand time (i.e., the time the data signal needs to be stable before the clock edge) is greater than the data arrival time (i.e., the time the data signal is actually stable before the clock edge). This difference is the setup time margin.

[0131] According to the setup margin of the path to be repaired, the repair type of the path to be repaired can be determined. In this embodiment, the repair type can be divided into two categories. When the setup margin of the path to be repaired is less than a first preset threshold, the repair type of the path to be repaired can be determined to be the first type; when the setup margin of the path to be repaired is greater than or equal to a second preset threshold, the repair type of the path to be repaired can be determined to be the second type.

[0132] When the setup margin of the path to be repaired is less than the first preset threshold, it can be indicated that the setup margin of the path to be repaired is small; and when the setup margin of the path to be repaired is greater than or equal to the second preset threshold, it can be indicated that the setup margin of the path to be repaired is sufficient.

[0133] S102: Determine a timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired.

[0134] The timing repair strategy includes: a first strategy and a second strategy. The first strategy is used to instruct to insert a delay unit into a specified area corresponding to each unit in the path to be repaired to perform path repair; the second strategy is used to instruct to perform step-by-step repair on each unit in the path to be repaired according to the set constraints, and to insert a delay unit into the specified area corresponding to each unit in the path to be repaired to perform path repair.

[0135] Optionally, the timing repair strategy of the path to be repaired can be determined according to the repair type of the path to be repaired. In the present embodiment, when the repair type is the first type, the corresponding timing repair strategy is the first strategy. Under the first strategy, the delay unit can be inserted in the specified area of ​​the unit according to the position of the unit in the path to be repaired, so as to repair the path to be repaired by the delay generated after the delay unit is inserted. When the repair type is the second type, the corresponding timing repair strategy is the second strategy. Under the second strategy, the path to be repaired can be distributedly repaired according to the set constraints, and multiple rounds of repairs can be performed by gradually relaxing the constraints to reduce the setup timing violation caused by the repair of the hold timing violation, wherein, in each round of repair process, the delay unit can also be inserted in the specified area of ​​the unit according to the position of the unit in the path to be repaired, so as to repair the path to be repaired by the delay generated after the delay unit is inserted.

[0136] S103 . Repair the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired.

[0137] Optionally, based on the timing repair strategy of the path to be repaired determined in the above manner, the hold timing violation of the path to be repaired may be repaired according to the repair method indicated by the timing repair strategy.

[0138] In summary, the method for repairing timing violations in a chip provided by the present embodiment includes: determining the repair type of each path to be repaired according to the setup time margin of each path to be repaired; determining the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired; and repairing the timing violations of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired. The present method can divide the repair types of the paths to be repaired into two categories according to the setup time margin of the paths to be repaired. For the category with a smaller setup time margin, without setting any constraints, a delay unit is inserted in a specified area of ​​a unit in the path to be repaired, so as to repair the path to be repaired by the delay generated by the insertion of the delay unit, thereby ensuring sufficient space and winding resources; for the category with sufficient setup time margin, based on the set constraints and the gradual relaxation of the constraints, the paths to be repaired are repaired in rounds of distributed repairs. In each round of repairs, a delay unit is also inserted in a specified area of ​​a unit in the path to be repaired, so as to repair the path to be repaired by the delay generated by the insertion of the delay unit. The method can maximize the use of the setup time margin of the cells in the path, and can reduce the setup time timing violation caused by repairing the hold timing violation while improving the hold timing violation.

[0139] Figure 2 A flowchart of another method for repairing a timing violation in a chip provided in an embodiment of the present application; Optionally, in step S101, determining the repair type of each path to be repaired according to the setup time margin of each path to be repaired may include:

[0140] S201 . Determine a setup time margin of a path to be repaired according to setup time margin information of a path end point of the path to be repaired under various process angles.

[0141] Optionally, static timing analysis can be used to count the endpoint points of all hold timing violation paths, where the endpoint point refers to the end point of the timing path, specifically the register or output port where the data signal reaches at the end of the time period in which the data signal needs to remain stable after the clock edge.

[0142] Calculate the setup margins of all endpoints of the path to be repaired in each process corner. Each endpoint has a corresponding setup margin in each process corner, and the setup margins in each process corner may be different. These data are usually obtained through timing analysis tools (such as the timing analysis module in EDA software).

[0143] Optionally, for a process corner, the minimum value of the setup margin among all endpoints may be taken as the setup margin of the path under the process corner; after obtaining the path setup margin under each process corner, these results need to be considered comprehensively. Usually, the setup margin under the slowest process corner (SS) is the most critical, because the circuit performance under this process corner is the worst and is more likely to have timing problems. Therefore, the setup margin under the slowest process corner can be used as the setup margin of the path to be repaired.

[0144] Alternatively, the setup margins of each endpoint at each process angle can be comprehensively considered, and the smaller value of the setup margin can be taken as the setup margin of the path to be repaired.

[0145] S202: If the establishment time margin is less than a first preset threshold, determine that the repair type of the path to be repaired is a first type.

[0146] In some embodiments, when the setup margin is less than a first preset threshold, it can be considered that the setup margin is small, and then it can be determined that the repair type of the path to be repaired is the first type.

[0147] S203: If the establishment time margin is greater than or equal to a second preset threshold, determine that the repair type of the path to be repaired is the second type.

[0148] When the setup margin is greater than or equal to the second preset threshold, it can be considered that the setup margin is sufficient, and then it can be determined that the repair type of the path to be repaired is the second type.

[0149] Optionally, in step S102, determining the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired may include: if the repair type of the path to be repaired is the first type, determining the timing repair strategy corresponding to the path to be repaired is the first strategy; if the repair type of the path to be repaired is the second type, determining the timing repair strategy corresponding to the path to be repaired is the second strategy.

[0150] When the repair type of the path to be repaired is the first type, the repair method indicated by the first strategy can be used to repair the hold timing violation; and when the repair type of the path to be repaired is the second type, the repair method indicated by the second strategy can be used to repair the hold timing violation.

[0151] First, the repair logic of the first strategy is described in detail.

[0152] Figure 3 A flowchart of another method for repairing a timing violation in a chip provided in an embodiment of the present application; optionally, in step S103, repairing the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired may include:

[0153] If the timing repair strategy corresponding to the path to be repaired is the first strategy, the following loop steps are executed:

[0154] S301 : Establish a first sequence of units to be processed according to the establishment time margin of each unit in the path to be repaired, and use the first unit to be processed in the first sequence of units to be processed as an initial current unit to be processed.

[0155] Generally, a path is composed of units and connections between units. A path may include multiple units, such as logic units, registers, buffers, inverters, etc.

[0156] Optionally, the setup margin of each unit in the path to be repaired may be calculated, and the units may be sorted in order according to the setup margin of each unit to obtain a first sequence of units to be processed. In this embodiment, the units are sorted from large to small according to the setup margin.

[0157] Optionally, the unit with the largest current setup margin in the first sequence of units to be processed may be used as the initial current unit to be processed.

[0158] In the case of sorting the units in descending order based on the setup margin, the first unit to be processed in the first sequence of units to be processed may be used as the initial current unit to be processed.

[0159] S302: Determine whether to perform setup time timing repair on the target path according to the setup time margin of the current unit to be processed.

[0160] The current unit to be processed is located in the target path, and the setup time margin of the current unit to be processed is output through the target path.

[0161] In some embodiments, if the setup margin of the current unit to be processed is less than 0, it is determined to perform setup timing repair on the target path; if the setup margin of the current unit to be processed is greater than or equal to 0, it is determined not to perform setup timing repair on the target path. In this case, step S303 is skipped and step S304 is directly executed.

[0162] It should be noted that the target path refers to the path of the setup time margin reported by the current unit to be processed. The target path does not refer to the path to be repaired. Exemplarily: the units in the hold violation path are unit A - unit B - unit C - unit D - unit E - unit F. For each unit to be processed, the path to obtain its setup time margin is not consistent with the hold violation path; for example: the setup time margin of unit C is 20ps, which is the setup time margin value reported in path 1 (unit A1 - unit B2 - unit C - unit D1 - unit E4 - unit F1). Then, when the unit to be processed is unit C in the path to be repaired, the setup time of unit C is repaired in path 1.

[0163] S303: If yes, then repair the target path to establish the time sequence, and re-execute step S301.

[0164] In some embodiments, after the setup timing repair of the target path of the current unit to be processed is completed, step S301 may be re-executed, that is, the current unit to be processed is re-placed into the first sequence of units to be processed for re-sequencing.

[0165] S304, if not, determining the insertion position and delay parameters of the target delay unit to be inserted according to the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired, and inserting the target delay unit in the path to be repaired according to the insertion position and delay parameters.

[0166] If it is determined that setup timing repair will not be performed on the target path corresponding to the current unit to be processed, classification processing can be performed based on the difference between the setup margin of the current unit to be processed and the current hold violation value of the path to be repaired. In different classification situations, the insertion position and delay parameters of the target delay unit to be inserted are determined, and the target delay unit is inserted according to the insertion position and delay parameters.

[0167] S305. Determine the current total delay time of the path to be repaired based on the delay parameters of the target delay unit and the newly added line delay related to the target delay unit in the path to be repaired, and determine the new current hold timing violation value of the path to be repaired based on the current total delay time and the current hold timing violation value, and determine the new setup time margin of the current unit to be processed based on the current total delay time and the setup time margin of the current unit to be processed.

[0168] Optionally, after the target delay unit is inserted, the current total delay time of the path to be repaired may be calculated according to the delay parameter of the target delay unit and the newly added line delay caused by the inserted target delay unit.

[0169] Among them, the delay parameter of the target delay unit is used to indicate the delay size of the target delay unit. The newly added line delay can refer to the line delay of the newly added connection between the target delay unit and the original unit in the path to be repaired after the target delay unit is inserted. For example: the original unit connection in the path to be repaired is as follows: A unit - line 1 - B unit; after inserting the target delay unit, it becomes: A unit - line 1 - delay unit a - line 2 - B unit; the delay parameter of the target delay unit is the unit delay of "delay unit a", and the newly added line delay is the line delay of the newly added "line 2".

[0170] Optionally, based on the current total delay time and the current hold timing violation value, the current hold timing violation value can be updated to obtain a new current hold timing violation value; and based on the current total delay time and the setup margin of the current unit to be processed, the setup margin of the current unit to be processed can be updated to obtain a new setup margin of the current unit to be processed.

[0171] S306: If the new setup time margin of the current unit to be processed is less than the new current hold timing violation value, a unit to be processed in the first sequence of units to be processed that is located after the current unit to be processed is used as a new current unit to be processed, and step S302 is executed again.

[0172] In some embodiments, if the new setup margin of the current unit to be processed is less than the new current hold timing violation value, return to step S301, take a unit to be processed in the first sequence of units to be processed that is located after the current unit to be processed as the new current unit to be processed, and continue to execute from step S302 for the new current unit to be processed.

[0173] Among them, when each unit in the first sequence of units to be processed is sorted from large to small according to the setup margin, a unit to be processed in the first sequence of units to be processed that is located after the current unit to be processed is taken as the new current unit to be processed, that is, the second unit to be processed in the first sequence of units to be processed is taken as the new current unit to be processed, because the second unit to be processed is currently the unit to be processed with the largest setup margin in the first sequence of units to be processed.

[0174] S307. If the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is less than the new setup time margin, then a unit to be processed in the first sequence of units to be processed that is located after the current unit to be processed is used as the new current unit to be processed, and step S302 is re-executed, or step S304 is re-executed.

[0175] The current estimated total delay time is determined according to the new setup time margin of the current unit to be processed and the new current hold timing violation value of the path to be repaired.

[0176] Optionally, the current estimated total delay can be estimated by looking up a table based on the new setup time margin of the current unit to be processed and the new current hold timing violation value of the path to be repaired. Timing analysis data under different circuit configurations can be collected in advance through simulation, experiment or experience, including setup time margin, hold timing violation value and corresponding total delay, and a query table or database can be constructed. These tables or databases contain the corresponding relationship between setup time margin, hold timing violation value and total delay under different conditions.

[0177] In other embodiments, if the new setup margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time is less than the new setup margin, there are two processing methods. The first method is to return to step S301, and use a unit to be processed after the current unit to be processed in the first sequence of units to be processed as the new current unit to be processed, and continue to execute from step S302 for the new current unit to be processed. The second method is to restart from step S304, that is, for the current unit to be processed, the operation of inserting the delay unit can be continued, and the specific method of inserting the delay unit can be executed according to step S304.

[0178] S308: If the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is greater than or equal to the new setup time margin, then the loop ends.

[0179] When the new setup margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time is greater than or equal to the new setup margin, the loop can be ended, and under the first strategy, the hold timing repair of the path to be repaired is completed.

[0180] Optionally, in step S303, performing establishment time timing repair on the target path may include: performing at least one of the following establishment time timing repair operations on the target path: crosstalk resolution, fan-out division, correction of signal transition time, delay capture clock, and shortening of launch time.

[0181] It is worth mentioning that the above-mentioned repair operations are all routine operations, and their detailed processing procedures will not be repeated here.

[0182] Figure 4 A flow chart of another method for repairing a hold timing violation in a chip provided by an embodiment of the present application; optionally, in step S304, according to the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired, determining the insertion position and delay parameters of the target delay unit to be inserted, and inserting the target delay unit in the path to be repaired according to the insertion position and the delay parameters, may include:

[0183] S401 , determining a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius.

[0184] Optionally, the delay unit placement area corresponding to the current unit to be processed may be determined according to the position of the current unit to be processed and a preset radius.

[0185] With the current unit to be processed as the center and the preset radius R as 10 μm, the area of ​​0-10 μm with the current unit to be processed as the delay unit placement area corresponding to the current unit to be processed can be used. In other words, with the current unit to be processed as the center and the preset radius, a circle is drawn, and the resulting circular area is the delay unit placement area corresponding to the current unit to be processed.

[0186] S402 , inserting a target delay unit into the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area.

[0187] Optionally, the position and delay parameters of the target delay unit to be inserted can be determined based on the difference between the setup margin of the current unit to be processed and the current hold violation value of the path to be repaired, combined with the free position information in the delay unit placement area, and the target delay unit can be inserted into the path to be repaired.

[0188] Optionally, in step S402, inserting a target delay unit in the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area may include:

[0189] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area meets the conditions, a first position that meets the first distance from the current unit to be processed is determined in the delay unit placement area, and a first delay parameter that is equal to the current hold timing violation value is determined, and a first target delay unit with the first delay parameter is inserted at the first position.

[0190] In the first case, if the difference between the setup margin of the current unit to be processed and the current hold violation value is greater than 0, and there is sufficient space in the delay unit placement area, the first target delay unit is preferentially placed in an area away from the current unit to be processed, and the delay parameter of the first target delay unit is equal to the current hold violation value.

[0191] The sufficient space in the delay unit placement area means that there are enough physical spaces in the delay unit placement area to place the delay units.

[0192] Taking the 0-10μm area centered on the current unit to be processed as the delay unit placement area corresponding to the current unit to be processed as an example, the area away from the current unit to be processed refers to the area within the delay unit placement area that is 10μm away from the current unit to be processed, that is, the boundary of the circle. Therefore, the first position that meets the first distance from the current unit to be processed can refer to the position that is 10μm away from the current unit to be processed. Of course, in practical applications, it is not limited to 10μm, and there can be a certain degree of fluctuation, that is, the first distance can also be between 9μm-10μm. As long as it meets the maximum possible distance from the current unit to be processed in the delay unit placement area.

[0193] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area does not meet the condition, a second position that meets the second distance from the current unit to be processed is determined in the delay unit placement area, and a third position is determined based on the second position and the position of the current unit to be processed, and a second target delay unit with a first preset delay parameter is inserted in the second position and a third target delay unit with a second preset delay parameter is inserted in the second position; the second preset delay parameter is a preset multiple of the first preset delay parameter.

[0194] In the second case, if the difference between the setup margin of the current unit to be processed and the current hold violation value is greater than 0, and there is insufficient space in the delay unit placement area, it is necessary to insert a second target delay unit with minimum delay near the current unit to be processed, and then insert a third delay unit with twice or four times the minimum delay between the inserted second target delay unit and the current unit to be processed in a sufficient area farther away from the current unit to be processed.

[0195] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area meets the conditions, a second delay parameter equal to the setup time margin of the current unit to be processed is determined, and a fourth target delay unit with the second delay parameter is inserted at the first position.

[0196] In the third case, if the difference between the setup margin of the current unit to be processed and the current hold violation value is less than 0, and there is sufficient space in the delay unit placement area, a fourth target delay unit with the same value as the setup margin of the current unit to be processed is inserted at the first position away from the current unit to be processed as determined above.

[0197] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area does not meet the conditions, then a fifth target delay unit with a first preset delay parameter is inserted at the second position; the target delay unit is one or more of the first target delay unit, the second target delay unit, the third target delay unit, the fourth target delay unit and the fifth target delay unit.

[0198] In the fourth case, if the difference between the setup margin of the current unit to be processed and the current hold violation value is less than 0, and there is insufficient space in the delay unit placement area, a fifth target delay unit with minimum delay is inserted near the current unit to be processed determined above, i.e., at the second position.

[0199] It is worth noting that the “first”, “second”, “third”, “fourth” and “fifth” in the above-mentioned first target delay unit, second target delay unit, third target delay unit, fourth target delay unit and fifth target delay unit are only for distinguishing the inserted delay units as different delay units. Not every delay unit needs to be inserted. Depending on the situation, the delay unit finally inserted is only one or more of the first target delay unit, the second target delay unit, the third target delay unit, the fourth target delay unit and the fifth target delay unit.

[0200] Figure 5 A flow chart of another method for repairing a hold timing violation in a chip provided in an embodiment of the present application; optionally, in step S305, according to the current total delay time and the current hold timing violation value, determining a new current hold timing violation value of the path to be repaired, and according to the current total delay time and the setup time margin of the current unit to be processed, determining a new setup time margin of the current unit to be processed, may include:

[0201] S501: Determine a first difference between a current total delay time and a current hold timing violation value, and use the first difference as a new current hold timing violation value of the path to be repaired.

[0202] In some embodiments, in the above Figure 3 In the loop logic shown, for each current processing unit, after the target delay unit is inserted, the current total delay time can be updated, and based on the update of the current total delay time, the current hold timing violation value and the setup margin of the current processing unit can be updated.

[0203] Optionally, for any round of updates, the difference between the current total delay time and the current hold timing violation value may be used as a new current hold timing violation value of the path to be repaired.

[0204] S502: Determine a second difference between the current total delay time and the setup time margin of the current unit to be processed, and determine the second difference as a new setup time margin of the current unit to be processed.

[0205] The difference between the current total delay time and the setup margin of the current unit to be processed is used as the new setup margin of the current unit to be processed.

[0206] Next, the repair logic of the second strategy is described in detail.

[0207] Figure 6A flow chart of another method for repairing a timing violation in a chip provided in an embodiment of the present application; optionally, in step S103, repairing the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired may include:

[0208] If the timing repair strategy corresponding to the path to be repaired is the second strategy, the initial current congestion constraint information and the initial current signal transition time constraint information are determined.

[0209] For the second strategy, the initial current congestion constraint information and the initial current signal jump time constraint information can be set first to ensure that the delay unit inserted to repair the hold violation will not cause congestion and signal jump time violation when the setup is sufficient, and the delay unit that repairs the hold timing violation can be placed at a farther position from the unit, thereby releasing space resources.

[0210] Determine parameter information of each unit in the path to be repaired, the parameter information including: setup time margin, congestion degree, and signal transition time.

[0211] Next, the setup margin, congestion, and signal transition time of each unit in the path to be repaired are calculated respectively as the main reference parameters for the subsequent repair of hold timing violations.

[0212] S601 . Establish a second sequence of units to be processed according to the establishment time margin of each unit, and use the first unit to be processed in the second sequence of units to be processed as an initial current unit to be processed.

[0213] Similarly, referring to step S301, the units can be sorted according to the setup margin of each unit in the path to be repaired to generate a second sequence of units to be processed. Here, the units are also sorted from large to small based on the setup margin. Thus, the first unit to be processed in the second sequence of units to be processed can be used as the initial current unit to be processed.

[0214] The same process as step S302 and step S303, if the setup margin of the current unit to be processed is less than 0, the setup timing is repaired for the target path reported by the current unit to be processed, and step S601 is re-executed. The repair method can be understood by referring to the above embodiment. If the setup margin of the current unit to be processed is greater than or equal to 0, step S602 is directly executed.

[0215] S602: Determine whether to insert a delay unit into the current unit to be processed according to parameter information of the current unit to be processed, current congestion constraint information, and current signal transition time constraint information.

[0216] Optionally, whether to insert a delay unit into the current unit to be processed may be determined according to the congestion degree, signal transition time, current congestion constraint information, and current signal transition time constraint information of the current unit to be processed determined above.

[0217] S603: If yes, insert a delay unit into the current unit to be processed, update the parameter information of the current unit to be processed, and execute step S605.

[0218] If it is determined that a delay unit needs to be inserted into the current unit to be processed, the delay parameters and insertion position of the delay unit to be inserted are determined, and the delay unit is inserted. After the insertion is completed, the congestion degree and signal jump time of the current unit to be processed can also be updated, and step S605 is executed.

[0219] In addition, in the same manner as step S305, the current total delay time of the path to be repaired can be determined based on the delay parameters of the inserted delay unit and the newly added line delay in the path to be repaired, and based on the current total delay time, the current hold timing violation value of the path to be repaired is updated to obtain a new current hold timing violation value; and based on the current total delay time, the setup margin of the current unit to be processed is updated to obtain a new setup margin of the current unit to be processed.

[0220] S604: If not, update the current congestion constraint information and the current signal transition time constraint information, and re-execute step S601.

[0221] If it is determined that there is no need to insert a delay unit into the current unit to be processed, the processing of the current unit to be processed will be suspended. After all units that need to insert a delay unit are processed, the current congestion constraint information and the current signal jump time constraint information are updated, that is, the congestion constraint information and the signal jump time constraint information are gradually relaxed, and the delay unit is inserted into the current unit to be processed again.

[0222] S605 , determining whether to end the loop according to the current timing violation information of the path to be repaired and the updated parameter information of the current unit to be processed; if so, end the loop.

[0223] S606. Otherwise, a unit to be processed that is located after the current unit to be processed in the second sequence of units to be processed is taken as a new current unit to be processed, and step S602 is executed again.

[0224] In some embodiments, the path to be repaired may be repaired continuously or the repair cycle may be terminated based on the same classification processing method as steps S306-S308 above, and the detailed process will not be described in detail here.

[0225] Optionally, in step S602, determining whether to insert a delay unit into the current unit to be processed is performed based on parameter information of the current unit to be processed, current congestion constraint information, and current signal jump time constraint information. This may include: if the congestion degree of the current unit to be processed satisfies the current congestion constraint information, and the signal jump time of the current unit to be processed satisfies the current signal jump time constraint information, then determining to insert a delay unit into the current unit to be processed.

[0226] In some embodiments, if it is determined that the congestion degree of the current unit to be processed is within the current congestion constraint information, and the signal jump time of the current unit to be processed is within the current signal jump time constraint information, it can be determined that the operation of inserting a delay unit needs to be performed immediately on the current unit to be processed.

[0227] Figure 7 A flowchart of another method for repairing timing violation in a chip provided in an embodiment of the present application; Optionally, in step S603, inserting a delay unit for the current unit to be processed may include:

[0228] S701 : Determine the number of target delay units currently allowed to be inserted and the total delay of the target delay units allowed to be inserted according to a pre-estimated congestion margin and a pre-estimated signal transition time margin.

[0229] Optionally, the congestion margin and the signal transition time margin can be estimated based on experience, and the number of target delay units that can be inserted and the total delay of the target delay units that can be inserted can be estimated when the congestion margin and the signal transition time margin are satisfied at the same time. That is, there can be multiple target delay units inserted, and the total delay refers to the total delay of the multiple inserted target delay units.

[0230] S702. Determine the insertion position and delay parameters of each target delay unit according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, and insert the target delay unit in the path to be repaired according to the insertion position and delay parameters of each target delay unit.

[0231] Optionally, based on the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the number of target delay units allowed to be inserted, the insertion position and delay parameters of each target delay unit to be inserted can be determined, and the target delay unit can be inserted.

[0232] Figure 8A flow chart of another method for repairing a hold timing violation in a chip provided by an embodiment of the present application; optionally, in step S702, according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, determining the insertion position and delay parameters of each target delay unit, and inserting the target delay unit in the path to be repaired according to the insertion position and delay parameters of each target delay unit, may include:

[0233] S801 . Determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius.

[0234] The implementation is the same as step S401 and will not be repeated here.

[0235] S802, inserting a target delay unit into the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area.

[0236] In some embodiments, classification processing can be performed based on the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value of the path to be repaired, combined with the free position information in the delay unit placement area, to determine the placement position and delay parameters of the target delay unit under different types of processing, and based on the number of target delay units allowed to be inserted, the insertion operation of the target delay unit is performed under various different types of processing.

[0237] Optionally, in step S802, inserting a target delay unit in the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area may include:

[0238] If the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is greater than 0, and the free positions in the delay unit placement area meet the conditions, then at least one target delay unit is inserted in the delay unit placement area according to the number of target delay units allowed to be inserted and the total delay of the target delay units allowed to be inserted.

[0239] In the first case, if the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is greater than 0, and there are sufficient free positions in the delay unit placement area, at least one target delay unit can be inserted in front of the current unit to be processed. The number of inserted target delay units is determined by the number of target delay units allowed to be inserted, and the total delay of the inserted target delay units is determined by the total delay of the target delay units allowed to be inserted. When there are multiple target delay units, each target delay unit can be placed within the specified interval, and each target delay unit is preferably placed together.

[0240] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is greater than 0, and the idle position in the delay unit placement area does not meet the condition, a fourth position that meets the third distance from the current unit to be processed is determined in the delay unit placement area, and a fifth position is determined based on the fourth position and the position of the current unit to be processed, and a sixth target delay unit with a first preset delay parameter is inserted at the fourth position and a seventh target delay unit with a second preset delay parameter is inserted at the fifth position.

[0241] In the second case, if the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is greater than 0, and there are insufficient free positions in the delay unit placement area, a sixth delay unit with minimum delay is inserted near the current unit to be processed, that is, at the fourth position; and a seventh target delay unit with twice or four times the minimum delay is inserted in an area with sufficient space farther away from the current unit to be processed, between the sixth target delay unit and the current unit to be processed, that is, at the fifth position.

[0242] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and the free position in the delay unit placement area meets the conditions, the delay parameters of the target delay unit to be inserted are determined according to the setup time margin of the current unit to be processed, and at least one target delay unit with the delay parameters is inserted in the delay unit placement area.

[0243] In the third case, if the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and there are sufficient free positions in the delay unit placement area, then at least one target delay unit with a value equal to the setup margin size of the current unit to be processed is inserted in front of the current unit to be processed.

[0244] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and the idle position in the delay unit placement area does not meet the conditions, an eighth target delay unit with the first preset delay parameter is inserted at the fourth position.

[0245] In the fourth case, if the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and there are insufficient free positions in the delay unit placement area, then an eighth delay unit with the minimum delay is inserted near the current unit to be processed, that is, at the fourth position determined above.

[0246] It is worth mentioning that when a hold timing violation occurs, it means that the data signal changes prematurely after the clock edge. By inserting a delay unit in the path to be repaired, the transmission delay of the data signal can be increased, so that it remains unchanged for a longer time after the clock edge.

[0247] In summary, the method for repairing timing violations in a chip provided by the present embodiment includes: determining the repair type of each path to be repaired according to the setup time margin of each path to be repaired; determining the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired; and repairing the timing violations of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired. The present method can divide the repair types of the paths to be repaired into two categories according to the setup time margin of the paths to be repaired. For the category with a smaller setup time margin, without setting any constraints, a delay unit is inserted in a specified area of ​​a unit in the path to be repaired, so as to repair the path to be repaired by the delay generated by the insertion of the delay unit, thereby ensuring sufficient space and winding resources; for the category with sufficient setup time margin, based on the set constraints and the gradual relaxation of the constraints, the paths to be repaired are repaired in rounds of distributed repairs. In each round of repairs, a delay unit is also inserted in a specified area of ​​a unit in the path to be repaired, so as to repair the path to be repaired by the delay generated by the insertion of the delay unit. The method can maximize the use of the setup time margin of the cells in the path, and can reduce the setup time timing violation caused by repairing the hold timing violation while improving the hold timing violation.

[0248] The following describes the apparatus, device, storage medium, etc. used to execute the method for repairing timing violations in the chip provided in this application. The specific implementation process and technical effects are described above and will not be repeated below.

[0249] Fig. 9 A schematic diagram of a device for repairing timing violations in a chip provided in an embodiment of the present application, wherein the functions implemented by the device for repairing timing violations in the chip correspond to the steps performed by the above method. The device can be understood as the above-mentioned computer device, or a server, or a processor of a server, or a component independent of the above-mentioned server or processor that implements the functions of the present application under the control of the server, such as Fig. 9 As shown, the device may include: a determination module 910 and a processing module 920;

[0250] The determination module 910 is used to determine the repair type of each path to be repaired according to the establishment time margin of each path to be repaired; the repair type includes: a first type and a second type, the first type is used to indicate that the establishment time margin of the path to be repaired is less than a first preset threshold; the second type is used to indicate that the establishment time margin of the path to be repaired is greater than or equal to a second preset threshold;

[0251] The determination module 910 is used to determine the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired, and the timing repair strategy includes: a first strategy and a second strategy, the first strategy is used to indicate that a delay unit is inserted into a designated area corresponding to each unit in the path to be repaired to repair the path; the second strategy is used to indicate that each unit in the path to be repaired is repaired step by step according to the set constraint conditions, and a delay unit is inserted into the designated area corresponding to each unit in the path to be repaired to repair the path;

[0252] The processing module 920 is used to repair the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired.

[0253] Optionally, the determination module 910 is specifically configured to determine the setup time margin of the path to be repaired according to setup time margin information of the path end point of the path to be repaired under each process angle;

[0254] If the establishment time margin is less than a first preset threshold, determining that the repair type of the path to be repaired is a first type;

[0255] If the establishment time margin is greater than or equal to the second preset threshold, it is determined that the repair type of the path to be repaired is the second type.

[0256] Optionally, the determination module 910 is specifically configured to determine that the timing repair strategy corresponding to the path to be repaired is the first strategy if the repair type of the path to be repaired is the first type;

[0257] If the repair type of the path to be repaired is the second type, it is determined that the timing repair strategy corresponding to the path to be repaired is the second strategy.

[0258] Optionally, the processing module 920 is specifically configured to execute the following loop steps if the timing repair strategy corresponding to the path to be repaired is the first strategy:

[0259] A1. Establish a first sequence of units to be processed according to the establishment time margin of each unit in the path to be repaired, and use the first unit to be processed in the first sequence of units to be processed as the initial current unit to be processed;

[0260] B1. Determine whether to perform setup time sequence repair on the target path according to the setup time margin of the current unit to be processed, wherein the current unit to be processed is located in the target path, and the setup time margin of the current unit to be processed is output through the target path;

[0261] C1. If yes, then repair the target path to establish the timing sequence and re-execute step A1;

[0262] D1. If not, determine the insertion position and delay parameters of the target delay unit to be inserted according to the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired, and insert the target delay unit in the path to be repaired according to the insertion position and delay parameters;

[0263] E1. Determine the current total delay time of the path to be repaired according to the delay parameter of the target delay unit and the newly added line delay related to the target delay unit in the path to be repaired, determine the new current hold timing violation value of the path to be repaired according to the current total delay time and the current hold timing violation value, and determine the new setup time margin of the current unit to be processed according to the current total delay time and the setup time margin of the current unit to be processed;

[0264] F1, if the new setup time margin of the current unit to be processed is less than the new current hold timing violation value, a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as a new current unit to be processed, and step B1 is executed again;

[0265] G1, if the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is less than the new setup time margin, then a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as the new current unit to be processed, and step B1 is re-executed, or step D1 is re-executed; wherein the current estimated total delay time is determined according to the new setup time margin of the current unit to be processed and the new current hold timing violation value of the path to be repaired;

[0266] H1. If the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is greater than or equal to the new setup time margin, then the loop ends.

[0267] Optionally, the processing module 920 is specifically configured to perform at least one of the following establishment time timing repair operations on the target path: crosstalk resolution, fan-out division, correction of signal transition time, delayed capture clock, and shortening of transmission time.

[0268] Optionally, the processing module 920 is specifically configured to determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius;

[0269] A target delay cell is inserted into the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the free position information in the delay cell placement area.

[0270] Optionally, the processing module 920 is specifically configured to determine a first position that meets a first distance from the current unit to be processed and a first delay parameter that is equal to the current hold timing violation value in the delay unit placement area if the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area meets the condition, and insert a first target delay unit with the first delay parameter in the first position;

[0271] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area does not meet the condition, then determine a second position in the delay unit placement area that meets the second distance from the current unit to be processed, and determine a third position according to the second position and the position of the current unit to be processed, and insert a second target delay unit with a first preset delay parameter at the second position and insert a third target delay unit with a second preset delay parameter at the second position; the second preset delay parameter is a preset multiple of the first preset delay parameter;

[0272] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area meets the condition, then determine a second delay parameter equal to the setup time margin of the current unit to be processed, and insert a fourth target delay unit with the second delay parameter at the first position;

[0273] If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area does not meet the conditions, then a fifth target delay unit with a first preset delay parameter is inserted at the second position; the target delay unit is one or more of the first target delay unit, the second target delay unit, the third target delay unit, the fourth target delay unit and the fifth target delay unit.

[0274] Optionally, the processing module 920 is specifically configured to determine a first difference between the current total delay time and the current hold timing violation value, and use the first difference as a new current hold timing violation value of the path to be repaired;

[0275] A second difference between the current total delay time and the setup time margin of the current unit to be processed is determined, and the second difference is determined as a new setup time margin of the current unit to be processed.

[0276] Optionally, the processing module 920 is specifically configured to determine initial current congestion constraint information and initial current signal transition time constraint information if the timing repair strategy corresponding to the path to be repaired is the second strategy;

[0277] Determine parameter information of each unit in the path to be repaired, the parameter information includes: setup time margin, congestion degree and signal transition time;

[0278] A2. Establish a second sequence of units to be processed according to the establishment time margin of each unit, and use the first unit to be processed in the second sequence of units to be processed as the initial current unit to be processed;

[0279] B2. Determine whether to insert a delay unit into the current unit to be processed according to the parameter information of the current unit to be processed, the current congestion constraint information and the current signal jump time constraint information;

[0280] C2, if yes, insert a delay unit into the current unit to be processed, update the parameter information of the current unit to be processed, and execute step E2;

[0281] D2. If not, update the current congestion constraint information and the current signal transition time constraint information, and re-execute step A2;

[0282] E2. Determine whether to end the loop based on the current timing violation information of the path to be repaired and the updated parameter information of the current unit to be processed. If so, end the loop. Otherwise, take a unit to be processed that is located after the current unit to be processed in the second unit to be processed sequence as the new current unit to be processed, and re-execute step B2.

[0283] Optionally, the processing module 920 is specifically configured to determine to insert a delay unit into the current unit to be processed if the congestion degree of the current unit to be processed satisfies the current congestion constraint information and the signal transition time of the current unit to be processed satisfies the current signal transition time constraint information.

[0284] Optionally, the processing module 920 is specifically configured to determine the number of target delay units currently allowed to be inserted and the total delay of the target delay units allowed to be inserted according to the pre-estimated congestion margin and the pre-estimated signal transition time margin;

[0285] The insertion position and delay parameter of each target delay unit are determined according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, and the target delay unit is inserted into the path to be repaired according to the insertion position and delay parameter of each target delay unit.

[0286] Optionally, the processing module 920 is specifically configured to determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius;

[0287] The target delay unit is inserted into the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area.

[0288] Optionally, the processing module 920 is specifically configured to insert at least one target delay unit in the delay unit placement area according to the number of target delay units allowed to be inserted and the total delay of the target delay units allowed to be inserted, if the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is greater than 0, and the free positions in the delay unit placement area meet the conditions;

[0289] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is greater than 0, and the idle position in the delay unit placement area does not meet the condition, a fourth position that meets the third distance from the current unit to be processed is determined in the delay unit placement area, and a fifth position is determined according to the fourth position and the position of the current unit to be processed, and a sixth target delay unit with a first preset delay parameter is inserted at the fourth position and a seventh target delay unit with a second preset delay parameter is inserted at the fifth position;

[0290] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and the free position in the delay unit placement area meets the condition, then according to the setup time margin of the current unit to be processed, the delay parameter of the target delay unit to be inserted is determined, and at least one target delay unit with the delay parameter is inserted in the delay unit placement area;

[0291] If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and the idle position in the delay unit placement area does not meet the conditions, an eighth target delay unit with the first preset delay parameter is inserted at the fourth position.

[0292] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0293] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital singnal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0294] The above modules can be connected or communicated with each other via a wired connection or a wireless connection. The wired connection may include a metal cable, an optical cable, a hybrid cable, etc., or any combination thereof. The wireless connection may include a connection in the form of a LAN, a WAN, Bluetooth, a ZigBee, or NFC, or any combination thereof. Two or more modules may be combined into a single module, and any one module may be divided into two or more units. Those skilled in the art will clearly understand that for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application.

[0295] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, which may be a computing device with data processing capabilities.

[0296] The device may include: a processor 801 and a storage medium 802 .

[0297] The storage medium 802 is used to store programs, and the processor 801 calls the programs stored in the storage medium 802 to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0298] Among them, the storage medium 802 stores program code, and when the program code is executed by the processor 801, the processor 801 executes various steps in the method of repairing timing violations in a chip according to various exemplary embodiments of the present application described in the above "Exemplary Method" section of this specification.

[0299] Processor 801 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware processor to be executed, or a combination of hardware and software modules in the processor can be executed.

[0300] Storage medium 802, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules. Storage medium may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type storage medium, random access storage medium (Random Access Memory, RAM), static random access storage medium (Static Random Access Memory, SRAM), programmable read-only storage medium (Programmable Read Only Memory, PROM), read-only storage medium (Read Only Memory, ROM), electrically erasable programmable read-only storage medium (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic storage medium, disk, optical disk, etc. Storage medium is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The storage medium 802 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0301] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute the above method embodiment when executed by a processor.

[0302] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0303] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0304] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0305] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only storage medium (English: Read-Only Memory, referred to as: ROM), random access storage medium (English: Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program code.

Claims

1. A method for repairing a timing violation in a chip, characterized in that: include: Determine the repair type of each path to be repaired according to the establishment time margin of each path to be repaired; The repair type includes: a first type and a second type, the first type is used to indicate that the establishment time margin of the path to be repaired is less than a first preset threshold; the second type is used to indicate that the establishment time margin of the path to be repaired is greater than or equal to a second preset threshold; Determine, according to the repair type of each path to be repaired, a timing repair strategy corresponding to each path to be repaired, wherein the timing repair strategy includes: a first strategy and a second strategy, wherein the first strategy is used to instruct to insert a delay unit into a designated area corresponding to each unit in the path to be repaired to perform path repair; and the second strategy is used to instruct to perform step-by-step repair on each unit in the path to be repaired according to set constraints, and to insert a delay unit into a designated area corresponding to each unit in the path to be repaired to perform path repair; According to the timing repair strategy corresponding to each path to be repaired, the hold timing violation of each path to be repaired is repaired.

2. The method according to claim 1, characterized in that The step of determining the repair type of each path to be repaired according to the establishment time margin of each path to be repaired includes: Determine the setup time margin of the path to be repaired according to setup time margin information of the path end point of the path to be repaired under each process angle; If the establishment time margin is less than the first preset threshold, determining that the repair type of the path to be repaired is the first type; If the establishment time margin is greater than or equal to the second preset threshold, it is determined that the repair type of the path to be repaired is the second type.

3. The method according to claim 1, characterized in that Determining the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired includes: If the repair type of the path to be repaired is the first type, determining that the timing repair strategy corresponding to the path to be repaired is the first strategy; If the repair type of the path to be repaired is the second type, it is determined that the timing repair strategy corresponding to the path to be repaired is the second strategy.

4. The method according to claim 1, characterized in that: The step of repairing the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired includes: If the timing repair strategy corresponding to the path to be repaired is the first strategy, the following loop steps are performed: A1. Establish a first sequence of units to be processed according to the establishment time margin of each unit in the path to be repaired, and use the first unit to be processed in the first sequence of units to be processed as the initial current unit to be processed; B1. Determine whether to perform setup time timing repair on a target path according to the setup time margin of the current unit to be processed, wherein the current unit to be processed is located in the target path, and the setup time margin of the current unit to be processed is output through the target path; C1. If yes, then repair the target path to establish the time sequence and re-execute step A1; D1, if not, determining the insertion position and delay parameter of the target delay unit to be inserted according to the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired, and inserting the target delay unit into the path to be repaired according to the insertion position and the delay parameter; E1. Determine the current total delay time of the path to be repaired according to the delay parameter of the target delay unit and the newly added line delay related to the target delay unit in the path to be repaired, determine the new current hold timing violation value of the path to be repaired according to the current total delay time and the current hold timing violation value, and determine the new setup time margin of the current unit to be processed according to the current total delay time and the setup time margin of the current unit to be processed; F1, if the new setup time margin of the current unit to be processed is less than the new current hold timing violation value, a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as a new current unit to be processed, and step B1 is executed again; G1, if the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is less than the new setup time margin, then a unit to be processed located after the current unit to be processed in the first sequence of units to be processed is used as the new current unit to be processed, and step B1 is re-executed, or step D1 is re-executed; wherein the current estimated total delay time is determined according to the new setup time margin of the current unit to be processed and the new current hold timing violation value of the path to be repaired; H1. If the new setup time margin of the current unit to be processed is greater than or equal to the new current hold timing violation value, and the current estimated total delay time of the path to be repaired is greater than or equal to the new setup time margin, then the loop ends.

5. The method according to claim 4, characterized in that The step of repairing the target path by establishing a time sequence includes: At least one of the following establishment time timing repair operations is performed on the target path: crosstalk resolution, fan-out division, correction of signal transition time, delayed capture clock, and shortening of transmission time.

6. The method according to claim 4, characterized in that The step of determining an insertion position and a delay parameter of a target delay unit to be inserted according to a setup time margin of a current unit to be processed and a current hold timing violation value of the path to be repaired, and inserting the target delay unit into the path to be repaired according to the insertion position and the delay parameter comprises: Determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius; The target delay unit is inserted into the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the free position information in the delay unit placement area.

7. The method according to claim 6, characterized in that The inserting the target delay unit into the path to be repaired according to the setup time margin of the current unit to be processed, the current hold timing violation value of the path to be repaired, and the idle position information in the delay unit placement area comprises: If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area meets the condition, then determine a first position that meets a first distance from the current unit to be processed and a first delay parameter that is equal to the current hold timing violation value in the delay unit placement area, and insert a first target delay unit having the first delay parameter at the first position; If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is greater than 0, and the idle position in the delay unit placement area does not meet the condition, then determine a second position in the delay unit placement area that meets a second distance from the current unit to be processed, and determine a third position according to the second position and the position of the current unit to be processed, and insert a second target delay unit with a first preset delay parameter in the second position and insert a third target delay unit with a second preset delay parameter in the second position; the second preset delay parameter is a preset multiple of the first preset delay parameter; If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area meets the condition, then determine a second delay parameter equal to the setup time margin of the current unit to be processed, and insert a fourth target delay unit with the second delay parameter at the first position; If the difference between the setup time margin of the current unit to be processed and the current hold timing violation value of the path to be repaired is less than 0, and the idle position in the delay unit placement area does not meet the conditions, a fifth target delay unit with the first preset delay parameter is inserted into the second position; the target delay unit is one or more of the first target delay unit, the second target delay unit, the third target delay unit, the fourth target delay unit and the fifth target delay unit.

8. The method according to claim 4, characterized in that The step of determining a new current hold timing violation value of the path to be repaired according to the current total delay time and the current hold timing violation value, and determining a new setup time margin of the current unit to be processed according to the current total delay time and the setup time margin of the current unit to be processed, comprises: Determine a first difference between the current total delay time and the current hold timing violation value, and use the first difference as a new current hold timing violation value of the path to be repaired; A second difference between the current total delay time and the setup time margin of the current unit to be processed is determined, and the second difference is determined as a new setup time margin of the current unit to be processed.

9. The method according to claim 1, characterized in that: The step of repairing the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired includes: If the timing repair strategy corresponding to the path to be repaired is the second strategy, determining initial current congestion constraint information and initial current signal transition time constraint information; Determine parameter information of each unit in the path to be repaired, wherein the parameter information includes: setup time margin, congestion degree, and signal transition time; A2. Establish a second sequence of units to be processed according to the establishment time margin of each unit, and use the first unit to be processed in the second sequence of units to be processed as the initial current unit to be processed; B2. Determine whether to insert a delay unit into the current unit to be processed according to the parameter information of the current unit to be processed, the current congestion constraint information and the current signal jump time constraint information; C2, if yes, insert a delay unit into the current unit to be processed, update the parameter information of the current unit to be processed, and execute step E2; D2. If not, update the current congestion constraint information and the current signal transition time constraint information, and re-execute step A2; E2. Determine whether to end the loop based on the current timing violation information of the path to be repaired and the updated parameter information of the current unit to be processed. If so, end the loop; otherwise, take a unit to be processed in the second unit to be processed sequence that is located after the current unit to be processed as a new current unit to be processed, and re-execute step B2.

10. The method according to claim 9, characterized in that The step of determining whether to insert a delay unit into the current unit to be processed according to the parameter information of the current unit to be processed, the current congestion constraint information, and the current signal transition time constraint information includes: If the congestion degree of the current unit to be processed satisfies the current congestion constraint information, and the signal transition time of the current unit to be processed satisfies the current signal transition time constraint information, it is determined to insert a delay unit into the current unit to be processed.

11. The method according to claim 9, characterized in that The inserting of a delay unit into the current unit to be processed comprises: Determine the number of target delay units currently allowed to be inserted and the total delay of the target delay units allowed to be inserted according to the pre-estimated congestion margin and the pre-estimated signal transition time margin; The insertion position and delay parameter of each target delay unit are determined according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, and the target delay unit is inserted into the path to be repaired according to the insertion position and delay parameter of each target delay unit.

12. The method according to claim 11, characterized in that The method further comprises: determining the insertion position and delay parameter of each target delay unit according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, and the current hold timing violation value of the path to be repaired, and inserting the target delay unit into the path to be repaired according to the insertion position and delay parameter of each target delay unit, including: Determine a delay unit placement area corresponding to the current unit to be processed according to the position of the current unit to be processed and a preset radius; The target delay unit is inserted into the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the idle position information in the delay unit placement area.

13. The method according to claim 12, characterized in that The inserting of the target delay unit in the path to be repaired according to the number of target delay units allowed to be inserted, the total delay of the target delay units allowed to be inserted, the current hold timing violation value of the path to be repaired, and the idle position information in the delay unit placement area comprises: If the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is greater than 0, and the free positions in the delay unit placement area meet the conditions, inserting at least one target delay unit in the delay unit placement area according to the number of the target delay units allowed to be inserted and the total delay of the target delay units allowed to be inserted; If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is greater than 0, and the idle position in the delay unit placement area does not meet the condition, a fourth position that meets the third distance from the current unit to be processed is determined in the delay unit placement area, and a fifth position is determined according to the fourth position and the position of the current unit to be processed, and a sixth target delay unit with a first preset delay parameter is inserted in the fourth position, and a seventh target delay unit with a second preset delay parameter is inserted in the fifth position; If the difference between the total delay of the target delay unit allowed to be inserted and the current hold timing violation value is less than 0, and the free position in the delay unit placement area meets the condition, then determine the delay parameter of the target delay unit to be inserted according to the setup time margin of the current unit to be processed, and insert at least one target delay unit with the delay parameter in the delay unit placement area; If the difference between the total delay of the target delay units allowed to be inserted and the current hold timing violation value is less than 0, and the idle positions in the delay unit placement area do not meet the conditions, an eighth target delay unit with the first preset delay parameter is inserted at the fourth position.

14. A device for repairing timing violation in a chip, characterized in that: include: Determine the module and the processing module; The determination module is used to determine the repair type of each path to be repaired according to the establishment time margin of each path to be repaired; The repair type includes: a first type and a second type, the first type is used to indicate that the establishment time margin of the path to be repaired is less than a first preset threshold; the second type is used to indicate that the establishment time margin of the path to be repaired is greater than or equal to a second preset threshold; The determination module is used to determine the timing repair strategy corresponding to each path to be repaired according to the repair type of each path to be repaired, and the timing repair strategy includes: a first strategy and a second strategy, the first strategy is used to instruct to insert a delay unit into the specified area corresponding to each unit in the path to be repaired to perform path repair; the second strategy is used to instruct to perform step-by-step repair on each unit in the path to be repaired according to the set constraint conditions, and insert a delay unit into the specified area corresponding to each unit in the path to be repaired to perform path repair; The processing module is used to repair the timing violation of each path to be repaired according to the timing repair strategy corresponding to each path to be repaired.

15. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the program instructions to implement a method for repairing timing violations in a chip as described in any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the method for repairing timing violation in a chip as claimed in any one of claims 1 to 13 is implemented.

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