Interrupt register processing method and device, product, equipment and medium

Abstract

The invention discloses an interrupt register processing method and device, a product, equipment and a medium. The method comprises the steps that configuration information and input signal indication information of an interrupt register set to be verified are acquired; the configuration information comprises working attribute information, and the working attribute information indicates working logic of the interrupt register block; the input signal indication information indicates whether the interrupt register group has an input signal; generating a reference output result of the interrupt register block based on the input signal indication information and the working attribute information; obtaining a target output result of the interrupt register block; the target output result is a result output when the interrupt register group executes work according to the corresponding work logic under the condition that the interrupt register group is indicated by the input signal indication information; and generating a target verification result of the interrupt register block based on the matching between the target output result and the reference output result. By adopting the method and the device, the verification efficiency and verification accuracy of the interrupt register block can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of digital chip verification, and in particular to a method, device, product, equipment and medium for processing an interrupt register. Background Art

[0002] In existing applications, there is no fixed method for verifying interrupt registers. Usually, the functions of interrupt registers are manually verified based on the subjective understanding of the relevant developers on the working of interrupt registers. Different developers may have different understandings of the working of interrupt registers, which may result in different verification results for interrupt register groups obtained by different developers. This leads to the fact that the accuracy of the verification results of interrupt registers cannot be guaranteed.

[0003] In addition, if there are multiple interrupt registers that need to be verified at the same time, the developer needs to verify each interrupt register in turn. The verification process of different interrupt registers usually generates some repeated work, which also leads to low verification efficiency of the interrupt registers. Summary of the invention

[0004] The present application provides a method, apparatus, product, device and medium for processing an interrupt register, which can improve the verification efficiency and verification accuracy of an interrupt register group.

[0005] On one hand, the present application provides a method for processing an interrupt register, the method comprising:

[0006] Obtain configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal in the interrupt register group;

[0007] Simulate the working process of the interrupt register group based on the input signal indication information and the working attribute information, and generate a reference output result of the interrupt register group;

[0008] Obtaining a target output result of the interrupt register group; the target output result is the result output by the interrupt register group when the interrupt register group performs work according to the corresponding work logic under the condition indicated by the input signal indication information;

[0009] Based on the matching between the target output result and the reference output result, a target verification result of the interrupt register group is generated.

[0010] On one hand, the present application provides a processing device for an interrupt register, the device comprising:

[0011] A first acquisition module is used to acquire configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal in the interrupt register group;

[0012] A first generating module, used for simulating the working process of the interrupt register group based on the input signal indication information and the working attribute information, and generating a reference output result of the interrupt register group;

[0013] The second acquisition module is used to acquire the target output result of the interrupt register group; the target output result is the result output by the interrupt register group when the interrupt register group performs the work according to the corresponding work logic under the condition indicated by the input signal indication information;

[0014] The second generating module is used to generate a target verification result of the interrupt register group based on the matching between the target output result and the reference output result.

[0015] Optionally, the interrupt register group includes an interrupt set register; and the process of the first acquisition module acquiring the input signal indication information of the interrupt register group includes:

[0016] Performing a write operation on the interrupt set register to obtain a first state value of the interrupt set register; the first state value is used to control the interrupt set register to be in an on state or an off state;

[0017] If the first state value is used to control the interrupt set register to be in an on state, calling the interrupt set register to generate a first interrupt source signal;

[0018] The first interrupt source signal is used as input signal indication information; the input signal indication information is used to indicate that the input signal of the interrupt register group is the first interrupt source signal.

[0019] Optionally, the above device is also used for:

[0020] If the first state value is used to control the interrupt setting register to be in a closed state, it is determined that the input signal indication information is information for indicating that there is no input signal in the interrupt register group.

[0021] Optionally, the configuration information includes interrupt source configuration information, and the interrupt source configuration information includes path information of at least one interrupt source; the process of the first acquisition module acquiring the input signal indication information of the interrupt register group includes:

[0022] Generate execution instruction information for interrupt source configuration information;

[0023] If the execution instruction information indicates that the interrupt source configuration information needs to be executed, selecting target path information from the path information of at least one interrupt source;

[0024] generating a second interrupt source signal based on the target path information, and using the second interrupt source signal as input signal indication information;

[0025] The input signal indication information is used to indicate that the input signal of the interrupt register group is the second interrupt source signal.

[0026] Optionally, the above device is also used for:

[0027] If the execution instruction information indicates that the interrupt source configuration information does not need to be executed, it is determined that the input signal indication information is information for indicating that the interrupt register group does not have an input signal.

[0028] Optionally, the interrupt register group includes multiple interrupt registers, and the multiple interrupt registers include an interrupt enable register, an interrupt status register, and an interrupt mask register in sequence; the working attribute information is used to indicate the working logic of each interrupt register in the interrupt register group;

[0029] The input signal indication information is used to indicate that the input signal of the interrupt register group is an interrupt source signal, or to indicate that the input signal of the interrupt register group does not exist; the input signal of the interrupt register group is used to input the interrupt enable register;

[0030] The working logic of the interrupt enable register includes: when in the on state, the input interrupt source signal is transmitted backward, and when in the off state, the interrupt source signal is not transmitted backward; the working logic of the interrupt status register includes: when receiving the interrupt source signal, the interrupt state is generated, and when not receiving the interrupt source signal, the interrupt state is not generated; the working logic of the interrupt mask register includes: when in the off state, the interrupt signal of the interrupt state of the interrupt status register is output, and when in the on state, the interrupt signal of the interrupt state of the interrupt status register is masked;

[0031] Among them, the target output result is output by the interrupt mask register.

[0032] Optionally, the second acquisition module acquires the target output result of the interrupt register group in a manner including:

[0033] Performing a write operation on the interrupt enable register to obtain a second state value of the interrupt enable register, and performing a write operation on the interrupt mask register to obtain a third state value of the interrupt mask register; the second state value is used to control the interrupt enable register to be in an off state or an on state, and the third state value is used to control the interrupt mask register to be in an off state or an on state;

[0034] Calling the interrupt enable register having the second state value written therein, and performing work according to the corresponding work logic under the condition indicated by the input signal indication information to obtain a fourth state value of the interrupt state register; the fourth state value is used to indicate whether the interrupt state register has generated an interrupt state or has not generated an interrupt state;

[0035] The interrupt mask register having the third state value written therein is called to perform work according to the corresponding work logic based on the fourth state value, and output the target output result.

[0036] Optionally, the reference interrupt result is generated after the interrupt register group is simulated to work based on the second state value, the working logic of the interrupt enable register, the working logic of the interrupt state register, the third state value, the working logic of the interrupt mask register and the signal indication information;

[0037] The second generation module generates a target verification result of the interrupt register group based on the matching between the target output result and the reference output result, including:

[0038] If the target output result does not match the reference output result, determining that the target verification result is a result of an output anomaly of the interrupt register group;

[0039] If the target output result matches the reference output result, it is determined that the target verification result is a result that the output of the interrupt register group is normal.

[0040] Optionally, the above device is also used for:

[0041] In the process of obtaining the target verification result, the verification results of the interrupt enable register, the interrupt status register and the interrupt mask register are obtained;

[0042] The abnormal verification results among the verification results of each interrupt register in the interrupt register group are output in real time.

[0043] Optionally, the method for the above-mentioned device to obtain the verification result of the interrupt enable register, the verification result of the interrupt status register, and the verification result of the interrupt mask register includes:

[0044] Based on the input signal indication information, the second state value, the fourth state value, the working logic of the interrupt enable register and the working logic of the interrupt status register, obtaining the verification result of the interrupt enable register and the verification result of the interrupt status register; and,

[0045] Based on the third state value, the fourth state value, the target output result and the working logic of the interrupt mask register, obtaining a verification result of the interrupt mask register;

[0046] Among them, the verification result of any interrupt register is used to indicate whether any interrupt register works according to the corresponding working logic; the abnormal verification result refers to the verification result of the abnormal register, and the abnormal register refers to the interrupt register that does not work according to the corresponding working logic.

[0047] Optionally, the configuration information includes an interrupt verification type of the interrupt register group, and the interrupt verification type is any of the following: a level interrupt type, a pulse interrupt type;

[0048] Among them, the level interrupt type and the pulse interrupt type are associated with their own interrupt verification programs; the input signal indication information, the target interrupt result, the reference interrupt result and the target verification result are obtained by calling the interrupt verification program associated with the interrupt verification type.

[0049] Optionally, if the interrupt verification type is a level interrupt type, the interrupt verification program associated with the level interrupt type is used to perform a write operation on the interrupt register group after generating an interrupt source level signal, and call the interrupt register group after the write operation to process the interrupt source level signal to obtain a target output result; the input signal indication information is used to indicate that the input signal of the interrupt register group is an interrupt source level signal;

[0050] If the interrupt verification type is a pulse interrupt type, the interrupt verification program associated with the pulse interrupt type is used to generate an interrupt source pulse signal after writing to the interrupt register group, and call the interrupt register group after the writing operation to process the interrupt source pulse signal to obtain the target output result; the input signal indication information is used to indicate that the input signal of the interrupt register group is an interrupt source pulse signal;

[0051] The write operation performed on the interrupt register group is used to control the working state of the interrupt register in the interrupt register group, and the working state includes a closed state and an open state.

[0052] Optionally, the interrupt verification program associated with the interrupt verification type is used to verify the interrupt register group using multiple verification methods, and one verification method is used to generate a target verification result;

[0053] The interrupt verification program associated with the interrupt verification type is used to output indication information of full verification coverage for the interrupt register group after the interrupt register group is verified using multiple verification methods.

[0054] In one aspect, the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes a method in one aspect of the present application.

[0055] In one aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the processor executes the method in the above aspect.

[0056] According to one aspect of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the method provided in various optional modes such as the above-mentioned one aspect.

[0057] The present application can obtain configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal of the interrupt register group; and the working process of the interrupt register group can be simulated based on the input signal indication information and the working attribute information to generate a reference output result of the interrupt register group; the target output result of the interrupt register group can also be obtained; the target output result is the result output by the interrupt register group when the interrupt register group performs the work according to the corresponding working logic under the condition indicated by the input signal indication information; and the target verification result of the interrupt register group can be generated based on the matching between the target output result and the reference output result. It can be seen that the method proposed in the present application can first configure the interrupt register group to obtain configuration information including the working attribute information of the interrupt register group, and can obtain the input signal indication information of the interrupt register group. Then, through the input signal indication information and the working attribute information, the working process of the interrupt register group can be simulated to generate a reference output result of the interrupt register group. In addition, the present application can also enable the interrupt register group to work under the situation indicated by the input signal indication information, that is, the interrupt register group can generate a target output result. Then, through the matching between the target output result and the reference output result, the target verification result of the interrupt register group can be quickly and accurately obtained. The target verification result can be a verification result used to indicate whether the output of the interrupt register group (such as the target output result) is correct. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0059] Figure 1It is a structural schematic diagram of a verification device provided by this application;

[0060] Figure 2 This is a schematic diagram of a scenario for verifying an interrupt register group provided by the present application;

[0061] Figure 3 It is a flowchart of a method for processing an interrupt register provided by the present application;

[0062] Figure 4 This is a schematic diagram of a scenario for generating an interrupt signal provided by the present application;

[0063] Figure 5 It is a schematic diagram of a framework of a verification interrupt register group provided by the present application;

[0064] Figure 6 This application provides a flow chart of obtaining a target output result;

[0065] Figure 7 It is a logic diagram of the operation of an interrupt register group provided by the present application;

[0066] Figure 8 It is a flowchart of verifying an interrupt register group provided by the present application;

[0067] Fig. 9 This is a flow chart of a level interrupt verification provided by this application;

[0068] Fig.10 It is a flow chart of a pulse interruption verification provided by the present application;

[0069] Fig.11 It is a structural schematic diagram of an interrupt register processing device provided by the present application;

[0070] Fig.12 It is a structural schematic diagram of a computer device provided by this application. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in this application to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0072] First of all, it needs to be explained that all data collected in this application (such as configuration information of the interrupt register group, input signal indication information, and other related data) are collected with the consent and authorization of the object to which the data belongs (such as a user, organization or enterprise), and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0073] Here, some chip processing processes related to this application are described:

[0074] Typically, the overall process of implementing a digital chip (such as an interrupt register) can be summarized into the following major stages:

[0075] 1. Design planning and requirements analysis stage: At this stage, the design goals and requirements of the digital chip can be determined, including but not limited to the requirements for the chip's functions, performance, power consumption, area, etc.

[0076] 2. Digital chip architecture design stage: At this stage, the overall architecture of the digital chip can be designed based on demand analysis, including but not limited to determining the chip's module division, signal flow, data path, control logic, etc.

[0077] 3. Logical design stage: In this stage, the functions of the digital chip can be divided into modules, and the functions of the digital chip can be logically designed, including writing the logic code of the module using a hardware description language to realize the functions of the digital chip. The hardware description language can be Verilog (a text-based hardware description language) or VHDL (a high-level language for circuit design).

[0078] 4. Logic simulation and verification stage: In this stage, the logic of the digital chip design can be simulated and verified to ensure that the function and performance of the chip meet expectations. This includes using simulation tools to simulate the logic code and perform functional verification and timing analysis.

[0079] 5. Physical design stage: In this stage, the logical design of the digital chip can be converted into a physical layout, including mapping the logical circuit of the digital chip to actual physical units (such as gates, registers, etc.), and performing layout and routing to generate the physical layout of the digital chip.

[0080] 6. Physical verification stage: In this stage, the physical layout of the digital chip can be verified to ensure that the layout and wiring of the digital chip meet the electrical specifications and design constraints, including but not limited to electrical rule checking, timing analysis, power consumption analysis, etc.

[0081] 7. Chip manufacturing and testing stage: In this stage, the physical layout of the digital chip can be sent to the chip manufacturer for the manufacture of the digital chip. After the manufacturing is completed, the digital chip is tested to verify the function and performance of the digital chip.

[0082] 8. Chip integration and system testing stage: In this stage, the digital chip can be integrated into the target system, and system-level testing can be performed in the target system to ensure that the functions and performance of the digital chip in actual applications meet the requirements.

[0083] The above stages can be the overall process of digital chip implementation, but it should be understood that the specific implementation process of the digital chip may vary depending on the scale and complexity of the digital chip project. At each stage, the digital chip can be properly verified and tested to ensure the quality and reliability of the digital chip.

[0084] Through the various stages of the digital chip described above, it can be known that the present application can be mainly used to verify (i.e. test) the logic code of the digital chip (such as the interrupt register) in the third stage in the fourth stage, such as verifying whether the function of the digital chip is correct. Therefore, the interrupt register described below in the present application (such as each interrupt register in the interrupt register group) can refer to the logic code of the interrupt register. In other words, the interrupt register described in the present application can be the logic code of the interrupt register.

[0085] See also Figure 1 , Figure 1 It is a structural diagram of a verification device provided by the present application. The verification device can be a device for verifying (i.e. testing) an interrupt register group. Optionally, the verification device can be a terminal device of a verification personnel or a server of a verification platform, etc.; the terminal device can be, but is not limited to: smart phones, tablet computers, laptops, desktop computers, smart TVs, car terminals and other smart terminals; the server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (content distribution network), and big data and artificial intelligence platforms, etc.

[0086] Among them, the verification device may include a verification module and a register module. The register module may contain locally executable logic code for the interrupt register group that needs to be verified. The verification module may be a functional module for verifying the interrupt register group that needs to be verified, that is, the verification module may contain relevant verification logic written to verify the interrupt register group.

[0087] Please also see Figure 2 , Figure 2 Schematic diagram of a scenario for verifying an interrupt register group provided by the present application. Figure 2 As shown, the interrupt register group to be verified can be included in the register module of the verification device. The interrupt register group to be verified can be verified by calling an interrupt verification program. The interrupt verification program can have a calling interface. Therefore, it can be understood that the above-mentioned verification module can call the interrupt verification program based on the calling interface to realize the verification of the interrupt register group by calling the interrupt verification program, as described below.

[0088] First, the verification personnel may configure the configuration information of the interrupt register group to be verified on the verification device. The configuration information may include the working attribute information of the interrupt register group. The working attribute information is used to indicate the working logic of the interrupt register group.

[0089] Furthermore, the verification device can start to verify the interrupt register group based on the above configuration information by calling the interrupt verification program, as described below.

[0090] The verification device can call the interrupt verification program to obtain the input signal indication of the interrupt register group to be verified, and the input signal indication information can be used to indicate whether there is an input signal in the interrupt register group. Furthermore, the verification device can call the interrupt verification program to obtain the target output result output by the interrupt register group working according to the corresponding working logic under the condition indicated by the input signal indication information.

[0091] The verification device can also call the interrupt verification program to simulate the working process of the interrupt register group through the above-mentioned input signal indication information and configuration information to obtain the reference output result of the interrupt register group. The reference output result can be understood as the correct result that the interrupt register group needs to output under the circumstances indicated by the above-mentioned input signal indication information.

[0092] Therefore, the verification device can obtain the target verification result of the interrupt register group through the matching between the above target output result and the reference output result, and the target verification result is a result used to indicate whether the output of the interrupt register group (such as the target output result) is normal. For example, if the target output result does not match the reference output result, it can be indicated that the output of the interrupt register group is abnormal. On the contrary, if the target output result matches the reference output result, it can be indicated that the output of the interrupt register group is normal.

[0093] By adopting the above method provided by the present application, the user only needs to configure the corresponding configuration information for the interrupt register group that needs to be verified, and then call the interrupt verification program to realize fast and accurate verification of the interrupt register group.

[0094] See also Figure 3 , Figure 3 The flowchart of the interrupt register processing method provided by the present application is shown in FIG. The execution subject in the embodiment of the present application may be a processing device (also referred to as a verification device), which may be a computer device or a computer device cluster composed of multiple computer devices, which may be a server, a terminal device, or other devices, without limitation. Figure 3 As shown, the method may include:

[0095] Step S101, obtain configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal in the interrupt register group.

[0096] Optionally, the processing device can obtain configuration information of the interrupt register group to be verified, and the configuration information can be used to indicate the interrupt register group to be verified. For example, the configuration information may include identification information of the configured interrupt register group that needs to be verified, and the interrupt register group that needs to be verified can be determined (i.e., found) subsequently through the identification information.

[0097] The interrupt register group to be verified can be any interrupt register group that needs to be functionally verified. The interrupt register group can include multiple interrupt registers, which can work together to control the generation of interrupt signals. The interrupt signal can control the interruption of the corresponding workflow, such as controlling the interruption of the workflow currently executed by the CPU (central processing unit) (which can be any business processing workflow). The interrupt register group is specifically used to control the interruption of what workflow can be determined according to the actual application scenario, and there is no restriction on this.

[0098] The functional verification of the interrupt register group may be to verify whether each interrupt register in the interrupt register group works normally, whether the entire interrupt register group works normally, and so on.

[0099] The above-mentioned configuration information may also include working attribute information of the configured interrupt register group, and the working attribute information may be used to indicate the working logic of the interrupt register group. More specifically, the working attribute information may be used to indicate the working logic of each interrupt register in the interrupt register group. The working logic of any interrupt register is the logic of the operation of any interrupt register (such as the read and write logic of the interrupt register). In other words, the working attribute information may include the reading and writing working logic of each interrupt register in the configured interrupt register group (that is, the read and write attributes of the interrupt register).

[0100] Among them, the interrupt register group can be expressed as a piece of computer code in the device to which it belongs (i.e., the device where the interrupt register group is located), and the computer code is the code to be verified (i.e., the code to be tested). Optionally, the multiple interrupt registers contained in the interrupt register group can include an interrupt set register, an interrupt enable register, an interrupt status register and an interrupt mask register in sequence, that is, the interrupt enable register can be connected behind the interrupt set register, the interrupt status register can be connected behind the interrupt enable register, and the interrupt mask register can be connected behind the interrupt status register.

[0101] The input signal of the interrupt register group can be used to input the interrupt enable register of the interrupt register group. If the interrupt register group has an input signal, the input signal can be an interrupt source signal. The input signal can be generated by an interrupt set register, or the input signal can be generated externally (such as generated by the configuration information of the interrupt register group, and the process can refer to the following description of this step), or the input signal can be generated by the interrupt set register and externally.

[0102] Or, optionally, if the interrupt register group does not include an interrupt enable register, the input signal of the interrupt register group can be used to input the interrupt status register.

[0103] It can be understood that the generation of the interrupt source signal can be used to indicate the occurrence of an interrupt event, and a corresponding interrupt signal needs to be generated to control the corresponding work flow to be interrupted.

[0104] Among them, when the interrupt set register is in the on state, it can be used to generate an interrupt source signal (i.e., a signal for generating an interrupt signal). For example, 1 can be written to the interrupt set register to allow the interrupt register to generate a corresponding interrupt source signal. Writing 1 to the interrupt set register can be understood as controlling the interrupt set register to be in the on state. When the interrupt set register is in the off state (such as when 1 is not written), no interrupt source signal will be generated. That is, the working logic of the interrupt set register may include: when writing 1 (when in the on state), an interrupt source signal can be generated, and when 1 is not written, no interrupt source signal is generated. Therefore, it can be understood that the interrupt set register can allow the interrupt register group to spontaneously generate an interrupt source signal.

[0105] The interrupt enable register can be used to control whether the input interrupt source signal will be transmitted backward to the interrupt status register. For example, the working logic of the interrupt enable register may include: when it is in the on state, the input interrupt source signal is transmitted backward, and when it is in the off state, the interrupt source signal is not transmitted backward; the backward transmission may refer to the backward transmission to the interrupt status register. The interrupt enable register can be understood as a switch for whether to transmit the interrupt source signal.

[0106] In some feasible implementations, if the interrupt register group does not include the interrupt enable register, it can be understood that the interrupt enable register is always open (i.e., always in the on state). Optionally, the configuration information can also be configured with indication information for the interrupt enable register, and the indication information is used to indicate whether the interrupt register group to be verified includes the interrupt enable register.

[0107] The working logic of the interrupt status register may include: when an interrupt source signal is received (such as when an interrupt source signal transmitted by an interrupt enable register is received), an interrupt state may be generated, and when no interrupt source signal is received, no interrupt state is generated. The interrupt state is also a state requiring an interrupt.

[0108] Therefore, it can be understood that when the interrupt enable register is turned off (ie, in an off state), the interrupt status register will not generate an interrupt state regardless of whether an interrupt source signal is input or not.

[0109] The working logic of the interrupt mask register may include: when in the closed state, outputting the interrupt signal of the interrupt state generated by the interrupt state register (i.e. sending the interrupt signal to the outside, i.e. outputting the interrupt signal); when in the open state, shielding the interrupt signal of the interrupt state generated by the interrupt state register (i.e. not sending the interrupt signal to the outside, i.e. not outputting the interrupt signal). The interrupt mask register may also be understood as a switch for whether to send an interrupt signal.

[0110] Similarly, it can be understood that when the interrupt mask register is enabled, no matter whether an interrupt state is generated or not, an interrupt signal will not be reported, that is, no interrupt signal will be output.

[0111] Therefore, it can be seen from the above that the output of the interrupt register group can be obtained by the interrupt mask register. If the interrupt mask register outputs an interrupt signal, then the interrupt signal can be the output result of the interrupt register group. If the interrupt mask register does not output an interrupt signal, then the output result of the interrupt register group can be an empty result, that is, the result of not outputting an interrupt signal.

[0112] The interrupt set register, interrupt enable register and interrupt mask register may all belong to the RW register, which is a readable and writable register. The interrupt status register may belong to the W1C register, which may be a register that is cleared when writing 1, has no effect when writing 0, and has no effect when reading.

[0113] Furthermore, the processing device may also obtain input signal indication information of the interrupt register group, and the output signal indication information may be used to indicate whether there is an input signal in the interrupt register group, and to indicate what the output signal is specifically if there is an input signal in the interrupt register group.

[0114] Therefore, the input signal indication information can be used to indicate that the input signal of the interrupt register is the corresponding interrupt source signal (ie, if the interrupt register has an input signal, the input signal is the corresponding interrupt source signal), or to indicate that the interrupt register group has no input signal.

[0115] Therefore, the process of the processing device obtaining the input signal indication information may include but is not limited to the following methods:

[0116] In the first mode, the processing device can generate the above-mentioned input signal indication information of the interrupt register group through the interrupt set register. The process may include: the processing device can perform a write operation (which can be a random write operation) on the interrupt set register to obtain a state value written to the interrupt set register, which can be referred to as a first state value, and the first state value can be used to control whether the interrupt set register is in an on state or a off state. If the first state value is 1, the first state value is used to control the interrupt set register to be in an on state, and if the first state value is not 1 (such as 0), the first state value can be used to control the interrupt set register to be in a off state.

[0117] If the first state value is used to control the interrupt set register to be in an on state, the processing device can call the interrupt set register to generate a corresponding interrupt source signal, and the interrupt source signal generated by the interrupt set register can be referred to as a first interrupt source signal.

[0118] Furthermore, the processing device may use the first interrupt source signal as the input signal indication information, and the input signal indication information may be used to indicate that the input signal of the interrupt register group is the first interrupt source signal.

[0119] If the first state value is used to control the interrupt set register to be in a closed state, the input signal indication information may be information for indicating that there is no input signal in the interrupt register group.

[0120] Among them, the first state value can be written into the interrupt bit field segment of the interrupt set register (which can be called the interrupt field segment of the interrupt set register), and the interrupt field segment can be included in the above-mentioned configuration information. In other words, the interrupt field segment of the interrupt set register can be configured in the configuration information.

[0121] In the second method, the processing device can externally generate the above-mentioned input signal indication information of the interrupt register group through the configuration information of the interrupt register group. The process may include: the configuration information may also include interrupt source configuration information for configuring the interrupt register group, and the interrupt source configuration information may include path information of at least one (i.e., one or more) interrupt sources, that is, the interrupt source configuration information indicates the interrupt source used to verify the interrupt register group (which can be understood as the interrupt event or reason that causes the interrupt source signal to be generated), and an interrupt source may have a path information, and the path information can be used to indicate the location of the interrupt source signal that generates the interrupt source.

[0122] Therefore, the processing device can perform a force operation (forced execution operation) on the interrupt source configuration information to generate execution indication information for the interrupt source configuration information. The execution indication information can be used to indicate whether it is necessary to generate an interrupt source signal through the interrupt source configuration information. For example, if a force operation is performed on the interrupt source configuration information, a force value (forced execution value) can be obtained. The force value can be used as the execution indication information. When the force value is 1, it indicates that an interrupt source signal needs to be generated through the interrupt source configuration information. When the force value is 0, it indicates that an interrupt source signal is not generated through the interrupt source configuration information.

[0123] Therefore, if the execution instruction information indicates that the interrupt source configuration information needs to be executed (ie, an interrupt source signal needs to be generated through the interrupt source configuration information), the processing device may select target path information from the path information of at least one interrupt source in the interrupt source configuration information.

[0124] Furthermore, the processing device can generate a corresponding interrupt source signal at the interrupt source at the position indicated by the target path information. The interrupt source signal can be referred to as a second interrupt source signal. The processing device can use the second interrupt source signal as the above-mentioned input signal indication information. The input signal indication information can be used to indicate that the input signal of the interrupt register group is the second interrupt source signal.

[0125] If the execution indication information is used to indicate that the interrupt source configuration information does not need to be executed (ie, the interrupt source signal is not generated through the interrupt source configuration information), the input signal indication information may be information for indicating that the interrupt register group does not have an input signal.

[0126] Among them, since the processing device can continuously repeat the verification process of the interrupt register, the execution instruction information for the interrupt source configuration information generated by the force operation in each verification process may be different. Therefore, the processing device can select a certain path information from the path information of the above-mentioned at least one interrupt source in turn as the target path information each time when the execution instruction information generated by the force operation is used to indicate the situation where the interrupt source configuration information needs to be executed.

[0127] For example, when the execution indication information generated by the first force operation of the processing device is used to indicate the situation where the interrupt source configuration information needs to be executed, the first path information in the path information of the at least one interrupt source can be selected as the target path information in this verification process; then, when the execution indication information generated by the second force operation of the processing device is used to indicate the situation where the interrupt source configuration information needs to be executed, the second path information in the path information of the at least one interrupt source can be selected as the target path information in this verification process, and so on. The processing device can verify the interrupt register group through the path information of each interrupt source in the interrupt source configuration information by continuously performing force operations on the interrupt source configuration information (that is, the path information of each interrupt source in the interrupt source configuration information can be selected at least once as the target path information).

[0128] Optionally, the configuration information may further include the number of interrupt sources configured for verifying the interrupt register group (the number may be the number of path information of the at least one interrupt source).

[0129] In the third method, the processing device can also generate input signal indication information of the interrupt register group through the above-mentioned interrupt set register and configuration information. The process is described in combination with the above-mentioned two methods. The process includes: if the above-mentioned first state value is used to control the interrupt set register to be in a closed state, and the execution indication information indicates that the interrupt source configuration information does not need to be executed, then the input signal indication information can be information used to indicate that there is no input signal in the interrupt register group.

[0130] If the first state value is used to control the interrupt set register to be in an on state, and the execution indication information indicates that the interrupt source configuration information does not need to be executed, the input signal indication information can be used to indicate that the input signal of the interrupt register group is the first interrupt source signal. In this case, the input signal of the interrupt register group can be generated by the interrupt set register.

[0131] If the first state value is used to control the interrupt set register to be in the off state, and the execution indication information indicates that the interrupt source configuration information needs to be executed, the input signal indication information can be used to indicate that the input signal of the interrupt register group is the second interrupt source signal. In this case, the input signal of the interrupt register group can be externally generated through the interrupt source configuration information.

[0132] If the first state value is used to control the interrupt set register to be in an on state, and the execution indication information indicates that the interrupt source configuration information needs to be executed, the input signal indication information can be used to indicate that the input signal of the interrupt register group includes the first interrupt source signal and the second interrupt source signal. In this case, the input signal of the interrupt register group can be generated by the interrupt set register and the external part.

[0133] It can be seen from the above that if the interrupt register group has an input signal, the input signal of the interrupt register group may be one or more interrupt source signals.

[0134] See also Figure 4 , Figure 4 Schematic diagram of a scenario for generating an interrupt signal provided by the present application. Figure 4 As shown, the interrupt register group includes an interrupt set register, an interrupt enable register, an interrupt status register and an interrupt mask register.

[0135] Among them, the input information of the interrupt register group can be an interrupt source signal, and the interrupt source signal can be generated by an interrupt set register or a force operation. First, the interrupt source signal can be input into the interrupt enable register. If the interrupt enable register is in the on state, the interrupt source signal can be transmitted to the interrupt status register. The interrupt status register can generate an interrupt status through the interrupt source signal. If the interrupt mask register is in the off state, the interrupt status can generate a corresponding interrupt signal after passing through the interrupt mask register.

[0136] Step S102, obtaining a target output result of the interrupt register set; the target output result is a result output by the interrupt register set when the interrupt register set performs work according to the corresponding work logic under the condition indicated by the input signal indication information.

[0137] Optionally, the processing device may also obtain a target output result of the interrupt register group, which may be an actual result output by the interrupt register group after executing the work according to the corresponding work logic (such as the work logic of each interrupt register) under the condition indicated by the above-mentioned input signal indication information. The target output result may be a result with an interrupt signal output, or a result without an interrupt signal output (which may be understood as an output result being empty).

[0138] Optionally, the interrupt signal may be a 1-bit (bit, the smallest unit of computer storage information) signal.

[0139] The situation indicated by the input signal indication information is the situation of the input signal of the indicated interrupt register group, such as whether there is an input signal, and when there is an input signal, what interrupt source signal the input signal is.

[0140] Step S103, simulating the working process of the interrupt register group based on the input signal indication information and the working attribute information, and generating a reference output result of the interrupt register group.

[0141] Optionally, since the working attribute information for configuring the interrupt register group in the above configuration information can be used to indicate the working logic of the interrupt register group, the processing device can simulate the working process of the interrupt register group under the condition indicated by the input signal indication information (i.e., simulate the process of the interrupt register group performing normal work under the condition indicated by the input signal indication information) through the above input signal indication information and working attribute information to generate a reference output result of the interrupt register group.

[0142] The reference output result can be understood as the correct result that can be output after the interrupt register group performs normal work (i.e., accurate work) according to the corresponding work logic under the condition indicated by the input signal indication information. Corresponding to the above-mentioned target output result, the reference output result can also be the result of output with an interrupt signal, or the result of output without an interrupt signal (which can be understood as the output result being empty).

[0143] Step S104: generating a target verification result of the interrupt register group based on the matching between the target output result and the reference output result.

[0144] Optionally, the processing device may generate a target verification result of the interrupt register group based on the matching between the target output result and the reference output result. The target verification result may be a result of whether the output of the interrupt register group is normal.

[0145] If the target output result does not match the reference output result, that is, the target output result is inconsistent with the reference output result, then the generated target verification result can be the result of abnormal output of the interrupt register group, that is, the target output result of the interrupt register group is abnormal; conversely, if the target output result matches the reference output result, that is, the target output result is consistent with the reference output result, then the generated target verification result can be the result of normal output of the interrupt register group, that is, the target output result of the interrupt register group is normal. The processing device can also output the above target verification result for the user to view and check.

[0146] The series of verification operations performed by the above-mentioned processing device on the interrupt register can be executed by the processing device calling a register verification program. The register verification program can be programmed with the standardized logic for verifying the interrupt register group described above, thereby ensuring the accuracy of the verification of the interrupt register group, and the register verification program can be reused in verification items of different interrupt register groups, thereby reducing the difficulty and overhead of verifying the interrupt register group.

[0147] By adopting the above method of the present application, the user only needs to simply configure the above configuration information for the interrupt register group that needs to be verified (i.e., tested), and the above register verification program can automatically complete the fast and accurate verification of the interrupt register group, making the user's verification of the interrupt register group simpler and easier to use, and also improving the efficiency of verifying the interrupt register group.

[0148] See also Figure 5 , Figure 5 This is a schematic diagram of a framework for verifying an interrupt register group provided by the present application. Figure 5As shown, env represents the entire environment where the interrupt register group is located, and DUT represents the platform to be tested. The interrupt register group to be verified in this application can be the interrupt register group in the DUT, and the interrupt register group can be expressed as the rtl code (register level code) in the DUT. The reference model can be a model used to verify the interrupt register group in this application, and the reference model can be used to generate a reference value for the interrupt register group. For example, the reference value can include the above-mentioned reference output result and the following Figure 6 Corresponding to the reference state value of the interrupt state register in the embodiment, the reference model can also be understood as an interrupt verification program for verifying the interrupt register group.

[0149] In the present application, the reference model can be instantiated by the configuration information of the interrupt register group configuration to generate a test case (test instance), and the name of the test case obtained by the instantiation can also be pre-configured in the configuration information. Furthermore, the verification of the interrupt register group can be realized through the test case, such as the corresponding interrupt source signal can be generated as the input signal of the interrupt register group in the DUT through the test case, and the interrupt signal output by the interrupt register group in the DUT for the input signal can be read, and the above-mentioned target verification result is obtained by the read interrupt signal to realize the verification of the interrupt register group. Moreover, in the process of verifying the interrupt register group based on the test case, the present application can also obtain the functional coverage rate for the interrupt register group from time to time or at intervals of a period of time, and the functional coverage rate can be used to indicate the progress of the verification of the interrupt register group. For example, the verification process of the interrupt register group can be realized by using multiple verification methods through the test case, and the collected functional coverage rate can be used to indicate how many verification methods of the multiple verification methods have been used to complete the verification process of the interrupt register group.

[0150] The environment may also include an interrupt register model, which is a model for reading and writing an interrupt register group. The interrupt register model may be a model in UVM (a verification platform framework), and the above configuration information of the interrupt register group in the present application may also be configured according to the data format of the UVM. The bus agent may be an agent for reading and writing an interrupt register group, and is used to realize the reading and writing of the interrupt register group together with the interrupt register model.

[0151] The present application can obtain configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal of the interrupt register group; and the working process of the interrupt register group can be simulated based on the input signal indication information and the working attribute information to generate a reference output result of the interrupt register group; the target output result of the interrupt register group can also be obtained; the target output result is the result output by the interrupt register group when the interrupt register group performs the work according to the corresponding working logic under the condition indicated by the input signal indication information; and the target verification result of the interrupt register group can be generated based on the matching between the target output result and the reference output result. It can be seen that the method proposed in the present application can first configure the interrupt register group to obtain configuration information including the working attribute information of the interrupt register group, and can obtain the input signal indication information of the interrupt register group. Then, through the input signal indication information and the working attribute information, the working process of the interrupt register group can be simulated to generate a reference output result of the interrupt register group. In addition, the present application can also enable the interrupt register group to work under the situation indicated by the input signal indication information, that is, the interrupt register group can generate a target output result. Then, through the matching between the target output result and the reference output result, the target verification result of the interrupt register group can be quickly and accurately obtained. The target verification result can be a verification result used to indicate whether the output of the interrupt register group (such as the target output result) is correct.

[0152] See also Figure 6 , Figure 6 This application provides a flow chart of obtaining a target output result. Figure 6 As shown, the process may include:

[0153] Step S201, perform a write operation on the interrupt enable register to obtain a second state value of the interrupt enable register, and perform a write operation on the interrupt mask register to obtain a third state value of the interrupt mask register; the second state value is used to control the interrupt enable register to be in an off state or an on state, and the third state value is used to control the interrupt mask register to be in an off state or an on state.

[0154] Optionally, the processing device can perform a write operation on the interrupt enable register (which can be a random write operation) to obtain a status value written to the interrupt enable register. This status value can be called a second status value, and the second status value is used to control the interrupt enable register to be in an off state or an on state.

[0155] For example, when the second state value is 1, it can be used to control the interrupt enable register to be in the on state (i.e., used to turn on the interrupt enable register); when the second state value is 0, it can be used to control the interrupt enable register to be in the off state (i.e., used to turn off the interrupt enable register).

[0156] The second state value may be in the domain to which the interrupt bit of the interrupt enable register written into it belongs (which may be referred to as the interrupt domain of the interrupt enable register), and the interrupt domain may also be included in the above configuration information, that is, the above configuration information may also include the interrupt domain configured for the interrupt enable register. The second state value may be written to the interrupt enable register by the above register verification program.

[0157] The processing device can also perform a write operation (or a random write operation) on the interrupt mask register to obtain a state value written to the interrupt mask register. This state value can be called a third state value, and the third state value is used to control the interrupt mask register to be in an off state or an on state.

[0158] For example, when the third state value is 1, it can be used to control the interrupt mask register to be in the on state (i.e., used to turn on the interrupt mask register); when the third state value is 0, it can be used to control the interrupt mask register to be in the off state (i.e., used to turn off the interrupt mask register).

[0159] Similarly, the third state value may be in the domain segment to which the interrupt bit written into the interrupt mask register belongs (which may be referred to as the interrupt domain segment of the interrupt mask register), and the interrupt domain segment may also be included in the above configuration information, that is, the above configuration information may also include the interrupt domain segment configured for the interrupt mask register. The third state value may be written to the interrupt mask register by the above register verification program.

[0160] Step S202, call the interrupt enable register with the second state value written in it, and perform work according to the corresponding work logic under the condition indicated by the input signal indication information to obtain the fourth state value of the interrupt state register; the fourth state value is used to indicate whether the interrupt state register has generated an interrupt state or not.

[0161] Optionally, the processing device may call an interrupt enable register having a second status value written therein, and perform work according to the corresponding working logic (i.e., the working logic of the interrupt enable register) under the condition indicated by the above-mentioned input signal indication information, and enable the interrupt status register to perform work according to the corresponding working logic (i.e., the working logic of the interrupt status register) to obtain the status value of the interrupt status register. This status value may be referred to as a fourth status value, and the fourth status value may be used to indicate whether the interrupt status register has generated an interrupt status, i.e., the fourth status value may be used to indicate whether the interrupt status register has generated an interrupt status or has not generated an interrupt status.

[0162] If the interrupt status register generates an interrupt status, the interrupt status can be written into the domain segment to which the interrupt bit in the interrupt status register belongs (which can be called the interrupt domain segment of the interrupt status register), and the interrupt domain segment can also be included in the above-mentioned configuration information, that is, the above-mentioned configuration information can also include the interrupt domain segment configured for the interrupt status register.

[0163] Step S203, calling the interrupt mask register written with the third state value to perform work according to the corresponding work logic based on the fourth state value, and outputting the target output result.

[0164] Optionally, the processing device can also call an interrupt mask register with a third status value written in it, and perform work according to the corresponding working logic (i.e., the working logic of the interrupt mask register) through the above-mentioned fourth status value generated by the interrupt status register, so as to output the above-mentioned target output result, which can be the result of outputting an interrupt signal or the result of outputting an empty signal (i.e., no interrupt signal is output).

[0165] It can be understood that, since in the present application a write operation can be performed on the interrupt register in the interrupt register group to control the working state (including the on state and the off state) of the corresponding interrupt register (such as the interrupt enable register and the interrupt mask register), that is, to control whether the corresponding interrupt register is in the on state or the off state, the above-mentioned target output result is output by executing the interrupt register after the write operation.

[0166] Therefore, in this application, when simulating the working process of the interrupt register group through working attribute information and input signal indication information, the interrupt register after executing the write operation (consistent with the state value of the interrupt register that outputs the target output result) can also be simulated to output the above reference output result.

[0167] In other words, the on or off state of the interrupt register in the interrupt register group simulated when generating the reference output result is consistent with the on or off state of the interrupt register in the interrupt register group outputting the target output result.

[0168] This allows the reference output result to be used as a comparison object for the target output result to obtain a target verification result to determine whether the target output result is correct.

[0169] Therefore, it can be understood that if the above-mentioned target output result is obtained through an interrupt enable register with a second state value written therein and an interrupt mask register with a third state value written therein, then the reference interrupt result can also be obtained by the processing device simulating the working process of each interrupt register in the interrupt register group (here it may refer to other interrupt registers except the interrupt set register) through the second state value, the working logic of the interrupt enable register, the working logic of the interrupt state register, the third state value, the working logic of the interrupt mask register and the signal indication information.

[0170] The processing device may be a status value of each interrupt register obtained by reading the interrupt domain segment of each interrupt register.

[0171] Furthermore, in the process of obtaining the above-mentioned target verification results, the processing device can also obtain the verification results of the interrupt set register, the interrupt enable register, the interrupt status register and the interrupt mask register in real time. An interrupt register can have a verification result in one verification process, and the verification result is whether the interrupt register is the result of normal operation or abnormal operation.

[0172] In other words, the verification result of an interrupt register can be used to indicate whether the interrupt register is working according to the corresponding working logic (i.e., the working logic of the interrupt register) under the condition indicated by the input signal indication information. If it is working according to the corresponding working logic, the interrupt register is working normally; if it is not working according to the corresponding working logic, the interrupt register is working abnormally.

[0173] Furthermore, the processing device may also output abnormal verification results in the verification results of each interrupt register in the interrupt register group in real time during the process of verifying the output results of the interrupt register group (ie, during the process of obtaining the target verification process).

[0174] Therefore, the abnormal verification result may be the verification result of the abnormal register, and the abnormal register may refer to an interrupt register that does not work according to the corresponding working logic (i.e., a register that works abnormally). In other words, the verification result of the abnormal register is used to indicate that the abnormal register is the result of abnormal operation.

[0175] By way of example, an interrupt set register with the first state value written therein, an interrupt enable register with the second state value written therein, an interrupt state register generating a fourth state value, and an interrupt mask register with the third state value written therein are used to obtain verification results of each interrupt register, as described below.

[0176] Optionally, in order to verify all interrupt registers with problems without omission, during the operation of the interrupt register group, the verification results of the interrupt registers that are inferred to have abnormal operation probability can all be abnormal verification results.

[0177] For example, in a feasible implementation, the verification result of the interrupt set register may be obtained by writing an interrupt enable register with a second status value and an interrupt status register with a fourth status value.

[0178] For example, if the input signal indication information is used to indicate that the input signal of the interrupt register group is the above-mentioned first interrupt source signal, and the second status value is used to control the interrupt enable register to be in an on state, the processing device can simulate the working process of the interrupt enable register and the interrupt status register through the second status value and the first interrupt source signal, and obtain a reference status value of the interrupt status register. The reference status value can be the status value that the interrupt status register needs to generate under normal working conditions, and the reference status value can be used to indicate that the interrupt status register has generated an interrupt status.

[0179] Therefore, when the fourth status value is used to indicate that the interrupt status register has not generated an interrupt status (that is, when the fourth status value is inconsistent with the above-mentioned reference status value of the interrupt status register), the interrupt set register, the interrupt enable register and the interrupt status register may all be operating abnormally. In this case, the verification results of the interrupt set register, the interrupt enable register and the interrupt status register may all be abnormal verification results.

[0180] When the fourth status value is used to indicate that the interrupt status register has an interrupt status (ie, the fourth status value is consistent with the reference status value of the interrupt status register), it can be considered that the verification results of the interrupt set register, the interrupt enable register and the interrupt status register are not abnormal verification results.

[0181] For example, in another feasible implementation, if the above-mentioned input signal indication information is used to indicate that the interrupt register group has an interrupt source signal, and the second status value is used to control the interrupt enable register to be in a closed state, the processing device can also generate a reference status value of the interrupt status register through the second status value and the input signal indication information. The reference status can be used to indicate that the interrupt status register has not generated an interrupt status. Therefore, when the fourth status value is used to indicate that the interrupt status register has generated an interrupt signal (that is, the fourth status value is inconsistent with the reference status value of the interrupt status register), the verification results of the interrupt enable register and the interrupt status register can both be abnormal verification results, indicating that both the interrupt enable register and the interrupt status register have the possibility of abnormal operation.

[0182] In another feasible implementation, the present application can generate a verification result of the interrupt enable register and a verification result of the interrupt status register through the above-mentioned input signal indication information, the second state value, the fourth state value, the working logic of the interrupt enable register, and the working logic of the interrupt status register, including but not limited to the following scenarios:

[0183] For example, if the input signal indication information is used to indicate that the interrupt register group has an input signal, and the second status value is used to control the interrupt enable register to be turned on, the processing device can simulate the corresponding working processes of the interrupt enable register and the interrupt status register (such as the working processes of the interrupt enable register and the interrupt status register when there is an input signal and the interrupt enable register is in the turned-on state) through the working logic of the interrupt enable register and the working logic of the interrupt status register, and obtain a reference status value of the interrupt status register (that is, the correct status value that the interrupt status register actually needs to generate). The reference status value can be used to indicate that the interrupt status register actually needs to generate an interrupt state.

[0184] Therefore, if the fourth state value is inconsistent with the reference state value (such as the fourth state value is used to indicate that the interrupt status register does not actually generate an interrupt state), it indicates that the interrupt enable register and / or the interrupt status register may be operating abnormally, and therefore, the verification results of the interrupt enable register and the interrupt status register can both be abnormal verification results; and if the fourth state value is consistent with the reference state value, it indicates that the interrupt enable register and the interrupt status register are operating normally, and the verification results of the interrupt enable register and the interrupt status register can both be normal verification results (i.e., not abnormal verification results).

[0185] For another example, if the input signal indication information is used to indicate that the interrupt register group has no input signal, and the second status value is used to control the interrupt enable register to be turned on, the processing device can simulate the corresponding working processes of the interrupt enable register and the interrupt status register (such as the working processes of the interrupt enable register and the interrupt status register when there is no input signal and the interrupt enable register is in the turned-on state) through the working logic of the interrupt enable register and the working logic of the interrupt status register, and obtain a reference status value of the interrupt status register (that is, the correct status value that the interrupt status register actually needs to generate). The reference status value can be used to indicate that the interrupt status register does not actually need to generate an interrupt status.

[0186] Therefore, if the fourth status value is inconsistent with the reference status value (such as the fourth status value is used to indicate that the interrupt status register actually generates an interrupt status), it indicates that the interrupt status register may be operating abnormally. Therefore, optionally, the verification result of the interrupt status register may be an abnormal verification result; and if the fourth status value is consistent with the reference status value, it indicates that the interrupt status register is operating normally, and the verification result of the interrupt status register may be a normal verification result (i.e., not an abnormal verification result).

[0187] For example, if the input signal indication information is used to indicate that the interrupt register group has an input signal, and the second status value is used to control the interrupt enable register to be turned off, the processing device can simulate the corresponding working processes of the interrupt enable register and the interrupt status register (such as the working processes of the interrupt enable register and the interrupt status register when there is an input signal and the interrupt enable register is in the turned-off state) through the working logic of the interrupt enable register and the working logic of the interrupt status register, and obtain a reference status value of the interrupt status register (that is, the correct status value that the interrupt status register actually needs to generate). The reference status value can be used to indicate that the interrupt status register will not actually generate an interrupt status.

[0188] Therefore, if the fourth state value is inconsistent with the reference state value (such as the fourth state value is used to indicate that the interrupt status register actually generates an interrupt state), it indicates that the interrupt enable register and / or the interrupt status register may be operating abnormally, and therefore, the verification results of the interrupt enable register and the interrupt status register can both be abnormal verification results; and if the fourth state value is consistent with the reference state value, it indicates that the interrupt enable register and the interrupt status register are operating normally, and the verification results of the interrupt enable register and the interrupt status register can both be normal verification results (i.e., not abnormal verification results).

[0189] In another feasible implementation manner, the present application may also obtain the verification result of the interrupt mask register through the third state value, the fourth state value, the target output result and the working logic of the interrupt mask register, including but not limited to the following scenarios:

[0190] For example, if the third state value is used to control the interrupt mask register to be closed, and the fourth state value is used to indicate that the interrupt state register generates an interrupt state, the processing device can also simulate the corresponding working process of the interrupt mask register (such as the working process of the interrupt mask register when there is an interrupt state input and the interrupt mask register is in the closed state) to obtain the above-mentioned reference output result of the interrupt mask register output, and the reference output result can be the result of an interrupt signal output.

[0191] Therefore, if the target output result is inconsistent with the reference output result (such as the target output result is the result of no interrupt signal output), it indicates that the interrupt mask register may be working abnormally, and the verification result of the interrupt mask register may be an abnormal verification result. On the contrary, if the target output result is consistent with the reference output result, it indicates that the interrupt mask register is working normally.

[0192] For another example, if the third state value is used to control the activation of the interrupt mask register, and the fourth state value is used to indicate that the interrupt state register generates an interrupt state, the processing device can also simulate the corresponding working process of the interrupt mask register (such as the working process of the interrupt mask register when there is an interrupt state input and the interrupt mask register is in the activated state) to obtain the above-mentioned reference output result of the interrupt mask register output, and the reference output result can be the result of no interrupt signal output.

[0193] Therefore, if the target output result is inconsistent with the reference output result (such as the target output result is the result of an interrupt signal output), it indicates that the interrupt mask register may be working abnormally, and the verification result of the interrupt mask register may be an abnormal verification result. On the contrary, if the target output result is consistent with the reference output result, it indicates that the interrupt mask register is working normally.

[0194] The logic of obtaining the verification results of each interrupt register described above is only an example. In fact, the working logic of each interrupt register can be combined with the corresponding parameters generated by each interrupt register during the working process (such as the first interrupt source signal, interrupt status and interrupt signal, etc.) to determine whether each interrupt register is working normally (that is, whether each interrupt register is working according to the corresponding working logic), and the verification result of each interrupt register can be obtained through the judgment result. If it is determined that a certain interrupt register is working according to the corresponding working logic, the verification result of the interrupt register can be a normal verification result. On the contrary, if it is determined that a certain interrupt register is not working according to the corresponding working logic, the verification result of the interrupt register can be an abnormal verification result.

[0195] The specific judgment logic used to obtain the verification results of each interrupt register can be determined according to the actual application scenario, and there is no restriction on this, as long as the judgment logic conforms to the working logic of each interrupt register.

[0196] Furthermore, the interrupt status register has its own specific function, that is, when writing 1 to the interrupt status register, the interrupt status register needs to be cleared (if the interrupt status register generates an interrupt status, the interrupt status will be cleared after the clearing process). Therefore, the processing device can also perform specific verification on the interrupt status register for this point, and obtain another verification result of the interrupt status register, which can be called a clearing verification result, and the clearing verification result can be used to indicate whether the interrupt status register can complete the clearing process when writing 1.

[0197] For example, the processing device can write 1 to the interrupt status register, and then detect whether the interrupt status register has completed the clearing process. If the clearing process is completed, it indicates that the function of writing 1 to clear the interrupt status register is normal; conversely, if the clearing process is not completed, it indicates that the function of writing 1 to clear the interrupt status register is abnormal, that is, the above-mentioned clearing verification result is abnormal. At this time, the processing device can also output the abnormal clearing verification result of the interrupt status register in real time.

[0198] Furthermore, the above configuration information may also include an interrupt verification type configured for the interrupt register group, and the interrupt verification type may be any of the following: a level interrupt type, a pulse interrupt type. In other words, the present application may provide two interrupt verification types, a level interrupt type and a pulse interrupt type, for the interrupt register group for the user to choose from, and the user may configure by himself what type of interrupt verification is required for the interrupt register group.

[0199] Therefore, it can be understood that the above-mentioned register verification program (which can be understood as a verification platform or called a test platform) can include an interrupt verification program associated with a level interrupt type (which can be called a level interrupt verification program), and an interrupt verification program associated with a pulse interrupt type (which can be called a pulse interrupt verification program).

[0200] Among them, the interrupt verification program associated with the level interrupt type is used to verify the level interrupt type of the interrupt register group, and the interrupt verification program associated with the pulse interrupt type is used to verify the pulse interrupt type of the interrupt register group. The process of verifying the level interrupt type of the interrupt register group and the process of verifying the pulse interrupt type of the interrupt register group can both be the processes described above. The above-mentioned input signal indication information, target interrupt result, reference interrupt result and target verification result can all be obtained by the interrupt verification program associated with the interrupt verification type of the interrupt register group.

[0201] Therefore, if the interrupt verification type configured for the interrupt register group is a level interrupt type, the level interrupt verification program can be used to perform the above verification processing on the interrupt register group according to the corresponding verification logic of the level interrupt (including the verification processing of each interrupt register in the interrupt register group and the verification processing of the output result of the entire interrupt register group). If the interrupt verification type configured for the interrupt register group is a pulse interrupt type, the pulse interrupt verification program can be used to perform the above verification processing on the interrupt register group according to the corresponding verification logic of the pulse interrupt.

[0202] The verification logic of the level interrupt type and the verification logic of the pulse interrupt type may differ as follows:

[0203] It can be understood that if the interrupt verification type of the interrupt register group is a level interrupt type, the input signal of the interrupt register group (i.e., the interrupt source signal) is the interrupt source level signal, that is, the input signal of the interrupt register group belongs to a level signal, and the interrupt source level signal can be a level signal that meets (such as being equal to) a set target level, and the target level can be a high level (such as 1) or a low level (such as 0), which can be determined according to the actual application scenario; and if the interrupt verification type of the interrupt register group is a pulse interrupt type, the input signal of the interrupt register group (i.e., the interrupt source signal) is the interrupt source pulse signal, that is, the input signal of the interrupt register group belongs to a pulse signal, and the pulse signal can be a rising edge signal.

[0204] Since the level signal can be a continuous signal for a period of time, the level interrupt verification program can first generate an interrupt source level signal of the interrupt register group (that is, the input signal, and the input signal indication information at this time is used to indicate that the input signal of the interrupt register group is the interrupt source level signal), and then perform a write operation on the interrupt register group. After the write operation is performed on the interrupt register group, the interrupt source level signal continues to exist (that is, the interrupt source level signal lasts for a time sufficient to perform a write operation on the interrupt register group). Therefore, the interrupt register group after the write operation can be successfully called to perform signal processing on the interrupt source level signal to obtain the above-mentioned target output result.

[0205] Since the pulse signal is a momentary signal, the pulse interrupt verification program can first perform a write operation on the interrupt register group, and then generate an interrupt source pulse signal of the interrupt register group (that is, the input signal, and the input signal indication information at this time is used to indicate that the input signal of the interrupt register group is the interrupt source pulse signal). Then, the interrupt register group after the write operation can be called to perform signal processing on the interrupt source pulse signal to obtain the above-mentioned target output result.

[0206] It is understandable that, if in this case, an interrupt source pulse signal is generated first, and then a write operation is performed on the interrupt register group, then after the write operation is performed on the interrupt register group, the generated interrupt source pulse signal has disappeared. At this time, it is equivalent to the interrupt register group after the write operation being unable to perform signal processing on the interrupt source pulse signal generated first, that is, it is equivalent to the interrupt register group after the write operation having no input signal.

[0207] Among them, the write operation performed on the interrupt register group can be used to control the working state of the interrupt register (here it can refer to the interrupt enable register and the interrupt mask register) in the interrupt register group, and the working state may include an off state and an on state. In other words, here, the write operation performed on the interrupt register group can be used to control whether the interrupt register in the interrupt register group is turned on, such as using the second state value written to the interrupt enable register to control whether the interrupt enable register is turned on, and using the third state value written to the interrupt mask register to control whether the interrupt mask register is turned on.

[0208] Among them, the interrupt verification program associated with the interrupt verification type of the interrupt register group can use multiple verification methods to verify the interrupt register group. The multiple verification methods can be all the methods set in the interrupt verification program to verify the interrupt register group. One verification method corresponds to a verification process. The process of each verification method is performed independently and in the same principle. The verification process corresponding to each verification method can be the above Figure 3 as well as Figure 6 The process described in the corresponding embodiment.

[0209] Optionally, the multiple verification methods can be determined by the input signal of the interrupt register group, the working status of each interrupt register in the interrupt register group, and a specific verification method for the interrupt register in the interrupt register group (such as a verification method of writing 1 to clear the interrupt status register).

[0210] It can be understood that the differences among the multiple verification methods may lie in that during the verification process, the input signals of the interrupt register group are different, the working states of the interrupt registers in the interrupt register group are different, or whether it is a specific verification for the interrupt registers in the interrupt register group.

[0211] Therefore, it can be understood that, for example, the multiple verification methods may include all combinations obtained after exhaustive combination of input signal indication information corresponding to several input signals generated by the interrupt register group (including input signals generated in different ways (such as interrupt source signals generated through path information of different interrupt sources, or interrupt source signals generated through different sources (such as interrupt set registers or force operations)), and several working states of each interrupt register in the interrupt register group (such as all combinations of each interrupt register being in an off state or an on state); in addition, the multiple verification methods may also include specific verification methods for interrupt registers in the interrupt register group (such as a verification method of writing 1 to clear the interrupt status register).

[0212] In other words, as long as the input signal indication information of the interrupt register group is different (such as the way the input signal is generated is different), or the working state of at least one interrupt register in the interrupt register group is different, or whether the specific verification of the interrupt register is different, it can be understood as a different verification method for the interrupt register group (i.e., a different verification process).

[0213] See also Figure 7 , Figure 7 This is a logic diagram of the operation of an interrupt register group provided by the present application. Figure 7 As shown, first, an interrupt source signal can be generated, and the interrupt source signal can be used as an input signal of the interrupt register group (can be generated by an interrupt set register, or generated by the path information of the interrupt source in the configuration information), and the input signal can be input into the interrupt enable register. If the interrupt enable register is turned on (i.e., in the on state), the interrupt status register can be set to generate an interrupt status. If the interrupt enable register is turned off (i.e., in the off state), the interrupt status will not be set, and no interrupt status will be generated.

[0214] Under the condition that the interrupt enable register is in the on state, if the interrupt mask register is off, the interrupt mask register will output an interrupt signal (ie, there is an interrupt signal). Then, if the interrupt status at this time is cleared, it will become a non-interrupt state and there will be no interrupt signal.

[0215] Under the condition that the interrupt enable register is in the on state, if the interrupt mask register is on, the interrupt mask register will not output an interrupt signal (i.e., no interrupt signal). If the interrupt mask register is turned off at this time, an interrupt signal will be output again. It can be understood that the interrupt mask register acts as a switch.

[0216] Furthermore, when the interrupt enable register is in the off state, if the interrupt mask register is on, no interrupt signal is output. Also, when the interrupt enable register is in the off state, if the interrupt mask register is off, no interrupt signal is output.

[0217] The working logic of each interrupt register in the interrupt register group of the present application can be the working logic described above. In the process of verifying the entire interrupt register group, it is also possible to implement verification processing of each interrupt register separately according to the working logic of each interrupt register mentioned above, obtain the verification results of each interrupt register, and output the abnormal verification results.

[0218] Furthermore, after the processing device calls the interrupt verification program associated with the interrupt verification type of the interrupt register group and completes the verification of the interrupt register group by adopting the above-mentioned multiple verification methods (such as obtaining the verification results of each interrupt register and the above-mentioned target verification results), it can also be used to call the interrupt verification program to output indication information of full coverage of verification for the interrupt register group. The indication information of full coverage of verification is used to indicate that the verification of the interrupt register group has been completed by all possible verification methods, that is, it is used to indicate that the verification methods for the interrupt register group are complete. Therefore, the indication information can prompt the user that the verification of the interrupt register group has been completed by all possible methods. The indication information of full coverage of verification can be a prompt information that the interrupt register group has been 100% verified by all verification methods.

[0219] Among them, each interrupt verification program (including a level interrupt verification program and a pulse interrupt verification program) can have its own calling interface, and the processing device can call the interrupt verification program associated with the interrupt verification type of the interrupt register group through the calling interface of the interrupt verification program associated with the interrupt verification type of the interrupt register group to implement the verification process of the interrupt register group.

[0220] Optionally, the present application can directly call the interrupt verification program through the calling interface of the interrupt verification program to instantiate the interrupt verification program (also referred to as the interrupt verification platform) into the verification environment (such as the above-mentioned env), and implement the verification of the interrupt register group through the test case obtained by instantiation; or, through the relevant script, the interrupt verification program can be used as an independent interrupt verification platform, and then the relevant parameters required in the verification process of the interrupt register group (such as configuration information and the interrupt status and interrupt signal of the interrupt register group) are passed to the interrupt verification platform through parameter passing to implement the verification of the interrupt register group; or, after the user configures the configuration information of the interrupt register group, the corresponding test case can be automatically generated according to the configuration information and the interrupt verification program, and the verification of the interrupt register group can be implemented through the test case.

[0221] By adopting the above method provided in the present application, during the entire process of verifying the interrupt register group, a variety of methods can be used to generate input signals of the interrupt register group, and random write operations can be performed on the interrupt registers in the interrupt register group, so as to realize comprehensive verification of the interrupt register group from a variety of verification methods, so as to ensure the accuracy and completeness of the verification of the interrupt register group.

[0222] See also Figure 8 , Figure 8 This is a flow chart of verifying an interrupt register group provided by the present application. The process may include related operations performed by three business layers for verification processing of the interrupt register group. The three business layers may include a user layer, an internal processing layer, and an output layer. The process may include:

[0223] Step S301: At the user layer, the user may configure interrupt parameters for the interrupt register group that needs to be verified. The configured interrupt parameters may be used as the above configuration information.

[0224] Step S302: At the user level, after the user configures the relevant interrupt parameters for the interrupt register group to be verified, the user can initiate the execution of the interrupt verification task (such as initiating to the processing device or in the processing device), and the interrupt verification task can be a verification task for the interrupt register group.

[0225] Step S303: The internal processing layer is a service layer for verifying the interrupt register set according to the process described above in the present application. The processing device can read the interrupt parameters configured by the user.

[0226] Step S304: The processing device can determine whether the interrupt verification type of the interrupt register group is a level interrupt type. If so, the following step S305 can be executed. If not, it indicates that the interrupt verification type of the interrupt register group is a pulse interrupt type, and the following step S306 can be executed.

[0227] Step S305: the processing device may verify the interrupt register set according to the verification process of the level interrupt type. For example, the processing device may verify the interrupt register set using a level interrupt verification program.

[0228] Step S306: the processing device may verify the interrupt register set according to the verification process of the pulse interrupt type. For example, the processing device may verify the interrupt register set using a pulse interrupt verification program.

[0229] Step S307: At the output layer, the processing device may generate a verification result for the interrupt register group during or after the verification of the interrupt register group. The verification result may include the target verification result of the interrupt register group as a whole and the verification result of each interrupt register, and may generate a functional coverage rate. The functional coverage rate may be an indication of the full coverage of the above-mentioned verification, such as a functional coverage rate of 100%, which indicates that the verification of all functions of the interrupt register group is covered by all verification methods.

[0230] Step S308: The processing device may output the verification result and the functional coverage generated in the above step S307.

[0231] Through the above process, the verification process of the level interrupt type or the pulse interrupt type of the interrupt register group can be realized.

[0232] See also Fig. 9 , Fig. 9 This is a flow chart of a level interrupt verification process provided by this application. Fig. 9 As shown, the process may include:

[0233] Step S401: the processing device may obtain configuration information of an interrupt register group to be verified.

[0234] Step S402: The processing device can perform a random force operation on the interrupt source configuration information in the configuration information. If the force value is 1, the corresponding interrupt source signal (belonging to the interrupt source level signal) is generated through the path information in the interrupt source configuration information. If the force value is 0, the interrupt source signal is not generated through the path information in the interrupt source configuration information.

[0235] Step S403: The processing device can perform a random write operation on the interrupt set register, the interrupt enable register and the interrupt mask register (used to control whether the interrupt set register, the interrupt enable register and the interrupt mask register are turned on), that is, whether the interrupt set register, the interrupt enable register and the interrupt mask register are turned on can be randomly determined.

[0236] Step S404: The processing device can automatically update RM (i.e., reference value, which can be understood as the correct answer of the interrupt register group, i.e., the result after the interrupt register group works normally, and the reference value can include the reference state value of the interrupt status register, and the reference output result) based on the status value of the random write of the interrupt set register, the interrupt enable register, and the interrupt mask register, and can check whether the interrupt status and interrupt signal of the DUT (i.e., the interrupt status and interrupt signal of the interrupt register group in the DUT, which can be the interrupt status and interrupt signal of the interrupt register group after performing the random write operation) are consistent with the updated RM.

[0237] Step S405: The processing device may also perform a random write operation on the interrupt status register. If the interrupt status register is working normally, when the random value written is 1, the interrupt flag bit of the interrupt status register (such as the bit where the interrupt status is located) will be cleared (i.e., cleared to zero, that is, if there is an interrupt status, the interrupt status will be cleared), and when the random value written is 0, the interrupt flag bit of the interrupt status register will not change.

[0238] Step S406: After performing a random write operation on the interrupt status register, the RM is automatically updated again, and the interrupt status of the DUT and the interrupt signal are checked to see if they are consistent with the updated RM. The current functional coverage can be collected to determine the current verification progress of the interrupt register group.

[0239] Step S407: After the Release rtl operation (the force operation is a forced operation, and the Release rtl operation can be to cancel the force operation to restore the interrupt register group to the original state before the forced operation), a random write operation is performed on the interrupt status register again.

[0240] Step S408: After the random write operation is performed on the interrupt status register again, the RM is automatically updated again, and it is checked whether the interrupt status and interrupt signal of the DUT are consistent with the updated RM.

[0241] Step S409: the processing device may perform a random write operation on the interrupt setting register, the interrupt enable register and the interrupt mask register again to randomly control the on or off state of the interrupt setting register, the interrupt enable register and the interrupt mask register again.

[0242] Step S410: Then, the processing device may perform a random force operation on the interrupt source configuration information in the configuration information again. If the force value is 1, the corresponding interrupt source signal is generated through the path information in the interrupt source configuration information. If the force value is 0, the interrupt source signal is not generated through the path information in the interrupt source configuration information.

[0243] Step S411: The processing device can automatically update the RM again by re-performing the status values ​​of the interrupt set register, the interrupt enable register and the interrupt mask register after the random write operation is performed again, and can check whether the interrupt status and interrupt signal of the DUT (the interrupt status and interrupt signal of the interrupt register group after the random write operation is performed again) are consistent with the updated RM.

[0244] Step S412: the processing device may perform a random write operation on the interrupt status register again.

[0245] Step S413: The processing device can automatically update the RM again through the status values ​​of the interrupt set register, the interrupt enable register and the interrupt mask register after random writing, and check whether the interrupt status and interrupt signal of the DUT are consistent with the updated RM.

[0246] Step S414: The processing device can continuously loop the above steps, and the number of loops can be determined according to the actual application scenario, such as looping until the functional coverage reaches 100%. In addition, the processing device can also perform joint verification (i.e., joint testing) on ​​multiple interrupt source signals to prevent signal adhesion between the multiple interrupt source signals. For example, the multiple interrupt source signals may include interrupt source signals generated by the path information of all or part of the interrupt sources in the interrupt source configuration information. The multiple interrupt source signals can be used together as input signals of the interrupt register group to perform verification processing on the interrupt register group. Alternatively, the multiple interrupt source signals can also include interrupt source signals generated by the path information of all or part of the interrupt sources in the interrupt source configuration information and interrupt source signals generated by the interrupt set register. Similarly, the multiple interrupt source signals can also be used together as input signals of the interrupt register group to perform verification processing on the interrupt register group.

[0247] Through the above process, the verification process of the level interrupt type of the interrupt register group is realized.

[0248] See also Fig.10 , Fig.10 This is a flow chart of a pulse interruption verification process provided by this application. Fig.10 As shown, the process may include:

[0249] Step S501: the processing device may obtain configuration information of an interrupt register group to be verified.

[0250] Step S502: The processing device can perform a random force operation on the interrupt source configuration information in the configuration information. If the force value is 1, the corresponding interrupt source signal (belonging to the interrupt source pulse signal) is generated through the path information in the interrupt source configuration information. If the force value is 0, the interrupt source signal is not generated through the path information in the interrupt source configuration information.

[0251] Step S503: The processing device can perform a random write operation on the interrupt set register, the interrupt enable register and the interrupt mask register (used to control whether the interrupt set register, the interrupt enable register and the interrupt mask register are turned on), that is, whether the interrupt set register, the interrupt enable register and the interrupt mask register are turned on can be randomly determined.

[0252] Step S504: The processing device can automatically update RM (i.e., reference value, which can be understood as the correct answer of the interrupt register group, i.e., the result after the interrupt register group works normally, and the reference value can include the reference state value of the interrupt status register, and the reference output result) based on the state value before the random write operation of the interrupt set register, the interrupt enable register, and the interrupt mask register (because if there is an input signal, the input signal is generated before the random write operation is performed on the interrupt set register, the interrupt enable register, and the interrupt mask register), and can check whether the interrupt status and interrupt signal of the DUT (i.e., the interrupt status and interrupt signal of the interrupt register group in the DUT, which can be the interrupt status and interrupt signal of the interrupt register group before the random write operation is performed) are consistent with the updated RM.

[0253] Step S505: The processing device may also perform a random write operation on the interrupt status register. Similarly, if the interrupt status register is working normally, when the random value written is 1, the interrupt flag bit of the interrupt status register (such as the bit where the interrupt status is located) will be cleared (i.e., cleared to zero, that is, if there is an interrupt status, the interrupt status will be cleared), and when the random value written is 0, the interrupt flag bit of the interrupt status register will not change.

[0254] Step S506: After performing the random write operation on the interrupt status register, the processing device may automatically update the RM again, and check whether the interrupt status and interrupt signal of the DUT are consistent with the updated RM.

[0255] Step S507: the processing device again performs a random write operation on the interrupt setting register, the interrupt enabling register, and the interrupt masking register.

[0256] Step S508: the processing device may perform a random force operation on the interrupt source configuration information in the configuration information.

[0257] Step S509: The processing device can automatically update the RM based on the state value after randomly writing the interrupt set register, the interrupt enable register, and the interrupt mask register again (because if there is an input signal, the input signal is generated after performing a random write operation on the interrupt set register, the interrupt enable register, and the interrupt mask register), and can check whether the interrupt status and interrupt signal of the DUT (that is, the interrupt status and interrupt signal of the interrupt register group in the DUT, which can be the interrupt status and interrupt signal of the interrupt register group after the random write operation is performed again) are consistent with the updated RM.

[0258] Step S510: the processing device may perform a random write operation on the interrupt status register again.

[0259] Step S511: After performing the random write operation on the interrupt status register again, the processing device can automatically update the RM again, and check whether the interrupt status of the DUT and the interrupt signal are consistent with the updated RM, and can collect the current functional coverage, so as to determine the current verification progress of the interrupt register group.

[0260] Step S512: Similar to the verification process of the level interrupt type, the processing device can also continuously loop the above steps, and the number of loops can be determined according to the actual application scenario, such as looping until the functional coverage reaches 100%. In addition, the processing device can also perform joint verification (i.e., joint testing) on ​​multiple interrupt source signals to prevent signal adhesion between the multiple interrupt source signals.

[0261] Through the above process, the verification process of the pulse interrupt type of the interrupt register group is realized.

[0262] By adopting the above method of the present application, a unified and standardized design is made for the verification logic of the interrupt register group, so that only the interrupt verification tool (such as the interrupt verification program) needs to be maintained to complete the upgrade and iterative use case development of the verification logic of the interrupt register group, thereby reducing the maintenance complexity of the verification of the interrupt register group.

[0263] See also Fig.11 , Fig.11 Schematic diagram of the structure of an interrupt register processing device provided by the present application. Fig.11 As shown, the interrupt register processing device 1 may include: a first acquisition module 11 , a first generation module 12 , a second acquisition module 13 and a second generation module 14 .

[0264] The first acquisition module 11 is used to acquire configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal in the interrupt register group;

[0265] A first generating module 12, configured to simulate the working process of the interrupt register group based on the input signal indication information and the working attribute information, and generate a reference output result of the interrupt register group;

[0266] The second acquisition module 13 is used to acquire the target output result of the interrupt register group; the target output result is the result output by the interrupt register group when the interrupt register group performs the work according to the corresponding work logic under the condition indicated by the input signal indication information;

[0267] The second generating module 14 is used to generate a target verification result of the interrupt register group based on the matching between the target output result and the reference output result.

[0268] Optionally, the interrupt register group includes an interrupt set register; and the process of the first acquisition module 11 acquiring the input signal indication information of the interrupt register group includes:

[0269] Performing a write operation on the interrupt set register to obtain a first state value of the interrupt set register; the first state value is used to control the interrupt set register to be in an on state or an off state;

[0270] If the first state value is used to control the interrupt set register to be in an on state, calling the interrupt set register to generate a first interrupt source signal;

[0271] The first interrupt source signal is used as input signal indication information; the input signal indication information is used to indicate that the input signal of the interrupt register group is the first interrupt source signal.

[0272] Optionally, the device 1 is also used for:

[0273] If the first state value is used to control the interrupt setting register to be in a closed state, it is determined that the input signal indication information is information for indicating that there is no input signal in the interrupt register group.

[0274] Optionally, the configuration information includes interrupt source configuration information, and the interrupt source configuration information includes path information of at least one interrupt source; the process of the first acquisition module 11 acquiring the input signal indication information of the interrupt register group includes:

[0275] Generate execution instruction information for interrupt source configuration information;

[0276] If the execution instruction information indicates that the interrupt source configuration information needs to be executed, selecting target path information from the path information of at least one interrupt source;

[0277] generating a second interrupt source signal based on the target path information, and using the second interrupt source signal as input signal indication information;

[0278] The input signal indication information is used to indicate that the input signal of the interrupt register group is the second interrupt source signal.

[0279] Optionally, the device 1 is also used for:

[0280] If the execution instruction information indicates that the interrupt source configuration information does not need to be executed, it is determined that the input signal indication information is information for indicating that the interrupt register group does not have an input signal.

[0281] Optionally, the interrupt register group includes multiple interrupt registers, and the multiple interrupt registers include an interrupt enable register, an interrupt status register, and an interrupt mask register in sequence; the working attribute information is used to indicate the working logic of each interrupt register in the interrupt register group;

[0282] The input signal indication information is used to indicate that the input signal of the interrupt register group is an interrupt source signal, or to indicate that the input signal of the interrupt register group does not exist; the input signal of the interrupt register group is used to input the interrupt enable register;

[0283] The working logic of the interrupt enable register includes: when in the on state, the input interrupt source signal is transmitted backward, and when in the off state, the interrupt source signal is not transmitted backward; the working logic of the interrupt status register includes: when receiving the interrupt source signal, the interrupt state is generated, and when not receiving the interrupt source signal, the interrupt state is not generated; the working logic of the interrupt mask register includes: when in the off state, the interrupt signal of the interrupt state of the interrupt status register is output, and when in the on state, the interrupt signal of the interrupt state of the interrupt status register is masked;

[0284] Among them, the target output result is output by the interrupt mask register.

[0285] Optionally, the second acquisition module 13 acquires the target output result of the interrupt register group in the following manner:

[0286] Performing a write operation on the interrupt enable register to obtain a second state value of the interrupt enable register, and performing a write operation on the interrupt mask register to obtain a third state value of the interrupt mask register; the second state value is used to control the interrupt enable register to be in an off state or an on state, and the third state value is used to control the interrupt mask register to be in an off state or an on state;

[0287] Calling the interrupt enable register having the second state value written therein, and performing work according to the corresponding work logic under the condition indicated by the input signal indication information to obtain a fourth state value of the interrupt state register; the fourth state value is used to indicate whether the interrupt state register has generated an interrupt state or has not generated an interrupt state;

[0288] The interrupt mask register having the third state value written therein is called to perform work according to the corresponding work logic based on the fourth state value, and output the target output result.

[0289] Optionally, the reference interrupt result is generated after the interrupt register group is simulated to work based on the second state value, the working logic of the interrupt enable register, the working logic of the interrupt state register, the third state value, the working logic of the interrupt mask register and the signal indication information;

[0290] The second generating module 14 generates a target verification result of the interrupt register group based on the matching between the target output result and the reference output result, including:

[0291] If the target output result does not match the reference output result, determining that the target verification result is a result of an output anomaly of the interrupt register group;

[0292] If the target output result matches the reference output result, it is determined that the target verification result is a result that the output of the interrupt register group is normal.

[0293] Optionally, the device 1 is also used for:

[0294] In the process of obtaining the target verification result, the verification results of the interrupt enable register, the interrupt status register and the interrupt mask register are obtained;

[0295] The abnormal verification results among the verification results of each interrupt register in the interrupt register group are output in real time.

[0296] Optionally, the method in which the apparatus 1 obtains the verification result of the interrupt enable register, the verification result of the interrupt status register, and the verification result of the interrupt mask register includes:

[0297] Based on the input signal indication information, the second state value, the fourth state value, the working logic of the interrupt enable register and the working logic of the interrupt status register, obtaining the verification result of the interrupt enable register and the verification result of the interrupt status register; and,

[0298] Based on the third state value, the fourth state value, the target output result and the working logic of the interrupt mask register, obtaining a verification result of the interrupt mask register;

[0299] Among them, the verification result of any interrupt register is used to indicate whether any interrupt register works according to the corresponding working logic; the abnormal verification result refers to the verification result of the abnormal register, and the abnormal register refers to the interrupt register that does not work according to the corresponding working logic.

[0300] Optionally, the configuration information includes an interrupt verification type of the interrupt register group, and the interrupt verification type is any of the following: a level interrupt type, a pulse interrupt type;

[0301] Among them, the level interrupt type and the pulse interrupt type are associated with their own interrupt verification programs; the input signal indication information, the target interrupt result, the reference interrupt result and the target verification result are obtained by calling the interrupt verification program associated with the interrupt verification type.

[0302] Optionally, if the interrupt verification type is a level interrupt type, the interrupt verification program associated with the level interrupt type is used to perform a write operation on the interrupt register group after generating an interrupt source level signal, and call the interrupt register group after the write operation to process the interrupt source level signal to obtain a target output result; the input signal indication information is used to indicate that the input signal of the interrupt register group is an interrupt source level signal;

[0303] If the interrupt verification type is a pulse interrupt type, the interrupt verification program associated with the pulse interrupt type is used to generate an interrupt source pulse signal after writing to the interrupt register group, and call the interrupt register group after the writing operation to process the interrupt source pulse signal to obtain the target output result; the input signal indication information is used to indicate that the input signal of the interrupt register group is an interrupt source pulse signal;

[0304] The write operation performed on the interrupt register group is used to control the working state of the interrupt register in the interrupt register group, and the working state includes a closed state and an open state.

[0305] Optionally, the interrupt verification program associated with the interrupt verification type is used to verify the interrupt register group using multiple verification methods, and one verification method is used to generate a target verification result;

[0306] The interrupt verification program associated with the interrupt verification type is used to output indication information of full verification coverage for the interrupt register group after the interrupt register group is verified using multiple verification methods.

[0307] According to one embodiment of the present application, Figure 3 The steps involved in the interrupt register processing method shown can be represented by Fig.11 The interrupt register processing device 1 shown in the figure is executed by each module. For example, Figure 3 The step S101 shown in FIG. 1 can be performed by Fig.11The first acquisition module 11 is executed, Figure 3 The step S102 shown in FIG. 1 can be performed by Fig.11 The first generation module 12 is executed; Figure 3 The step S103 shown in FIG. 1 can be performed by Fig.11 The second acquisition module 13 is executed, Figure 3 The step S104 shown in FIG. 1 can be performed by Fig.11 The second generation module 14 is executed.

[0308] The present application can obtain configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal of the interrupt register group; and the working process of the interrupt register group can be simulated based on the input signal indication information and the working attribute information to generate a reference output result of the interrupt register group; the target output result of the interrupt register group can also be obtained; the target output result is the result output by the interrupt register group when the interrupt register group performs the work according to the corresponding working logic under the condition indicated by the input signal indication information; and the target verification result of the interrupt register group can be generated based on the matching between the target output result and the reference output result. It can be seen that the device proposed in the present application can first configure the interrupt register group, obtain configuration information including the working attribute information of the interrupt register group, and obtain the input signal indication information of the interrupt register group. Then, through the input signal indication information and the working attribute information, the working process of the interrupt register group can be simulated to generate a reference output result of the interrupt register group. In addition, the present application can also enable the interrupt register group to work under the situation indicated by the input signal indication information, that is, the interrupt register group can generate a target output result. Then, through the matching between the target output result and the reference output result, the target verification result of the interrupt register group can be quickly and accurately obtained. The target verification result can be a verification result used to indicate whether the output of the interrupt register group (such as the target output result) is correct.

[0309] According to one embodiment of the present application, Fig.11The various modules in the processing device 1 of the interrupt register shown can be combined into one or several units separately or in whole, or one (some) of the units can be further divided into multiple functionally smaller sub-units, which can achieve the same operation without affecting the realization of the technical effects of the embodiments of the present application. The above modules are divided based on logical functions. In practical applications, the functions of one module can also be implemented by multiple units, or the functions of multiple modules can be implemented by one unit. In other embodiments of the present application, the processing device 1 of the interrupt register can also include other units. In practical applications, these functions can also be implemented with the assistance of other units, and can be implemented by the collaboration of multiple units.

[0310] According to one embodiment of the present application, a computer program capable of executing the steps involved in the corresponding methods shown in the embodiments of the present application can be run on a general-purpose computer device (the computer device may include processing elements and storage elements such as a central processing unit (CPU), a random access storage medium (RAM), and a read-only storage medium (ROM)) to construct the following. Fig.11 The interrupt register processing device 1 shown in FIG. The computer program may be recorded on a computer-readable recording medium, and may be loaded into the computer device through the computer-readable recording medium and run therein.

[0311] See also Fig.12 , Fig.12 Schematic diagram of the structure of a computer device provided by this application. Fig.12 As shown, the computer device 1000 may include: a processor 1001, a network interface 1004 and a memory 1005. In addition, in some embodiments, the computer device 1000 may also include: a user interface 1003, and at least one communication bus 1002. The communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), a keyboard (Keyboard), and the user interface 1003 may optionally include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a non-volatile memory (non-volatile memory), such as at least one disk storage. The memory 1005 may optionally be at least one storage device located away from the aforementioned processor 1001. As Fig.12 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a device control application program.

[0312] exist Fig.12In the computer device 1000 shown, the network interface 1004 can provide a network communication function; the user interface 1003 is mainly used to provide an input interface for the user; and the processor 1001 can be used to call the device control application stored in the memory 1005 to achieve:

[0313] Obtain configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal in the interrupt register group;

[0314] Obtaining a target output result of the interrupt register group; the target output result is the result output by the interrupt register group when the interrupt register group performs work according to the corresponding work logic under the condition indicated by the input signal indication information;

[0315] Simulate the working process of the interrupt register group based on the input signal indication information and the working attribute information, and generate a reference output result of the interrupt register group;

[0316] Based on the matching between the target output result and the reference output result, a target verification result of the interrupt register group is generated.

[0317] It should be understood that the computer device 1000 described in the embodiments of the present application can execute the description of the processing method of the above interrupt register in each embodiment of the present application, and can also execute the above Fig.11 The description of the interrupt register processing device 1 in the corresponding embodiment will not be repeated here. In addition, the description of the beneficial effects of the same method will not be repeated here either.

[0318] In addition, it should be pointed out here that: the present application also provides a computer-readable storage medium, and a computer program is stored in the computer-readable storage medium. When the processor executes the computer program, it can execute the description of the processing method of the interrupt register in each embodiment of the present application, so it will not be repeated here. In addition, the description of the beneficial effects of using the same method will not be repeated. For technical details not disclosed in the computer storage medium embodiment involved in the present application, please refer to the description of the method embodiment of the present application.

[0319] As an example, the above-mentioned computer program may be deployed on one computer device for execution, or deployed on multiple computer devices located at one location for execution, or executed on multiple computer devices distributed at multiple locations and interconnected by a communication network. Multiple computer devices distributed at multiple locations and interconnected by a communication network may constitute a blockchain network.

[0320] The computer-readable storage medium may be an internal storage unit of the computer device, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device. Further, the computer-readable storage medium may also include both an internal storage unit and an external storage device of the computer device. The computer-readable storage medium is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

[0321] The present application provides a computer program product, which includes a computer program, which is stored in a computer-readable storage medium. The processor of the computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the description of the processing method of the above-mentioned interrupt register in each embodiment of the present application, so it will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the computer-readable storage medium embodiment involved in the present application, please refer to the description of the method embodiment of the present application.

[0322] The terms "first", "second", etc. in the description, claims, and drawings of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, device, product, or equipment that includes a series of steps or units is not limited to the listed steps or modules, but optionally includes steps or modules that are not listed, or optionally includes other step units inherent to these processes, methods, devices, products, or equipment.

[0323] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0324] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A method for processing an interrupt register, characterized in that: The method comprises: Acquire configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal in the interrupt register group; Acquire a target output result of the interrupt register group; the target output result is a result output by the interrupt register group when the interrupt register group performs work according to the corresponding work logic under the condition indicated by the input signal indication information; Simulate the working process of the interrupt register group based on the input signal indication information and the working attribute information to generate a reference output result of the interrupt register group; A target verification result of the interrupt register group is generated based on the matching between the target output result and the reference output result.

2. The method according to claim 1, characterized in that The interrupt register group includes an interrupt set register; and the process of obtaining the input signal indication information of the interrupt register group includes: Performing a write operation on the interrupt set register to obtain a first state value of the interrupt set register; the first state value is used to control the interrupt set register to be in an on state or a off state; If the first state value is used to control the interrupt set register to be in an on state, calling the interrupt set register to generate a first interrupt source signal; The first interrupt source signal is used as the input signal indication information; the input signal indication information is used to indicate that the input signal of the interrupt register group is the first interrupt source signal.

3. The method according to claim 2, characterized in that The method further comprises: If the first state value is used to control the interrupt setting register to be in a closed state, it is determined that the input signal indication information is information for indicating that there is no input signal in the interrupt register group.

4. The method according to claim 1, characterized in that The configuration information includes interrupt source configuration information, and the interrupt source configuration information includes path information of at least one interrupt source; The process of obtaining the input signal indication information of the interrupt register group includes: Generate execution instruction information for the interrupt source configuration information; If the execution instruction information indicates that the interrupt source configuration information needs to be executed, selecting target path information from the path information of the at least one interrupt source; generating a second interrupt source signal based on the target path information, and using the second interrupt source signal as the input signal indication information; The input signal indication information is used to indicate that the input signal of the interrupt register group is the second interrupt source signal.

5. The method according to claim 4, characterized in that The method further comprises: If the execution instruction information indicates that the interrupt source configuration information does not need to be executed, it is determined that the input signal indication information is information for indicating that there is no input signal in the interrupt register group.

6. The method according to claim 1, characterized in that The interrupt register group includes a plurality of interrupt registers, and the plurality of interrupt registers include an interrupt enable register, an interrupt status register and an interrupt mask register in sequence; the working attribute information is used to indicate the working logic of each interrupt register in the interrupt register group; The input signal indication information is used to indicate that the input signal of the interrupt register group is an interrupt source signal, or to indicate that there is no input signal in the interrupt register group; the input signal of the interrupt register group is used to input the interrupt enable register; The working logic of the interrupt enable register includes: transmitting the input interrupt source signal backward when in the on state, and not transmitting the interrupt source signal backward when in the off state; the working logic of the interrupt status register includes: generating an interrupt state when receiving an interrupt source signal, and not generating an interrupt state when not receiving an interrupt source signal; the working logic of the interrupt mask register includes: outputting an interrupt signal of the interrupt state of the interrupt status register when in the off state, and masking the interrupt signal of the interrupt state of the interrupt status register when in the on state; Wherein, the target output result is output by the interrupt mask register.

7. The method according to claim 6, characterized in that The obtaining of the target output result of the interrupt register group includes: Performing a write operation on the interrupt enable register to obtain a second state value of the interrupt enable register, and performing a write operation on the interrupt mask register to obtain a third state value of the interrupt mask register; the second state value is used to control the interrupt enable register to be in an off state or an on state, and the third state value is used to control the interrupt mask register to be in an off state or an on state; Calling the interrupt enable register having the second state value written therein, and performing work according to the corresponding work logic under the condition indicated by the input signal indication information, so as to obtain a fourth state value of the interrupt state register; the fourth state value is used to indicate whether the interrupt state register has generated an interrupt state or has not generated an interrupt state; The interrupt mask register having the third state value written therein is called to perform work according to the corresponding work logic based on the fourth state value, and output the target output result.

8. The method according to claim 7, characterized in that The reference interrupt result is generated after simulating the operation of the interrupt register group based on the second state value, the working logic of the interrupt enable register, the working logic of the interrupt state register, the third state value, the working logic of the interrupt mask register and the signal indication information; The generating a target verification result of the interrupt register group based on the matching between the target output result and the reference output result includes: If the target output result does not match the reference output result, determining that the target verification result is a result of an output abnormality of the interrupt register group; If the target output result matches the reference output result, it is determined that the target verification result is a result that the output of the interrupt register group is normal.

9. The method according to claim 7, characterized in that The method further comprises: In the process of obtaining the target verification result, obtaining the verification results of the interrupt enable register, the interrupt status register and the interrupt mask register respectively; The abnormal verification results among the verification results of each interrupt register in the interrupt register group are output in real time.

10. The method according to claim 9, characterized in that The obtaining of the verification result of the interrupt enable register, the verification result of the interrupt status register and the verification result of the interrupt mask register comprises: Based on the input signal indication information, the second state value, the fourth state value, the working logic of the interrupt enable register and the working logic of the interrupt status register, obtaining a verification result of the interrupt enable register and a verification result of the interrupt status register; and, Based on the third state value, the fourth state value, the target output result and the working logic of the interrupt mask register, obtaining a verification result of the interrupt mask register; Among them, the verification result of any interrupt register is used to indicate whether the interrupt register works according to the corresponding working logic; the abnormal verification result refers to the verification result of the abnormal register, and the abnormal register refers to the interrupt register that does not work according to the corresponding working logic.

11. The method according to claim 1, characterized in that The configuration information includes an interrupt verification type of the interrupt register group, and the interrupt verification type is any one of the following: a level interrupt type, a pulse interrupt type; The level interrupt type and the pulse interrupt type are associated with respective interrupt verification programs; the input signal indication information, the target interrupt result, the reference interrupt result and the target verification result are obtained by calling the interrupt verification program associated with the interrupt verification type.

12. The method according to claim 11, characterized in that If the interrupt verification type is the level interrupt type, the interrupt verification program associated with the level interrupt type is used to perform a write operation on the interrupt register group after generating an interrupt source level signal, and call the interrupt register group after the write operation to process the interrupt source level signal to obtain the target output result; the input signal indication information is used to indicate that the input signal of the interrupt register group is the interrupt source level signal; If the interrupt verification type is the pulse interrupt type, the interrupt verification program associated with the pulse interrupt type is used to generate an interrupt source pulse signal after the interrupt register group is written, and call the interrupt register group after the write operation to process the interrupt source pulse signal to obtain the target output result; the input signal indication information is used to indicate that the input signal of the interrupt register group is the interrupt source pulse signal; The write operation performed on the interrupt register group is used to control the working state of the interrupt register in the interrupt register group, and the working state includes a closed state and an open state.

13. The method according to claim 11, characterized in that The interrupt verification program associated with the interrupt verification type is used to verify the interrupt register group using multiple verification methods, and one verification method is used to generate one of the target verification results; The interrupt verification program associated with the interrupt verification type is used to output indication information of full verification coverage for the interrupt register group after the verification of the interrupt register group is completed using the multiple verification methods.

14. A processing device for an interrupt register, characterized in that: The device comprises: A first acquisition module is used to acquire configuration information and input signal indication information of the interrupt register group to be verified; the configuration information includes working attribute information of the interrupt register group, and the working attribute information is used to indicate the working logic of the interrupt register group; the input signal indication information is used to indicate whether there is an input signal in the interrupt register group; A first generating module, configured to simulate the working process of the interrupt register group based on the input signal indication information and the working attribute information, and generate a reference output result of the interrupt register group; A second acquisition module is used to acquire a target output result of the interrupt register group; the target output result is a result output by the interrupt register group when the interrupt register group performs work according to the corresponding work logic under the condition indicated by the input signal indication information; The second generating module is used to generate a target verification result of the interrupt register group based on the matching between the target output result and the reference output result.

15. A computer program product, comprising a computer program, which implements the steps of the method according to any one of claims 1 to 13 when executed by a processor.

16. A computer device, characterized in that: The invention comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the method according to any one of claims 1 to 13.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded by a processor and executing the method according to any one of claims 1 to 13.

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