Design block verification within semiconductor layout design

Abstract

A computing system implementing a physical verification tool can extract cells describing an integrated circuit from a semiconductor layout design, identify that one or more of the extracted cells correspond to candidate cells for verification based on sizes of the extracted cells relative to a size of a target design of the integrated circuit, and modifying the semiconductor layout design to remove integrated circuits that do not correspond to the candidate cells. The physical verification tool may also generate a target layout design that includes a copy of a target design of the integrated circuit at a location corresponding to a candidate cell in the semiconductor layout design, and performing verification of the semiconductor layout design by determining that at least one of the extracted cells corresponds to a modified version of the target design of the integrated circuit based on a comparison of the modified semiconductor layout design and the target layout design.

Description

Technical Field

[0001] The present application relates generally to electronic design automation and, more particularly, to semiconductor layout design verification with identification of modified circuit blocks. Background Art

[0002] In the design process for manufacturing integrated circuits, the physical design of the integrated circuit can describe specific geometric elements, which are usually called layout designs. Geometric elements, which are usually polygonal, define the shapes that will be produced in various materials to manufacture integrated circuits. Typically, the designer will select groups of geometric elements representing circuit device components (such as contacts, gates, etc.) and place them in the design area. These groups of geometric elements can be custom designed, selected from previously created design libraries, sometimes referred to as semiconductor intellectual property (IP), design IP, IP blocks, etc., or some combination of the two. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connecting lines are then placed between these geometric elements according to a predetermined route. These lines will form wiring for interconnecting electronic devices.

[0003] The description of the physical design of the integrated circuit can be provided in many different formats, such as the graphic data system II (GDSII) format, the open access format, the Milkyway format, the component-level netlist EDDM format, and the open artwork system interchange standard (OASIS) format. These various industry formats can be used to define geometric information in the layout design used to manufacture the integrated circuit. Some of these formats (such as the GDSII format) can include a hierarchy of structures, each structure having layout elements such as polygons, paths, polylines, circles, text boxes, etc. Once the layout design is completed, a mask or mask can be generated from the layout design, which can be used to manufacture the integrated circuit using a photolithography process.

[0004] Since most layout designs of integrated circuits include one or more previously created IP blocks, designers typically perform a verification process after placing the IP blocks, routing the wiring into the layout design, and inserting dummy fill structures into the layout design to determine whether the IP blocks remain unmodified in the layout design and thus avoid degrading their performance. Existing methods for verifying IP blocks incorporated into the layout design of an integrated circuit (such as complex design rule check (DRC) analysis, layout versus layout (LVL) and pattern matching) are generally error-prone, time-consuming and heavily dependent on manual setup or supervision. For example, performing a complex design rule check (DRC) analysis for verification requires custom-written design rules for the specific IP block being verified, which involves a large amount of manual work. The LVL method can compare a portion of the layout design to compare with the IP block to perform verification, but the method relies on the ability to identify the IP block in the portion of the layout by the assigned name, and also relies on the ability to identify the exact location of the portion of the layout design for comparison, both of which are error-prone. The pattern matching method can identify an exact match of an IP block in the layout design, but it is difficult to identify when the layout design includes a modified version of the IP block. Summary of the invention

[0005] The present application discloses a computing system that implements a physical verification tool that extracts cells describing an integrated circuit from a semiconductor layout design, identifies one or more of the extracted cells as corresponding to candidate cells for verification based on the size of the extracted cells relative to a target design of the integrated circuit (e.g., an intellectual property (IP) design block, a standard design cell, etc.). The physical verification tool can modify the semiconductor layout design to remove integrated circuits that do not correspond to the candidate cells. The physical verification tool can also generate a target layout design that includes a copy of the target design of the integrated circuit at a location corresponding to the candidate cell in the semiconductor layout design, and performs verification of the semiconductor layout design by determining that at least one of the extracted cells corresponds to a modified version of the target design of the integrated circuit based on a comparison of the modified semiconductor layout design and the target layout design. Embodiments will be described in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 and Figure 2 Illustrated are examples of the types of computer systems that may be used to implement the various embodiments.

[0007] Figure 3 An example layout verification system utilizing identification of modified circuit blocks that can be implemented in accordance with various embodiments is illustrated.

[0008] Figure 4 Examples of layout design generation for circuit block verification and identification of modifications to circuit blocks according to various examples are illustrated.

[0009] FIG. 5A to FIG. 5D Examples of identifiable circuit block modifications in a physical layout design according to various embodiments are illustrated.

[0010] Figure 6 An example flow diagram of circuit block verification and identification of circuit block modifications that may be implemented in accordance with various embodiments is illustrated. DETAILED DESCRIPTION

[0011] Illustrative operating environment

[0012] Various examples may be implemented by executing software instructions by a computing device (e.g., a programmable computer). Figure 1 An illustrative example of a computing device 101 is shown. As seen in the figure, computing device 101 includes a computing unit 103 having a processor unit 105 and a system memory 107. Processor unit 105 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. System memory 107 can include read-only memory (ROM) 109 and random access memory (RAM) 111. As will be appreciated by one of ordinary skill in the art, both read-only memory (ROM) 109 and random access memory (RAM) 111 can store software instructions for execution by processor unit 105.

[0013] Processor unit 105 and system memory 107 are connected to one or more peripheral devices 115-123 directly or indirectly through bus 113 or alternative communication structures. For example, processor unit 105 or system memory 107 can be directly or indirectly connected to one or more additional memory storage devices, such as hard disk drive 117, removable optical drive 119, and / or flash memory card, which can be magnetic and / or removable. Processor unit 105 and system memory 107 can also be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. Input device 121 can include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. Output device 123 can include, for example, a monitor display, a printer, and a speaker. For various examples of computing device 101, one or more peripheral devices 115-123 can be housed internally with computing unit 103. Alternatively, one or more peripheral devices 115 - 123 may be external to the housing of computing unit 103 and connected to bus 113 via, for example, a universal serial bus (USB) connection.

[0014] For some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 to communicate with other devices that make up the network. The network interface 115 may convert data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP). Furthermore, the network interface 115 may use any suitable connection agent (or combination of agents) to connect to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and therefore will not be discussed in more detail herein.

[0015] It should be understood that computing device 101 is illustrated only as an example and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices including Figure 1 The components of the computing device 101 illustrated in the example include only Figure 1 A subset of the components illustrated in, or alternative combinations of components, including Figure 1 For example, various embodiments may be implemented using a multi-processor computer, multiple single-processor and / or multi-processor computers arranged in a network, or some combination of the two.

[0016] For some implementations, processor unit 105 may have more than one processor core. Figure 2 An example of a multi-core processor unit 105 that can be used with various embodiments is illustrated. As seen in the figure, the processor unit 105 includes multiple processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B and a memory cache 205A and a memory cache 205B, respectively. As known to those of ordinary skill in the art, the computing engine 203A and the computing engine 203B may include a logic device for performing various computing functions (e.g., obtaining software instructions and then performing the actions specified in the instructions obtained). These actions may include, for example, adding, subtracting, multiplying and comparing numbers, performing logical operations (e.g., AND, OR, NOR and XOR) and retrieving data. Each computing engine 203A and the computing engine 203B can then use its corresponding memory cache 205A and memory cache 205B to quickly store and retrieve data and / or instructions for execution.

[0017] Each processor core 201A and 201B is connected to an interconnect 207. The specific configuration of interconnect 207 may vary depending on the architecture of processor unit 105. For some processor cores 201A and 201B (e.g., the Cell microprocessor created by Sony Corporation, Toshiba Corporation, and IBM Corporation), interconnect 207 may be implemented as an interconnect bus. However, for other processor units 201A and 201B (e.g., the Opteron microprocessor available from Advanced Micro Devices, Inc. of Sunnyvale, California), interconnect 207 may be implemented as a bus. TM and Athlon TM In some implementations, the processor unit 105 may include additional components, such as a shared high-level cache memory that can be accessed by the processor cores 201A and 201B. It should also be understood that Figure 1 and Figure 2 The description of the illustrated computer network is provided by way of example only, and is not intended to suggest any limitation as to the scope of use or functionality of the alternative embodiments.

[0018] Semiconductor layout design verification using identification of modified circuit blocks

[0019] Figure 3 An example layout verification system 300 utilizing identification of modified circuit blocks that can be implemented according to various embodiments is illustrated. Figure 3 , for example by Figure 1 The layout verification system 300 implemented by the computing device 101 in can receive a physical layout design 301, which describes an integrated circuit as geometric information defining shapes (e.g., polygonal structures) that can be created in various materials to manufacture the integrated circuit. The physical layout design 301 can be specified in a Graphic Data System II (GDSII) format, an open access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, etc.

[0020] The layout verification system 300 may also receive at least one target design 302, which describes a block or cell of an integrated circuit as geometric information defining a shape (e.g., a polygonal structure) that can be created in various materials to manufacture the integrated circuit. The target design 302 may be a previously created design block or design cell, for example, a standard cell included in a standard cell library, a design block or design cell of design intellectual property (IP) such as acquired from a third-party supplier, etc. The target design 302 may be specified in a Graphic Data System II (GDSII) format, an open access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, etc.

[0021] Layout verification system 300 may perform a verification process that determines whether target design 302 is included within physical layout design 301, and also identifies whether physical layout design 301 includes a modified version of target design 302. Layout verification system 300 may generate layout design verification report 303 that identifies one or more design cells or design blocks in physical layout design 301 that correspond to target design 302 or a modified version of target design 302. In some embodiments, layout design verification report 303 may identify the type of modification to target design 302 included in physical layout design 302. Layout verification system 300 may output layout design verification report 303 to, for example, physical verification tool 350, which in some embodiments may utilize the identification of target design 302 and the modified version of target design 302 to modify physical layout design 301, such as routing lines, inserting or removing dummy fill structures, and the like.

[0022] Layout verification system 300 may include cell extraction system 310 that identifies one or more design cells in physical layout design 301 to verify against target design 302. Cell extraction system 310 may determine the size of target design 302, for example, the height and width of target design 302. In some embodiments, cell extraction system 310 may query target design 302 to determine the height and width of target design 302.

[0023] Cell extraction system 310 may analyze physical layout design 301 to identify a plurality of design cells in physical layout design 301, and then extract one or more of the identified design cells to have a size or dimension corresponding to a determined size of target design 302. Cell extraction system 310 may consider the extracted design cells as candidate cells for verification against target design 302. Cell extraction system 310 may also determine locations of the candidate cells extracted from physical layout design 301.

[0024] The layout verification system 300 may include a layout verification system 320 that performs verification of candidate cells extracted from the physical layout design 301 against a target design 302. The layout verification system 320 may include a layout preparation system 321 that modifies the physical layout design 301 to remove design cells that do not correspond to candidate cells. In some embodiments, the layout preparation system 321 may generate a layout design and insert candidate cells into locations of the layout design that correspond to locations of candidate cells in the physical layout design 301. The layout preparation system 321 may also generate a target layout that includes a copy of the target design 302 at locations that correspond to locations of the candidate cells in the physical layout design 301. By generating two layout designs: a reduced physical layout design with candidate cells and a target layout design with a copy of the target design 302 at the same relative locations in its corresponding layout design, the layout verification system 300 may perform a layout-to-layout comparison to identify whether the candidate cells extracted from the physical layout design 301 correspond to the target design 302 or a modified version of the target design 302. Reference will be made to the following. Figure 4 An embodiment of layout preparation is described.

[0025] Figure 4 Examples of layout design generation for circuit block verification and identification of circuit block modifications according to various examples are illustrated. Figure 4 , the target block 410 may correspond to a physical design of an integrated circuit, which may be placed in a physical layout design 430 of a larger integrated circuit device. The physical layout design 430 may include a plurality of design blocks 431-435, which also correspond to a physical design of an integrated circuit.

[0026] For example, by Figure 3 The layout preparation system 321 and the layout comparison system 322 in the physical layout design 430 perform automatic verification of the physical layout design 430 and can generate a pair of layout designs - a target layout design 420 and a reduced physical layout design 440 - which are configured to be compared during the automatic verification process. The generation of the layout design can begin with the characterization of the target block 410, such as determining the size of the target block 410, such as the height and width. Next, one or more design blocks 431-435 can be extracted from the physical layout design 430, for example, the size of the design blocks 431-435 can be compared with the size of the target block 410, and those design blocks 431-435 having a size corresponding to the target block 410 can be extracted. In this example, the design blocks 431 and 435 have a size that matches the size of the target block 410, which indicates that these design blocks 431 and 435 can be verified to determine whether they correspond to the target design block 410.

[0027] The automatic verification process may generate a reduced physical layout design 440 by removing design blocks 432-434 from physical layout design 420 because those design blocks 432-434 do not have a size that matches the size of target block 410. The automatic verification process may generate target layout design 420 by identifying the locations of design blocks 431 and 435 in physical layout design 420 and inserting target block 410 into target layout design 420 at the identified locations of design blocks 431 and 435 in physical layout design 420. By generating a pair of layout designs having target block 410 and design blocks 431 and 435 at the same corresponding locations, the pair of layout designs may be compared to determine whether design blocks 431 and 435 correspond to an unmodified version or a modified version of target block 410. In some embodiments, the automatic verification process may copy design blocks 431 and 435 into a new layout design instead of generating a reduced physical design layout 440, and the new layout design may be used to compare design blocks 431 and 435 with target block 410. For example, design blocks 431 and 435 may be located in the new layout design at the same respective positions as target block 410 was located in target layout design 420. In another example, the new layout design may be populated with design blocks 431 and 435 and at least one target block 410 that is shifted in relative position from design blocks 431 and 435. The automatic verification process may compare target block 410 and design blocks 431 and 435 in the new layout design with the shifted relative positions for determining whether design blocks 431 and 435 correspond to an unmodified version or a modified version of target block 410.

[0028] Return to reference Figure 3 , the layout verification system 320 may include a layout comparison system 322 that compares the target layout design with the reduced physical layout design to determine whether any candidate cells in the reduced physical layout design match the target design 302. When the candidate cell matches the target design 302, the layout comparison system 322 may treat the candidate cell as an unmodified version of the target design 302. In some embodiments, the layout comparison system 322 may perform the comparison using an exclusive OR (XOR) operation on different layers of the target layout design and the reduced physical layout design.

[0029] In some embodiments, the layout comparison system 322 can perform comparisons of the target layout design with the reduced physical layout design in different modes, a cell-level mode and a higher-level mode. In the cell-level mode, the layout comparison system 322 can compare the target layout design with the reduced physical layout design corresponding to a level of the target design 302 while ignoring design features in higher levels of the hierarchy within the reduced physical layout design. In the higher-level mode, the layout comparison system 322 can compare the target layout design with a reduced physical layout design at the top level of the reduced physical layout design, thereby allowing comparisons within the scope of the target design 302 and across levels of the hierarchy in the reduced physical layout design.

[0030] In some embodiments, layout verification system 320 can perform comparison of candidate cells to target design 302 directly, rather than during a layout-to-layout comparison process, for example, by generating a checksum of the candidate cells and a checksum of target design 302, and then comparing the checksums to identify when the candidate cells match target design 302. In some embodiments, this direct comparison can be performed prior to layout preparation, wherein any matching candidate cells are excluded from the reduced physical layout design, and copies of corresponding target design 302 are excluded from the target layout design at locations corresponding to the excluded candidate cells.

[0031] When the comparison of the target layout design with the reduced physical layout design by the layout comparison system 322 results in one or more candidate cells in the reduced physical layout design not matching the target design 302, the layout verification system 320 may include a modification identification system 323 that determines whether any of the non-matching candidate cells correspond to a modified version of the target design 302. FIG. 5A to FIG. 5D Examples of identifiable circuit block modifications are described.

[0032] FIG. 5A to FIG. 5D Examples of identifiable circuit block modifications in a physical layout design according to various embodiments are illustrated. FIG. 5A to FIG. 5D , target blocks 510, 530, 550, and 570 may describe an integrated circuit that may be placed or inserted into a physical layout design describing an integrated circuit device. After the target blocks 510, 530, 550, and 570 are placed into the physical layout design, the physical layout design may undergo additional design modifications, such as placing other design blocks, laying out wiring lines between design blocks, inserting dummy fill structures, and the like. These additional design modifications to the physical layout design may modify the target blocks 510, 530, 550, and 570 and affect the design and / or performance of the target blocks 510, 530, 550, and 570.

[0033] exist Figure 5A In the example, target block 510 - after being placed in the physical layout design - can be modified to change the location of the circuit structure. In this example, one of the structures in target block 510 is moved, which is shown as a modified target block 522 in a higher design unit 520 of the physical layout design.

[0034] exist Figure 5B , a target block 530 - after being placed in a physical layout design - can be modified by the insertion of a dummy fill structure 544, which is shown as a modified target block 542 in a higher design unit 540 of the physical layout design. The dummy fill structure can be an electrically isolating fill material that can be added to the physical layout design to make the structure density of a region of the integrated circuit substantially uniform, thereby avoiding the creation of non-uniform layers during manufacturing, such layer non-uniformities may cause CMP defects during the chemical mechanical polishing process. In this example, the dummy fill structure 544 is included in and outside of the modified target block 542, but within the higher design unit 540.

[0035] exist Figure 5C , target block 550—after being placed in the physical layout design—can be modified to include conductive lines routed within the layer of the integrated circuit having target block 550. In this example, higher design unit 560 of the physical layout design includes a modified target block 562 corresponding to target block 550 and a target layer conductive line 564 passing through the layer of the integrated circuit having the modified target block 562.

[0036] exist Figure 5D , target block 570—after being placed in the physical layout design—can be modified to include conductive lines routed at a higher level of the integrated circuit than the layer of target block 570. In this example, a higher design unit 580 of the physical layout design includes a modified target block 582 corresponding to target block 570 and a higher level conductive line 584 that passes through a layer of the integrated circuit above the layer including the modified target block 582.

[0037] Return to reference Figure 3 , the modification identification system 323 can utilize the comparison of the candidate cells with the target design 302 during the layout-to-layout comparison verification process to determine a similarity metric for each candidate cell. In some embodiments, the modification identification system 323 can identify the region evaluated in the XOR operation during the comparison and determine a ratio of the region relative to the candidate range, which ratio can correspond to the similarity metric. The modification identification system 323 can compare the similarity metric with a predetermined threshold to determine whether each non-matching candidate cell can be considered a modified version of the target design 302 or corresponds to a design unrelated to the target design 302.

[0038] The layout verification system 300 may include a verification reporting system 330 that generates a layout design verification report 303 to identify one or more design cells or design blocks in the physical layout design 301 that correspond to the target design 302 or a modified version of the target design 302. In some embodiments, the layout design verification report 303 may identify the type of modification to the target design 302 included in the physical layout design 302. For example, when the layout verification system 300 performs the verification process in the cell-only mode and the higher-level mode, the layout verification system 300 may determine whether the modification of the target design 302 in the physical layout design 301 is within the level of the target design 302 or in a higher-level of the physical layout design 301. The layout design verification report 303 may include the level of the modification within the layout design verification report 303, for example, within the level of the target design 302 or in a higher-level of the physical layout design 301.

[0039] Figure 6 An example flow chart of circuit block verification and identification of circuit block modifications that may be implemented according to various embodiments is illustrated. Figure 6 In block 601, a computing system implementing a layout verification system may determine the size of a target design for an integrated circuit. The target design may describe a block or cell of an integrated circuit as geometric information defining a shape (e.g., a polygonal structure) that can be created in various materials to manufacture the integrated circuit. The target design may be a previously created design block or design cell, for example, a standard cell included in a standard cell library, a design block or design cell of design intellectual property (IP) such as acquired from a third-party supplier, etc. The target design may be specified in a Graphic Data System II (GDSII) format, an open access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, etc. The layout verification system may determine the size of the target design for the integrated circuit by measuring the height and width of a range of the integrated circuit in the target design.

[0040] In block 602, a computing system implementing a layout verification system may extract cells describing an integrated circuit from a semiconductor layout design. The semiconductor layout design may describe the integrated circuit as geometric information defining shapes (e.g., polygonal structures) that can be created in various materials to manufacture the integrated circuit. The semiconductor layout design may be specified in a Graphic Data System II (GDSII) format, an open access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, etc. In some embodiments, the layout verification system may extract cells from the semiconductor layout design by identifying locations of cells in the semiconductor layout design and determining a bounding box around the extent of the extracted cells in the semiconductor layout design.

[0041] In block 603, a computing system implementing a layout verification system may identify that one or more of the extracted cells correspond to candidate cells for verification based on the size of the extracted cells relative to the size of a target design for the integrated circuit. In some embodiments, the layout verification system may compare the size of the bounding box of the extracted cells to the size of the target design to determine which of the extracted cells correspond to candidate cells for verification. The candidate cells may correspond to those extracted cells having the same size and / or dimensions as the target design.

[0042] The layout verification system may perform verification to determine whether the target design matches any of the candidate cells, which would indicate that an unmodified version of the target design is located in the semiconductor layout design. In some embodiments, the layout verification system may perform a comparison of the target design with the candidate cells, for example, by generating a checksum of the target design and a checksum of the candidate cells and then comparing the checksum of the candidate cells with the checksum of the target design. When the checksum of the target design matches the checksum of the candidate cells, the layout verification system may consider the matching candidate cells as the unmodified version of the target design placed in the semiconductor layout design.

[0043] In block 604, a computing system implementing a layout verification system may modify the semiconductor layout design to remove integrated circuits that do not correspond to the candidate cells. The resulting modified semiconductor layout design includes the identified candidate cells without other integrated circuits in the original semiconductor layout design. In some embodiments, the modified semiconductor layout design may also remove any candidate cells that the verification system previously believed corresponded to an unmodified version of the target design, such as by the above-described checking and matching process.

[0044] In block 605, a computing system implementing a layout verification system may generate a target layout design including a copy of the target design of the integrated circuit at a location corresponding to the candidate cell in the semiconductor layout design. The layout verification system may generate the target layout design by identifying the location of the candidate cell in the modified semiconductor layout design and placing the copy of the target design into the target layout design at the identified location of the candidate cell in the modified semiconductor layout design.

[0045] In block 606, a computing system implementing a layout verification system may compare the modified semiconductor layout design to the target layout design. In some embodiments, the comparison of the modified semiconductor layout design to the target layout design may be a level-by-level exclusive-OR (XOR) comparison of the target cell in the target layout design with the candidate cell in the modified semiconductor layout design. The comparison of the modified semiconductor layout design to the target layout design may be performed on an area corresponding to a range of the target cell and the candidate cell. In some embodiments, the comparison of the modified semiconductor layout design to the target layout design may be performed at a different level within the hierarchy of the semiconductor layout design, for example, within a level of the hierarchy corresponding to the target design and the candidate cell or within a higher level of the hierarchy in the semiconductor layout design.

[0046] In block 607, a computing system implementing a layout verification system may perform verification of the semiconductor layout design to determine, based on the comparison, that at least one of the extracted cells corresponds to a modified version of a target design for the integrated circuit. The layout verification system may utilize a comparison of the target layout design with the modified semiconductor layout design to determine when a candidate cell in the modified semiconductor layout design corresponds to an exact match with the target design, and when it is determined that there is no exact match, calculate a similarity metric between the candidate cell and the target design. For example, the similarity metric may correspond to a ratio of an area used in the comparison to an area of ​​a range of the candidate cell. The layout verification system may utilize the similarity metric to identify whether the candidate cell corresponds to a modified version of a target design placed in the semiconductor layout design or does not correspond to the target design.

[0047] The above-mentioned systems and devices may use a dedicated processor system, a microcontroller, a programmable logic device, a microprocessor or any combination thereof to perform some or all of the operations described herein. Some of the above-mentioned operations may be implemented in software, while other operations may be implemented in hardware. Any operation, process and / or method described herein may be performed by an apparatus, device and / or system substantially similar to the apparatus, device and / or system described herein and with reference to the illustrated drawings.

[0048] The processing device may execute instructions or "code" stored in the memory. The memory may also store data. The processing device may include, but is not limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system locally or remotely via wireless transmission.

[0049] Processor memory can be integrated with the processing device, for example, RAM or flash memory arranged in an integrated circuit microprocessor, etc. In other examples, the memory can include independent devices, such as external disk drives, storage arrays, portable flash key cards, etc. The memory and the processing device can be operably coupled together or communicate with each other, for example, through I / O ports, network connections, etc., and the processing device can read files stored on the memory. Depending on the permission settings, the associated memory can be "read-only" (ROM) or not by design. Other examples of memory can include, but are not limited to, WORM, EPROM, EEPROM, flash memory, etc., which can be implemented in solid-state semiconductor devices. Other memories can include moving parts, such as known rotating disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0050] The operating instructions or commands may be implemented or embodied in a tangible form of stored computer software (also referred to as a "computer program" or "code"). The program or code may be stored in a digital memory and may be read by a processing device. "Computer-readable storage media" (or alternatively, "machine-readable storage media") may include all of the aforementioned types of memory as well as new technologies of the future, as long as the memory is capable of storing digital information having the properties of a computer program or other data at least temporarily, and as long as the stored information can be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical use of "computer" to imply a complete mainframe, minicomputer, desktop or even laptop computer. On the contrary, "computer-readable" may include storage media that can be read by a processor, a processing device or any computing system. Such a medium may be any available medium that can be accessed locally and / or remotely by a computer or processor, and may include volatile and non-volatile media, removable and non-removable media, or any combination thereof.

[0051] Programs stored in computer-readable storage media may include computer program products. For example, storage media may be used as a convenient means for storing or transmitting computer programs. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams can be equivalently aggregated into a single logical device, program or operation without clear boundaries.

[0052] in conclusion

[0053] Although the present application describes specific examples of implementing embodiments of the present invention, it will be appreciated by those skilled in the art that there are many variations and permutations of the above-described systems and techniques that fall within the spirit and scope of the present invention as set forth in the appended claims. For example, although specific terms have been employed above to refer to design processes, it will be appreciated that any desired combination of electronic design automation processes may be used to implement various examples of the present invention.

[0054] Those skilled in the art will also recognize that the concepts taught herein can be adapted to specific applications in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are only one of many alternative implementations that will become apparent upon reading this disclosure.

[0055] Although the specification may refer to "one", "another", or "some" examples in several places, this does not necessarily mean that each such reference is to the same example or examples or that the feature applies to only a single example.

Claims

1. A method comprising: extracting, by a computing system, cells describing an integrated circuit from a semiconductor layout design; identifying, by the computing system, that one or more of the extracted cells correspond to candidate cells for verification based at least in part on a size of the extracted cells relative to a size of a target design for an integrated circuit; modifying, by the computing system, the semiconductor layout design to remove integrated circuits that do not correspond to the candidate cells; generating, by the computing system, a target layout design comprising a copy of the target design of the integrated circuit at a location corresponding to the candidate cell in the semiconductor layout design; as well as Verification of the semiconductor layout design is performed by the computing system by determining that at least one of the extracted cells corresponds to a modified version of the target design of an integrated circuit based on a comparison of the modified semiconductor layout design with the target layout design.

2. The method according to claim 1, further comprising: A bounding box is determined, by the computing system, for each of the extracted cells, wherein a size of the bounding box corresponds to a size of the extracted cells.

3. The method according to claim 1, further comprising: The modified semiconductor layout design is compared layer by layer with the target layout design by the computing system.

4. The method according to claim 3, wherein: Comparing the modified semiconductor layout design with the target layout design is performed on at least one of the levels of the semiconductor layer including the integrated circuit corresponding to the extracted cell or all the levels of the semiconductor layer.

5. The method according to claim 1, wherein: Comparing the modified semiconductor layout design with the target layout design further includes performing an exclusive OR (XOR) logic operation on the candidate cells in the modified semiconductor layout design and the target design of the integrated circuit in the target layout design.

6. The method according to claim 1, wherein: The modified version of the target design of an integrated circuit includes at least one of a modification to the integrated circuit in the target design, an additional dummy fill structure in the scope of the target design of an integrated circuit, a wiring layout in the semiconductor layer corresponding to the extracted cell, or a wiring layout in a semiconductor layer higher than the extracted cell.

7. The method according to claim 1, wherein: Performing the verification of the semiconductor layout design also includes determining a similarity percentage corresponding to a degree of difference between the candidate design and the target design of the integrated circuit, and comparing the similarity percentage to a threshold to determine that at least one of the extracted cells corresponds to the modified version of the target design of the integrated circuit.

8. A system comprising: a storage system configured to store computer-executable instructions; as well as A computing system, responsive to execution of the computer executable instructions, configured to: Extracting cells describing integrated circuits from semiconductor layout designs; identifying that one or more of the extracted cells correspond to candidate cells for verification based at least in part on a size of the extracted cells relative to a size of a target design for an integrated circuit; modifying the semiconductor layout design to remove integrated circuits that do not correspond to the candidate cells; generating a target layout design comprising a copy of the target design of the integrated circuit at a location corresponding to the candidate cell in the semiconductor layout design; as well as Verification of the semiconductor layout design is performed by determining that at least one of the extracted cells corresponds to a modified version of the target design of an integrated circuit based on a comparison of the modified semiconductor layout design with the target layout design.

9. The system according to claim 8, wherein: The computing system, in response to execution of the computer-executable instructions, is further configured to determine a bounding box for each of the extracted cells, wherein a size of the bounding box corresponds to a size of the extracted cells.

10. The system according to claim 9, wherein: The computing system, responsive to execution of the computer-executable instructions, is further configured to compare the modified semiconductor layout design with the target layout design on a layer-by-layer basis.

11. The system according to claim 10, wherein: The computing system, in response to execution of the computer-executable instructions, is further configured to compare the modified semiconductor layout design with the target layout design for at least one of the levels of the semiconductor layer including the integrated circuit corresponding to the extracted cell or for all levels of the semiconductor layer.

12. The system according to claim 8, wherein: The computing system, in response to execution of the computer-executable instructions, is further configured to compare the modified semiconductor layout design with the target layout design by performing an exclusive OR (XOR) logic operation on candidate cells in the modified semiconductor layout design and the target design of the integrated circuit in the target layout design.

13. The system according to claim 8, wherein: The computing system, in response to execution of the computer-executable instructions, is further configured to: perform the verification of the semiconductor layout design by determining a similarity percentage corresponding to a degree of difference between the candidate design and the target design of the integrated circuit, and comparing the similarity percentage to a threshold to determine that at least one of the extracted cells corresponds to the modified version of the target design of the integrated circuit.

14. An apparatus comprising at least one computer-readable storage device storing instructions, the instructions configured to cause one or more processing devices to perform operations comprising: Extracting cells describing integrated circuits from semiconductor layout designs; identifying that one or more of the extracted cells correspond to candidate cells for verification based at least in part on a size of the extracted cells relative to a size of a target design for an integrated circuit; modifying the semiconductor layout design to remove integrated circuits that do not correspond to the candidate cells; generating a target layout design comprising a copy of the target design of the integrated circuit at a location corresponding to the candidate cell in the semiconductor layout design; as well as Verification of the semiconductor layout design is performed by determining that at least one of the extracted cells corresponds to a modified version of the target design of an integrated circuit based on a comparison of the modified semiconductor layout design with the target layout design.

15. The device according to claim 14, wherein: The instructions are configured to cause one or more processing devices to perform operations further comprising determining a bounding box for each of the extracted cells, wherein a size of the bounding box corresponds to a size of the extracted cells.

16. The device according to claim 15, wherein: The instructions are configured to cause one or more processing devices to perform operations further comprising comparing the modified semiconductor layout design to the target layout design on a layer-by-layer basis.

17. The device according to claim 16, wherein: The instructions are configured to cause one or more processing devices to perform operations, the operations also including: comparing the modified semiconductor layout design with the target layout design for at least one of the levels of the semiconductor layer including the integrated circuit corresponding to the extracted unit or all the levels of the semiconductor layer.

18. The device according to claim 14, wherein: The instructions are configured to cause one or more processing devices to perform operations, the operations also including comparing the modified semiconductor layout design with the target layout design by performing an exclusive OR (XOR) logic operation on candidate cells in the modified semiconductor layout design and the target design of the integrated circuit in the target layout design.

19. The device according to claim 14, wherein: The modified version of the target design of an integrated circuit includes at least one of a modification to the integrated circuit in the target design, an additional dummy fill structure in the scope of the target design of an integrated circuit, a wiring layout in the semiconductor layer corresponding to the extracted cell, or a wiring layout in a semiconductor layer higher than the extracted cell.

20. The device according to claim 14, wherein: The instructions are configured to cause one or more processing devices to perform operations, the operations also including: performing the verification of the semiconductor layout design by determining a similarity percentage corresponding to a degree of difference between the candidate design and the target design of the integrated circuit, and comparing the similarity percentage to a threshold to determine that at least one of the extracted cells corresponds to the modified version of the target design of the integrated circuit.

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