Memory and memory module
By setting up the local data lines and reverse-set selection units in each set of memory modules, the compatibility problem of memory prefetch reduction and data wiring optimization is solved, and the effects of prefetch reduction and wiring optimization are achieved, supporting chip size reduction and wiring reliability improvement.
Patent Information
- Application Number
- CN202411450801.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2025-02-25
AI Technical Summary
In the case where memory prefetching is needed, it is difficult to take into account the reduction of prefetching and optimization of data wiring, resulting in adverse effects on memory data processing speed and chip size.
By setting the local data lines of odd and even amplifiers in each set of memory modules through connection, the first stage amplifiers in each memory module share the local data lines with each other, and the selection unit is set at the opposite end of the corresponding amplifier to reduce the cross-parallel arrangement of the main data lines.
On the premise of maintaining the constant number of word lines in the first stage amplifier, the reduction of prefetching is achieved by increasing the load of local data lines, while optimizing the layout of the main data lines, reducing chip size and improving wiring reliability.
Smart Images
Figure CN119517101A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a memory and a memory module. Background Art
[0002] With the development of various electronic products, the performance requirements for memory are getting higher and higher. The performance of memory is closely related to the wiring status of its data lines.
[0003] In some cases where it is necessary to reduce memory prefetch, it is often difficult to balance the reduction of prefetch and the optimization of data line wiring, thereby adversely affecting the data processing speed of the memory and / or the size of the chip. Summary of the invention
[0004] In view of the above problems, the present invention is proposed to provide a memory and a memory module that overcome the above problems or at least partially solve the above problems.
[0005] In a first aspect, a memory is provided, comprising:
[0006] K groups of storage modules, each group of the storage modules includes at least two adjacent sub-storage modules, each of the sub-storage modules includes a storage array and two first-stage amplifiers; the two first-stage amplifiers are an odd-numbered amplifier and an even-numbered amplifier, which are respectively located at two sides of the storage array and are respectively connected to corresponding selection units via local data lines;
[0007] Wherein, in each group of the storage modules, the local data lines of the odd-numbered amplifiers are connected through and shared, and the local data lines of the even-numbered amplifiers are connected through and shared;
[0008] Among them, in each of the sub-storage modules, the selection unit connected to the odd amplifier is set at the first direction end of the odd amplifier; the selection unit connected to the even amplifier is set at the second direction end of the even amplifier, and the first direction is set opposite to the second direction.
[0009] Optionally, in each group of the storage modules, any of the odd-numbered amplifiers is connected to the selection units corresponding to each of the odd-numbered amplifiers; and any of the even-numbered amplifiers is connected to the selection units corresponding to each of the even-numbered amplifiers.
[0010] Optionally, in each group of the storage modules, the selection units connected to the odd amplifiers are all arranged at the same direction end of the corresponding odd amplifiers; and the selection units connected to the even amplifiers are all arranged at the same direction end of the corresponding even amplifiers.
[0011] Optionally, each group of the storage modules further includes: a main data line and a second-stage amplifier, the selection units are connected to the second-stage amplifier via the main data line, and the second-stage amplifier is connected to the input and output channels of the memory to transmit data.
[0012] Optionally, in each group of the storage modules, the number of the sub-storage modules is A, and the second-stage amplifiers are divided into A groups, where A is an integer greater than 1; wherein the second-stage amplifiers in group A are connected one-to-one with the selection units of A sub-storage modules, and wherein each group of the second-stage amplifiers corresponds to the sub-storage module that is closest to it.
[0013] Optionally, each group of the second-stage amplifiers is divided into two sub-groups, the two sub-groups respectively corresponding to the odd amplifiers and the even amplifiers, and respectively connected to the selection units of the corresponding amplifiers; wherein the sub-group corresponding to the odd amplifiers is located at the first direction end of the second-stage amplifiers of the group; and the sub-group corresponding to the even amplifiers is located at the second direction end of the second-stage amplifiers of the group.
[0014] Optionally, in any of the sub-storage modules, the selection unit corresponding to each first-stage amplifier is connected to the second-stage amplifier through a group B of main data lines; the number of main data line channels in the area where the second-stage amplifier corresponding to the sub-storage module is located is B groups, and B is an integer greater than 1.
[0015] Optionally, in each group of the sub-storage modules, the maximum transmission delay of the data in the area where the second-stage amplifier is located is less than or equal to one half of the total delay of the second-stage amplifier; wherein the total delay of the second-stage amplifier is the delay of the data crossing a group of second-stage amplifiers corresponding to the group of the sub-storage modules along the arrangement direction of the second-stage amplifiers.
[0016] Optionally, in each group of the storage modules: the number of the sub-storage modules is 2; the local data lines of the two odd amplifiers are connected through, so that any one of the odd amplifiers is connected to the selection units corresponding to the two odd amplifiers; the local data lines of the two even amplifiers are connected through, so that any one of the even amplifiers is connected to the selection units corresponding to the two even amplifiers; the selection units connected to the two odd amplifiers are all arranged at the first direction end of the corresponding odd amplifiers; and the selection units connected to the two even amplifiers are all arranged at the second direction end of the corresponding even amplifiers.
[0017] In a second aspect, a memory module is provided, which includes a communication module, a power module and a storage module, wherein: the power module is used to provide power to the memory module; the storage module is used to store data and instructions; the communication module is used for internal communication within the memory module, or for the memory module to communicate with external devices; and the storage module includes any memory described in the first aspect.
[0018] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:
[0019] The memory and memory module provided by the embodiment of the present invention are arranged in each group of storage modules, and the local data lines of the odd amplifiers are connected through, and the local data lines of the even amplifiers are also connected through, so that the first-stage amplifiers in each storage module share the local data lines with each other, thereby reducing the pre-fetching by increasing the load of the local data lines under the premise of maintaining the number of word lines in the first-stage amplifier unchanged. In addition, a selection unit connected to the odd amplifier and a selection unit connected to the even amplifier are respectively arranged at the opposite direction ends of the corresponding amplifiers, thereby avoiding excessive overlap and parallel arrangement of the two groups of main data lines respectively connected to the odd amplifier and the even amplifier, which can reduce the group number density of the main data line layout, optimize the dispersed layout of the main data line channels, and provide support for chip size reduction and wiring reliability.
[0020] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0022] Figure 1 A schematic diagram of the structure of an existing memory in an embodiment of the present invention;
[0023] Figure 2 In the embodiment of the present invention Figure 1 Enlarged schematic diagram of the middle ellipse area;
[0024] Figure 3 A schematic diagram of the structure of a memory provided in an embodiment of the present invention Figure 1 ;
[0025] Figure 4 A schematic diagram of the structure of a memory provided in an embodiment of the present invention Figure 2 ;
[0026] Figure 5 A schematic diagram of the structure of a memory provided in an embodiment of the present invention Figure 3 ;
[0027] Figure 6 A schematic diagram of the structure of a memory provided in an embodiment of the present invention Figure 4 ;
[0028] Figure 7 A schematic diagram of the structure of a memory provided in an embodiment of the present invention Figure 5 ;
[0029] Figure 8 A schematic diagram of the structure of a memory provided in an embodiment of the present invention Figure 6 ;
[0030] Fig. 9 A schematic structural diagram of a memory module is provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0031] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0032] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0033] See also Figure 1, which is a schematic diagram of the structure of an existing memory. The memory array 1 of the memory is controlled by the bit line (WL) and the word line (BL). Among them, the word line (BL) of the memory array 1 is connected to the second-stage amplifier (SSA) 6 through the first-stage amplifier (SA) 2, the local data line (LDQ) 3, the selection unit (SWITCH) 4 and the main data line (MDQ) 5 in sequence. The first-stage amplifier (SA) 2 is mainly responsible for the first-stage amplification of the data. The second-stage amplifier (SSA) 6 is mainly responsible for the second-stage amplification of the data, and transmits the data to the input and output circuit (I / O) and the calculation unit on the logic chip through the read and write data line (RWDL). The connection method between the memory array 1 and the first-stage amplifier (SA) 2 in the memory is an open word line (openbitline) structure. In this connection method, the input end of the first-stage amplifier 2 comes from two different memory arrays 1, and one memory array 1 is connected to two first-stage amplifiers 2 located on the left and right sides respectively. That is, each sub-storage module includes two first-stage amplifiers 2, namely an odd amplifier 21 and an even amplifier 22. The two first-stage amplifiers 2 are respectively located on both sides of the storage array 1 and are respectively connected to the corresponding selection units 4 via local data lines 3.
[0034] See also Figure 2 ,for Figure 1 Enlarged schematic diagram of the elliptical area in the middle. When the WL of the storage cell in the storage array 1 is turned on, the charge in the capacitor is shared with the charge of the BL to change the voltage of the BL. After the voltage difference between a pair of BLs is amplified by the first-stage amplifier 2, the data is sequentially transmitted through the local data line 3, the selection unit 4, and the main data line 5 to the second-stage amplifier 6 for amplification, and finally the data is sent to the input and output circuit.
[0035] Figure 2The elliptical track in the middle represents the transmission path of the data of the farthest storage unit from BL to the second-stage amplifier 6 (i.e., the farthest transmission path), the dotted line represents the connection mode of the odd amplifier 21 via LDQ, SWITCH, MDQ and SSA (the arrow represents the data transmission direction), and the solid line represents the connection mode of the even amplifier 22 via LDQ, SWITCH, MDQ and SSA (the arrow represents the data transmission direction). The delay of the data of the farthest storage unit on the transmission path from BL to the second-stage amplifier 6 is the sum of the first delay T1, the second delay T2 and the third delay T3, wherein T1 is the delay of the data crossing a single first-stage amplifier 2 along the direction from the first-stage amplifier 2 to the selection unit 4, i.e., the maximum delay from BL to the selection unit 4 (according to the conventional layout, T1 is the maximum load delay of the LDQ parallel to the WL direction). T2 is the delay of the data transmission on the main data line 5 (according to the conventional layout, T2 is the metal line delay of the MDQ parallel to the BL direction). T3 is the maximum delay of data transmission in the layout area of the second-stage amplifier 6 (according to conventional layout, T3 is the maximum delay of the metal line parallel to the WL direction).
[0036] See also Figure 3 The present application provides a memory, comprising: K groups of storage modules 301, each group of storage modules 301 comprises at least two adjacently arranged sub-storage modules 302, and each sub-storage module 302 comprises a storage array 1 and two first-stage amplifiers 2. The two first-stage amplifiers 2 are odd amplifiers 21 and even amplifiers 22, which are respectively located on both sides of the storage array 1, and are respectively connected to the corresponding selection units 4 via local data lines 3. In each group of storage modules 301, the local data lines 3 of each odd amplifier 21 are connected through and shared, and the local data lines 3 of each even amplifier 22 are connected through and shared. In each sub-storage module 302, the selection unit 4 connected to the odd amplifier 21 is arranged at the first direction end of the odd amplifier 21; the selection unit 4 connected to the even amplifier 22 is arranged at the second direction end of the even amplifier 22, and the first direction 303 is arranged opposite to the second direction 304.
[0037] Specifically, in the case where the memory prefetch needs to be reduced (for example, the prefetch of LDDR3 X32 mode is 8*N, and the prefetch of LPDDR2 X32 mode is 4*N, where N is the number of data pins), in each group of storage modules 301, local data lines 3 of multiple sub-storage modules 302 are set to be connected through, so that the first-stage amplifiers 2 in each sub-storage module 302 share the local data lines 3, thereby reducing the prefetch by increasing the load of the local data lines 3 while maintaining the number of word lines in the first-stage amplifier 2 unchanged. Assuming that the prefetch is M when there is no shared local data line between the sub-storage modules 302, then if there are A sub-storage modules 302 in each group of storage modules 301, and the local data lines 3 of the A sub-storage modules 302 are connected through for sharing, then the prefetch is That is, when A is equal to 2, the prefetch is When A is equal to 4, the prefetch is
[0038] It should be noted that, for the open word line structure, the local data lines 3 between the sub-storage modules 302 are connected through, so that in each group of storage modules 301, any odd amplifier 21 is connected to the selection unit 4 corresponding to each odd amplifier 21; any even amplifier 22 is connected to the selection unit 4 corresponding to each even amplifier 22.
[0039] In an optional embodiment, each group of storage modules 301 also includes: a main data line 5 and a second-stage amplifier 6, and the selection unit 4 is connected to the second-stage amplifier 6 through the main data line 5, and the second-stage amplifier 6 is connected to the input and output channels of the memory to transmit data.
[0040] See also Figure 4 , Figure 4 The elliptical track in the middle represents the transmission path of the data of the farthest storage unit from BL to the second-stage amplifier 6 (i.e., the farthest transmission path), the dotted arrow is the transmission direction of the data output by the odd amplifier 21, and the solid arrow represents the transmission direction of the data output by the even amplifier 22. It can be seen that if the setting position of the selection unit 4 is not improved and it is set on the same side of the odd amplifier 21 and the even amplifier 22, then in a group of storage modules 301, the data output by the odd amplifier 21 is transmitted to the second-stage amplifier 6, and the transmission route of the data output by the even amplifier 22 is transmitted to the second-stage amplifier 6 is almost overlapped, that is, the two parts of the main data line 5 respectively connected to the odd amplifier 21 and the even amplifier 22 are almost mostly overlapped and arranged in parallel. This requires more routing groups to be arranged in the overlapping arrangement area of the main data line, resulting in an increase in the group density of the main data line layout, which will have an adverse effect on the chip size and wiring reliability.
[0041] And, if Figure 4 As shown, if the setting position of the selection unit 4 is not improved, the delay of the data transmission path of the farthest storage unit will be increased. Taking the number of sub-storage modules 302 in each group of storage modules 301 as 2, for the farthest storage unit, the delay of its data on the transmission path from BL to the second-stage amplifier 6 is 2*T1+T2+2*T3, where T1 is the first delay, T2 is the second delay, and T3 is the third delay. Figure 2 The T1, T2 and T3 marked in are the same. It can be seen that when two sub-storage modules 302 share the local data line 3, although pre-fetching can be reduced, since the data may cross multiple first-stage amplifiers 2 to reach the selection unit 4, the maximum delay of data transmission from BL to the selection unit 4 will be increased by at least 2*T1. In addition, due to the reduction of pre-fetching, the same number of second-stage amplifiers 6 need to be arranged in the areas of multiple sub-storage modules 302, so the gaps between the second-stage amplifiers 6 will be increased, which will also cause the maximum delay of data transmission in the arrangement area of the second-stage amplifiers 6 to increase to 2*T3.
[0042] See also Figure 5 , Figure 5 The middle elliptical track represents the transmission path (i.e., the farthest transmission path) of the data of the farthest storage unit from BL to the second-stage amplifier 6, the dotted arrow is the data flow direction of the odd amplifier 21, and the solid arrow is the data flow direction of the even amplifier 22. The present application sets the selection unit 4 connected to the odd amplifier 21, and the selection unit 4 connected to the even amplifier 22 are respectively set at the opposite direction ends of the corresponding amplifiers, thereby avoiding the overlapping and parallel arrangement of the two parts of the main data line 5 respectively connected to the odd amplifier 21 and the even amplifier 22, which can reduce the group number density of the main data line layout and optimize the dispersed layout of the main data line channel.
[0043] Specifically, in each group of storage modules 301, the data transmission path from the selection unit 4 to the second-stage amplifier 6 can be divided into two sections. The first section is the transmission path from the selection unit 4 to the layout area of the second-stage amplifier 6, which is a metal line of MDQ parallel to the BL direction according to the conventional layout. The second section is the transmission path within the layout area of the second-stage amplifier 6, which is a metal line parallel to the WL direction according to the conventional layout. Using the solution provided by this application: Figure 5As shown, on the first transmission path, the data lines connected to the odd amplifier 21 and the data lines connected to the even amplifier 22 can be arranged in a staggered manner, with only a small overlap in the area between the sub-storage modules 302; on the second transmission path, in a single sub-storage module 302, the main data lines 6 connected to the odd amplifier 21 and the even amplifier 22 are connected to the second-stage amplifier 6 from the upper and lower sides of the sub-storage module 302, respectively, so in the arrangement area of the second-stage amplifier 6, the starting points of the two main data transmission paths are different, and the transmission directions are also different, so non-overlapping arrangement can be achieved, reducing the number of wiring groups in this area. In this way, by dispersing the layout of the main data lines 6, the number of wiring groups in the data transmission path area can be reduced, which can help reduce the chip size and reduce the reliability problems caused by excessive data line density.
[0044] For example, using the solution provided by this application, such as Figure 5 As shown, after the selection units 4 of the odd amplifier 21 and the even amplifier 22 are reversely staggered, it is assumed that in any sub-storage module 302, the selection units 4 corresponding to each first-stage amplifier 2 are connected to the second-stage amplifier 6 through the B-group main data lines 5. Then, on the above-mentioned second transmission path, since the data transmission starting points of the two parts of the main data lines are respectively located at the two ends of the arrangement area of the second-stage amplifier 6, and the transmission directions are opposite, it can be achieved that the main data lines corresponding to the odd and even amplifiers are completely non-overlappingly arranged on the above-mentioned second transmission path, so the number of main data line channels in the area where the second-stage amplifier 6 of the sub-storage module 302 is located is B groups, and B is an integer greater than 1. If the Figure 4 In the scheme shown, since the data transmission starting points of the two parts of the main data lines are the same and the transmission directions are the same on the second transmission path, they inevitably need to be overlapped, so the number of main data line channels in the arrangement area of the second-stage amplifier 6 is 2*B groups. It can be seen that the scheme of the present application can reduce the number of main data line channels in the area where the second-stage amplifier 6 is located by half.
[0045] In an optional embodiment, the number A of sub-storage modules 302 included in each group of storage modules 301 can be an even number such as 2, 4 or 6, which is not limited here. Figure 5 The layout shown in the figure can be used when A is equal to 4. Figure 6 The layout shown ensures that the selection unit 4 connected to the odd amplifier 21 and the selection unit 4 connected to the even amplifier 22 are arranged at opposite ends of the corresponding amplifiers.
[0046] In an optional implementation, in each group of storage modules 301, the selection units 4 connected to the odd amplifiers 21 are all arranged at the same direction end of the corresponding odd amplifiers 21; the selection units 4 connected to the even amplifiers 22 are all arranged at the same direction end of the corresponding even amplifiers 22. In this way, not only can the overlapping length of the two groups of data lines be minimized, but also the regularity of the wiring can be taken into account to avoid line reliability problems. Of course, in the specific implementation process, it can also be as follows Figure 7 As shown, it is only ensured that in a single sub-storage module 302, the selection unit 4 connected to the odd amplifier 21 and the selection unit 4 connected to the even amplifier 22 are set at the opposite direction ends of the corresponding amplifiers, and each group of sub-storage modules 302 is not required to maintain the same setting of the selection unit 4, and no limitation is made here.
[0047] In an optional implementation, the second-stage amplifiers 6 can also be grouped to reduce delay. That is, it can be set that in each group of storage modules 301, the number of sub-storage modules 302 is A, and the corresponding second-stage amplifiers 6 are also divided into A groups, where A is an integer greater than 1. Among them, the A groups of second-stage amplifiers 6 are connected to the selection units of the A sub-storage modules 302 in a one-to-one correspondence, and each group of second-stage amplifiers 6 corresponds to the sub-storage module 302 that is closest to it. For example, Figure 5 As shown, the second-stage amplifier 6 on the lower right side is connected to the selection unit 4 of the sub-storage module 302 on the lower left side, and the second-stage amplifier 6 on the upper right side is connected to the selection unit 4 of the sub-storage module 302 on the upper left side. In this way, data will only be transmitted to the group of second-stage amplifiers 6 that are closest, and will not cross to other second-stage amplifiers 6 in more distant areas, thereby reducing transmission delay.
[0048] In an optional embodiment, each group of second-stage amplifiers 6 may be further divided into two subgroups, the two subgroups respectively corresponding to the odd-numbered amplifiers 21 and the even-numbered amplifiers 22, and respectively connected to the corresponding amplifier selection units 4. The subgroup corresponding to the odd-numbered amplifiers 21 is located at the first direction end of the group of second-stage amplifiers 6; the subgroup corresponding to the even-numbered amplifiers 22 is located at the second direction end of the group of second-stage amplifiers 6.
[0049] Specifically, since each sub-storage module 302 has two first-stage amplifiers 2, one odd and one even, each group of second-stage amplifiers 6 is divided into two sub-groups, which are connected to the odd amplifiers 21 and the even amplifiers 22 in a one-to-one correspondence. In addition, in each sub-storage module 302, the sub-group corresponding to the odd amplifier 21 is located at the first direction end of the group of second-stage amplifiers 6, and the selection unit 4 corresponding to the odd amplifier 21 is also located at the first direction end of the odd amplifier 21. The sub-group corresponding to the even amplifier 22 is located at the second direction end of the group of second-stage amplifiers 6, and the selection unit 4 corresponding to the even amplifier 22 is also located at the second direction end of the even amplifier 22. In other words, the sub-group and the selection unit 4 corresponding to the same first-stage amplifier 2 are both arranged on the same side, so that data will only be transmitted to the sub-group of second-stage amplifiers 6 that is closest to it, and will not cross to other second-stage amplifiers 6 in a farther area, further reducing transmission delay.
[0050] For example, Figure 8 As shown, it is assumed that the number of sub-storage modules 302 in each group of storage modules 301 is 2. Set the second-stage amplifier 6 marked with a to be connected to the selection unit 4 (marked with a) corresponding to the odd-numbered amplifier 21 marked with a, the second-stage amplifier 6 marked with b to be connected to the selection unit 4 (marked with b) corresponding to the odd-numbered amplifier 21 marked with b, the second-stage amplifier 6 marked with c to be connected to the selection unit 4 (marked with c) corresponding to the even-numbered amplifier 22 marked with c, and the second-stage amplifier 6 marked with d to be connected to the selection unit 4 (marked with d) corresponding to the even-numbered amplifier 22 marked with d.
[0051] Specifically, the solution provided by the present application not only reduces the number of channel groups of the main data line 5, but also optimizes the data transmission delay. In each group of sub-storage modules 302, the maximum transmission delay of the data in the area where the second-stage amplifier 6 is located is less than or equal to one-half of the total delay of the second-stage amplifier. The total delay of the second-stage amplifier refers to the delay of the data crossing a group of second-stage amplifiers 6 corresponding to the group of sub-storage modules 302 along the arrangement direction of the second-stage amplifiers 6. That is to say, since the selection unit 4 of the odd amplifier 21 and the even amplifier 22 is reversely staggered, in the arrangement area of the second-stage amplifier 6, the data transmission starting points of the two parts of the main data lines connected to the odd amplifier 21 and the even amplifier 22 are respectively located at the two ends of the arrangement area, and the transmission directions are opposite. Since each group of the second-stage amplifier 6 is further divided into two sub-groups, and their positions are set to correspond to the odd / even amplifiers respectively, when the data is transmitted to the second-stage amplifier 6, it does not need to cross all or most of the second-stage amplifiers 6, but only needs to be transmitted in the area where the corresponding sub-group is located. Therefore, for the farthest storage unit, compared with Figure 4 The solution can reduce the total delay of the second-stage amplifier by half, that is, it can reduce the delay of at least one T3.
[0052] For example, Figure 5 As shown, it is assumed that the number of sub-storage modules 302 in each group of storage modules 301 is 2. The local data lines 3 of the two odd amplifiers 21 are connected through, so that any odd amplifier 21 is connected to the selection units 4 corresponding to the two odd amplifiers 21; the local data lines 3 of the two even amplifiers 22 are connected through, so that any even amplifier 22 is connected to the selection units 4 corresponding to the two even amplifiers 22. And the selection units 4 connected to the two odd amplifiers 21 are all arranged at the first direction end of the corresponding odd amplifier 21; the selection units 4 connected to the two even amplifiers 22 are all arranged at the second direction end of the corresponding even amplifier 22. After such improvement, the arrangement of the main data lines can be dispersed and the number of lines can be reduced.
[0053] Continuing with the above example, the second-stage amplifiers 6 are further grouped, and the second-stage amplifiers 6 corresponding to each group of sub-storage modules 302 are divided into two sub-groups, corresponding to the odd amplifiers 21 and the even amplifiers 22, respectively, and are arranged at the same direction end as the corresponding selection unit 4. Therefore, in the arrangement area of the second-stage amplifiers 6, the data transmission starting points of the two parts of the main data lines connected to the odd amplifiers 21 and the even amplifiers 22 are respectively located at the two ends of the area, and the transmission directions are opposite. And due to the position division of the sub-groups, the data does not need to cross all or most of the second-stage amplifiers 6, but only needs to be transmitted in the area where the corresponding sub-group is located, and the transmission delay of this part is significantly reduced. In this way, Figure 5 As shown, for the most remote storage unit, the delay of its data on the transmission path from BL to the second-stage amplifier 6 is 2*T1+T2+T3, where T1 is the aforementioned first delay, T2 is the aforementioned second delay, and T3 is the aforementioned third delay. Figure 2 The T1, T2 and T3 marked in are the same. Figure 4 According to the scheme, the maximum transmission delay of data in the arrangement area of the second-stage amplifier 6 is reduced from 2*T3 to T3.
[0054] Based on the same inventive concept, the embodiment of the present invention further provides a memory module 900, such as Fig. 9 As shown, the memory module 900 includes a communication module 901, a power module 902 and a storage module 903, wherein: the power module 902 is used to provide power to the memory module; the storage module 903 is used to store data and instructions; the communication module 901 is used for internal communication within the memory module, or for the memory module to communicate with external devices; the storage module 903 includes any memory provided by the embodiments of the present invention.
[0055] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:
[0056] The memory and memory module provided by the embodiment of the present invention are arranged in each group of storage modules, and the local data lines of the odd amplifiers are connected through, and the local data lines of the even amplifiers are also connected through, so that the first-stage amplifiers in each storage module share the local data lines with each other, thereby maintaining the number of word lines in the first-stage amplifier unchanged, and achieving the expected reduction by increasing the load of the local data lines. In addition, a selection unit connected to the odd amplifier and a selection unit connected to the even amplifier are respectively arranged at the opposite direction ends of the corresponding amplifiers, thereby avoiding excessive overlap and parallel arrangement of two groups of main data lines respectively connected to the odd amplifier and the even amplifier, which can reduce the group number density of the main data line layout, optimize the dispersed layout of the main data line channels, and provide support for chip size reduction and wiring reliability.
[0057] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages can be utilized to realize the content of the present invention described herein, and the description of the above specific languages is for disclosing the best mode of the present invention.
[0058] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.
[0059] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.
[0060] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.
[0061] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.
[0062] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "one" or "an" preceding a component does not exclude the presence of a plurality of such components. The present invention may be implemented by means of hardware comprising a number of different components and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.
Claims
1. A memory, characterized in that: include: K groups of storage modules, each group of the storage modules includes at least two adjacent sub-storage modules, each of the sub-storage modules includes a storage array and two first-stage amplifiers; the two first-stage amplifiers are an odd-numbered amplifier and an even-numbered amplifier, which are respectively located at two sides of the storage array and are respectively connected to corresponding selection units via local data lines; Wherein, in each group of the storage modules, the local data lines of the odd-numbered amplifiers are connected through and shared, and the local data lines of the even-numbered amplifiers are connected through and shared; Among them, in each of the sub-storage modules, the selection unit connected to the odd amplifier is set at the first direction end of the odd amplifier; the selection unit connected to the even amplifier is set at the second direction end of the even amplifier, and the first direction is set opposite to the second direction.
2. The memory according to claim 1, wherein: In each group of the storage modules, any of the odd-numbered amplifiers is connected to the selection units corresponding to the odd-numbered amplifiers; and any of the even-numbered amplifiers is connected to the selection units corresponding to the even-numbered amplifiers.
3. The memory according to claim 1, wherein: In each group of the storage modules, the selection units connected to the odd amplifiers are all arranged at the same direction end of the corresponding odd amplifiers; and the selection units connected to the even amplifiers are all arranged at the same direction end of the corresponding even amplifiers.
4. The memory according to claim 1, wherein: Each group of storage modules also includes: A main data line and a second-stage amplifier, the selection units are connected to the second-stage amplifier through the main data line, and the second-stage amplifier is connected to the input and output channels of the memory to transmit data.
5. The memory according to claim 4, wherein: In each group of the storage modules, the number of the sub-storage modules is A, the second-stage amplifiers are divided into A groups, and A is an integer greater than 1; A groups of the second-stage amplifiers are connected to the selection units of A sub-storage modules in a one-to-one correspondence, and each group of the second-stage amplifiers corresponds to the sub-storage module that is closest to it.
6. The memory according to claim 5, wherein: Each group of the second-stage amplifiers is divided into two sub-groups, the two sub-groups respectively correspond to the odd-numbered amplifiers and the even-numbered amplifiers, and are respectively connected to the selection units of the corresponding amplifiers; The subgroup corresponding to the odd-numbered amplifiers is located at the first direction end of the second-stage amplifiers in the group; and the subgroup corresponding to the even-numbered amplifiers is located at the second direction end of the second-stage amplifiers in the group.
7. The memory according to claim 6, wherein: In any of the sub-storage modules, the selection unit corresponding to each of the first-stage amplifiers is connected to the second-stage amplifier via B groups of main data lines; the number of main data line channels in the area where the second-stage amplifier corresponding to the sub-storage module is located is B groups, and B is an integer greater than 1.
8. The memory according to claim 6, wherein: In each group of the sub-storage modules, the maximum transmission delay of data in the area where the second-stage amplifier is located is less than or equal to one half of the total delay of the second-stage amplifier; The total delay of the second-stage amplifier is the delay of a group of second-stage amplifiers corresponding to the group of sub-storage modules when data crosses the arrangement direction of the second-stage amplifiers.
9. The memory according to claim 1, wherein: In each set of said storage modules: The number of the sub-storage modules is 2; The local data lines of the two odd-numbered amplifiers are connected through, so that any of the odd-numbered amplifiers is connected to the selection units corresponding to the two odd-numbered amplifiers; the local data lines of the two even-numbered amplifiers are connected through, so that any of the even-numbered amplifiers is connected to the selection units corresponding to the two even-numbered amplifiers; The selection units connected to the two odd amplifiers are both arranged at the first direction end of the corresponding odd amplifiers; the selection units connected to the two even amplifiers are both arranged at the second direction end of the corresponding even amplifiers.
10. A memory module, characterized in that: The memory module includes a communication module, a power module and a storage module, wherein: the power module is used to provide power to the memory module; the storage module is used to store data and instructions; the communication module is used for internal communication within the memory module, or for the memory module to communicate with external devices; the storage module includes the memory described in any one of claims 1 to 9.