Nonvolatile memory and configuration method thereof

Abstract

The invention discloses a nonvolatile memory and a configuration method thereof. The nonvolatile memory includes: a memory array for storing data, the memory array including a plurality of memory blocks; a plurality of sets of configuration information are pre-stored in the parameter configuration unit, corresponding configuration information is provided when the nonvolatile memory executes the erasing / writing instruction, and the configuration information is used for configuring working parameters of the storage block corresponding to the erasing / writing instruction; the multiple groups of configuration information comprise a first group of configuration information used for configuring the first storage block and a second group of configuration information used for configuring the second storage block, and under the configuration of the first group of configuration information and the second group of configuration information, at least one working parameter of the first storage block is different from that of the second storage block; therefore, the first storage block and the second storage block bear different abrasion amounts in response to the erase / write instruction. By selecting different configuration parameters, each storage block can adjust the number of executable erase / write instructions according to data storage requirements, and the universality of nonvolatile storage is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a non-volatile memory and a configuration method thereof. Background Art

[0002] Non-volatile memory refers to non-volatile memory that can retain stored data after power is turned off. The storage unit of non-volatile memory is composed of floating gate transistors. For each storage unit in the non-volatile memory, the amount of charge stored in the floating gate layer of the floating gate transistor determines the threshold voltage of the storage unit, and the threshold voltage of the storage unit determines whether the data stored in the storage unit is 0 or 1.

[0003] When a non-volatile memory performs an erase / program operation, the amount of charge in the floating gate layer needs to be changed, which causes the tunneling layer in the floating gate transistor to be continuously worn. The data retention capability of a non-volatile memory mainly depends on how long the charge in the floating gate layer can be retained. If the quality of the tunneling layer decreases, the charge leakage rate will increase, and the data retention capability of the non-volatile memory will decrease. Therefore, non-volatile memory often cannot take into account both the number of erase / program operations and the data retention capability.

[0004] In the prior art, a compromise is usually made between the number of erase / program operations and the data retention capability, which greatly limits the use scenarios of non-volatile memory. Summary of the invention

[0005] In view of the above problems, the purpose of the present application is to provide a non-volatile memory and a configuration method thereof, which can improve the universality of the non-volatile memory.

[0006] According to one aspect of the present application, a non-volatile memory is provided, wherein the non-volatile memory includes: a storage array for storing data, the storage array including multiple storage blocks; a parameter configuration unit, which pre-stores multiple groups of configuration information and provides corresponding configuration information when the non-volatile memory executes an erase / write instruction, the configuration information is used to configure the working parameters of the storage block corresponding to the erase / write instruction, wherein the multiple groups of configuration information include a first group of configuration information for configuring a first storage block and a second group of configuration information for configuring a second storage block, and under the configuration of the first group of configuration information and the second group of configuration information, at least one of the working parameters of the first storage block and the second storage block is different, so that the first storage block and the second storage block are subjected to different amounts of wear in response to the erase / write instruction.

[0007] Optionally, under the configuration of the first set of configuration information, the first storage block performs n erase / program operations in response to the erase / write instruction, and / or under the second set of configuration information, the second storage block performs m erase / program operations in response to the erase / write instruction, n and m are both positive integers, and m>n.

[0008] Optionally, the parameter configuration unit includes: a configuration register, which determines the corresponding storage block according to the received erase / write instruction and provides a corresponding selection signal; and a parameter register, which pre-sets multiple groups of the configuration information and provides the corresponding configuration information to the storage block corresponding to the erase / write instruction according to the selection signal.

[0009] Optionally, each of the storage blocks includes multiple storage cells, each of the storage cells includes a floating gate transistor, and the operating parameters include: a gate voltage, a drain voltage and a substrate voltage of the floating gate transistor; during a programming operation, the gate voltage and the drain voltage corresponding to the first set of configuration information are greater than the gate voltage and the drain voltage corresponding to the second set of configuration information; during an erasing operation, a starting negative voltage of the gate voltage and a starting positive voltage of the substrate voltage corresponding to the first set of configuration information are greater than a starting negative voltage of the gate voltage and a starting positive voltage of the substrate voltage corresponding to the second set of configuration information.

[0010] Optionally, the non-volatile memory also includes a circuit unit, which receives the configuration parameters and provides corresponding operating parameters, and the circuit unit includes: a gate voltage generating module, which provides the gate voltage of the floating gate transistor; a drain voltage generating module, which provides the drain voltage of the floating gate transistor; and a substrate voltage generating module, which provides the substrate voltage of the floating gate transistor.

[0011] Optionally, the operating parameters also include a programming verification voltage and an erasure verification voltage, and the circuit unit also includes a verification voltage generating module for generating the programming verification voltage or the erasure verification voltage, and in the programming verification phase of the programming operation, the programming verification voltage corresponding to the first group of configuration information is greater than the programming verification voltage corresponding to the second group of configuration information; in the erasure verification phase of the erasure operation, the erasure verification voltage corresponding to the first group of configuration information is less than the erasure verification voltage corresponding to the second group of configuration information.

[0012] Optionally, the operating parameters also include a reference current, the circuit unit also includes a reference current generating module to provide the reference current, the non-volatile memory compares the reference current with the corresponding detection current of the storage unit to perform programming verification or erasure verification, and in the programming verification stage, the reference current corresponding to the first group of configuration information is smaller than the reference current corresponding to the second group of configuration information; in the erasure verification stage, the reference current corresponding to the first group of configuration information is larger than the reference current corresponding to the second group of configuration information.

[0013] Optionally, the operating parameters also include a single power supply duration of the gate voltage in the programming operation or the erasing operation, and the non-volatile memory also includes a control unit, which adjusts the single power supply duration of the gate voltage according to the configuration information, and in the programming operation or the erasing operation, the single power supply duration of the gate voltage corresponding to the first set of configuration information is greater than the single power supply duration of the gate voltage corresponding to the second set of configuration information.

[0014] According to another aspect of the present application, a configuration method for a non-volatile memory is provided, wherein the storage array of the non-volatile memory includes multiple storage blocks, wherein the configuration method includes: pre-storing multiple groups of configuration information; providing corresponding configuration information to corresponding storage blocks according to erase / write instructions; and configuring working parameters of corresponding storage blocks according to the configuration information, wherein the multiple groups of configuration information include a first group of configuration information for configuring a first storage block and a second group of configuration information for configuring a second storage block, and under the configuration of the first group of configuration information and the second group of configuration information, at least one of the working parameters of the first storage block and the second storage block is different, so that the first storage block and the second storage block experience different amounts of wear in response to the erase / write instructions.

[0015] Optionally, under the configuration of the first set of configuration information, the first storage block performs n erase / program operations in response to the erase / write instruction, and / or under the second set of configuration information, the second storage block performs m erase / program operations in response to the erase / write instruction, n and m are both positive integers, and m>n.

[0016] Optionally, providing the corresponding configuration information to the corresponding storage block according to the erase / write instruction includes: receiving the erase / write instruction; determining the storage block corresponding to the erase / write instruction; providing a selection signal according to the determined storage block; and selecting the corresponding configuration information from multiple groups of configuration information according to the selection signal.

[0017] Optionally, each of the storage blocks includes multiple storage cells, each of the storage cells includes a floating gate transistor, and configuring the working parameters of the corresponding storage block according to the configuration information includes: configuring the gate voltage, drain voltage and substrate voltage of each floating gate transistor of the storage block, during a programming operation, the gate voltage and the drain voltage corresponding to the first set of configuration information are greater than the gate voltage and the drain voltage corresponding to the second set of configuration information; during an erasing operation, the starting negative voltage of the gate voltage and the starting positive voltage of the substrate voltage corresponding to the first set of configuration information are greater than the starting negative voltage of the gate voltage and the starting positive voltage of the substrate voltage corresponding to the second set of configuration information.

[0018] Optionally, the operating parameters also include a programming verification voltage and an erasure verification voltage. In the programming verification phase of the programming operation, the programming verification voltage corresponding to the first group of configuration information is greater than the programming verification voltage corresponding to the second group of configuration information; in the erasure verification phase of the erasure operation, the programming verification voltage corresponding to the first group of configuration information is less than the programming verification voltage corresponding to the second group of configuration information.

[0019] Optionally, configuring the working parameters of each storage block according to the corresponding configuration information also includes: configuring a reference current of the non-volatile memory, the non-volatile memory comparing the reference current with the detection current of the corresponding storage unit to perform programming verification or erasure verification, in the programming verification stage, the reference current corresponding to the first group of configuration information is smaller than the reference current corresponding to the second group of configuration information; in the erasure verification stage, the reference current corresponding to the first group of configuration information is larger than the reference current corresponding to the second group of configuration information.

[0020] Optionally, configuring the working parameters of each storage block according to the corresponding configuration information also includes: configuring a single power supply duration of the gate voltage, wherein in the programming operation or the erasing operation, the single power supply duration of the gate voltage corresponding to the first set of configuration information is greater than the single power supply duration of the gate voltage corresponding to the second set of configuration information.

[0021] According to the non-volatile memory and configuration method thereof provided by the present application, multiple storage blocks are set and multiple groups of configuration information are preset. Under the working parameters corresponding to each group of configuration information, the amount of wear and tear of the storage block in response to the erase / write instruction is different. In other words, different storage blocks corresponding to different configuration information have different numbers of executable erase / write instructions. Therefore, by selecting different configuration parameters, each storage block can adjust the number of executable erase / write instructions according to data storage requirements, thereby improving the universality of the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0023] Figure 1 A schematic structural diagram of a floating gate transistor is shown;

[0024] Figure 2 A schematic structural diagram of a non-volatile memory according to an embodiment of the present application is shown;

[0025] Figure 3 A flow chart of a configuration method of a non-volatile memory according to an embodiment of the present application is shown;

[0026] Figure 4 A schematic flow chart of providing corresponding configuration information to corresponding storage blocks according to erase / write instructions is shown. DETAILED DESCRIPTION

[0027] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0028] At the same time, certain words are used in this specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0029] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0030] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0031] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0032] Non-volatile memory (NVM) is a non-volatile memory that does not lose data after power failure, so it can be used to store data for a long time. In non-volatile memory, there are three basic operations: erase, program, and read. In most cases, before programming the non-volatile memory, an erase operation needs to be performed to delete the previously stored data, and then new data is written through programming.

[0033] In non-volatile memory, data is erased / written in memory blocks. Each memory block includes multiple memory cells. Each memory cell can store a preset number of bits of data (hereinafter, each memory cell stores a binary number as an example). The memory cell is usually composed of a floating gate transistor. Figure 1 FIG. 2 shows a schematic structural diagram of a floating gate transistor. Figure 1 As shown, the floating gate transistor 10 includes a semiconductor substrate 11, a source region 12 and a drain region 13 located in the semiconductor substrate, and a floating gate structure 14 located between the source region 12 and the drain region 13. An electrode, namely a source 15 and a drain 16, is connected to each of the source region 12 and the drain region 13. The floating gate structure 14 includes a first oxide layer 141, a floating gate layer 142, a second oxide layer 143 and a control gate 144 stacked in sequence. The amount of charge stored in the floating gate layer 142 determines the threshold voltage of the storage cell, and the threshold voltage of the storage cell determines whether the data stored in the storage cell is 0 or 1.

[0034] For example, during the programming operation, by adjusting the voltage of the control gate 144 and the drain 16, the electrons (negative charges) in the substrate 11 pass through the first oxide layer 141 and enter the floating gate layer 142 under the action of the electric field. When the charge in the floating gate layer 142 increases, the threshold voltage of the floating gate transistor 10 increases. The threshold voltage of the floating gate transistor 10 is checked by checking the current in the floating gate transistor. When the threshold voltage is higher than the programming verification voltage, the floating gate transistor is considered to be in a "programmed state", and the data stored in the floating gate transistor is recorded as 0, for example.

[0035] During the erase operation, a positive voltage is applied to the substrate 11 and a negative voltage is applied to the control gate 144, so that the electrons (negative charges) of the floating gate layer 142 pass through the first oxide layer 141 and enter the substrate 11 under the action of the electric field. In some embodiments, the voltage is applied in stages so that the gate voltage of the control gate 144 is increased step by step on the basis of the initial negative voltage, and the substrate voltage of the substrate 11 is increased step by step on the basis of the initial positive voltage, so as to avoid the voltage difference between the substrate 11 and the control gate 144 being too high when the pressure is directly applied, resulting in damage to the floating gate structure. When the charge in the floating gate layer 142 decreases, the threshold voltage of the floating gate transistor decreases. The threshold voltage of the floating gate transistor is checked by checking the current in the floating gate transistor. When the threshold voltage is lower than the erase verification voltage, the floating gate transistor is considered to be in the "erased state", and the data stored in the floating gate transistor is recorded as 1, for example.

[0036] When the non-volatile memory executes an erase instruction, it is necessary to loop through at least one erase operation and erase verification operation to ensure that the data is erased; accordingly, when executing a write instruction, it is also necessary to loop through at least one programming operation and programming verification operation to ensure that the data is written. In the following, the erase / write instruction represents an erase instruction or a write instruction, and the erase / programming operation represents an erase operation or a programming operation performed when executing the corresponding erase instruction or write instruction. As the number of erase / programming operations increases, the number of times that electrons cross the first oxide layer 141 increases, the degree of wear of the first oxide layer 141 also increases, and the charge retention capacity of the floating gate layer decreases accordingly. In some embodiments, a compromise is usually made between the number of erase / programming operations and the data retention capacity, which will limit the use scenarios of the non-volatile memory and fail to meet the singleness requirements for the number of erase / programming operations or the data retention capacity.

[0037] The present application provides a non-volatile memory and a configuration method thereof, which enables each storage block to adjust the number of executable erase / write instructions according to data storage requirements by selecting different configuration parameters, thereby improving the universality of non-volatile storage.

[0038] Figure 2 Schematic diagram of the structure of the non-volatile memory of the embodiment of the present application is shown. Figure 2As shown, the non-volatile memory 100 provided in the present application includes a parameter configuration unit 110 , a control unit 120 , a circuit unit 130 , a row decoder 140 , a column decoder 150 , a reading unit 160 and a storage array 170 .

[0039] The storage array 170 is used to store data. Figure 2 As shown, the memory array 170 includes a plurality of memory blocks (in Figure 2 In the figure, three storage blocks, namely, the first storage block 171-1, the second storage block 171-2 and the third storage block 171-3, are taken as examples. Each storage block includes a plurality of storage cells (not shown in the figure), and each storage cell includes a floating gate transistor for storing data.

[0040] The parameter configuration unit 110 pre-stores multiple sets of configuration information. During the operation of the non-volatile memory 100, the parameter configuration unit 110 provides corresponding configuration information according to the received erase / write instruction, and the configuration information is used to configure the working parameters of the storage block 171 corresponding to the erase / write instruction (i.e., the storage block that executes the erase / write instruction).

[0041] like Figure 2 As shown, by way of example, the parameter configuration unit 110 includes a configuration register 111 and a parameter register 112 that are connected.

[0042] The configuration register 111 receives an erase / write instruction, determines the storage block 171 that executes the erase / write instruction according to the received erase / write instruction, and provides a corresponding selection signal.

[0043] Multiple sets of configuration information are pre-stored in the parameter register 112. The same storage block requires different erase / program operations under different configuration information to execute the same erase / write instruction. The parameter register 112 provides corresponding configuration information according to the selection signal, thereby configuring the working parameters of the storage block 171 according to the storage requirements of the data to adjust the number of executable erase / write instructions of the storage block 171.

[0044] In some embodiments, at least two sets of configuration information are pre-stored in the parameter register 112. And as an example, in the following, the first set of configuration information is used to configure the first storage block 171-1, and the second set of configuration information is used to configure the second storage block 171-2 as an example. Under the configuration of the first set of configuration information, each storage unit in the first storage block 171-1 performs n erase / program operations in response to an erase / write instruction; and / or under the second set of configuration information, each storage unit in the second storage block 171-2 performs m erase / program operations in response to the erase / write instruction. Wherein, n and m are both positive integers, and m>n. That is, for an erase / write instruction, the number of erase / program operations performed by the first storage block configured by the first set of configuration information in response to the erase / write instruction is less than the number of erase / program operations performed by the second storage block configured by the second set of configuration information in response to the erase / write instruction.

[0045] The circuit unit 130 is used to provide the operating parameters required for each storage block 171 to operate according to the configuration information. Specifically, the operating parameters of the storage block 171 include the gate voltage VG (provided to the control gate of the floating gate transistor), the drain voltage VD and the substrate voltage VS of the floating gate transistor in each storage unit in the storage block. Accordingly, the circuit unit 130 includes a gate voltage generation module 131, a drain voltage generation module 132 and a substrate voltage generation module 133 to provide the gate voltage VG, the drain voltage VD and the substrate voltage VS respectively.

[0046] For the above-mentioned first set of configuration information and second set of configuration information, based on the working principle of the floating gate transistor, during the programming operation, the gate voltage and drain voltage corresponding to the first set of configuration information are greater than the gate voltage and drain voltage corresponding to the second set of configuration information; during the erasing operation, the gate voltage corresponding to the first set of configuration information is greater than the gate voltage corresponding to the second set of configuration information.

[0047] It should be noted that during the programming operation / after the erasing operation, in order to verify whether the data is written or erased, programming verification and erasure verification are also required. In some embodiments, programming verification or erasure verification is performed by applying a preset programming verification voltage or erasure verification voltage to the control gate of the floating gate transistor. In this case, the gate voltage is the programming verification voltage / erasure verification voltage. Therefore, for the above-mentioned first set of configuration information and second set of configuration information, in the programming verification stage of the programming operation, the gate voltage corresponding to the first set of configuration information (that is, the programming verification voltage) is greater than the gate voltage corresponding to the second set of configuration information (that is, the programming verification voltage); in the erasure verification stage of the erasure operation, the gate voltage corresponding to the first set of configuration information (that is, the erasure verification voltage) is less than the gate voltage corresponding to the second set of configuration information (that is, the erasure verification voltage).

[0048] However, it should be understood that the present application is not limited to this. For example, in some embodiments, programming verification or erasure verification is performed by a separate verification circuit. Accordingly, the circuit unit 130 also includes a verification voltage generating unit for generating a programming verification voltage in the programming verification stage or generating an erasure verification voltage in the erasure verification stage. Moreover, in the programming verification stage, the programming verification voltage corresponding to the first set of configuration information is greater than the programming verification voltage corresponding to the second set of configuration information; in the erasure verification stage, the erasure verification voltage corresponding to the first set of configuration information is less than the erasure verification voltage corresponding to the second set of configuration information.

[0049] Furthermore, the working parameters of the storage block 171 also include a reference current Iref. The circuit unit 130 also includes a reference current generating module 134. Specifically, the reading unit 160 includes a plurality of comparators (not shown in the figure). The comparator is used to compare the detection current Isen of the corresponding storage unit and the reference current Iref to determine the charge state in the storage unit so as to perform an erase check or a programming check. It should be noted that due to the different preset voltages of the storage unit during the programming check phase or the erase check phase, the current value of the reference current Iref is also different. Corresponding to the above-mentioned first set of configuration information and second set of configuration information, wherein, in the programming check phase, the reference current corresponding to the first set of configuration information is less than the reference current corresponding to the second set of configuration information; in the erase check phase, the reference current corresponding to the first set of configuration information is greater than the reference current corresponding to the second set of configuration information.

[0050] Furthermore, the working parameters of each storage block 171 also include a single power supply duration of the gate voltage. The non-volatile memory 100 also includes a control unit 120, which provides a control signal to the gate voltage generating unit according to the configuration information to adjust the single power supply duration of the gate voltage. Specifically, in some embodiments, a step-by-step erasing / programming operation mode is adopted to avoid over-erasing or over-programming of each storage unit of the storage block 171. In an erasing operation / programming operation, a programming operation / erasing operation is divided into a plurality of programming sub-stages / erasing sub-stages by dividing the total power supply duration of the gate voltage in a programming / erasing operation into a plurality of single power supply durations, and a programming check / erasing check is performed in each programming sub-stage / erasing sub-stage, so that the erasing / writing of the storage unit can be stopped immediately when the erasing check or the programming check is passed. Accordingly, corresponding to the above-mentioned first set of programming information and the second set of programming information, during a programming operation or an erasing operation, the single power supply duration of the gate voltage corresponding to the first set of configuration information is greater than the single power supply duration of the gate voltage corresponding to the second set of configuration information. Therefore, under the second set of configuration information, the storage block can stop erasing / writing the storage cell more promptly, which is beneficial to reducing wear on the floating gate transistor.

[0051] The row decoder 140 and the column decoder 150 address the memory array 170 according to the row address and the column address respectively, and provide the drain voltage VD and the gate voltage VG to the drain and the control gate of the floating gate transistor in the memory cell via the corresponding word line and the column line, so as to perform programming / erasing operations on the memory cell.

[0052] According to the non-volatile memory provided by the present application, multiple storage blocks are set and multiple groups of configuration information are preset. Under the working parameters corresponding to each group of configuration information, the amount of wear and tear of the storage block in response to the erase / write instruction is different. In other words, different storage blocks corresponding to different configuration information have different numbers of executable erase / write instructions. Therefore, by selecting different configuration parameters, each storage block can adjust the number of executable erase / write instructions according to data storage requirements, thereby improving the universality of the non-volatile memory.

[0053] Figure 3 The flowchart of the configuration method of the non-volatile memory of the embodiment of the present application is shown. The storage array of the non-volatile memory includes a plurality of storage blocks, each storage block includes a plurality of storage cells, and each storage cell includes a floating gate transistor for storing data. The non-volatile memory is, for example, the non-volatile memory provided by the present application. Figure 3 As shown, the configuration method of the non-volatile memory of the embodiment of the present application includes the following steps:

[0054] In step S11, multiple sets of configuration information are pre-stored:

[0055] When a non-volatile memory executes an erase instruction, it needs to loop through at least one erase operation and erase verification operation to ensure that the data is erased; accordingly, when a write instruction is executed, it also needs to loop through at least one program operation and program verification operation to ensure that the data is written. The number of erase / program operations required to execute the same erase / write instruction in the same storage block under different configuration information is different.

[0056] In some embodiments, at least two sets of configuration information are pre-stored. And as an example, in the following, the first storage block is configured by the first set of configuration information, and the second storage block is configured by the second set of configuration information. Under the configuration of the first set of configuration information, each storage unit in the first storage block performs n erase / program operations in response to an erase / write instruction; under the second set of configuration information, each storage unit in the second storage block performs m erase / program operations in response to the erase / write instruction. Wherein, n and m are both positive integers, and m>n. That is, for an erase / write instruction, the number of erase / program operations performed by the first storage block configured by the first set of configuration information in response to the erase / write instruction is less than the number of erase / program operations performed by the second storage block configured by the second set of configuration information in response to the erase / write instruction.

[0057] In step S12, corresponding configuration information is provided to the corresponding storage block according to the erase / write instruction:

[0058] Figure 4 FIG. 2 shows a schematic flow of providing corresponding configuration information (i.e., step S12) to corresponding storage blocks according to the erase / write instruction. Figure 4 As shown, this step specifically includes the following steps:

[0059] In step S21, an erase / write instruction is received;

[0060] In step S22, a storage block corresponding to the erase / write instruction is determined;

[0061] In step S23, a selection signal is provided according to the determined storage block;

[0062] In step S24, corresponding configuration information is selected from multiple groups of configuration information according to the selection signal.

[0063] Therefore, in step S12, the configuration information of the corresponding storage block is substantially selected according to the storage requirement of the data corresponding to the erase / write instruction.

[0064] Step S13, configuring the working parameters of the corresponding storage block according to the configuration information:

[0065] The operating parameters include a gate voltage VG (provided to a control gate of the floating gate transistor), a drain voltage VD, and a substrate voltage VS of a floating gate transistor in each memory cell in the memory block.

[0066] For the above-mentioned first set of configuration information and second set of configuration information, based on the working principle of the floating gate transistor, during the programming operation, the gate voltage and drain voltage corresponding to the first set of configuration information are greater than the gate voltage and drain voltage corresponding to the second set of configuration information; during the erasing operation, the gate voltage corresponding to the first set of configuration information is greater than the gate voltage corresponding to the second set of configuration information.

[0067] It should be noted that during the programming operation / after the erasing operation, in order to verify whether the data is written or erased, programming verification and erasure verification are also required. In some embodiments, programming verification or erasure verification is performed by applying a preset programming verification voltage or erasure verification voltage to the control gate of the floating gate transistor. In this case, the gate voltage is the programming verification voltage / erasure verification voltage. Therefore, for the above-mentioned first set of configuration information and second set of configuration information, in the programming verification stage of the programming operation, the gate voltage corresponding to the first set of configuration information (that is, the programming verification voltage) is greater than the gate voltage corresponding to the second set of configuration information (that is, the programming verification voltage); in the erasure verification stage of the erasure operation, the gate voltage corresponding to the first set of configuration information (that is, the erasure verification voltage) is less than the gate voltage corresponding to the second set of configuration information (that is, the erasure verification voltage).

[0068] However, it should be understood that the present application is not limited to this. For example, in some embodiments, programming verification or erasure verification is performed by a separate verification circuit. Accordingly, the circuit unit 130 also includes a verification voltage generating unit for generating a programming verification voltage in the programming verification stage or generating an erasure verification voltage in the erasure verification stage. Moreover, in the programming verification stage, the programming verification voltage corresponding to the first set of configuration information is greater than the programming verification voltage corresponding to the second set of configuration information; in the erasure verification stage, the erasure verification voltage corresponding to the first set of configuration information is less than the erasure verification voltage corresponding to the second set of configuration information.

[0069] Furthermore, the working parameters also include a reference current, and the non-volatile memory compares the reference current with the detection current of the corresponding storage unit to perform programming verification or erasure verification. It should be noted that due to the different preset voltages of the storage unit in the programming verification stage or the erasure verification stage, the current value of the reference current is also different. Corresponding to the above-mentioned first group of configuration information and the second group of configuration information, corresponding to the above-mentioned first group of configuration information and the second group of configuration information, wherein, in the programming verification stage, the reference current corresponding to the first group of configuration information is less than the reference current corresponding to the second group of configuration information; in the erasure verification stage, the reference current corresponding to the first group of configuration information is greater than the reference current corresponding to the second group of configuration information.

[0070] In addition, in some embodiments, the working parameters also include a single power supply duration of the gate voltage. Specifically, in some embodiments, a step-by-step erasing / programming operation is adopted to avoid over-erasing or over-programming of each storage unit of the storage block. In the erasing operation / programming operation, the total power supply duration of the gate voltage in a programming / erasing operation is divided into multiple single power supply durations, so that a programming operation / erasing operation is divided into multiple programming sub-stages / erasing sub-stages, and programming verification / erasing verification is performed in each programming sub-stage / erasing sub-stage, so that the erasing / writing of the storage unit can be stopped immediately when the erasing verification or the programming verification is passed. Correspondingly, corresponding to the above-mentioned first set of programming information and the second set of programming information, during the programming operation or the erasing operation, the single power supply duration of the gate voltage corresponding to the first set of configuration information is greater than the single power supply duration of the gate voltage corresponding to the second set of configuration information, so under the second set of configuration information, the storage block can stop erasing / writing the storage unit more timely, which is conducive to reducing the wear of the floating gate transistor.

[0071] According to the configuration method of the non-volatile memory provided by the present application, multiple storage blocks are set and multiple groups of configuration information are preset. Under the working parameters corresponding to each group of configuration information, the amount of wear and tear of the storage block in response to the erase / write instruction is different. In other words, different storage blocks corresponding to different configuration information have different numbers of executable erase / write instructions. Therefore, by selecting different configuration parameters, each storage block can adjust the number of executable erase / write instructions according to data storage requirements, thereby improving the universality of the non-volatile memory.

[0072] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A non-volatile memory, wherein: The non-volatile memory comprises: A storage array, used for storing data, wherein the storage array comprises a plurality of storage blocks; a parameter configuration unit, pre-stored with multiple sets of configuration information, and providing corresponding configuration information when the non-volatile memory executes an erase / write instruction, wherein the configuration information is used to configure the working parameters of the storage block corresponding to the erase / write instruction, The multiple groups of configuration information include a first group of configuration information for configuring the first storage block and a second group of configuration information for configuring the second storage block. Under the configuration of the first set of configuration information and the second set of configuration information, at least one operating parameter of the first storage block and the second storage block is different, so that the first storage block and the second storage block experience different amounts of wear in response to the erase / write instruction.

2. The nonvolatile memory according to claim 1, wherein: Under the configuration of the first set of configuration information, the first storage block performs n erase / program operations in response to the erase / write instruction, and / or under the second set of configuration information, the second storage block performs m erase / program operations in response to the erase / write instruction, n and m are both positive integers, and m>n.

3. The nonvolatile memory according to claim 1, wherein: The parameter configuration unit includes: A configuration register is configured to determine the corresponding storage block according to the received erase / write instruction and provide a corresponding selection signal; and A parameter register is used to preset a plurality of groups of the configuration information, and to provide corresponding configuration information to the storage block corresponding to the erase / write instruction according to the selection signal.

4. The nonvolatile memory according to claim 2, wherein: Each of the storage blocks includes a plurality of storage cells, each of the storage cells includes a floating gate transistor, and the operating parameters include: a gate voltage, a drain voltage, and a substrate voltage of the floating gate transistor, During a programming operation, the gate voltage and the drain voltage corresponding to the first set of configuration information are greater than the gate voltage and the drain voltage corresponding to the second set of configuration information; During an erase operation, a starting negative voltage of the gate voltage and a starting positive voltage of the substrate voltage corresponding to the first set of configuration information are greater than a starting negative voltage of the gate voltage and a starting positive voltage of the substrate voltage corresponding to the second set of configuration information.

5. The nonvolatile memory according to claim 4, wherein: The non-volatile memory further includes a circuit unit, which receives the configuration parameters and provides corresponding working parameters, and the circuit unit includes: A gate voltage generating module, providing a gate voltage of the floating gate transistor; a drain voltage generating module, providing a drain voltage of the floating gate transistor; and The substrate voltage generating module provides the substrate voltage of the floating gate transistor.

6. The nonvolatile memory according to claim 5, wherein: The operating parameters also include a programming verification voltage and an erasure verification voltage, and the circuit unit also includes a verification voltage generation module for generating the programming verification voltage or the erasure verification voltage. In a programming verification phase of the programming operation, the programming verification voltage corresponding to the first set of configuration information is greater than the programming verification voltage corresponding to the second set of configuration information; In an erase verification phase of the erase operation, the erase verification voltage corresponding to the first set of configuration information is smaller than the erase verification voltage corresponding to the second set of configuration information.

7. The nonvolatile memory according to claim 6, wherein: The operating parameters also include a reference current, The circuit unit further includes a reference current generating module to provide the reference current, and the non-volatile memory compares the reference current with the detection current of the corresponding storage unit to perform programming verification or erasure verification. In the programming verification stage, the reference current corresponding to the first set of configuration information is smaller than the reference current corresponding to the second set of configuration information; In the erase verification phase, the reference current corresponding to the first set of configuration information is greater than the reference current corresponding to the second set of configuration information.

8. The nonvolatile memory according to claim 7, wherein: The operating parameters also include a single power supply duration of the gate voltage in the programming operation or the erasing operation, The non-volatile memory further includes a control unit, which adjusts a single power supply duration of the gate voltage according to the configuration information. In the programming operation or the erasing operation, a single power supply duration of the gate voltage corresponding to the first set of configuration information is greater than a single power supply duration of the gate voltage corresponding to the second set of configuration information.

9. A configuration method for a non-volatile memory, wherein the storage array of the non-volatile memory comprises a plurality of storage blocks, wherein: The configuration method comprises: Pre-store multiple sets of configuration information; Providing the corresponding configuration information to the corresponding storage block according to the erase / write instruction; and According to the configuration information, the working parameters of the corresponding storage block are configured; The multiple groups of configuration information include a first group of configuration information for configuring the first storage block and a second group of configuration information for configuring the second storage block. Under the configuration of the first set of configuration information and the second set of configuration information, at least one operating parameter of the first storage block and the second storage block is different, so that the first storage block and the second storage block experience different amounts of wear in response to the erase / write instruction.

10. The configuration method according to claim 8, wherein: Under the configuration of the first set of configuration information, the first storage block performs n erase / program operations in response to the erase / write instruction, and / or under the second set of configuration information, the second storage block performs m erase / program operations in response to the erase / write instruction, n and m are both positive integers, and m>n.

11. The configuration method according to claim 9, wherein: Providing the corresponding configuration information to the corresponding storage block according to the erase / write instruction comprises: receiving the erase / write instruction; Determine the storage block corresponding to the erase / write instruction; providing a selection signal according to the determined storage block; and The corresponding configuration information is selected from a plurality of groups of configuration information according to the selection signal.

12. The configuration method according to claim 9, wherein: Each of the memory blocks includes a plurality of memory cells, each of the memory cells includes a floating gate transistor, Configuring the working parameters of the corresponding storage block according to the configuration information includes: configuring the gate voltage, drain voltage and substrate voltage of each floating gate transistor of the storage block, During a programming operation, the gate voltage and the drain voltage corresponding to the first set of configuration information are greater than the gate voltage and the drain voltage corresponding to the second set of configuration information; During an erase operation, a starting negative voltage of the gate voltage and a starting positive voltage of the substrate voltage corresponding to the first set of configuration information are greater than a starting negative voltage of the gate voltage and a starting positive voltage of the substrate voltage corresponding to the second set of configuration information.

13. The configuration method according to claim 12, wherein: The operating parameters also include a programming verification voltage and an erasure verification voltage. In a programming verification phase of the programming operation, the programming verification voltage corresponding to the first set of configuration information is greater than the programming verification voltage corresponding to the second set of configuration information; In an erase verification phase of the erase operation, the programming verification voltage corresponding to the first set of configuration information is smaller than the programming verification voltage corresponding to the second set of configuration information.

14. The configuration method according to claim 13, wherein: Configuring the working parameters of each storage block according to the corresponding configuration information also includes: configuring a reference current of the non-volatile memory, wherein the non-volatile memory compares the reference current with a detection current of the corresponding storage unit to perform programming verification or erasure verification, In the programming verification stage, the reference current corresponding to the first set of configuration information is smaller than the reference current corresponding to the second set of configuration information; In the erase verification phase, the reference current corresponding to the first set of configuration information is greater than the reference current corresponding to the second set of configuration information.

15. The configuration method according to claim 14, wherein: Configuring the working parameters of each storage block according to the corresponding configuration information also includes: configuring the single power supply duration of the gate voltage, In the programming operation or the erasing operation, a single power supply duration of the gate voltage corresponding to the first set of configuration information is greater than a single power supply duration of the gate voltage corresponding to the second set of configuration information.

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