Wafer-level packaging method and wafer-level packaging structure adopting glass cover plate

Abstract

The invention provides a wafer-level packaging method adopting a glass cover plate and a wafer-level packaging structure, and relates to the technical field of semiconductor packaging. The packaging method comprises the following steps: providing an assembly of a carrier plate and a glass cover plate layer; a first groove and a second groove are formed in the side, away from the carrier plate, of the glass cover plate layer. A wafer having a plurality of chips is provided. Cutting channels are formed between the adjacent chips; each chip comprises a functional area and a metal interconnection layer. Bonding glue is formed on the glass cover plate layer and / or the chip, so that the glass cover plate layer covers the wafer through the bonding glue; wherein the functional area is located in the first groove; the cutting channel is located in the second groove; the bonding glue is located between the first groove and the second groove and covers part of the metal interconnection layer. Removing the carrier plate; conductive layers are formed on the side wall of the second groove of the glass cover plate layer and the surface of the side, away from the wafer, of the glass cover plate layer, and the conductive layers are electrically connected with the metal interconnection layer. The packaging process is simplified, and the packaging efficiency and the packaging reliability can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a wafer-level packaging method and a wafer-level packaging structure using a glass cover plate. Background Art

[0002] Traditional packaging technology first cuts the wafer into individual chips, and then packages the individual chips one by one. This packaging method is inefficient and costly. Wafer-level packaging (WLP) is an advanced packaging technology currently used by discrete devices. Compared with traditional packaging, WLP packages all the chips on the wafer before the entire wafer is cut, and then cuts the wafer into individual chips after the packaging and internal circuit connection are completed. WLP has the advantages of smaller package size, higher efficiency, short production cycle, low process cost, and easier integration. Therefore, WLP packaging currently has great advantages in the field of discrete devices and module integrated devices.

[0003] However, current cavity-type WLP packaging solutions usually add one or more layers of support structures above the wafer and between the top cover to form a cavity. This structure not only increases the process steps and costs, but also increases the reliability risk due to the additional multi-layer structure. Summary of the invention

[0004] The object of the present invention is to provide a wafer-level packaging method and a wafer-level packaging structure using a glass cover plate, which simplifies the packaging process and is conducive to improving packaging efficiency and packaging reliability.

[0005] In a first aspect, the present invention provides a wafer-level packaging method using a glass cover plate, comprising:

[0006] Providing a combination of a carrier plate and a glass cover plate layer;

[0007] Wherein, a first groove and a second groove are arranged at intervals on a side of the glass cover layer away from the carrier; the depth of the first groove is less than the thickness of the glass cover layer, and the second groove penetrates the glass cover layer in the thickness direction;

[0008] A wafer having a plurality of chips is provided, wherein a dicing path is formed between adjacent chips; each chip comprises a functional area and a metal interconnection layer extending outward from the functional area;

[0009] Forming bonding glue on the glass cover layer and / or the chip, so that the glass cover layer is covered on the wafer through the bonding glue; wherein the functional area is located in the first groove; the cutting road is located in the second groove; the bonding glue is located between the first groove and the second groove, and covers a portion of the metal interconnection layer;

[0010] removing the carrier plate;

[0011] A conductive layer is formed on the side wall of the second groove of the glass cover layer and on a surface of the glass cover layer away from the wafer, and the conductive layer is electrically connected to the metal interconnection layer.

[0012] In an optional embodiment, the step of providing a combination of a carrier plate and a glass cover plate layer comprises:

[0013] Providing the carrier board;

[0014] affixing a film layer on the carrier plate;

[0015] Pasting the glass cover layer on the adhesive film layer;

[0016] The first groove and the second groove are respectively formed on the glass cover layer.

[0017] In an optional embodiment, the chip includes a coating area, and the coating area is located between the functional area and the cutting road; the glass cover layer includes a supporting side wall located between the first groove and the second groove;

[0018] The step of forming a bonding adhesive on the glass cover layer and / or the chip comprises:

[0019] A bonding glue is formed on the coating area and / or the supporting sidewall.

[0020] In an optional embodiment, the width of the supporting side wall is equal to the width of the coating area.

[0021] In an optional embodiment, the width of the bonding adhesive is not greater than the width of the coating area or the supporting side wall.

[0022] In an optional embodiment, the coating area includes an inner ring and an outer ring, the distance between the inner ring and the outer ring is the width of the coating area; the inner ring and the outer ring are both located on the metal interconnection layer; a portion of the metal interconnection layer is located in the first groove, and a portion is located in the second groove.

[0023] In an optional embodiment, the step of forming a conductive layer on the sidewall of the second groove of the glass cover layer and on the surface of the side of the glass cover layer away from the wafer includes:

[0024] Multiple metal layers are sequentially formed on the sidewall of the second groove of the glass cover layer and on the surface of one side of the glass cover layer away from the wafer.

[0025] In an optional embodiment, the multi-layer metal layer includes an aluminum layer, a copper layer, a titanium layer and a gold layer formed in sequence, and the aluminum layer is in contact with the surface of the glass cover plate.

[0026] In an optional embodiment, the method further includes: forming an electrical connection terminal on the conductive layer.

[0027] In a second aspect, the present invention provides a wafer-level packaging structure, comprising:

[0028] A glass cover plate layer, wherein the glass cover plate layer has a first groove and a supporting side wall forming a circumferential wall surface of the first groove;

[0029] A chip; the chip comprises a functional area and a metal interconnection layer extending outward from the functional area;

[0030] Bonding glue;

[0031] The supporting sidewall is fixed to the chip by the bonding glue, so that the functional area is located in the first groove, and the metal interconnection layer at least partially extends outside the first groove;

[0032] A conductive layer is disposed on the outer surface of the glass cover layer and is electrically connected to the metal interconnect layer.

[0033] In an optional embodiment, the chip includes a coating area, the coating area is located at the periphery of the functional area, and the coating area is arranged corresponding to the supporting side wall; the bonding glue is arranged between the coating area of ​​the chip and the supporting side wall.

[0034] In an optional embodiment, the width of the coating area is equal to the width of the supporting side wall; the width of the bonding glue is not greater than the width of the coating area or the width of the supporting side wall.

[0035] In an optional embodiment, the coating area includes an inner ring and an outer ring, and the distance between the inner ring and the outer ring is the width of the coating area; the inner ring and the outer ring are both located on the metal interconnection layer;

[0036] And / or, a portion of the metal interconnection layer is located in the first groove, and another portion extends outside the first groove after passing through the coating area.

[0037] In an optional embodiment, the outer surface of the glass cover layer includes a connected side surface and an upper surface, the side surface is connected to the chip, and the upper surface is a side surface of the glass cover layer away from the chip; the conductive layer extends along the side surface to the upper surface, and an electrical connection terminal is provided on the conductive layer located on the upper surface.

[0038] The beneficial effects of the wafer-level packaging method and wafer-level packaging structure using a glass cover provided by the present invention include:

[0039] The wafer-level packaging method using a glass cover provided by the present invention is particularly suitable for wafer-level packaging that requires the formation of a cavity structure. The glass cover layer has a high structural strength and is easy to process. The glass cover layer having a first groove and a second groove structure is bonded to the wafer, so that the chip is located in the cavity formed by the first groove, thereby realizing the packaging of the cavity structure. The process is simple, and the multi-layer support structure for preparing the cavity in the traditional process is omitted, so the process efficiency is higher and the cost is lower.

[0040] The wafer-level packaging structure provided by the present invention is manufactured by the aforementioned wafer-level packaging method using a glass cover plate, and has a reliable structure, low cost, and higher process efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic structural diagram of a combination of a carrier plate and a glass cover plate layer provided in a wafer-level packaging method using a glass cover plate provided in an embodiment of the present invention;

[0043] Figure 2 A schematic structural diagram of forming a first groove and a second groove on a glass cover layer in a wafer-level packaging method using a glass cover provided by an embodiment of the present invention;

[0044] Figure 3 In the wafer-level packaging method using a glass cover provided in an embodiment of the present invention, a schematic structural diagram of a wafer having multiple chips is provided;

[0045] Figure 4 A schematic structural diagram of a single chip from a first perspective in a wafer-level packaging method using a glass cover provided by an embodiment of the present invention;

[0046] Figure 5 A schematic diagram of a structure for forming a bonding adhesive on a wafer in a wafer-level packaging method using a glass cover plate provided by an embodiment of the present invention;

[0047] Figure 6 A schematic structural diagram of bonding between a glass cover plate layer and a wafer in a wafer-level packaging method using a glass cover plate provided by an embodiment of the present invention;

[0048] Figure 7 for Figure 6 A schematic diagram of a structure in which the carrier is removed after the bonding step;

[0049] Figure 8 A schematic structural diagram of forming a conductive layer on the surface of a glass cover layer in a wafer-level packaging method using a glass cover provided by an embodiment of the present invention;

[0050] Fig. 9 A schematic diagram of a structure in which an electrical connection terminal is formed on a conductive layer in a wafer-level packaging method using a glass cover plate provided by an embodiment of the present invention;

[0051] Fig.10 A schematic diagram of a single product structure of a wafer-level packaging structure provided in an embodiment of the present invention.

[0052] Icons: 1-carrier; 2-film layer; 3-glass cover layer; 4-first groove; 5-second groove; 31-support side wall; 6-chip; 7-coating area; 8-metal interconnect layer; 9-functional area; 10-cutting path; 11-bonding glue; 12-conductive layer; 13-electrical connection terminal. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0056] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0057] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0058] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0059] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0060] The wafer-level packaging method using a glass cover plate proposed in the embodiment of the present invention is suitable for wafer-level packaging with a cavity structure, such as packaging of a surface acoustic wave filter chip, and is conducive to simplifying the packaging process and improving packaging efficiency and packaging reliability.

[0061] Combination Figure 1 , Figure 2 The wafer-level packaging method using a glass cover plate mainly includes the following steps:

[0062] S1: Provide a combination of a carrier plate 1 and a glass cover plate layer 3. A first groove 4 and a second groove 5 are provided at intervals on a side of the glass cover plate layer 3 away from the carrier plate 1. The depth of the first groove 4 is less than the thickness of the glass cover plate layer 3, and the second groove 5 penetrates the glass cover plate layer 3 in the thickness direction.

[0063] Optionally, step S1 is implemented by including step S11, step S12, step S13 and step S14.

[0064] Step S11: providing a carrier 1. The carrier 1 may be an organic carrier.

[0065] Step S12: pasting the adhesive film layer 2 on the carrier board 1.

[0066] Step S13: Paste the glass cover layer 3 on the adhesive film layer 2. The glass cover layer 3 is fixed on the carrier 1 through the adhesive film layer 2 to form an integral structure of the carrier 1 and the glass cover layer 3.

[0067] Step S14: forming the first groove 4 and the second groove 5 spaced apart on the glass cover layer 3. The first groove 4 and the second groove 5 can be formed by etching, sandblasting or laser grooving. The depth of the first groove 4 is shallower, and the depth of the first groove 4 is less than the thickness of the glass cover layer 3. The first groove 4 is used to accommodate the chip 6 and form a cavity structure above the chip 6. It should be noted that the depth of the first groove 4 is used to form a cavity structure to ensure that the chip can fully exert its function, such as ensuring that the surface acoustic wave filter chip has good filtering performance. Therefore, the depth of the first groove 4 can be flexibly designed according to the size specifications and types of the actual chip. Optionally, the depth of the first groove 4 accounts for 20% to 80% of the thickness of the glass cover layer 3. For example, the ratio of the depth of the first groove 4 to the thickness of the glass cover layer 3 is about 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, etc., which is not specifically limited here. The second groove 5 is deeper, and the depth of the second groove 5 is equal to the thickness of the glass cover layer 3 , that is, the second groove 5 penetrates the glass cover layer 3 . The second groove 5 is used to form a separation groove between adjacent chips 6 .

[0068] In some implementations, the first groove 4 and the second groove 5 may be formed on the glass cover layer 3 before bonding the glass cover layer 3 to the carrier 1. This is not specifically limited here.

[0069] Combination Figure 3 , Figure 4 Step S2: Provide a wafer with a plurality of chips 6. The wafer can be silicon Si, lithium tantalate LiTaO 3 or lithium niobate LiNbO 3 A single crystal or composite thin film crystal formed of semiconductor materials such as . Among them, a cutting path 10 is formed between adjacent chips 6. Each chip 6 includes a functional area 9 and a metal interconnection layer 8 extending outward from the functional area 9. Here, extending outward means extending from the functional area 9 to the cutting path 10. The metal interconnection layer 8 is used to connect the circuit of the functional area 9 and the pins outside the package.

[0070] Combination Figure 5 , Figure 6Step S3: forming a bonding adhesive 11 on the glass cover layer 3 and / or the chip 6, so that the glass cover layer 3 is covered on the wafer through the bonding adhesive 11. The functional area 9 is located in the first groove 4, which can effectively protect the functional area 9 of the chip 6. The cutting road 10 is located in the second groove 5; the bonding adhesive 11 is located between the first groove 4 and the second groove 5, and covers part of the metal interconnect layer 8.

[0071] It can be understood that the bonding glue 11 can be formed on the glass cover layer 3 or on the wafer. Alternatively, the bonding glue 11 is formed on the glass cover layer 3 and the wafer respectively. As long as the bonding fixation of the glass cover layer 3 and the wafer can be achieved. In this embodiment, the bonding glue 11 is formed on the wafer, so that the dispensing accuracy is higher, and the bonding glue 11 can be effectively prevented from entering the functional area 9 of the chip 6 to contaminate the functional area 9 and reduce the performance of the chip 6.

[0072] Optionally, the chip 6 includes a coating area 7, and the coating area 7 is located between the functional area 9 and the cutting path 10. The glass cover layer 3 includes a supporting side wall 31 located between the first groove 4 and the second groove 5. The bonding glue 11 can be formed on at least one of the bottom of the supporting side wall 31 and the coating area 7. The following description takes the formation of the bonding glue 11 on the coating area 7 as an example.

[0073] A bonding glue 11 is coated on the coating area 7 of the chip 6, and then the side of the glass cover layer 3 away from the carrier 1 is fixed on the wafer through the bonding glue 11. Among them, the bonding glue 11 can be a solid glue. The coating area 7 includes an inner circle and an outer circle, and the distance between the inner circle and the outer circle is the width of the coating area 7; the inner circle and the outer circle are both located on the metal interconnection layer 8. In other words, the width of the coating area 7 is less than the extension length of the metal interconnection layer 8. In this way, after the glass cover layer 3 and the wafer are bonded, a part of the metal interconnection layer 8 is located in the first groove 4, and a part is located in the second groove 5. This arrangement is conducive to the subsequent formation of a conductive layer 12 electrically connected to the metal interconnection layer 8 on the glass cover layer 3.

[0074] Optionally, the width of the supporting sidewall 31 is substantially equal to the width of the coating area 7. The width of the bonding glue 11 is not greater than the width of the coating area 7 or the supporting sidewall 31. In this way, a sealed connection can be achieved, the connection is reliable, and the risk of excessive glue contaminating the functional area 9 of the chip 6 can be reduced.

[0075] Combination Figure 7 , step S4: removing the carrier 1. Optionally, the carrier 1 is removed after the bonding adhesive 11 is hardened and stabilized. For example, the carrier 1 can be removed by grinding. Alternatively, according to the characteristics of the film layer 2, the carrier 1 and the glass cover layer 3 can be peeled off by chemical cleaning, heating, or light. At this time, the film layer 2 is also removed. The peeled carrier 1 can also be reused to reduce packaging costs.

[0076] Optionally, after removing the carrier 1, the surface of the glass cover layer 3 needs to be cleaned to remove organic residues on the surface. This step includes but is not limited to cleaning the upper surface and side surfaces of the glass cover layer 3 so that the conductive layer 12 subsequently formed on the surface has better bonding strength to prevent detachment and delamination.

[0077] Combination Figure 8 Step S5: forming a conductive layer 12 on the side wall of the second groove 5 of the glass cover layer 3 and on the side surface of the glass cover layer 3 away from the wafer, and the conductive layer 12 is electrically connected to the metal interconnection layer 8. That is, metallization is performed on the upper surface and side surface of the glass cover layer 3 to form the conductive layer 12, so as to lead the metal interconnection layer 8 to the top of the glass cover layer 3.

[0078] Optionally, the conductive layer 12 includes multiple metal layers to improve the bonding force and the conductive performance. In this embodiment, multiple metal layers are sequentially formed on the side wall of the second groove 5 of the glass cover layer 3 and the surface of the glass cover layer 3 on the side away from the wafer. The surface metallization can be performed by evaporation to form the conductive layer 12, and the evaporation method is efficient and low in cost. The multiple metal layers include four layers, which are an aluminum layer, a copper layer, a titanium layer and a gold layer formed in sequence, and the aluminum layer is in contact with the surface of the glass cover. This arrangement can not only improve the bonding force and the conductive performance, but also improve the heat dissipation performance.

[0079] Of course, in some other embodiments, the conductive layer 12 may also be a one-layer, two-layer, three-layer, five-layer or more-layer structure. The conductive material of each layer is not limited, and may be a single metal or an alloy. The metallization method for forming the conductive layer 12 may also be electroplating, sputtering or conductive film pasting, which is not specifically limited here.

[0080] Combination Fig. 9 Step S6: forming an electrical connection terminal 13 on the conductive layer 12. Optionally, the electrical connection terminal 13 may be a bump or a solder ball, etc., which may be implemented by a conventional ball implantation process. Finally, the wafer is cut along the cutting path 10 to form a single product. In this way, the wafer-level package with a cavity structure is completed.

[0081] In this embodiment, the organic carrier is bonded to the glass cover layer 3 through the adhesive film layer 2, and the glass cover layer 3 is grooved by sandblasting or laser technology to realize the cavity structure. After the groove is made on the glass cover layer 3, the chip 6 equipped with the circuit and the metal interconnection layer 8 is sealed and bonded to the glass cover layer 3 and the wafer through the bonding glue 11, so that the functional area 9 with the circuit structure that needs to be isolated and protected on the chip 6 corresponds to the first groove 4 on the glass cover layer 3, so that the more sensitive circuit structure is protected in the glass cover layer 3. After the glass cover layer 3 is bonded to the wafer as a whole, the carrier 1 on the glass cover layer 3 is peeled off to realize that each chip 6 has an independent accommodating cavity formed by a corresponding glass cover layer 3 on the entire wafer. Then, the metal evaporation technology is used to evaporate the metal conductive layer 12 on the top and side of the glass cover layer 3, so that the circuit of the bottom chip 6 is led out to the top of the glass cover layer 3 to realize the interconnection of the pins. Finally, solder bumps are made in the conductive layer 12 region on top of the glass cover layer 3 to form spherical electrical terminals 13 .

[0082] The embodiment of the present invention adopts the above process to realize the integration of the cavity structure, and enhances the sealing and structural strength of the wafer-level packaging structure without increasing the complexity and cost of the process. In addition, after the groove structure of the whole piece is realized on the glass cover layer 3, the embodiment of the present invention directly performs the bonding of multiple chips 6 and the groove cavity on the glass cover layer 3. During the entire process, there are very few process processes on the surface of the wafer, which greatly reduces the risk of damage to the circuit layer on the surface of the wafer during the packaging process, and improves the reliability of the packaging quality.

[0083] The embodiment of the present invention further provides a wafer-level packaging structure, which can be manufactured by using the wafer-level packaging method using a glass cover plate in the aforementioned embodiment.

[0084] Combination Fig.10 The wafer-level packaging structure includes a glass cover layer 3, a bonding glue 11, a chip 6, a bonding glue 11 and a conductive layer 12. The chip 6 includes a coating area 7, a functional area 9 and a metal interconnection layer 8. The glass cover layer 3 is provided with a first groove 4 and a supporting sidewall 31 forming the first groove 4. The bonding glue 11 is coated on the coating area 7 of the chip 6, and the side of the glass cover layer 3 having the first groove 4 is bonded toward the chip 6. The supporting sidewall 31 is bonded and fixed to the coating area 7 of the chip 6 by the bonding glue 11.

[0085] The functional area 9 of the chip 6 is located in the first groove 4. The cavity formed by the first groove 4 accommodates the functional area 9 of the chip 6 and effectively protects the functional area 9.

[0086] Optionally, the width of the coating area 7 is substantially equal to the width of the supporting sidewall 31. The width of the bonding glue 11 is not greater than the width of the coating area 7 or the width of the supporting sidewall 31. In this way, a sealed connection can be achieved, the connection is reliable, and the risk of excessive glue contaminating the functional area 9 of the chip 6 can be reduced.

[0087] Optionally, the coating area 7 includes an inner circle and an outer circle, and the distance between the inner circle and the outer circle is the width of the coating area 7; the inner circle and the outer circle are both located on the metal interconnection layer 8. In other words, the width of the coating area 7 is less than the extension length of the metal interconnection layer 8. In this way, after the glass cover layer 3 and the chip 6 are bonded, a part of the metal interconnection layer 8 is located in the first groove 4, and the other part extends to the outside of the first groove 4 after passing through the coating area 7. This arrangement is conducive to the subsequent formation of a conductive layer 12 electrically connected to the metal interconnection layer 8 on the glass cover layer 3.

[0088] In this embodiment, a portion of the metal interconnection layer 8 of the chip 6 is located in the first groove 4, and the other portion extends along the bottom of the supporting side wall 31 to the outside of the first groove 4. The conductive layer 12 is provided on the side of the glass cover layer 3 away from the first groove 4, and the conductive layer 12 is electrically connected to the metal interconnection layer 8. Optionally, the conductive layer 12 is electrically connected to the portion of the metal interconnection layer 8 located outside the first groove 4. The conductive layer 12 extends along the side wall of the glass cover layer 3 to the upper surface. A bump or solder ball is provided on the conductive layer 12 located on the upper surface as an electrical connection terminal 13.

[0089] In summary, the wafer-level packaging method and wafer-level packaging structure using a glass cover provided by the present invention have the following beneficial effects:

[0090] The wafer-level packaging method using a glass cover plate provided by an embodiment of the present invention is particularly suitable for wafer-level packaging that requires the formation of a cavity structure. The glass cover plate has a high structural strength and is easy to process. The glass cover plate having a first groove 4 and a second groove 5 structure is bonded to the wafer so that the functional area 9 of the chip 6 is located in the cavity formed by the first groove 4, thereby realizing the packaging of the cavity structure. The process is simple, and the multi-layer support structure for preparing the cavity in the traditional process is omitted, so the process efficiency is higher and the cost is lower. In addition, the cavity structure and the cover plate are integrally formed, with good sealing, preventing detachment and delamination, and having higher packaging reliability. In addition, during the entire process, there are very few process steps on the surface of the wafer, which greatly reduces the risk of damage to the circuit layer on the surface of the wafer during the packaging process, which is beneficial to improving the packaging quality and yield rate.

[0091] The wafer-level packaging structure provided by the embodiment of the present invention is manufactured by the aforementioned wafer-level packaging method using a glass cover plate, and has a reliable structure, low cost, and higher process efficiency, which is conducive to improving packaging quality and yield rate.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the protection scope of the present invention.

Claims

1. A wafer-level packaging method using a glass cover plate, characterized in that: include: Providing a combination of a carrier plate (1) and a glass cover plate layer (3); Wherein, a first groove (4) and a second groove (5) are arranged at intervals on a side of the glass cover layer (3) away from the carrier plate (1); the depth of the first groove (4) is less than the thickness of the glass cover layer (3); and the second groove (5) penetrates the glass cover layer (3) in the thickness direction; A wafer having a plurality of chips (6) is provided; wherein a cutting path (10) is formed between adjacent chips (6); each chip (6) comprises a functional area (9) and a metal interconnection layer (8) extending outward from the functional area (9); A bonding adhesive (11) is formed on the glass cover layer (3) and / or the chip (6), so that the glass cover layer (3) is covered on the wafer through the bonding adhesive (11); wherein the functional area (9) is located in the first groove (4); the cutting path (10) is located in the second groove (5); the bonding adhesive (11) is located between the first groove (4) and the second groove (5), and covers a portion of the metal interconnect layer (8); Removing the carrier plate (1); A conductive layer (12) is formed on the side wall of the second groove (5) of the glass cover layer (3) and on a surface of the glass cover layer (3) away from the wafer, and the conductive layer (12) is electrically connected to the metal interconnect layer (8).

2. The wafer-level packaging method using a glass cover plate according to claim 1, characterized in that: The step of providing a combination of a carrier plate (1) and a glass cover plate layer (3) comprises: Providing the carrier board (1); Affixing an adhesive film layer (2) on the carrier board (1); affixing the glass cover layer (3) on the adhesive film layer (2); The first groove (4) and the second groove (5) are respectively formed on the glass cover layer (3).

3. The wafer-level packaging method using a glass cover plate according to claim 1, characterized in that: The chip (6) comprises a coating area (7), wherein the coating area (7) is located between the functional area (9) and the cutting path (10); the glass cover layer (3) comprises a supporting side wall (31) located between the first groove (4) and the second groove (5); The step of forming a bonding adhesive (11) on the glass cover layer (3) and / or the chip (6) comprises: forming a bonding adhesive (11) on the coating area (7) and / or the supporting side wall (31); The width of the supporting side wall (31) is equal to the width of the coating area (7), and the width of the bonding glue (11) is not greater than the width of the coating area (7) or the supporting side wall (31).

4. The wafer-level packaging method using a glass cover plate according to claim 1, characterized in that: The step of forming a conductive layer (12) on the side wall of the second groove (5) of the glass cover layer (3) and on a surface of the glass cover layer (3) on a side away from the wafer comprises: A plurality of metal layers are sequentially formed on the side wall of the second groove (5) of the glass cover layer (3) and on the surface of the side of the glass cover layer (3) away from the wafer; wherein the plurality of metal layers include an aluminum layer, a copper layer, a titanium layer and a gold layer formed sequentially, and the aluminum layer is in contact with the surface of the glass cover.

5. The wafer-level packaging method using a glass cover plate according to any one of claims 1 to 4, characterized in that: After the step of forming a conductive layer (12) on the side wall of the second groove (5) of the glass cover layer (3) and on the surface of one side of the glass cover layer (3) away from the wafer, the method further comprises: forming an electrical connection terminal (13) on the conductive layer (12).

6. A wafer-level packaging structure, characterized in that: include: A glass cover plate layer (3), the glass cover plate layer (3) having a first groove (4) and a supporting side wall (31) forming a circumferential wall surface of the first groove (4); A chip (6); the chip (6) comprises a functional area (9) and a metal interconnection layer (8) extending outward from the functional area (9); Bonding glue (11); The supporting side wall (31) is fixed to the chip (6) by means of the bonding adhesive (11), so that the functional area (9) is located in the first groove (4), and the metal interconnection layer (8) at least partially extends outside the first groove (4); A conductive layer (12), the conductive layer (12) being arranged on the outer surface of the glass cover layer (3) and being electrically connected to the metal interconnect layer (8).

7. The wafer-level packaging structure according to claim 6, characterized in that: The chip (6) comprises a coating area (7), the coating area (7) is located at the periphery of the functional area (9), and the coating area (7) is arranged corresponding to the supporting side wall (31); the bonding glue (11) is arranged between the coating area (7) of the chip (6) and the supporting side wall (31).

8. The wafer-level packaging structure according to claim 7, characterized in that: The width of the coating area (7) is equal to the width of the supporting side wall (31); the width of the bonding glue (11) is not greater than the width of the coating area (7) or the width of the supporting side wall (31).

9. The wafer-level packaging structure according to claim 7, characterized in that: The coating area (7) comprises an inner ring and an outer ring, the distance between the inner ring and the outer ring being the width of the coating area (7); the inner ring and the outer ring are both located on the metal interconnection layer (8); And / or, a portion of the metal interconnection layer (8) is located in the first groove (4), and another portion extends outside the first groove (4) after passing through the coating area (7).

10. The wafer-level packaging structure according to any one of claims 6 to 9, characterized in that: The outer surface of the glass cover layer (3) comprises a connected side surface and an upper surface, the side surface being connected to the chip (6), and the upper surface being a side surface of the glass cover layer (3) away from the chip (6); the conductive layer (12) extends along the side surface to the upper surface, and an electrical connection terminal (13) is provided on the conductive layer (12) located on the upper surface.

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