Power semiconductor module and method of forming power semiconductor module

Abstract

A power semiconductor module and a method of forming a power semiconductor module are provided. The power semiconductor module includes: a first substrate; a second substrate that is formed over the first substrate; a conductive member disposed between the first substrate and the second substrate; a first power semiconductor device disposed between the first substrate and the conductive member; and a second power semiconductor device disposed between the conductive member and the second substrate. The conductive member is electrically connected to the first power semiconductor device and the second power semiconductor device.

Description

Technical Field

[0001] Embodiments related to power semiconductor modules and methods of forming power semiconductor modules are disclosed. Background Art

[0002] Compared to system semiconductors or memories that process and store information or signals, power semiconductors are components that convert, store, distribute and / or control power supplied to electronic devices. Power semiconductor devices are widely used in many electronic products.

[0003] In recent years, with the global trend of strengthening environmental protection, environmentally friendly vehicles based on electricity or hydrogen are increasingly replacing existing fossil fuel-based vehicles. Many power semiconductor devices are used in these environmentally friendly vehicles. Examples of environmentally friendly vehicles include hybrid electric vehicles (HEV), plug-in hybrid electric vehicles (PHEV), electric vehicles (EV), fuel cell electric vehicles (PCEV), etc.

[0004] Existing silicon (Si) power semiconductor devices have low power, low dielectric breakdown characteristics, and low thermal conductivity.

[0005] Therefore, research on power semiconductor devices based on semiconductor compounds having an energy band gap approximately three times higher than that of Si power semiconductor devices has been actively conducted. Power semiconductor devices based on such semiconductor compounds have high power, high dielectric breakdown characteristics, and high thermal conductivity.

[0006] Recently, a power semiconductor module in which a plurality of power semiconductor devices are packaged has been widely studied, and a power converter having such a power semiconductor module is applied to various technical fields.

[0007] A plurality of power semiconductor devices included in a power semiconductor module may be connected in series or in parallel. In this case, when each power semiconductor device is turned off, stray inductance may be formed in the corresponding power semiconductor device, and the stray inductance is largely affected by the electrical connection path of the power semiconductor device. More specifically, for example, as the length of the electrical connection path between the power semiconductor devices increases, the length of the current path increases, and the stray inductance increases due to the increased length of the current path.

[0008] Since stray inductance hinders the flow of current and thus hinders the high power output of power semiconductor devices, it is necessary to minimize or eliminate stray inductance. In particular, when stray inductance increases, a transient voltage overshoot may occur. When the overshoot voltage exceeds the withstand voltage of the power semiconductor device, the power semiconductor device may be damaged or switching losses of the power semiconductor device may occur. Therefore, a technical solution for minimizing or eliminating stray inductance is needed.

[0009] In addition, as the high power output required of power semiconductor devices increases, the size of the power semiconductor devices may also need to increase. However, there is a strong demand to reduce the size of products that employ multiple power semiconductor devices. Therefore, there is also a need to develop a power semiconductor module that allows the size of the product including the power semiconductor module to be smaller or the same while increasing the high power output per unit area of ​​the power semiconductor devices. Summary of the invention

[0010] Some embodiments of the present disclosure are intended to solve the above-mentioned problems.

[0011] More specifically, one object of some embodiments is to provide a power semiconductor module capable of preventing damage to a power semiconductor device and a method of forming a power semiconductor module. Another object of some embodiments is to provide a power semiconductor module capable of reducing switching losses of a power semiconductor device and a method of forming a power semiconductor module. Still another object of some embodiments is to provide a power semiconductor module capable of increasing high power output per unit area and a method of forming a power semiconductor module. Still another object of some embodiments is to provide a power semiconductor module with reduced size and a method of forming a power semiconductor module.

[0012] Technical problems of the embodiments are not limited to the above-mentioned technical problems, and may include technical problems that can be grasped through the following description.

[0013] A power semiconductor module according to the embodiment includes: a first substrate; a second substrate formed above the first substrate; a conductive member disposed between the first substrate and the second substrate; a first power semiconductor device disposed between the first substrate and the conductive member; and a second power semiconductor device disposed between the conductive member and the second substrate, wherein the conductive member is electrically connected to the first power semiconductor device and the second power semiconductor device.

[0014] The first power semiconductor device and the second power semiconductor device at least partially overlap.

[0015] The first power semiconductor device and the second power semiconductor device are electrically connected in series.

[0016] The conductive member includes a second portion and a connecting portion connected to the second portion, and the second power semiconductor device is provided on a surface of the second portion.

[0017] The conductive member includes a first portion positioned lower than the second portion and connected to the connecting portion, the conductive member includes a recess formed by the first portion, the connecting portion, and the second portion, and the first power semiconductor device is disposed within the recess.

[0018] The first portion is fixed to the first substrate.

[0019] The power semiconductor module also includes a spacer disposed between the first power semiconductor device and the conductive member.

[0020] The spacer extends from the conductive member toward the first power semiconductor device.

[0021] The first power semiconductor device includes a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode is electrically connected to the first substrate using a wire, the first source electrode is electrically connected to the conductive member, and the first drain electrode is electrically connected to the first substrate.

[0022] The upper surface of the spacer is at a higher position compared to the uppermost position of the conductive wire.

[0023] The conductive member includes an opening through which the conductive wire is disposed.

[0024] The second power semiconductor device includes a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode and the second source electrode being electrically connected to the second substrate, and the second drain electrode being electrically connected to the conductive member.

[0025] The first substrate includes a first conductive layer, a first insulating layer, and a second conductive layer, the first conductive layer includes a plurality of first signal patterns, the wire is connected to one of the plurality of first signal patterns, and the first drain electrode is connected to another one of the plurality of first signal patterns.

[0026] The second substrate includes a third conductive layer, a second insulating layer, and a fourth conductive layer, the third conductive layer includes a plurality of second signal patterns, the second gate electrode is connected to one of the plurality of second signal patterns, and the second source electrode is connected to another of the plurality of second signal patterns.

[0027] The power semiconductor module includes: a plurality of first power semiconductor devices including the first power semiconductor device, wherein the plurality of first power semiconductor devices are connected in parallel between a first substrate and a conductive member.

[0028] The power semiconductor module includes: a plurality of second power semiconductor devices including the second power semiconductor device, wherein the plurality of second power semiconductor devices are connected in parallel between the conductive member and the second substrate.

[0029] Each of the first plurality of power semiconductor devices and each of the second plurality of power semiconductor devices at least partially overlap.

[0030] The current path is configured to be formed through the first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate in this order.

[0031] A method for forming a power semiconductor module according to this embodiment, the method comprising the following steps: forming a first substrate; forming a first power semiconductor device on the first substrate; forming a conductive member above the first power semiconductor device so that the first power semiconductor device is arranged between the first substrate and the conductive member; forming a second power semiconductor device on the conductive member; forming a second substrate above the second power semiconductor device so that the second power semiconductor device is arranged between the conductive member and the second substrate, wherein the conductive member is arranged between the first substrate and the second substrate.

[0032] The current path is configured to be formed through the first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate in this order.

[0033] Each of the first plurality of power semiconductor devices and each of the second plurality of power semiconductor devices at least partially overlap.

[0034] The current path is configured to be formed through the first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate in this order.

[0035] A method for forming a semiconductor module according to this embodiment, the method comprising the following steps: forming a first substrate; forming a first power semiconductor device on the first substrate; forming a conductive member above the first power semiconductor device so that the first power semiconductor device is arranged between the first substrate and the conductive member; forming a second power semiconductor device on the conductive member; forming a second substrate above the second power semiconductor device so that the second power semiconductor device is arranged between the conductive member and the second substrate, wherein the conductive member is arranged between the first substrate and the second substrate.

[0036] The current path is configured to be formed through the first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate in this order.

[0037] Effects of a power semiconductor module and a method of forming the power semiconductor module according to some embodiments are described below.

[0038] According to at least one embodiment, switching loss suppression and high-precision switching control of a power semiconductor device can be achieved.

[0039] More specifically, in these embodiments, since the first power semiconductor device and / or the second power semiconductor device is connected to the conductive support member having a plate shape in surface contact, the contact resistance between the first power semiconductor device and / or the second power semiconductor device and the conductive support member can be minimized, thereby minimizing current loss. Therefore, the switching loss of the first power semiconductor device or the second power semiconductor device can be prevented, thereby achieving a predetermined high power output and high-precision switching control.

[0040] Furthermore, according to at least one embodiment, damage to a power semiconductor device can be prevented.

[0041] In a power semiconductor module according to some embodiments, a first power semiconductor device and a second power semiconductor device may overlap vertically with a support member between and between a first substrate and a second substrate. Since the first power semiconductor device and the second power semiconductor device are separated by the thickness of the support member, a separation gap between the first power semiconductor device and the second power semiconductor device may be minimized.

[0042] The electrical connection path between the first power semiconductor device and the second power semiconductor device can greatly affect the stray inductance. However, in the power semiconductor module according to some embodiments, since the separation gap between the first power semiconductor device and the second power semiconductor device can be minimized, the stray inductance can be removed or minimized. Therefore, even when the first power semiconductor device or the second power semiconductor device is turned off, no stray inductance is generated and no overshoot voltage is generated. Therefore, damage to the first power semiconductor device or the second power semiconductor device due to the overshoot voltage can be prevented.

[0043] Furthermore, according to at least one embodiment, switching loss can be reduced.

[0044] The stray inductance affects the switching loss of the first power semiconductor device or the second power semiconductor device. However, in the power semiconductor module according to some embodiments, since the separation gap between the first power semiconductor device and the second power semiconductor device is minimized, the stray inductance is removed or minimized. Therefore, it does not affect the switching loss of the first power semiconductor device or the second power semiconductor device, and a predetermined high power output is possible.

[0045] In addition, according to at least one embodiment, high power output per unit area can be increased and the size can be reduced.

[0046] In a power semiconductor module according to some embodiments, the first power semiconductor device and the second power semiconductor device are vertically overlapped with a support therebetween to minimize the placement area of ​​the first power semiconductor device and the second power semiconductor device, thereby minimizing the size of the power semiconductor module or the power semiconductor device. Therefore, since more first power semiconductor devices or second power semiconductor devices can be installed per unit area, higher power output is possible.

[0047] In addition, according to at least one embodiment, electrical short circuit of the conductive line can be prevented.

[0048] In a power semiconductor module according to some embodiments, a first power semiconductor device and a second power semiconductor device may overlap vertically with a support therebetween. One side of the first power semiconductor device and the first substrate may be electrically connected by a wire. A spacer may be disposed between the first power semiconductor device and the support. The spacer may prevent the wire from being electrically short-circuited with the support. For example, an upper surface of the spacer may be positioned higher than the uppermost side of the wire.

[0049] Additionally, according to at least one embodiment, high power output can be increased.

[0050] In a power semiconductor module according to some embodiments, a first power semiconductor device and a second power semiconductor device may overlap vertically with a support therebetween. Since a plurality of first power semiconductor devices are arranged in parallel with each other and a plurality of second power semiconductor devices are arranged in parallel with each other, current characteristics are improved and high power output is possible.

[0051] Through the following detailed description, the further applicable scope of the embodiment will become apparent. However, since those skilled in the art can clearly understand various changes and modifications within the spirit and scope of the embodiment, it should be understood that the detailed description and specific implementation of the preferred embodiment are given by way of example only.

[0052] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a circuit diagram illustrating an automotive inverter according to some embodiments.

[0054] Figure 2 is a plan view illustrating a power semiconductor module according to some embodiments.

[0055] Figure 3 is a cross-sectional view illustrating a power semiconductor module according to some embodiments.

[0056] Figure 4is a detailed cross-sectional view illustrating a power semiconductor module according to some embodiments.

[0057] Figure 5 is a cross-sectional view illustrating a power semiconductor device according to some embodiments.

[0058] Fig. 6A The current paths of a power semiconductor module are shown.

[0059] Figure 6B Shown are current paths of a power semiconductor module according to some embodiments.

[0060] 7A to 7E A manufacturing process of a power semiconductor module according to some embodiments is illustrated.

[0061] Figure 8 is a plan view illustrating a power semiconductor module according to some embodiments.

[0062] Fig. 9 is a cross-sectional view illustrating a power semiconductor module according to some embodiments.

[0063] Fig.10 is a cross-sectional view illustrating a power semiconductor module according to some embodiments.

[0064] Fig.11 is a circuit diagram illustrating an automotive inverter according to some embodiments.

[0065] Fig.12 is a plan view illustrating a power semiconductor module according to some embodiments.

[0066] Fig.13 is a cross-sectional view illustrating a power semiconductor module according to some embodiments. DETAILED DESCRIPTION

[0067] The embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings. The same or similar elements are given the same reference numerals, and redundant descriptions thereof are omitted. The suffixes "module" and "unit" used in the following description can be used interchangeably to facilitate the preparation of the specification, and they themselves do not have different meanings or functions from each other. In addition, the accompanying drawings are for the convenience of understanding the embodiments disclosed in this specification, and the technical concepts disclosed in this specification are not limited by the accompanying drawings. In addition, when an element such as a layer, a region or a substrate is referred to as being "on" another element, this means that the element can be directly on the other element or indirectly on the other element via one or more other intermediate elements arranged between the element and the other element.

[0068] Terms including ordinal numbers such as first and second may be used to describe various components, but the components are not limited by these terms. The above terms are used only for the purpose of distinguishing one component from another.

[0069] Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0070] In the present disclosure, it should be understood that terms such as “including,” “having,” or “providing” are intended to specify the presence of features, quantities, steps, operations, components, parts, or a combination thereof described in the specification, but do not exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0071] According to some embodiments, the power converter is used for an inverter or converter included in devices such as computers, home appliances, automobiles, solar equipment, and smart grids. The power converter may include one power semiconductor module or multiple power semiconductor modules. The power semiconductor module may include one or more power semiconductor devices.

[0072] exist Figures 1 to 11 In the illustrated embodiment, an automotive inverter for driving a motor included in a vehicle is described as a device including a power converter. Examples of the vehicle are environmentally friendly vehicles such as HEV, PHEV, EV, PCEV, and the like.

[0073] However, the use of the power converter is not limited to the motor in the vehicle. The power converter can be applied to an inverter or a converter in the above-mentioned other various technical fields.

[0074] In the following about Figures 1 to 11 In the described embodiments, the terms "switching element" and "power semiconductor device" may be used interchangeably. Similarly, the terms "leg" and "power semiconductor module" may be used interchangeably.

[0075] In the present disclosure, a power semiconductor module may refer to a module encapsulating at least one power semiconductor device for converting, distributing and / or controlling power input to at least one electronic device. Similarly, a power semiconductor device may refer to at least one semiconductor device for converting, distributing and / or controlling power input to at least one electronic device.

[0076] Figure 1 is a circuit diagram illustrating an automotive inverter according to some embodiments.

[0077] Reference Figure 1, the car inverter 1000 can be configured to convert DC power into AC power and supply the converted AC power to the load 1200 to drive the load 1200. In the car inverter 1000, the battery can be connected to the input terminal so that the DC power of the battery can be converted into AC power. Although not shown, the converter can be connected to the input terminal of the battery, and the input terminal of the converter can be connected to the charger of the charging station. In this case, the AC power supplied by the charger can be converted into DC power by the converter, and the converted DC power can charge the battery. In addition, the DC power charged in the battery can be converted into AC power by the car inverter 1000 and can be used to drive the load.

[0078] The load 1200 may be a motor, but is not limited thereto.

[0079] The automobile inverter 1000 may include a three-phase inverter-a first phase, a second phase and a third phase, but is not limited thereto. In this case, there may be a phase difference of 120 degrees between the first phase, the second phase and the third phase. The automobile inverter 1000 may include a plurality of branches 100A, 100B and 100C. For example, the first branch 100A, the second branch 100B and the third branch 100C may be connected to a load (i.e., a motor) in parallel via a first node N1, a second node N2 and a third node N3, respectively. The first branch 100A may include a first arm 100a and a second arm 100b connected in series to each other, the second branch 100B may include a third arm 100c and a fourth arm 100d connected in series to each other, and the third branch 100C may include a fifth arm 100e and a sixth arm 100f connected in series to each other. Here, the first arm 100a, the third arm 100c and the fifth arm 100e may be referred to as an upper arm, and the second arm 100b, the fourth arm 100d and the sixth arm 100f may be referred to as a lower arm. Each of the first to sixth arms 100a to 100f may be referred to as a switch module or a submodule.

[0080] The first arm 100a to the sixth arm 100f may include switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1 and diodes 100a-2 and 100b-2, 100c-2, 100d-2, 100e-2, and 100f-2, respectively. The switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, 100f-1 and the diodes 100a-2, 100b-2, 100c-2, 100d-2, 100e-2, and 100f-2 may be formed simultaneously using the same semiconductor process. Each of the switching elements 100 a - 1 , 100 b - 1 , 100 c - 1 , 100 d - 1 , 100 e - 1 , and 100 f - 1 may include at least one power semiconductor device.

[0081] In order to convert DC power into AC power by the inverter, the switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1 of each of the first to sixth arms 100a to 100f may be on / off controlled.

[0082] For example, when the first switching element 100a-1 of the first arm 100a of the first branch 100A is in the on state, the fourth switching element 100d-1 of the fourth arm 100d of the second branch 100B and / or the sixth switching element 100f-1 of the sixth arm 100f of the third branch 100C may be turned on. Thus, DC power may be supplied to the first phase inductor (not shown) of the motor.

[0083] For example, when the second switching element 100b-1 of the second arm 100b of the second branch 100B is in the on state, the sixth switching element 100f-1 of the sixth arm 100f of the third branch 100C and / or the second switching element 100b-1 of the second arm 100b of the first branch 100A may be turned on. Thus, DC power may be supplied to the second phase inductor (not shown) of the motor. The second phase may be delayed by 120 degrees relative to the first phase.

[0084] For example, when the third switching element 100c-1 of the third arm 100c of the third branch 100C is in the on state, the second switching element 100b-1 of the second arm 100b of the first branch 100A and / or the fourth switching element 100d-1 of the fourth arm 100d of the second branch 100B can be turned on. Therefore, DC power can be supplied to the third phase inductor (not shown) of the motor. The third phase can be delayed by 120 degrees relative to the second phase.

[0085] Therefore, AC power may be generated by the DC power supplied to each of the first phase inductor, the second phase inductor, and the third phase inductor.

[0086] Although not shown, the switching element of each of the first to sixth arms 100a to 100f (that is, the power semiconductor devices 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1) may be connected in series to one another.

[0087] Alternatively, although not shown, the switching element of each of the first to sixth arms 100a to 100f (that is, the power semiconductor devices 100a-1, 100b-1, 100c-1, 100d-1, 100e-1, and 100f-1) may be connected in parallel to each other.

[0088] Two or more of the switching elements 100a-1, 100b-1, 100c-1, 100d-1, 100e-1 and 100f-1 and the diodes 100a-2, 100b-2, 100c-2, 100d-2, 100e-2 and 100f-2 constituting the first to sixth arms 100a to 100f may be packaged and configured as a power semiconductor module.

[0089] As an example, each of the first branch 100A, the second branch 100B, and the third branch 100C can be configured as a power semiconductor module. That is, the first arm 100a and the second arm 100b of the first branch 100A can be packaged to form a first power semiconductor module. The third arm 100c and the fourth arm 100d of the second branch 100B can be packaged to form a second power semiconductor module. The fifth arm 100e and the sixth arm 100f of the third branch 100C can be packaged to form a third power semiconductor module.

[0090] In another example, the first branch 100A, the second branch 100B, and the third branch 100C may be configured as a single power semiconductor module. That is, the first arm 100a and the second arm 100b of the first branch 100A, the third arm 100c and the fourth arm 100d of the second branch 100B, and the fifth arm 100e and the sixth arm 100f of the third branch 100C may be packaged to form a single power semiconductor module.

[0091] Figure 2 is a plan view illustrating a power semiconductor module according to some embodiments. Figure 3 is a cross-sectional view illustrating a power semiconductor module according to some embodiments.

[0092] Figure 2 The power semiconductor module 201 shown may be Figure 1 One of the first branch 100A, the second branch 100B, and the third branch 100C is shown. Although not shown, the power semiconductor module 201 may include all of the first branch 100A, the second branch 100B, and the third branch 100C.

[0093] Reference Figure 2 and Figure 3 The power semiconductor module 201 may include a first substrate 210 , a second substrate 220 , a support member 230 , a first power semiconductor device 240 , and a second power semiconductor device 250 .

[0094] The second substrate 220 may be disposed on the first substrate 210, and the support member 230 may be disposed between the first substrate 210 and the second substrate 220. In this case, the first power semiconductor device 240 is disposed between the first substrate 210 and the support member 230, and the second power semiconductor device 250 is disposed between the support member 230 and the second substrate 220.

[0095] The first power semiconductor device 240 and the second power semiconductor device 250 may overlap vertically. The first power semiconductor device 240 and the second power semiconductor device 250 may overlap vertically between the first substrate 210 and the second substrate 220. The first power semiconductor device 240 and the second power semiconductor device 250 may overlap vertically with the support member 230 interposed therebetween. For example, the first power semiconductor device 240 may be disposed on a lower surface of a specific portion of the support member 230, and the second power semiconductor device 250 may be disposed on an upper surface of a specific portion of the support member 230. Therefore, the first power semiconductor device 240 and the second power semiconductor device 250 may overlap vertically in a specific portion of the support member 230.

[0096] The first power semiconductor device 240 and the second power semiconductor device 250 , which vertically overlap each other, may be connected in series.

[0097] As described above, the power semiconductor module 201 may include Figure 1 In this case, the first power semiconductor device 240 is one of the first switching element 100a-1 of the first arm 100a, the third switching element 100c-1 of the third arm 100c, and the fifth switching element 100e-1 of the fifth arm 100e, and the second power semiconductor device 250 may be one of the second switching element 100b-1 of the second arm 100b, the fourth switching element 100d-1 of the fourth arm 100d, and the sixth switching element 100f-1 of the sixth arm 100f.

[0098] The first power semiconductor device 240 and the second power semiconductor device 250 may be any one of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a P-type MOSFET.

[0099] Figure 5 is a cross-sectional view illustrating a power semiconductor device according to some embodiments.

[0100] Figure 5 The power semiconductor device 101 shown may be Figure 3 A first power semiconductor device 240 or a second power semiconductor device 250 is shown.

[0101] Reference Figure 5 , the power semiconductor device 101 may include a substrate 110, a first conductive type epitaxial layer 120, a second conductive type well 130, a first conductive type source region 140, a gate insulating layer 150, a gate electrode 160, and a drain electrode 105. The first conductive type may be an N type, and the second conductive type may be a P type, but they are not limited thereto.

[0102] For example, the power semiconductor device 101 may include a first conductive type epitaxial layer 120 formed on a substrate 110 and a second conductive type well 130 formed on the first conductive type epitaxial layer 120, a first conductive type source region 140 formed in the second conductive type well 130, a gate insulating layer 150 and a gate electrode 160 formed on the first conductive type source region 140, and a drain electrode 105 arranged under the substrate 110.

[0103] The substrate 110 and the first conductive type epitaxial layer 120 may include a semiconductor compound such as SiC, GaN, or Ga 2 O 3 .

[0104] Return to reference Figure 2 and Figure 3 , the first substrate 210 is disposed under the first power semiconductor device 240, and the second substrate 220 is disposed on the second power semiconductor device 250. The support member 230 may be disposed between the first power semiconductor device 240 and the second power semiconductor device 250.

[0105] The first substrate 210 and the second substrate 220 may be heat dissipation substrates having excellent heat dissipation characteristics. The first substrate 210 and the second substrate 220 may be electrode substrates having excellent electrical conductivity.

[0106] The first power semiconductor device 240 may be electrically connected to the first substrate 210. Heat generated in the first power semiconductor device 240 may be emitted to the outside through the first substrate 210. The second power semiconductor device 250 may be electrically connected to the second substrate 220. Heat generated in the second power semiconductor device 250 may be emitted to the outside through the second substrate 220.

[0107] The support member 230 may stably support the second power semiconductor device 250. The support member 230 may be referred to as a support body, a seat portion, a clip, or the like.

[0108] The support member 230 may be a conductive support member or a conductive member. That is, the support member 230 may be made of metal. The support member 230 may have a plate shape. The size of the support member 230 may be larger than the size of the first power semiconductor device 240 or the second power semiconductor device 250. In this case, the first power semiconductor device 240 may be disposed below the conductive support member 230 so that the upper surface of the first power semiconductor device 240 may be connected to the conductive support member 230 in surface contact. In addition, the second power semiconductor device 250 may be disposed on the conductive support member 230 so that the lower surface of the second power semiconductor device 250 may be connected to the conductive support member 230 in surface contact. In this way, since the first power semiconductor device 240 and / or the second power semiconductor device 250 are connected to the conductive support member 230 in a plate shape in surface contact, the contact resistance between the first power semiconductor device 240 and / or the second power semiconductor device 250 and the conductive support member 230 is minimized, thereby minimizing current loss. Therefore, switching loss of the first power semiconductor device 240 or the second power semiconductor device 250 does not occur, thereby achieving high power output and high-precision switching control.

[0109] The support member 230 may include a first portion 231, a second portion 232, and a connecting portion 233. The second portion 232 may be positioned higher than the first portion 231. The second power semiconductor device 250 may be disposed on the second portion 232. The second portion 232 is located in the center and the first portion 231 may be located on at least one side of the second portion 232. The connecting portion 233 may connect the first portion 231 and the second portion 232. The first portion 231, the second portion 232, and the connecting portion 233 may be integrally formed, but are not limited thereto.

[0110] In the drawing, the connection portion 233 has an inclined shape, but it may have a shape perpendicular to the ground or have other shapes.

[0111] The support member 230 may have a recess 235. The recess 235 may be formed by the first portion 231, the connecting portion 233, and the second portion 232. The recess 235 may be formed below the support member 230. This may be due to the fact that the second portion 232 is positioned higher than the first portion 231. That is, the recess 235 is formed by a step between the first portion 231 and the second portion 232 and the connecting portion 233 connecting the first portion 231 and the second portion 232.

[0112] The first power semiconductor device 240 may be accommodated in the recess 235 .

[0113] like Figure 2 As shown, the size of the support member 230 may be larger than the size of the first power semiconductor device 240 or the second power semiconductor device 250 .

[0114] The first portion 231 may be fixed to the first substrate 210 to enhance the stability of the support member 230. The support member 230 may be electrically connected to the first substrate 210. For example, the first portion 231 of the support member 230 may be electrically connected to the first substrate 210.

[0115] The support member 230 may be Figure 1 One of the first node N1, the second node N2, and the third node N3 shown. Therefore, when the first power semiconductor device 240 or the second power semiconductor device 250 is turned on, the power at the input side can be output to the load 1200. Therefore, the support member 230 can be an output terminal.

[0116] In some embodiments, the power semiconductor module 201 may include a spacer 260 .

[0117] The spacer 260 may be disposed between the first power semiconductor device 240 and the support member 230. The spacer 260 may be disposed on the first power semiconductor device 240. The spacer 260 may be made of a metal having excellent electrical conductivity. Therefore, the first power semiconductor device 240 may be electrically connected to the support member 230 through the spacer 260.

[0118] A portion of the upper side of the first power semiconductor device 240 (that is, the gate electrode) and the first substrate 210 may be electrically connected using a wire 290. In this case, a space between the first power semiconductor device 240 and the support 230 may be ensured to prevent an electrical short between the wire 290 and the support 230. To this end, a spacer 260 may be provided between the first power semiconductor device 240 and the support 230.

[0119] For example, the thickness of the spacer 260 may be ensured so that the upper surface of the spacer 260 is higher than the uppermost side of the conductive line 290 .

[0120] Since the wire 290 is connected to a portion of the upper side of the first power semiconductor device 240, the uppermost side of the wire 290 may be higher than the upper side of the first power semiconductor device 240. When there is no spacer 260, the wire 290 and the support member 230 may be electrically short-circuited. Therefore, a spacer 260 having a thickness thick enough so that the upper surface of the spacer 260 is higher than the uppermost side of the wire 290 may be provided on the first power semiconductor device 240, so that an electrical short circuit between the wire 290 and the support member 230 may be prevented.

[0121] like Figure 2 and Figure 3 As shown, the size of the second portion 232 of the support member 230 may be larger than the size of the spacer 260 . The size of the second portion 232 of the support member 230 may be larger than the size of the second power semiconductor device 250 .

[0122] Fig. 6A shows a current path of a power semiconductor module according to some embodiments, and Figure 6B Shown are current paths of a power semiconductor module according to some embodiments.

[0123] like Fig. 6A As shown, Fig. 6A The power semiconductor module shown includes a first power semiconductor device 3 and a second power semiconductor device 4 between a first substrate 1 and a second substrate 2. The first power semiconductor device 3 and the second power semiconductor device 4 are connected in series through the second substrate 2. In this case, a current path is formed by a first signal pattern (not shown) of the first substrate 1, the first power semiconductor device 3, the second substrate 2, the second power semiconductor device 4, and a second signal pattern (not shown) of the first substrate 1. Although not shown, the first power semiconductor device 3 and the second power semiconductor device 4 may be connected in series through the first substrate 1. In this case, a current path is formed by a first signal pattern (not shown) of the second substrate 2, the first power semiconductor device 3, the first substrate 1, the second power semiconductor device 4, and a second signal pattern (not shown) of the second substrate 2.

[0124] The first power semiconductor device 3 and the second power semiconductor device 4 are spaced apart at regular intervals to prevent an electrical short circuit between the first substrate 1 and the second substrate 2. Therefore, as the separation gap (or interval) between the first power semiconductor device 3 and the second power semiconductor device 4 increases, the current path (see arrow) between the first power semiconductor device 3 and the second power semiconductor device 4 increases. When the first power semiconductor device 3 or the second power semiconductor device 4 is turned off, the stray inductance increases due to the increase in the current path. Due to the increase in stray inductance, high power output is difficult. In addition, when the overshoot voltage caused by the increase in stray inductance exceeds the withstand voltage of the first power semiconductor device 3 or the second power semiconductor device 4, there is a problem that the first power semiconductor device 3 or the second power semiconductor device 4 is damaged or switching loss of the first power semiconductor device 3 or the second power semiconductor device 4 occurs.

[0125] However, if Figure 6B As shown, in the power semiconductor module 201, the first power semiconductor device 240 and the second power semiconductor device 250 may be connected in series via the support member 230 between the first substrate 210 and the second substrate 220. In this case, a current path is formed through the first substrate 210 (or its first signal pattern), the first power semiconductor device 240, the support member 230, the second power semiconductor device 250, and the second substrate (or its second signal pattern).

[0126] At this time, since the space between the first power semiconductor device 240 and the second power semiconductor device 250 is separated only by the thickness of the support member 230, the separation gap between the first power semiconductor device 240 and the second power semiconductor device 250 can be minimized. Therefore, since the current path between the first power semiconductor device 240 and the second power semiconductor device 250 is minimized, when the first power semiconductor device 240 or the second power semiconductor device 250 is turned off, the stray inductance can be minimized or not generated. Therefore, since the overshoot voltage is not generated or minimized and the overshoot voltage does not exceed the withstand voltage of the first power semiconductor device 240 or the second power semiconductor device 250, the first power semiconductor device 240 or the second power semiconductor device 250 may not be damaged. In addition, since the switching loss of the first power semiconductor device 240 or the second power semiconductor device 250 does not occur, a preset high power output is possible.

[0127] In addition, in the power semiconductor module 201, the first power semiconductor device 240 and the second power semiconductor device 250 can be vertically overlapped with the support member therebetween, so that the placement area of ​​the first power semiconductor device 240 and the second power semiconductor device 250 can be minimized. Therefore, the size of the power semiconductor module 201 or the power semiconductor device can be minimized. Therefore, more first power semiconductor devices 240 or second power semiconductor devices 250 can be installed per unit area in the power semiconductor module 201 or the power semiconductor device, thereby achieving higher power output.

[0128] The power semiconductor module 201 may include a plurality of first terminals 270 and a plurality of second terminals 280. The first terminals 270 may be input terminals and the second terminals 280 may be output terminals. Instead of terminals, it may also be referred to as terminals, pins, lead frames, etc.

[0129] The plurality of first terminals 270 may be electrically connected to the first substrate 210 and / or the second substrate 220. The plurality of second terminals 280 may be electrically connected to the first substrate 210 and / or the second substrate 220.

[0130] The plurality of first terminals 270 may be components for receiving gate signals, high potential voltages, low potential voltages, ground voltages, and other various signals. The plurality of second terminals 280 may be components for outputting output voltages, ground voltages, and other various signals.

[0131] In the drawing, the plurality of first terminals 270 are provided in four and the plurality of second terminals 280 are provided in four, but more terminals than these may be provided.

[0132] The power semiconductor module 201 may include a mold 295 .

[0133] The mold 295 may be disposed between the first substrate 210 and the second substrate 220. The mold 295 may surround the outer surface of the first power semiconductor device 240 between the first substrate 210 and the second substrate 220. The mold 295 may surround each of the plurality of first terminals 270 and each of the plurality of second terminals 280 between the first substrate 210 and the second substrate 220.

[0134] The mold 295 may be disposed outside the first substrate 210 and outside the second substrate 220. The mold 295 may surround each of the plurality of first terminals 270 on the outside of the first substrate 210. The mold 295 may surround each of the plurality of second terminals 280 on the outside of the second substrate 220.

[0135] The mold 295 is a semiconductor encapsulant and can be a material that encapsulates a power semiconductor device such as a silicon chip, a wire 290 or a lead frame to protect it from heat, moisture, impact, etc. For example, an epoxy molding compound (EMC) can be used as the mold 295. EMC is a composite material using about 10 raw materials such as silicon dioxide, epoxy resin, phenolic resin, carbon black and flame retardant. EMC can be used as a sealant for the first power semiconductor device 240, the second power semiconductor device 250, the plurality of first terminals 270 and the plurality of second terminals 280.

[0136] By using the EMC composite process, the mold 295 may be formed between the first substrate 210 and the second substrate 220 , outside the first substrate 210 , outside the second substrate 220 , and the like.

[0137] The first power semiconductor device 240 may be attached to the first substrate 210 and the support 230 using an adhesive member (not shown). For example, the first power semiconductor device 240 may be attached to the first substrate 210 and the support 230 using an adhesive process such as welding, sintering, or eutectic bonding. The second power semiconductor device 250 may be attached to the second substrate 220 and the support 230 using an adhesive member. For example, the second power semiconductor device 250 may be attached to the second substrate 220 and the support 230 using an adhesive process such as welding, sintering, or eutectic bonding.

[0138] The bonding member may be made of a metal or metal alloy having excellent electrical conductivity and / or bonding properties, but is not limited thereto. In the welding process, Pb or the like may be used as the bonding member. In the sintering process, Fe-Cu-C based materials and additives such as Ni, Mo, MnS, Pb, etc. may be used as the bonding member. During the eutectic bonding process, Sn-Pb, Cu-Sn, Au-Sn, Au-Si, etc. may be used as the bonding member.

[0139] Therefore, the first power semiconductor device 240 may be physically fixed and electrically connected to the first substrate 210 and the support 230 by the adhesive member. In addition, the second power semiconductor device 250 may be physically fixed and electrically connected to the second substrate 220 and the support 230 by the adhesive member.

[0140] Figure 4 is a detailed cross-sectional view illustrating a power semiconductor module.

[0141] Reference Figure 4The first power semiconductor device 240 may include a first gate electrode 241, a first source electrode 242, and a first drain electrode 243 outside thereof. When the first power semiconductor device 240 is turned on in response to a gate signal applied to the first gate electrode 241, current may flow from the first drain electrode 243 to the first source electrode 242.

[0142] The first drain electrode 243 may be disposed on the lower side, and the first gate electrode 241 and the first source electrode 242 may be disposed on the upper side. In this case, the first drain electrode 243 may be physically fixed and electrically connected to the upper side of the first substrate 210 by surface contact. The first source electrode 242 may be physically fixed and electrically connected to the lower side of the spacer 260 by surface contact. The first gate electrode 241 may be electrically connected to the first substrate 210 by a wire 290.

[0143] The second power semiconductor device 250 may include a second gate electrode 251, a second source electrode 252, and a second drain electrode 253 outside thereof. When the second power semiconductor device 250 is turned on in response to a gate signal applied to the second gate electrode 251, current may flow from the second drain electrode 253 to the second source electrode 252.

[0144] The second drain electrode 253 may be disposed on the lower side, and the second gate electrode 251 and the second source electrode 252 may be disposed on the upper side. In this case, the second drain electrode 253 may be physically fixed and electrically connected to the upper side of the support 230 in surface contact. The second source electrode 252 may be physically and electrically connected to the lower side of the second substrate 220 in surface contact. The second gate electrode 251 may be physically and electrically connected to the lower side of the second substrate 220 in surface contact.

[0145] The structures of the first power semiconductor device 240 and the second power semiconductor device 250 may be similar to Figure 5 The structures of the power semiconductor devices shown are the same, but are not limited thereto.

[0146] The first substrate 210 may include a plurality of layers. For example, the first substrate 210 may include a first metal layer 211 , a first insulating layer 212 , and a second metal layer 213 .

[0147] The first metal layer 211 may be made of a material having excellent conductivity. The first metal layer 211 may include a plurality of first signal patterns 211a to 211e. The plurality of first signal patterns 211a to 211e may be electrically connected to a plurality of first terminals 270, the first power semiconductor device 240, the support member 230, and a plurality of second terminals 280.

[0148] For example, each of the plurality of first-first signal patterns 211a may be physically fixed using an adhesive member and electrically connected to the plurality of first terminals 270. For example, each of the plurality of first-second signal patterns 211b may be physically fixed using an adhesive member and electrically connected to the plurality of second terminals 280. For example, the first-third signal pattern 211c may be physically fixed using an adhesive member and electrically connected to the first portion 231 of the support 230. The first-third signal pattern 211c is electrically connected to one of the plurality of second terminals 280 so that a positive polarity voltage or a negative polarity voltage may be supplied to the outside according to the conduction of the first power semiconductor device 240 or the second power semiconductor device 250.

[0149] For example, the first to fourth signal patterns 211d may be physically fixed and electrically connected to the first drain electrode 243 of the first power semiconductor device 240 by using an adhesive member. The first to fourth signal patterns 211d may be electrically connected to one of the plurality of first terminals 270 to receive a high potential voltage (or a positive polarity voltage) from the outside. For example, the first to fifth signal patterns 211e may be electrically connected to the first gate electrode 241 of the first power semiconductor device 240 through a wire 290. The first to fifth signal patterns 211e may be electrically connected to one of the plurality of first terminals 270 to receive a gate signal from the outside.

[0150] The first insulating layer 212 may electrically insulate the first metal layer 211 from the second metal layer 213. The first insulating layer 212 may be made of a ceramic material having high thermal conductivity, such as Al2O3.

[0151] The second metal layer 213 may be made of a material having excellent heat dissipation characteristics. One side of the second metal layer 213 may be in contact with the first insulating layer 212 and heat may be emitted to the other side of the second metal layer 213. Although not shown, a heat dissipation device including a cooling medium may be provided on the other side of the second metal layer 213.

[0152] The second substrate 220 may include a plurality of layers. For example, the second substrate 220 may include a third metal layer 221 , a second insulating layer 222 , and a fourth metal layer 223 .

[0153] The third metal layer 221 may be made of a material having excellent conductivity. The third metal layer 221 may include a plurality of second signal patterns 221a to 221d. The plurality of second signal patterns 221a to 221d may be electrically connected to the plurality of first terminals 270, the second power semiconductor device 250, and the plurality of second terminals 280.

[0154] For example, the plurality of second-first signal patterns 221a are input signal patterns and may be physically fixed and electrically connected to the plurality of first terminals 270 using an adhesive member. For example, the plurality of second-second signal patterns 221b are output signal patterns and may be physically fixed and electrically connected to the plurality of second terminals 280 using an adhesive member. For example, the second-third signal pattern 221c may be physically fixed and electrically connected to the second gate electrode 251 of the second power semiconductor device 250 using an adhesive member. The second-third signal pattern 221c is electrically connected to one of the plurality of second terminals 280 to receive a gate signal from the outside. For example, the second-fourth signal pattern 221d may be physically fixed and electrically connected to the second source electrode 252 of the second power semiconductor device 250 using an adhesive member. For example, the second-fourth signal pattern 221d may be electrically connected to one of the plurality of second terminals 280 to receive a low potential voltage (or a negative polarity voltage) from the outside.

[0155] The second insulating layer 222 may electrically insulate the third metal layer 221 and the fourth metal layer 223 from each other. The second insulating layer 222 may be made of a ceramic material having high thermal conductivity, such as Al2O3.

[0156] The fourth metal layer 223 may be made of a material having excellent heat dissipation characteristics. One side of the fourth metal layer 223 may be in contact with the second insulating layer 222 and heat may be emitted to the other side. Although not shown, a heat dissipation device including a cooling medium may be provided on the other side of the fourth metal layer 223.

[0157] Return to reference Figure 4 , each of the plurality of first terminals 270 may include a first-first terminal 271 , a first insulating layer 272 , and a first-second terminal 273 .

[0158] The first insulating layer 272 may electrically insulate the first-first terminal 271 and the first-second terminal 273 from each other. The first-first terminal 271 may be physically fixed and electrically connected to the first-first signal pattern 211a of the first substrate 210. The first-second terminal 273 may be physically fixed and electrically connected to the second-first signal pattern 221a of the second substrate 220.

[0159] Each of the plurality of second terminals 280 may include a second-first terminal 281 , a second insulating layer 282 , and a second-second terminal 283 .

[0160] The second insulating layer 282 may electrically insulate the second-first terminal 281 and the second-second terminal 283 from each other. The second-first terminal 281 may be physically fixed and electrically connected to the first-second signal pattern 211b of the first substrate 210. The second-second terminal 283 may be physically fixed and electrically connected to the second-second signal pattern 221b of the second substrate 220.

[0161] As described above, the first power semiconductor device 240 and the second power semiconductor device 250 may overlap vertically. In this case, the first power semiconductor device 240 and the second power semiconductor device 250 may be connected in series, with the support member 230 and the spacer 260 interposed therebetween. That is, the spacer 260 and the support member 230 are electrically connected to each other, the first source electrode 242 of the first power semiconductor device 240 is electrically connected to the spacer 260, and the second drain electrode 253 of the second power semiconductor device 250 is electrically connected to the support member 230, so that the first power semiconductor device 240 and the second power semiconductor device 250 may be connected in series.

[0162] exist Fig. 6A In the embodiment of the present invention, when the first power semiconductor device 3 and the second power semiconductor device 4 are connected in series horizontally through the second substrate 2, due to the separation gap between the first power semiconductor device 3 and the second power semiconductor device 4, the current path between the first power semiconductor device 3 and the second power semiconductor device 4 increases, thereby increasing the stray inductance. Due to the increase in stray inductance, the first power semiconductor device 3 or the second power semiconductor device 4 is damaged. In addition, the switching loss of the first power semiconductor device 3 or the second power semiconductor device 4 increases due to the increase in stray inductance, and it is difficult to obtain a preset high power output due to such switching loss. In addition, since the first power semiconductor device 3 or the second power semiconductor device 4 is spaced apart from each other in the horizontal direction, the size increases, and a larger size is required to increase the high power output.

[0163] However, if Figure 6B As shown, in the power semiconductor module 201 according to some embodiments, the first power semiconductor device 240 and the second power semiconductor device 250 can be connected in series vertically through the support member 230, and the current path is significantly reduced, so that stray inductance does not occur or can be minimized. Therefore, damage to the first power semiconductor device 240 or the second power semiconductor device 250 is prevented, and switching loss is not generated, so that a preset high power output is possible. In addition, by arranging the first power semiconductor device 240 and the second power semiconductor device 250 in the vertical direction, the size is reduced, so that the output characteristics per unit area can be improved. In addition, the size and weight of the product are significantly reduced, thereby improving the fuel efficiency of the vehicle including the power semiconductor module 201.

[0164] 7A to 7E A manufacturing process of a power semiconductor module according to some embodiments is illustrated.

[0165] like Fig. 7A As shown, a support member 230 may be provided. The support member 230 may be made of metal.

[0166] The support member 230 may include a first portion 231, a second portion 232, and a connecting portion 233. The second portion 232 may be positioned higher than the first portion 231. The connecting portion 233 may connect the first portion 231 and the second portion 232. A recess 235 may be formed by the first portion 231, the connecting portion 233, and the second portion 232, and the recess 235 may be formed below the second portion 232. The first portion 231, the connecting portion 233, and the second portion 232 may be integrally formed, but are not limited thereto.

[0167] The second power semiconductor device 250 may be formed on the support 230. The second power semiconductor device 250 may be formed on the second portion 232 of the support 230. The second power semiconductor device 250 may be attached to the support 230 using an adhesive member. For example, after an adhesive member is formed on a lower side of the second power semiconductor device 250 or an upper side of the second portion 232 of the support 230, the second power semiconductor device 250 may be attached to the support 230 by an adhesive process.

[0168] like Figure 7B As shown, a first substrate 210 may be provided. The first substrate 210 may be made of a material having excellent electrical conductivity and / or heat dissipation properties.

[0169] The first power semiconductor device 240 may be formed on the first substrate 210. The first power semiconductor device 240 may be attached to the first substrate 210 using an adhesive member. The first power semiconductor device 240 may be electrically connected to the first substrate 210 through the adhesive member.

[0170] The spacer 260 may be formed on the first power semiconductor device 240. The spacer 260 may be attached to the first power semiconductor device 240 using an adhesive member. The spacer 260 may be electrically connected to the first power semiconductor device 240 through the adhesive member.

[0171] The first power semiconductor device 240 may be electrically connected to the first substrate 210 through a wire 290 .

[0172] Reference Figure 4 The first power semiconductor device 240 may have a first drain electrode 243 disposed on a lower side thereof and a first source electrode 242 and a first gate electrode 241 disposed on an upper side thereof.

[0173] The first drain electrode 243 of the first power semiconductor device 240 can be electrically connected to the first to fourth signal patterns 211d of the first substrate 210 through an adhesive member, and the first source electrode 242 of the first power semiconductor device 240 can be electrically connected to the spacer 260 through an adhesive member, and the first gate electrode 241 of the first power semiconductor device 240 can be electrically connected to the first to fifth signal patterns 211e of the first substrate 210 through a wire 290.

[0174] like Figure 7C As shown, one side of the support member 230 may be fixed to the first substrate 210. The first portion 231 of the support member 230 may be attached to the first substrate 210 by an adhesive member. Figure 4 , the first portion 231 of the support 230 may be electrically connected to the first to third signal patterns 211 c of the first substrate 210 through an adhesive member.

[0175] The second portion 232 of the support 230 is positioned higher than the uppermost side of the conductive line 290 , so that an electrical short circuit between the conductive line 290 and the support 230 can be prevented by making the recess 235 sufficiently large.

[0176] The spacer 260 can maintain the second portion 232 of the support member 230 at a constant height without sagging downward. Therefore, the spacer 260 prevents the second portion 232 of the support member 230 from sagging downward while maintaining the second portion 232 of the support member 230 at a constant height, thereby preventing an electrical short circuit between the support member 230 and the wire 290. In addition, the spacer 260 can serve as a medium for electrical connection between the first power semiconductor device 240 and the support member 230.

[0177] like Fig.7D As shown, after positioning the plurality of first terminals 270 and the plurality of second terminals 280 on both sides of the first substrate 210 , the second substrate 220 may be placed on the first substrate 210 , the plurality of first terminals 270 , and the plurality of second terminals 280 .

[0178] Thereafter, by pressurizing the first substrate 210 and / or the second substrate 220 and applying heat, the plurality of first terminals 270 and the plurality of second terminals 280 may be attached to the first substrate 210, and the plurality of first terminals 270, the plurality of second terminals 280, and the second power semiconductor device 250 may be attached to the second substrate 220. An adhesive member may be pre-formed on the lower side of the second substrate 220 or on the upper side of each of the plurality of first terminals 270, the plurality of second terminals 280, and the second power semiconductor device 250. Therefore, the plurality of first terminals 270 and the plurality of second terminals 280 may be attached to the first substrate 210 by the adhesive member, and the plurality of first terminals 270 and the plurality of second terminals 280 and the second power semiconductor device 250 may be attached to the second substrate 220.

[0179] Reference Figure 4 , a plurality of first-first terminals 271 may be physically fixed by an adhesive member and electrically connected to a plurality of first-first signal patterns 211a of the first substrate 210. A plurality of first-second terminals 273 may be physically fixed by an adhesive member and electrically connected to a plurality of second-first signal patterns 221a of the second substrate 220. A plurality of second-first terminals 281 may be physically fixed by an adhesive member and electrically connected to a plurality of first-second signal patterns 211b of the first substrate 210. A plurality of second-second terminals 283 may be physically fixed by an adhesive member and electrically connected to a plurality of second-second signal patterns 221b of the second substrate 220. A second gate electrode 251 and a second source electrode 252 may be disposed on an upper side of the second power semiconductor device 250. The second source electrode 252 of the second power semiconductor device 250 may be physically fixed by an adhesive member and electrically connected to the second-fourth signal pattern 221d of the second substrate 220. The second gate electrode 251 of the second power semiconductor device 250 may be physically fixed by an adhesive member and electrically connected to the second-third signal pattern 221c of the second substrate 220.

[0180] like Fig. 7E As shown, a mold 295 is formed between the first substrate 210 and the second substrate 220, outside the first substrate 210 and outside the second substrate 220 using an EMC composite process. Figure 2 and Figure 3 201).

[0181] Figure 8 is a plan view illustrating a power semiconductor module according to some embodiments.

[0182] In addition to the opening 236, Figure 8 The embodiment shown is similar to Figure 2 The embodiment shown is the same. Figure 8 In the Figure 2 Components having the same shape, structure and / or function are given the same reference numerals, and detailed description is omitted.

[0183] Reference Figure 4 and Figure 8 The power semiconductor module 202 may include a first substrate 210, a second substrate 220, a support 230, a first power semiconductor device 240, and a second power semiconductor device 250. The power semiconductor module 202 may include a spacer 260, a plurality of first terminals 270, a plurality of second terminals 280, and a mold 295.

[0184] The support member 230 may include a first portion 231, a second portion 232, and a connecting portion 233. The connecting portion 233 may connect the first portion 231 and the second portion 232. The first portion 231, the connecting portion 233, and the second portion 232 may be integrally formed, but are not limited thereto. The second portion 232 may be positioned higher than the first portion 231. A recess 235 may be formed by the first portion 231, the connecting portion 233, and the second portion 232. The recess 235 may be formed below the second portion 232.

[0185] In this case, the first power semiconductor device 240 may be disposed in the recess 235 and the second power semiconductor device 250 may be disposed on the second portion 232. The first power semiconductor device 240 and the second power semiconductor device 250 may vertically overlap with the second portion 232 of the support member 230 interposed therebetween.

[0186] In addition, a spacer 260 may be formed in the recess 235. The spacer 260 may be disposed on the first power semiconductor device 240.

[0187] In the first power semiconductor device 240, the first drain electrode 243 may be disposed on the lower side thereof, and the first gate electrode 241 and the first source electrode 242 may be disposed on the upper side thereof. In this case, the first drain electrode 243 may be electrically connected to the first to fourth signal patterns 211 d of the first substrate 210, the first gate electrode 241 may be electrically connected to the first to fifth signal patterns 211 e of the first substrate 210 through the wire 290, and the first source electrode 242 may be electrically connected to the spacer 260.

[0188] When the gate signal is supplied to the first gate electrode 241 of the first power semiconductor device 240 through the wire 290 and the first power semiconductor device 240 is turned on, the high potential voltage (or positive polarity voltage) can be supplied to the support member 230 via the first power semiconductor device 240 and the spacer 260. Therefore, since different voltages are supplied to the wire 290 and the support member 230, they must not be electrically short-circuited. However, since the wire 290 can be bent in a curved shape or moved to a higher position, an electrical short circuit may occur between the wire 290 and the support member 230.

[0189] To overcome this problem, an opening 236 may be formed in the support member 230 in the power semiconductor module 202. For example, the opening 236 may be formed to correspond to the wire 290. For example, the opening 236 may be formed in the second portion 232 of the support member 230. For example, the opening 236 may be formed in the connection portion 233 of the support member 230. For example, the opening 236 may be formed in the first portion 231 of the support member 230.

[0190] Therefore, even if the conductive line 290 is deformed, the conductive line 290 may be located in the opening 236 of the support member 230 , so that an electrical short circuit between the support member 230 and the conductive line 290 may be prevented.

[0191] Fig. 9 is a cross-sectional view illustrating a power semiconductor module.

[0192] In addition to the shape of the support member 230, Fig. 9 The embodiment shown is similar to Figure 3 and / or Figure 4 The embodiment shown is the same. Fig. 9 In the illustrated embodiment, components having the same shape, structure, and / or function as those in the previously discussed embodiment are given the same reference numerals, and a detailed description is omitted.

[0193] Reference Fig. 9 The power semiconductor module 203 may include a first substrate 210 , a second substrate 220 , a support 230 , a first power semiconductor device 240 , and a second power semiconductor device 250 . The power semiconductor module 203 may include a spacer 260 , a plurality of first terminals 270 , a plurality of second terminals 280 , and a mold 295 .

[0194] The support member 230 may include a first portion 231, a second portion 232, and a connecting portion 233. The connecting portion 233 may connect the first portion 231 and the second portion 232. The first portion 231, the connecting portion 233, and the second portion 232 may be integrally formed, but are not limited thereto. The second portion 232 may be positioned higher than the first portion 231.

[0195] The connection portion 233 may have a shape perpendicular to the ground. Figure 3 and / or Figure 4 In the embodiment shown, the connecting portion 233 has a shape inclined relative to the ground. Fig. 9 In each of the illustrated embodiments, the connection portion 233 may have a shape perpendicular to the ground.

[0196] according to Fig. 9 In the illustrated embodiment, since the connection portion 233 has a shape perpendicular to the ground, the connection portion 233 is further spaced apart from the wire 290 , thereby further reducing the possibility of an electrical short circuit between the support member 230 and the wire 290 .

[0197] according to Fig. 9 In the embodiment shown, since the connection portion 233 has a shape perpendicular to the ground, the rigidity of the support member 230 can be further increased. Therefore, the stability of the support member 230 can be enhanced, and the left-right displacement of the support member 230 can be suppressed, so that the possibility of an electrical short circuit between the support member 230 and the wire 290 can be further reduced. In addition, as the support strength of the support member 230 increases, the second power semiconductor device 250 can be stably supported.

[0198] Fig.10 is a cross-sectional view illustrating a power semiconductor module according to some embodiments.

[0199] In addition to the support member 230 and the spacer 260 being integrally formed, Fig.10 The embodiment shown is similar to Figure 3 , Figure 4 and / or Fig. 9 The embodiment shown is the same. Fig.10 In the embodiment shown, Figure 3 , Figure 4 and / or Fig. 9 Those components of the illustrated embodiments that have the same shape, structure, and / or function are given the same reference numerals, and detailed description is omitted.

[0200] Reference Fig.10 The power semiconductor module 204 may include a first substrate 210, a second substrate 220, a support 230, a first power semiconductor device 240, and a second power semiconductor device 250. The power semiconductor module 204 may include a spacer 260, a plurality of first terminals 270, a plurality of second terminals 280, and a mold 295.

[0201] The support member 230 may include a first portion 231, a second portion 232, and a connecting portion 233. The connecting portion 233 may connect the first portion 231 and the second portion 232. The first portion 231, the connecting portion 233, and the second portion 232 may be integrally formed, but are not limited thereto. The second portion 232 may be positioned higher than the first portion 231. A recess 235 may be formed by the first portion 231, the connecting portion 233, and the second portion 232. The recess 235 may be formed below the second portion 232.

[0202] In this case, the first power semiconductor device 240 may be disposed in the recess 235 and the second power semiconductor device 250 may be disposed on the second portion 232. The first power semiconductor device 240 and the second power semiconductor device 250 may vertically overlap with the second portion 232 of the support member 230 interposed therebetween.

[0203] In addition, a spacer 260 may be formed in the recess 235. The spacer 260 may be disposed on the first power semiconductor device 240.

[0204] exist Fig.10 In the power semiconductor module 204 shown, the support member 230 and the spacer 260 may be formed integrally. In other words, the spacer 260 may protrude from the support member 230 toward the first power semiconductor device 240 .

[0205] As an example, the support member 230 may be etched using an etching process to form an unetched area as the spacer 260. As another example, the spacer 260 may be attached to the lower side of the support member 230 using an adhesive process. As another example, a plurality of metal layers may be formed under the support member 230 by using a plurality of deposition processes, and the plurality of metal layers may be formed as the spacer 260. In addition, the support member 230 and the spacer 260 may be integrally formed by various processes.

[0206] exist Fig.10 In the illustrated embodiment, a process of attaching the spacer 260 and the supporter 230 using an adhesive member is not required, so that the process can be simplified.

[0207] Fig.11 is a circuit diagram illustrating an automotive inverter according to some embodiments.

[0208] In addition to the plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1, and 100f2 being connected in parallel to each arm 100a to 100f, Fig.11 The embodiment shown is similar to Figure 1The embodiments shown are identical.

[0209] Reference Fig.11 , the automobile inverter 2000 may include a three-phase inverter, but is not limited thereto. The automobile inverter 2000 may include a plurality of branches 100A, 100B, and 100C. For example, the first branch 100A, the second branch 100B, and the third branch 100C may be connected in parallel to the load 1200 (that is, the motor) through the first node N1, the second node N2, and the third node N3, respectively. The first branch 100A may include a first arm 100a and a second arm 100b connected in series to each other, and the second branch 100B may include a third arm 100c and a fourth arm 100d connected in series to each other. Here, the first arm 100a, the third arm 100c, and the fifth arm 100e are referred to as upper arms, and the second arm 100b, the fourth arm 100d, and the sixth arm 100f are referred to as lower arms.

[0210] Each of the first to sixth arms 100a to 100f has a plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1, and 100f2 connected in parallel. Although not shown, in the first to sixth arms 100a to 100f, the plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1, and 100f2 may be connected in parallel to diodes 100a-2, 100b-2, 100c-2, 100d-2, 100e-2, and 100f-2, respectively.

[0211] In the first arm 100a, a plurality of first power semiconductor devices 100a1 and 100a2 may be connected in parallel. In the second arm 100b, a plurality of second power semiconductor devices 100b1 and 100b2 may be connected in parallel. In the third arm 100c, a plurality of first power semiconductor devices 100c1 and 100c2 may be connected in parallel. In the fourth arm 100d, a plurality of second power semiconductor devices 100d1 and 100d2 may be connected in parallel. In the fifth arm 100e, a plurality of first power semiconductor devices 100e1 and 100e2 may be connected in parallel. In the sixth arm 100f, a plurality of second power semiconductor devices 100f1 and 100f2 may be connected in parallel.

[0212] In this case, one side of each of the plurality of first power semiconductor devices 100a1 and 100a2 of the first arm 100a, one side of each of the plurality of first power semiconductor devices 100c1 and 100c2 of the third arm 100c, and one side of each of the plurality of first power semiconductor devices 100e1 and 100e2 of the fifth arm 100e may be connected in common. Here, one side may be a drain electrode.

[0213] The other side of each of the plurality of first power semiconductor devices 100a1 and 100a2 of the first arm 100a may be connected in common and connected to the first node N1. The other side of each of the plurality of first power semiconductor devices 100c1 and 100c2 of the third arm 100c may be connected in common and connected to the second node N2. The other side of each of the plurality of first power semiconductor devices 100e1 and 100e2 of the fifth arm 100e may be connected in common and connected to the third node N3. Here, the other side may be a source electrode.

[0214] One side of each of the plurality of second power semiconductor devices 100b1 and 100b2 of the second arm 100b may be commonly connected and connected to the first node N1. One side of each of the plurality of second power semiconductor devices 100d1 and 100d2 of the fourth arm 100d may be commonly connected and connected to the second node N2. One side of each of the plurality of second power semiconductor devices 100f1 and 100f2 of the sixth arm 100f may be commonly connected and connected to the third node N3. Here, one side may be a drain electrode.

[0215] The other side of each of the plurality of second power semiconductor devices 100b1 and 100b2 of the second arm 100b, the other side of each of the plurality of second power semiconductor devices 100d1 and 100d2 of the fourth arm 100d, and the other side of each of the plurality of second power semiconductor devices 100f1 and 100f2 of the sixth arm 100f may be connected in common. Here, one side may be a source electrode.

[0216] Each of the plurality of first power semiconductor devices 100a1 and 100a2 of the first arm 100a included in the first branch 100A and each of the plurality of second power semiconductor devices 100b1 and 100b2 of the second arm 100b may be connected in series. Each of the plurality of first power semiconductor devices 100c1 and 100c2 of the third arm 100c included in the second branch 100B and each of the plurality of second power semiconductor devices 100d1 and 100d2 of the fourth arm 100d may be connected in series. Each of the plurality of first power semiconductor devices 100e1 and 100e2 of the fifth arm 100e included in the third branch 100C and each of the plurality of second power semiconductor devices 100f1 and 100f2 of the sixth arm 100f may be connected in series.

[0217] In this way, a plurality of power semiconductor devices 100a1, 100a2, 100b1, 100b2, 100c1, 100c2, 100d1, 100d2, 100e1, 100e2, 100f1 and 100f2 may be connected in parallel to each arm 100a to 100f, so that current characteristics may be improved and higher power output may be achieved.

[0218] Fig.12 is a plan view illustrating a power semiconductor module according to some embodiments. Fig.13 is a cross-sectional view illustrating a power semiconductor module according to some embodiments.

[0219] Fig.13 The power semiconductor module 205 shown may be Fig.11 One of the first branch 100A, the second branch 100B, and the third branch 100C shown. Although not shown, the power semiconductor module 205 may be included in any one or more of the first branch 100A, the second branch 100B, and the third branch 100C.

[0220] In addition to the plurality of first power semiconductor devices 240 and 245 and the plurality of second power semiconductor devices 250 and 255, Fig.12 The embodiment shown is the same as the embodiment described above. Fig.12 Components having the same shape, structure and / or function as those in the above-described embodiment are given the same reference numerals, and detailed description is omitted.

[0221] Reference Fig.12 and Fig.13The power semiconductor module 205 may include a first substrate 210, a second substrate 220, a support 230, a plurality of first power semiconductor devices 240 and 245, and a plurality of second power semiconductor devices 250 and 255. The power semiconductor module 205 may include a plurality of spacers 260 and 265, a plurality of first terminals 270, a plurality of second terminals 280, and a mold 295.

[0222] The first substrate 210 , the second substrate 220 , the support member 230 , the plurality of first terminals 270 , and the plurality of second terminals 280 have been described in the above embodiment. Therefore, a detailed description is omitted.

[0223] A plurality of spacers 260 and 265 may be disposed between the first substrate 210 and the support member 230. A plurality of spacers 260 and 265 may be disposed on the plurality of first power semiconductor devices 240 and 245, respectively. Although not shown, the plurality of spacers 260 and 265 may be integrally formed as a single spacer, rather than being individually separated. Therefore, a single spacer may be disposed not only on the plurality of first power semiconductor devices 240 and 245, but also in the space between the plurality of first power semiconductor devices 240 and 245.

[0224] The plurality of first power semiconductor devices 240 and 245 may include Fig.11 The first arm 100a of the first branch 100A, the third arm 100c of the second branch 100B, and / or the fifth arm 100e of the third branch 100C are shown. A plurality of first power semiconductor devices 240 and 245 may be connected in parallel. One side of each of the plurality of first power semiconductor devices 240 and 245 may be commonly connected to the first substrate 210, and the other side of each of the plurality of first power semiconductor devices may be connected to a plurality of spacers 260 and 265. A plurality of spacers 260 and 265 may be commonly connected to the support member 230. Here, the one side may be the first drain electrode 243, and the other side may be the first source electrode 242.

[0225] The other side of each of the plurality of first power semiconductor devices 240 and 245 may be connected to the first substrate 210 through a plurality of wires 290 and 291. For example, the other side of each of the plurality of first power semiconductor devices 240 and 245 may be connected to the first substrate 210 independently or collectively through a plurality of wires 290 and 291. Here, the other side may be the first gate electrode 241,

[0226] The plurality of second power semiconductor devices 250 and 255 may be included in Fig.11The second arm 100b of the first branch 100A, the fourth arm 100d of the second branch 100B, and / or the sixth arm 100f of the third branch 100C are shown. One side of each of the plurality of second power semiconductor devices 250 and 255 may be commonly connected to the support member 230, and the other side of each of the plurality of second power semiconductor devices 250 and 255 may be commonly connected to the second substrate 220. Here, the one side may be the second drain electrode 253, and the other side may be the second source electrode 252.

[0227] The other side of each of the plurality of second power semiconductor devices 250 and 255 may be connected to the second substrate 220. For example, the other side of each of the plurality of second power semiconductor devices 250 and 255 may be independently or commonly connected to the second substrate 220. Here, an example of the other side may be the second gate electrode 251.

[0228] Each of the plurality of first power semiconductor devices 240 and 245 and each of the plurality of second power semiconductor devices 250 and 255 may overlap vertically. For example, each of the plurality of first power semiconductor devices 240 and 245 and each of the plurality of second power semiconductor devices 250 and 255 may overlap vertically with the support member 230 therebetween. The plurality of first power semiconductor devices 240 and 245 and the plurality of second power semiconductor devices 250 and 255 may be connected in series through the support member 230.

[0229] Although not shown, multiple first power semiconductor devices 240 and 245 included in the first arm 100a, the third arm 100c and the fifth arm 100e can be connected in series to increase the withstand voltage characteristics, and multiple second power semiconductor devices 250 and 255 included in the second arm 100b, the fourth arm 100d and the sixth arm 100f can be connected in series.

[0230] Although not shown, the plurality of first power semiconductor devices 240 and 245 may be connected in parallel in the horizontal direction or in series in the vertical direction. Alternatively, the plurality of first power semiconductor devices 240 and 245 may be connected in parallel in the horizontal direction or in series in the vertical direction.

[0231] The plurality of second power semiconductor devices 250 and 255 may be connected in parallel in the horizontal direction or in series in the vertical direction. Alternatively, the plurality of second power semiconductor devices 250 and 255 may be connected in parallel in the horizontal direction or in series in the vertical direction.

[0232] according to Fig.12In the illustrated embodiment, a plurality of first power semiconductor devices 240 and 245 may be connected in parallel, and a plurality of second power semiconductor devices 250 and 255 may be connected in parallel, so that current characteristics may be improved and high power output may be achieved.

[0233] The above detailed description should not be interpreted as limiting in all aspects and should be regarded as illustrative. The scope of the embodiments should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent range of the embodiments are included in the scope of the embodiments.

[0234] Although various embodiments are described herein, it should be understood that they are presented by way of example only and not limitation. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments. In addition, unless otherwise indicated herein or clearly contradictory to the context, any combination of the above elements in all possible variations thereof is encompassed by the present disclosure.

[0235] In addition, although the processes illustrated above and in the accompanying drawings are shown as a series of steps, this is only for illustrative purposes. Therefore, it is contemplated that some steps can be added, some steps can be omitted, the order of the steps can be rearranged, and some steps can be performed in parallel.

Claims

1. A power semiconductor module, comprising: a first substrate; a second substrate formed above the first substrate; a conductive member disposed between the first substrate and the second substrate; a first power semiconductor device disposed between the first substrate and the conductive member; as well as a second power semiconductor device, the second power semiconductor device being disposed between the conductive member and the second substrate, wherein The conductive member is electrically connected to the first power semiconductor device and the second power semiconductor device.

2. The power semiconductor module according to claim 1, wherein: The first power semiconductor device and the second power semiconductor device at least partially overlap.

3. The power semiconductor module according to claim 1, wherein: The first power semiconductor device and the second power semiconductor device are electrically connected in series.

4. The power semiconductor module according to claim 1, wherein: The conductive member comprises: Part II; and a connecting portion connected to the second portion, and The second power semiconductor device is disposed on a surface of the second portion.

5. The power semiconductor module according to claim 4, wherein: The conductive member comprises: a first portion, the first portion being positioned lower than the second portion and connected to the connecting portion, The conductive member includes a recess formed by the first portion, the connecting portion, and the second portion, and The first power semiconductor device is disposed in the recess. 6 . The power semiconductor module according to claim 1 , further comprising a spacer disposed between the first power semiconductor device and the conductive member.

7. The power semiconductor module according to claim 6, wherein: The first power semiconductor device includes a first gate electrode, a first source electrode and a first drain electrode, The first gate electrode is electrically connected to the first substrate using a wire, The first source electrode is electrically connected to the conductive member, and The first drain electrode is electrically connected to the first substrate, wherein an upper surface of the spacer is located at a higher position than an uppermost position of the wire.

8. The power semiconductor module according to claim 1, further comprising: a plurality of first power semiconductor devices, the plurality of first power semiconductor devices including the first power semiconductor device; as well as a plurality of second power semiconductor devices, the plurality of second power semiconductor devices including the second power semiconductor device, wherein: The plurality of first power semiconductor devices are connected in parallel between the first substrate and the conductive member, and The plurality of second power semiconductor devices are connected in parallel between the conductive member and the second substrate.

9. The power semiconductor module according to claim 1, wherein: A current path is configured to be formed through the first substrate, the first power semiconductor device, the conductive member, the second power semiconductor device, and the second substrate in this order.

10. A method for forming a power semiconductor module, the method comprising the following steps: forming a first substrate; forming a first power semiconductor device on the first substrate; forming a conductive member over the first power semiconductor device such that the first power semiconductor device is disposed between the first substrate and the conductive member; forming a second power semiconductor device on the conductive member; A second substrate is formed above the second power semiconductor device so that the second power semiconductor device is disposed between the conductive member and the second substrate, wherein: The conductive member is disposed between the first substrate and the second substrate.

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