Integrated packaging structure and preparation method thereof
By adopting an interposer structure in the integrated packaging structure, integrating passive devices and power modules, and connecting chips and external circuit modules through conductive via structures, the poor performance in traditional processes is solved, and higher integration density and heat dissipation are achieved.
Patent Information
- Application Number
- CN202411691667.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-02-25
AI Technical Summary
During the formation process, traditional integrated packaging structures use organic film layers such as polyimide (PI) and photolithography copper plating processes, resulting in poor product performance.
The interposer structure is adopted, including an interposer substrate, a wiring layer and a conductive via structure, and the first passive device and/or a power supply module are integrated, the chip and the external circuit module are connected through the conductive via structure, and the chip and the interposer structure are covered with a plastic sealing layer.
Connecting the chip with the external circuit module through the interposer structure improves the circuit integration density and heat dissipation, reduces the risk of structural warping, and saves preparation time and cost.
Smart Images
Figure CN119517895A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated packaging structure and a preparation method thereof. Background Art
[0002] For some packaging structure products, circuit structures are formed on both sides of the wiring layer, wherein the circuit structure on one side includes a chip wrapped by a plastic packaging layer, and the other side includes an external circuit module.
[0003] For this type of product, the traditional process usually first coats an organic film layer such as polyimide (PI), and then forms each wiring layer through processes such as photolithography and copper electroplating. However, the performance of the product formed in this way is poor. Summary of the invention
[0004] Based on this, the present application provides an integrated packaging structure and a preparation method thereof that can improve product performance.
[0005] An integrated packaging structure, comprising:
[0006] An interposer structure, comprising an interposer substrate, a wiring layer and a conductive through-hole structure, wherein the wiring layer is located on one side of the interposer substrate, and the conductive through-hole structure penetrates the interposer substrate and connects the wiring layer; a first passive device and / or a power module are integrated in the wiring layer;
[0007] A chip, located on a side of the wiring layer away from the interposer substrate;
[0008] A plastic packaging layer, covering the chip and the interposer structure;
[0009] The external circuit module is located at a side of the interposer structure away from the chip and is connected to the chip through the interposer structure.
[0010] In one of the embodiments, the interposer structure further includes a protective layer, the protective layer is located on a side of the interposer substrate away from the wiring layer, and the conductive via structure penetrates the protective layer and the interposer substrate.
[0011] In one of the embodiments, the interposer structure further includes a first pad, the first pad is located on the surface of the wiring layer, and the chip is mounted or hybrid bonded to the first pad.
[0012] In one of the embodiments, the interposer structure further includes a second pad, which is located on a side of the interposer substrate away from the wiring layer and covers the conductive through-hole structure, and the integrated packaging structure further includes a first frame structure, which includes a first frame and a socket located on the first frame, and the first frame structure covers the second pad;
[0013] The external circuit module comprises:
[0014] The external plug-in is located at a side of the first frame structure away from the interposer structure and is connected to the second pad through the socket.
[0015] In one embodiment, the interposer substrate includes a silicon wafer, and / or the integrated packaging structure further includes:
[0016] A heat sink is located on a side of the plastic packaging layer away from the intermediate layer structure;
[0017] A first fixing hole, penetrating the intermediate layer structure and the plastic packaging layer;
[0018] A fixing member passes through the first fixing hole to fix the heat sink.
[0019] A method for preparing an integrated packaging structure, comprising:
[0020] Providing an interposer initial structure, the interposer initial structure comprising an interposer initial sheet, a wiring layer, and a conductive initial structure, the wiring layer being located on one side of the interposer initial sheet, and the conductive initial structure extending inwardly from a side of the interposer initial sheet where the wiring layer is provided;
[0021] forming a chip on a side of the wiring layer away from the initial sheet of the interposer;
[0022] Forming a plastic encapsulation layer covering the chip and the initial structure of the interposer;
[0023] Using the plastic packaging layer as a support, etching a side of the intermediary layer initial sheet away from the wiring layer to form an intermediary layer substrate, wherein the conductive initial structure protrudes from the surface of the intermediary layer substrate;
[0024] Grinding the conductive initial structure to flatten the protruding portion of the conductive initial structure, and forming the remaining conductive initial structure into a conductive through-hole structure;
[0025] An external circuit module is formed on a side of the interposer substrate away from the wiring layer. The external circuit module is connected to the chip through an interposer structure. The interposer structure includes the interposer substrate, the wiring layer and the conductive through-hole structure.
[0026] In one embodiment, an initial structure of an interposer is provided, including:
[0027] Provide initial interposer sheets;
[0028] forming a conductive initial structure in the initial intermediary layer sheet, wherein in the thickness direction of the initial intermediary layer sheet, the height of the conductive initial structure is less than the thickness of the initial intermediary layer sheet;
[0029] A wiring layer is formed on the side of the intermediate layer initial sheet where the conductive initial structure is formed, the wiring layer is in contact with the conductive initial structure, and a first passive device and / or a power module is integrated on the wiring layer.
[0030] In one embodiment, before forming a chip on a side of the wiring layer away from the initial sheet of the interposer, the method includes:
[0031] forming a first pad on the wiring layer;
[0032] A chip is formed on a side of the wiring layer away from the initial sheet of the interposer, comprising:
[0033] mounting the chip onto the first pad,
[0034] Or, forming a chip on a side of the wiring layer away from the initial sheet of the interposer, comprising:
[0035] The chip is hybrid bonded to the first pad.
[0036] In one embodiment, before grinding the conductive initial structure to flatten the protruding portion of the conductive initial structure, the process includes:
[0037] forming a protective material layer covering the conductive initial structure and the interposer substrate;
[0038] The grinding process of the conductive initial structure to grind the protruding portion of the conductive initial structure flat comprises:
[0039] The conductive initial structure and the protective material layer are ground to flatten the protruding portion of the conductive initial structure, and the remaining conductive initial structure forms a conductive through-hole structure, and the remaining protective material layer forms a protective layer.
[0040] In one embodiment, before forming the external circuit module on the side of the interposer substrate away from the wiring layer, the method includes:
[0041] forming a second pad covering the conductive via structure and the protective layer;
[0042] Forming a first fixing hole penetrating the intermediate layer structure and the plastic packaging layer;
[0043] The external circuit module is formed on a side of the interposer substrate away from the wiring layer, comprising:
[0044] forming a first frame structure covering the second pad, wherein the first frame structure comprises a first frame and a socket located on the first frame;
[0045] An external circuit module is formed on a side of the first frame structure away from the interposer substrate, wherein the external circuit module is connected to the second pad via the socket;
[0046] After the external circuit module is formed on the side of the interposer substrate away from the wiring layer, the method further includes:
[0047] A fixing piece is passed through the first fixing hole to fix and install a heat sink on a side of the plastic packaging layer away from the intermediate layer structure.
[0048] The above-mentioned integrated packaging structure includes an interposer structure, a chip, a plastic encapsulation layer and an external circuit module. The interposer structure includes an interposer substrate, a wiring layer and a conductive through-hole structure. A first passive device and / or a power module are integrated in the wiring layer. The chip is located on a side of the wiring layer away from the interposer substrate, and the plastic encapsulation layer covers the chip and the interposer structure. Integrating the first passive device and / or the power module in the wiring layer can reduce the number of external components, thereby reducing the volume and thickness of the entire integrated packaging structure and increasing the integration of the integrated packaging structure.
[0049] At the same time, the preparation method of the integrated packaging structure of the present application uses an interposer structure to connect the chip and the external circuit module, instead of using the traditional wiring layer structure formed by coating the PI film layer and then photolithography copper plating, thereby preventing the structure from warping due to the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer with a high degree of integration. Therefore, connecting the chip and the external circuit module through the interposer structure can effectively improve the circuit integration density. Moreover, when the interposer structure is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the method of the present application can effectively improve the performance of the integrated packaging structure. In addition, in the process of forming the interposer structure, the plastic sealing layer is directly used as a support, which reduces the preparation process, thereby effectively saving preparation time and reducing preparation costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0051] Figure 1 A schematic diagram of a partial cross-sectional structure of an integrated packaging structure provided in an embodiment;
[0052] Figure 2 A schematic diagram of a partial cross-sectional structure of an integrated packaging structure provided in another embodiment;
[0053] Figure 3 is a flow chart of a method for preparing an integrated packaging structure provided in an embodiment;
[0054] Figures 4 to 12 A schematic diagram of a partial cross-sectional structure of a structure obtained in each step of a method for preparing an integrated packaging structure provided in an embodiment;
[0055] Fig.13 It is a schematic diagram of a partial cross-sectional structure of a first frame structure provided in one embodiment.
[0056] Explanation of the accompanying drawings: 100-intermediary layer structure, 110-intermediary layer substrate, 111-intermediary layer initial structure, 1110-intermediary layer initial sheet, 120-wiring layer, 130-conductive through-hole structure, 1301-conductive initial structure, 170-first solder pad, 180-second solder pad, 200-chip, 210-first graphic dielectric layer, 220-second graphic dielectric layer, 300-plastic encapsulation layer, 400-external circuit module, 140-first passive device, 150-power module, 410-external plug-in, 411-voltage management module, 412-connector, 160-protective layer, 1601-protective material layer, 800-fixing part, 500-first frame structure, 600-heat sink, 610-adhesive, 700-first fixing hole, 900-second fixing hole. DETAILED DESCRIPTION
[0057] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0059] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0060] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0061] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0062] In one embodiment, see Figure 1 , an integrated packaging structure is provided, which includes an intermediate layer structure 100, a chip 200, a plastic packaging layer 300 and an external circuit module 400.
[0063] The interposer structure 100 includes an interposer substrate 110 , a wiring layer 120 , and a conductive via structure 130 .
[0064] The interposer structure 100 may include but is not limited to being a silicon interposer. The interposer substrate 110 may include but is not limited to being a silicon wafer.
[0065] The wiring layer 120 is located on one side of the interposer substrate 110. One side of the interposer substrate 110 may be provided with multiple interconnected wiring layers 120, and an insulating dielectric layer may be provided between adjacent wiring layers 120. It should be noted that the figure only simply illustrates a partial structure of the wiring layer 120.
[0066] The first passive device 140 and / or the power module 150 are also integrated in the wiring layer 120. By integrating the first passive device 140 and / or the power module 150 in the wiring layer 120, the number of external components can be reduced, thereby reducing the volume and thickness of the entire package. In addition, the first passive device 140 integrated in the wiring layer 120 can be connected to the active device through a shorter interconnection path, reducing the loss in the signal transmission process, and improving the integrity of the signal and the performance of the system.
[0067] The conductive via structure 130 penetrates the interposer substrate 110 and connects the wiring layer 120. The material of the conductive via structure 130 may include but is not limited to metal materials such as copper.
[0068] The chip 200 is located on a side of the wiring layer 120 away from the interposer substrate 110 .
[0069] A plurality of chips 200 may be disposed on a side of the wiring layer 120 away from the interposer substrate 110. The chips 200 may be electrically connected to the wiring layer 120. The plurality of chips 200 may be disposed at intervals. Different chips 200 may have different functions.
[0070] The plastic encapsulation layer 300 covers the chip 200 and the interposer structure 100, thereby performing plastic encapsulation protection on the chip 200. The material of the plastic encapsulation layer 300 may include but is not limited to epoxy molding compound (EMC).
[0071] The external circuit module 400 is located on a side of the interposer structure 100 away from the chip 200 .
[0072] The external circuit module 400 may include an external plug-in 410 . The external plug-in 410 may include a voltage management module 411 and / or a connector 412 , etc. The external circuit module 400 is connected to the chip 200 via the interposer structure 100 .
[0073] In this embodiment, the first passive device 140 and / or the power module 150 are integrated in the wiring layer 120, which can reduce the number of external components, thereby reducing the volume and thickness of the entire integrated packaging structure and increasing the integration of the integrated packaging structure. At the same time, the interposer structure 100 is used to connect the chip 200 and the external circuit module 400, instead of the traditional wiring layer 120 structure formed by coating the film layer and then photolithography copper plating, so as to prevent the structure from warping due to the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer 120 with a high degree of integration. Therefore, connecting the chip 200 and the external circuit module 400 through the interposer structure 100 can effectively improve the circuit integration density. In addition, when the interposer structure 100 is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the method of this embodiment can effectively improve the performance of the integrated packaging structure.
[0074] In one embodiment, the interposer structure 100 further includes a protective layer 160. The material of the protective layer 160 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride.
[0075] The protection layer 160 is located on a side of the interposer substrate 110 away from the wiring layer 120 , and the conductive via structure 130 penetrates the protection layer 160 and the interposer substrate 110 .
[0076] The protection layer 160 can prevent metal in the conductive via structure 130 from entering the interposer substrate 110 , thereby preventing leakage between adjacent conductive via structures 130 .
[0077] In one embodiment, the interposer structure 100 further includes a first pad 170. The material of the first pad 170 may include but is not limited to copper.
[0078] The first pad 170 is located on the surface of the wiring layer 120 and may cover at least a portion of the wiring layer 120 , thereby being electrically connected to the wiring layer 120 .
[0079] The chip 200 is die mounted or hybrid bonded to the first pad 170 .
[0080] In one embodiment, the interposer structure 100 further includes a second pad 180 .
[0081] The second pad 180 is located on a side of the interposer substrate 110 away from the wiring layer 120 and covers the conductive via structure 130, thereby being electrically connected to the conductive via structure 130. The material of the second pad 180 may include, but is not limited to, copper, etc. The number of the second pad 180 may be multiple. The external circuit module 400 includes an external plug-in 410.
[0082] The integrated package structure further includes a first frame structure 500 , which includes a first frame 510 and a socket 520 located on the first frame 510 . The first frame structure 500 covers the second pad 180 .
[0083] The external plug-in 410 is located on a side of the first frame structure 500 away from the interposer structure 100 .
[0084] The external plug-in 410 may include but is not limited to a voltage management module 411 and / or a connector 412 , etc. The external plug-in 410 may be plugged into the socket 520 in a pluggable manner, thereby connecting to the second pad 180 through the first frame structure 500 .
[0085] In one embodiment, see Figure 2 , the external circuit module 400 may further include a second passive component 420 .
[0086] The second passive component 420 may be mounted to a portion of the second pad 180. The second passive component 420 may be directly mounted to the second pad 180 by patch mounting. Meanwhile, the integrated package structure may also have another portion of the second pad 180 not covered by the second passive component 420.
[0087] The first frame structure 500 can seal the second passive device 420 and the second pad 180. The same first frame structure 500 can cover multiple second passive devices 420 and / or multiple second pads 180. And the same first frame structure 500 can cover the second passive device 420 and the second pad 180 at the same time, or only cover the second pad 180 or the second passive device 420. At the same time, the second passive devices 420 and the second pad 180 at different positions can be covered by different first frame structures 500.
[0088] In one embodiment, see Figure 1 or Figure 2 The integrated packaging structure also includes a heat sink 600 , a first fixing hole 700 and a fixing member 800 .
[0089] The heat dissipation plate 600 is located on a side of the plastic encapsulation layer 300 away from the interposer structure 100. As an example, the heat dissipation plate 600 may be bonded to the plastic encapsulation layer 300 by means of an adhesive 610 (such as TIM adhesive).
[0090] The first fixing hole 700 passes through the intermediate layer structure 100 and the plastic packaging layer 300 .
[0091] The fixing member 800 passes through the first fixing hole 700 to fix the heat sink 600. The fixing member 800 may include but is not limited to bolts and the like.
[0092] After passing through the first fixing hole 700 , the fixing member 800 may not penetrate the heat dissipation plate 600 , or may penetrate the heat dissipation plate 600 .
[0093] As an example, the integrated package structure may further include a first frame structure 500 and a second frame structure, etc. The first frame structure 500 may include a first frame 510 and a socket 520, etc. The external circuit module 400 may be located on a side of the first frame structure 500 away from the interposer structure 100.
[0094] The second frame structure (not shown) may be located at a side of the external circuit module 400 away from the interposer structure 100 for mechanical fixing and limiting.
[0095] The first frame structure 500 may also have a second fixing hole 900. The second frame structure may also have a third fixing hole. The second fixing hole 900 and the third fixing hole may be arranged opposite to the first fixing hole 700. The fixing member 800 may also pass through the second fixing hole and the third fixing hole at the same time, so as to fix the second frame structure and the first frame structure 500 at the same time.
[0096] In this embodiment, the fixing member 800 can make the connection between the heat dissipation plate 600 and the plastic packaging layer 300 more reliable.
[0097] In one embodiment, see Figure 3 , a method for preparing an integrated packaging structure is provided, comprising the following steps:
[0098] Step S10, providing an interposer initial structure 111, the interposer initial structure 111 includes an interposer initial sheet 1110, a wiring layer 120, and a conductive initial structure 1301, wherein the wiring layer 120 is located on one side of the interposer initial sheet 1110, and the conductive initial structure 1301 extends inward from the side of the interposer initial sheet 1110 where the wiring layer 120 is located (see Figure 4 ).
[0099] The interposer initial sheet 1110 may include but is not limited to a silicon sheet. The material of the conductive initial structure 1301 may include but is not limited to metal materials such as copper. One side of the interposer initial sheet 1110 may be provided with multiple interconnected wiring layers 120, and an insulating dielectric layer may be provided between adjacent wiring layers 120. The conductive initial structure 1301 extends inward from the side of the interposer initial sheet 1110 provided with the wiring layer 120. It should be noted that the figure only simply illustrates a partial structure of the wiring layer 120.
[0100] Step S20, forming a chip 200 on the side of the wiring layer 120 away from the initial interposer sheet 1110 (see Figure 6 ).
[0101] A plurality of chips 200 may be formed on a side of the wiring layer 120 away from the interposer initial sheet 1110. The chips 200 may be electrically connected to the wiring layer 120. The plurality of chips 200 may be arranged at intervals. Different chips 200 may have different functions.
[0102] Step S30, forming a plastic encapsulation layer 300 covering the chip 200 and the initial structure of the interposer 111 (see Figure 7 ).
[0103] The plastic encapsulation layer 300 can completely cover the chip 200, thereby performing plastic encapsulation protection on the chip 200. The material of the plastic encapsulation layer 300 can include but is not limited to epoxy molding compound (EMC).
[0104] Step S40, using the plastic encapsulation layer 300 as a support, etching the side of the interposer initial sheet 1110 away from the wiring layer 120 to form the interposer substrate 110, and the conductive initial structure 1301 protrudes from the surface of the interposer substrate 110 (see Figure 8 ).
[0105] After the molding layer 300 is formed, the entire structure is turned upside down so that the molding layer 300 can be used as a support for subsequent processes to process the side of the intermediate layer initial sheet 1110 away from the molding layer 300 .
[0106] The etching can be performed by dry etching process, etc., to etch and thin the interposer initial sheet 1110 from the side away from the wiring layer 120 until the thickness of the remaining interposer initial sheet 1110 is less than the height of the conductive initial structure 1301. A portion of the conductive initial structure 1301 is exposed, thereby forming the interposer substrate 110.
[0107] Step S50, grinding the conductive initial structure 1301 to flatten the protruding portion of the conductive initial structure 1301, and the remaining conductive initial structure 1301 forms a conductive through-hole structure 130 (see Fig.10 ).
[0108] The conductive initial structure 1301 is ground to make the raised conductive initial structure 1301 flat, and the ground conductive initial structure 1301 is the conductive through-hole structure 130. The conductive through-hole structure 130 facilitates subsequent electrical connection.
[0109] Step S60, forming an external circuit module 400 on the side of the interposer substrate 110 where the conductive via structure 130 is formed, the external circuit module 400 is connected to the chip 200 through the interposer structure 100, the interposer structure 100 includes the interposer substrate 110, the wiring layer 120 and the conductive via structure 130 (see Fig.12 ).
[0110] After grinding, the conductive via structure 130 is formed, and the interposer structure 100 is obtained. The interposer structure 100 includes an interposer substrate 110, a wiring layer 120, and a conductive via structure 130. The interposer structure 100 is connected to the chip 200. At this time, an external circuit module 400 can be set on the side of the interposer substrate 110 where the conductive via structure 130 is formed, and the external circuit module 400 is connected to the chip 200 through the interposer structure 100. The external circuit module 400 may include an external plug-in 410, etc. The external plug-in 410 may include a voltage management module 411 and / or a connector 412, etc.
[0111] In this embodiment, an interposer initial structure 111 is first provided, including an interposer initial sheet 1110, a wiring layer 120, and a conductive initial structure 1301. Then, a chip 200 is formed on the side of the wiring layer 120 of the interposer initial structure 111 away from the interposer initial sheet 1110, and a plastic encapsulation layer 300 is formed to cover the chip 200. Afterwards, the formed structure is inverted as a whole, and the plastic encapsulation layer 300 is used as a support to etch the side of the interposer initial sheet 1110 away from the wiring layer 120 to form an interposer substrate 110. Afterwards, the conductive initial structure 1301 raised after etching is ground to form a conductive through-hole structure 130, and thus an interposer structure 100 is obtained, and the interposer structure 100 includes an interposer substrate 110, a wiring layer 120, and a conductive through-hole structure 130. Afterwards, an external circuit module 400 is formed on a side of the interposer substrate 110 away from the wiring layer 120 . The external circuit module 400 is connected to the chip 200 via the interposer structure 100 , thereby effectively realizing the preparation of an integrated packaging structure.
[0112] The integrated packaging structure formed by the method of this embodiment uses an interposer structure 100 to connect the chip 200 and the external circuit module 400, instead of the traditional wiring layer 120 structure formed by coating the PI film layer and then photolithography copper plating, thereby preventing the structure from warping due to the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer 120 with a high degree of integration. Therefore, connecting the chip 200 and the external circuit module 400 through the interposer structure 100 can effectively improve the circuit integration density. Moreover, when the interposer structure 100 is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the performance of the integrated packaging structure can be effectively improved by using the method of this embodiment. In addition, in the process of forming the middle-level structure, the plastic encapsulation layer 300 is directly used as a support, which reduces the preparation process, thereby effectively saving preparation time and reducing preparation costs.
[0113] In one embodiment, step S10 includes:
[0114] Step S11, providing an initial interposer sheet 1110 (see Figure 4 ).
[0115] The interposer initial wafer 1110 may include, but is not limited to, a silicon wafer.
[0116] Step S12, forming a conductive initial structure 1301 in the initial interposer sheet 1110, wherein the height of the conductive initial structure 1301 is less than the thickness of the initial interposer sheet 1110 in the thickness direction of the initial interposer sheet 1110 (see Figure 4 ).
[0117] The material of the conductive initial structure 1301 may include but is not limited to metal materials such as copper. The conductive initial structure 1301 may be formed in the intermediate layer initial sheet 1110 by using TSV technology. The TSV technology may make vertical holes on a silicon wafer and fill these holes with conductive materials such as copper, tungsten, etc., thereby forming a vertical conductive initial structure 1301. The height of the conductive initial structure 1301 is less than the height of the intermediate layer.
[0118] Step S13, forming a wiring layer 120 on the side of the intermediate layer initial sheet 1110 where the conductive initial structure 1301 is formed, the wiring layer 120 is in contact with the conductive initial structure 1301, and the first passive device 140 and / or the power module 150 are integrated on the wiring layer 120 (see Figure 4 ).
[0119] In the interposer initial structure 111 , one end of the conductive initial structure 1301 may be connected to the wiring layer 120 , and the other end of the conductive initial structure 1301 may extend to the inside of the interposer initial sheet 1110 , but does not penetrate the interposer initial sheet 1110 .
[0120] When forming the wiring layer 120, the first passive device 140 and / or the power module 150 can be integrated at the same time. By integrating the first passive device 140 and / or the power module 150 in the wiring layer 120, the number of external components can be reduced, thereby reducing the volume and thickness of the entire package. In addition, the first passive device 140 integrated in the wiring layer 120 can be connected to the active device through a shorter interconnection path, reducing the loss in the signal transmission process, and improving the integrity of the signal and the performance of the system.
[0121] In this embodiment, in the interposer initial structure 111 provided at the beginning, the conductive initial structure 1301 does not penetrate the interposer initial sheet 1110. In the subsequent process, the interposer initial sheet 1110 is formed into the interposer substrate 110 through etching, grinding and other processes, thereby effectively reducing the thickness of the interposer substrate, and then reducing the thickness of the integrated packaging structure, thereby facilitating the improvement of the packaging integration. At the same time, at this time, in the process of forming the conductive initial structure 1301, it is also possible not to form a through hole penetrating the interposer initial sheet 1110, thereby reducing the process difficulty of the conductive initial structure 1301.
[0122] In one embodiment, before step S20, the method includes:
[0123] Step S14, forming a first pad 170 on the wiring layer 120 (see Figure 5 ).
[0124] First, a first patterned dielectric layer 210 may be formed by a photolithography process, etc., and the first patterned dielectric layer 210 has a first opening. The material of the first patterned dielectric layer 210 may include, but is not limited to, a PI material. Then, a first patterned photoresist layer may be formed on the first patterned dielectric layer 210. The first patterned photoresist layer has a second opening, and the second opening is arranged opposite to the first opening. Then, a first pad 170 may be formed in the second opening and the first opening by an electroplating process, etc., and the first patterned photoresist layer is removed.
[0125] At this time, as an example, step S20 may include: step S21 , mounting the chip 200 on the first pad 170 .
[0126] Or, as an example, step S20 may include: step S22, hybrid bonding the chip 200 to the first pad 170. This is not specifically limited.
[0127] In this embodiment, the first pad 170 is formed on the wiring layer 120, which can increase the electrical connection performance between the wiring layer 120 and the chip 200 and improve the stability and reliability of the circuit.
[0128] In one embodiment, before step S50, the method includes:
[0129] Step S41, forming a protective material layer 1601 covering the conductive initial structure 1301 and the intermediate layer substrate 110 (see Fig. 9 ).
[0130] The protective material layer 1601 may be formed by a deposition process (such as chemical vapor deposition or atomic layer deposition, etc.). The material of the protective material layer 1601 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride, etc.
[0131] Step S50 includes:
[0132] Step S51, grinding the conductive initial structure 1301 and the protective material layer 1601 to grind the protruding portion of the conductive initial structure 1301 flat, and the remaining conductive initial structure 1301 forms the conductive through-hole structure 130, and the remaining protective material layer 1601 forms the protective layer 160 (see Fig.10 ).
[0133] In this embodiment, before the conductive initial structure 1301 and the protective material layer 1601 are ground, a protective material layer 1601 covering the conductive initial structure 1301 and the interposer substrate 110 is formed in step S41. Therefore, during the grinding process, the protective material layer 1601 can prevent the metal of the conductive initial structure 1301 from entering the interposer substrate 110, thereby preventing leakage between adjacent conductive via structures 130.
[0134] In one embodiment, before step S60, the method includes:
[0135] Step S52, forming a second pad 180 covering the conductive via structure 130 and the protective layer 160 (see Fig.11 ).
[0136] The material of the second pad 180 may include, but is not limited to, copper or the like.
[0137] The second pad 180 may be formed in a similar manner to the first pad 170 .
[0138] First, a second patterned dielectric layer 220 may be formed by a photolithography process, etc., and the second patterned dielectric layer 220 has a third opening. The material of the second patterned dielectric layer 220 may include, but is not limited to, PI. Then, a second patterned photoresist layer may be formed on the second patterned dielectric layer 220. The second patterned photoresist layer has a fourth opening, and the fourth opening is arranged opposite to the third opening. Then, a second pad 180 may be formed in the fourth opening and the third opening by an electroplating process, etc., and the second patterned photoresist layer is removed.
[0139] The second pad 180 can be provided to increase the electrical connection performance between the wiring layer 120 and the external circuit module 400 , thereby improving the stability and reliability of the circuit.
[0140] Step S53, forming a first fixing hole 700 penetrating the interposer structure 100 and the plastic encapsulation layer 300 (see Fig.12 ).
[0141] Step S60 includes:
[0142] Step S61, forming a first frame structure 500 covering the second pad 180, the first frame structure 500 includes a first frame 510 and a socket 520 located on the first frame 510 (see Fig.13 ).
[0143] The provision of the first frame structure 500 may facilitate the installation of the external circuit module 400. The first frame structure 500 may seal the second pad 180.
[0144] As an example, a mounting groove may be provided on the surface of the first frame 510, and the socket 820 may be placed in the mounting groove to position the socket.
[0145] Optionally, the first frame structure 500 may further include a conductive portion 530. The conductive portion 530 may be located in the first frame 510 and may be disposed at the bottom of the socket 520. The material of the conductive portion 530 may include, but is not limited to, conductive rubber.
[0146] It should be noted that, as an example, before forming the first frame structure 500 covering the second solder pad 180, it can also include installing a second passive component 420 on part of the second solder pad 180. The second passive component 420, as a part of the external circuit module 400, can be directly installed on the second solder pad 180 by means of surface mount installation.
[0147] At this time, the first frame structure 500 can seal the second passive component 420 and the second pad 180 .
[0148] Step S62 , forming an external circuit module 400 on a side of the first frame structure 500 away from the interposer substrate 110 , and the external circuit module 400 is connected to the second pad 180 through the first frame structure 500 .
[0149] The external circuit module 400 may include an external plug-in 410, which may include but is not limited to a voltage management module 411 and / or a connector 412, etc. The external plug-in 410 may be plugged into the first frame structure 500 in a pluggable manner, thereby connecting the second pad 180 through the first frame structure 500.
[0150] After step S60, the following steps are included:
[0151] In step S70 , a fixing member 800 is passed through the first fixing hole 700 to fix the heat sink 600 on a side of the plastic packaging layer 300 away from the interposer structure 100 .
[0152] The fixing member 800 may include but is not limited to a bolt or the like.
[0153] As an example, the heat sink 600 may be first bonded to the side of the plastic layer 300 away from the interposer structure 100 by means of adhesive 610 (such as TIM adhesive). Then, the fixing member 800 is passed through the first fixing hole 700 to fix the heat sink 600.
[0154] After passing through the first fixing hole 700 , the fixing member 800 may not penetrate the heat dissipation plate 600 , or may penetrate the heat dissipation plate 600 .
[0155] In this embodiment, the fixing member 800 can make the connection between the heat dissipation plate 600 and the plastic packaging layer 300 more reliable.
[0156] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0157] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0158] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0159] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. An integrated packaging structure, characterized in that: include: An interposer structure, comprising an interposer substrate, a wiring layer and a conductive through-hole structure, wherein the wiring layer is located on one side of the interposer substrate, and the conductive through-hole structure penetrates the interposer substrate and connects the wiring layer; a first passive device and / or a power module are integrated in the wiring layer; A chip, located on a side of the wiring layer away from the interposer substrate; A plastic packaging layer, covering the chip and the interposer structure; The external circuit module is located at a side of the interposer structure away from the chip and is connected to the chip through the interposer structure.
2. The integrated packaging structure according to claim 1, characterized in that: The interposer structure further includes a protection layer, which is located on a side of the interposer substrate away from the wiring layer, and the conductive via structure penetrates the protection layer and the interposer substrate.
3. The integrated packaging structure according to claim 1, characterized in that: The interposer structure further includes a first pad, which is located on the surface of the wiring layer, and the chip is mounted or hybrid-bonded to the first pad.
4. The integrated packaging structure according to claim 1, characterized in that: The interposer structure further includes a second pad, which is located on a side of the interposer substrate away from the wiring layer and covers the conductive through-hole structure. The integrated packaging structure further includes a first frame structure, which includes a first frame and a socket located on the first frame, and the first frame structure covers the second pad. The external circuit module comprises: The external plug-in is located at a side of the first frame structure away from the interposer structure and is connected to the second pad through the socket.
5. The integrated packaging structure according to claim 1, characterized in that: The interposer substrate includes a silicon wafer, and / or the integrated packaging structure further includes: A heat sink is located on a side of the plastic packaging layer away from the intermediate layer structure; A first fixing hole, penetrating the intermediate layer structure and the plastic packaging layer; A fixing member passes through the first fixing hole to fix the heat sink.
6. A method for preparing an integrated packaging structure, characterized in that: include: Providing an interposer initial structure, the interposer initial structure comprising an interposer initial sheet, a wiring layer, and a conductive initial structure, the wiring layer being located on one side of the interposer initial sheet, and the conductive initial structure extending inwardly from a side of the interposer initial sheet where the wiring layer is provided; forming a chip on a side of the wiring layer away from the initial sheet of the interposer; Forming a plastic encapsulation layer covering the chip and the initial structure of the interposer; Using the plastic packaging layer as a support, etching a side of the intermediary layer initial sheet away from the wiring layer to form an intermediary layer substrate, wherein the conductive initial structure protrudes from the surface of the intermediary layer substrate; Grinding the conductive initial structure to flatten the protruding portion of the conductive initial structure, and forming the remaining conductive initial structure into a conductive through-hole structure; An external circuit module is formed on a side of the interposer substrate away from the wiring layer. The external circuit module is connected to the chip through an interposer structure. The interposer structure includes the interposer substrate, the wiring layer and the conductive through-hole structure.
7. The method for preparing an integrated packaging structure according to claim 6, characterized in that: Provides the initial structure of the interposer layer, including: Provide initial interposer sheets; forming a conductive initial structure in the initial intermediary layer sheet, wherein in the thickness direction of the initial intermediary layer sheet, the height of the conductive initial structure is less than the thickness of the initial intermediary layer sheet; A wiring layer is formed on the side of the intermediate layer initial sheet where the conductive initial structure is formed, the wiring layer is in contact with the conductive initial structure, and a first passive device and / or a power module is integrated on the wiring layer.
8. The method for preparing an integrated packaging structure according to claim 6, characterized in that: Before forming a chip on a side of the wiring layer away from the initial sheet of the interposer, the method comprises: forming a first pad on the wiring layer; A chip is formed on a side of the wiring layer away from the initial sheet of the interposer, comprising: mounting the chip onto the first pad, Or, forming a chip on a side of the wiring layer away from the initial sheet of the interposer, comprising: The chip is hybrid bonded to the first pad.
9. The method for preparing an integrated packaging structure according to claim 6, characterized in that: Before grinding the conductive initial structure to flatten the protruding portion of the conductive initial structure, the method includes: forming a protective material layer covering the conductive initial structure and the interposer substrate; The grinding process of the conductive initial structure to grind the protruding part of the conductive initial structure flat comprises: The conductive initial structure and the protective material layer are ground to flatten the protruding portion of the conductive initial structure, and the remaining conductive initial structure forms a conductive through-hole structure, and the remaining protective material layer forms a protective layer.
10. The method for preparing an integrated packaging structure according to claim 6, characterized in that: Before forming an external circuit module on a side of the interposer substrate away from the wiring layer, the method includes: forming a second pad covering the conductive via structure and the protective layer; Forming a first fixing hole penetrating the intermediate layer structure and the plastic packaging layer; The external circuit module is formed on a side of the interposer substrate away from the wiring layer, comprising: forming a first frame structure covering the second pad, wherein the first frame structure comprises a first frame and a socket located on the first frame; An external circuit module is formed on a side of the first frame structure away from the interposer substrate, wherein the external circuit module is connected to the second pad via the socket; After the external circuit module is formed on the side of the interposer substrate away from the wiring layer, the method further includes: A fixing piece is passed through the first fixing hole to fix and install a heat sink on a side of the plastic packaging layer away from the intermediate layer structure.