Photonic chip package structure including controlled underfill fillet

Abstract

The invention relates to photonic chip package structures including controlled underfill corners. Structures for packaging photonic chips and related methods are provided. The structure includes a photonic chip, a package substrate, a plurality of electrical connections disposed in a gap between the photonic chip and the package substrate, and a fillet including an underfill material. The fillet is disposed to overlap a portion of the photonic chip adjacent the gap, the fillet having a width dimension and a height dimension transverse to the width dimension, and a ratio of the width dimension to the height dimension is greater than or equal to 1.5.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices and integrated circuit manufacturing, and more particularly to structures for packaging photonic chips and related methods. Background Art

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication systems and data computing systems. Photonic chips include photonic integrated circuits, which are composed of photonic components (such as modulators, polarizers, and optical couplers) that are used to manipulate light received from a light source (such as an optical fiber or a laser).

[0003] The photonic chip can be mounted on a laminate substrate to produce a package assembly. Typically, solder joints are formed by reflowing solder to connect connection pads on the laminate substrate and the photonic chip. The solder joints provide electrical connections between the laminate substrate and the photonic chip, and create a gap between the laminate substrate and the photonic chip.

[0004] Filling the gap with an underfill material improves the reliability of the electrical connection between the photonic chip and the laminate substrate. Underfilling prevents the electrical connection from being exposed to the surrounding environment and provides mechanical strength to the package assembly. In addition, when the photonic chip and the laminate substrate have significantly different coefficients of thermal expansion, the underfill material increases the fatigue life of the package assembly and reduces the stress experienced by the electrical connection during thermal cycling. Therefore, underfilling can significantly increase the operating life of the package assembly.

[0005] The bottom fill material can be introduced into the gap by capillary action. The low viscosity fluid bottom fill material can be preheated and distributed on the surface of the laminate substrate adjacent to one or more sides of the photonic chip. Capillary action causes the fluid bottom fill material to flow into the gap. After filling the gap, additional fluid bottom fill material can be distributed around the periphery of the photonic chip to provide a fillet. The bottom fill material is solidified and hardened after the dispensing operation. Unfortunately, conventional fillets may not prevent cracking of the back-end process stack of the photonic chip adjacent to the fillet and / or delamination of the fillet.

[0006] Improved structures for packaging photonic chips and related methods are needed. Summary of the invention

[0007] In one embodiment, a structure includes a photonic chip, a packaging substrate, a plurality of electrical connections disposed in a gap between the photonic chip and the packaging substrate, and a fillet including an underfill material, the fillet being disposed to overlap a portion of the photonic chip adjacent to the gap, the fillet having a width dimension and a height dimension transverse to the width dimension, and a ratio of the width dimension to the height dimension being greater than or equal to 1.5.

[0008] In one embodiment, a method includes attaching a photonic chip to a packaging substrate via a plurality of electrical connections. The electrical connections are provided in a gap between the photonic chip and the packaging substrate. The method also includes forming a fillet including an underfill material. The fillet overlaps a portion of the photonic chip adjacent to the gap, the fillet having a width dimension and a height dimension transverse to the width dimension, and a ratio of the width dimension to the height dimension being greater than or equal to 1.5. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0010] Figure 1 A cross-sectional view of a packaging assembly according to an embodiment of the present invention is shown.

[0011] Figure 2 show Figure 1 Magnified view of a portion of.

[0012] Figure 3 show Figure 1 Magnified view of a portion of. DETAILED DESCRIPTION

[0013] Please refer to Figure 1 , 2 , 3 and according to an embodiment of the present invention, a structure 10 of a lidded package assembly includes a photonic chip 12, a laminate substrate 14 providing a representative package substrate, and a lid 16. The photonic chip 12 is disposed between the laminate substrate 14 and the lid 16. The laminate substrate 14 may include an epoxy-glass cloth core and alternating layers of metal and electrical insulator laminated on the core. In one embodiment, the laminate substrate 14 may include a plurality of copper film layers and insulating resin layers (e.g., Ajinomoto Build-up Film (ABF)) alternating. The build-up layers of the alternating layers of the laminate substrate 14 may be disposed adjacent to the photonic chip 12.

[0014] The photonic chip 12 includes photonic components (e.g., modulators, polarizers, and optical couplers) arranged in a functional photonic integrated circuit that is configured to manipulate light received from a light source (e.g., an optical fiber or a laser). The photonic chip 12 includes a substrate 17 (on which the photonic integrated circuit is disposed) and a back-end process stack 25 disposed on the substrate 17. The substrate 17 may be composed of, for example, silicon. The back-end process stack 25 (which may include bonding pads, an inorganic passivation layer (e.g., a TEOS silicon dioxide layer), a set of interlayer dielectric layers, and interconnects located in the interlayer dielectric layers) may be disposed adjacent to the laminate substrate 14.

[0015] The laminate substrate 14 includes bonding pads coupled to the metal layer in the build-up layer through vias. A surface 32 of the laminate substrate 14 (which is adjacent to the top surface 28 of the photonic chip 12) may be coated with a solder mask layer 30 that is adjacent to an edge 15 of the laminate substrate 14. The laminate substrate 14 has a height H0 at the edge 15. An electrical connection 18 coupling the bonding pads of the photonic chip 12 to the bonding pads of the laminate substrate 14 is arranged in a gap G between the top surface 28 of the photonic chip 12 and the surface 32 of the laminate substrate 14. The electrical connection 18 may include reflowed solder from solder balls or solder-capped pillars.

[0016] The photonic chip 12 also includes a bottom surface 20 opposite to the top surface 28, a side surface 11, and a side surface 13 opposite to the side surface 11. The side surfaces 11 and 13 are connected by the bottom surface 20 and the top surface 28. The photonic chip 12 includes a portion disposed between the side surface 13 and the edge 15 of the laminate substrate 14. Due to the lateral offset in the attachment of the photonic chip 12 to the laminate substrate 14, the top surface 28 of this portion of the photonic chip 12 is exposed, and the exposed top surface 28 has a width W0. The back-end process stack 25 of the photonic chip 12 can extend together with the top surface 28 so that the bonding pad is disposed adjacent to the top surface 28.

[0017] A cover 16 (which may be composed of an electrically and thermally conductive material, such as nickel-coated copper) is attached to the same side of the laminate substrate 14 as the photonic chip 12. The photonic chip 12 overlaps a portion of the cover 16. A thermal interface material layer 19 may be disposed between the overlapping portions of the photonic chip 12 and the cover 16. The thermal interface material in the layer 19 may be composed of, for example, a thermal adhesive or thermal grease, which is used to improve heat flow between the photonic chip 12 and the overlapping portions of the cover 16.

[0018] Another portion of the cover 16 may be attached to a portion of the surface 32 of the laminate substrate 14 by an adhesive layer 23. An open space 21 is provided between the side surface 11 of the photonic chip 12, the cover 16, and a portion of the surface 32 of the laminate substrate 14. The different portions of the cover 16 are characterized by a vertical offset that accommodates the arrangement of the photonic chip 12 between the laminate substrate 14 and the cover 16. The attachment of the portion of the cover 16 to the laminate substrate 14 increases the mechanical strength of the structure 10 and, if the adhesive constituting the adhesive layer 23 is conductive, may provide a conductive path from the cover 16 to the laminate substrate 14.

[0019] A layer 22 composed of an underfill material is disposed in the gap G between the photonic chip 12 and the laminate substrate 14, including the electrical connection 18. The layer 22 may have a thickness substantially equal to the height dimension of the gap G. The layer 22 protects the electrical connection 18 from various adverse environmental factors, redistributes mechanical stresses caused by impact, and prevents the electrical connection 18 from moving under strain during thermal cycling when the photonic chip 12 is in operation.

[0020] A fillet 24 composed of an underfill material is provided on a portion of the top surface 28 of the photonic chip 12 adjacent to the edge 15 of the laminate substrate 14 and adjacent to the gap G. Fillet 24 is also provided on a portion of the edge 15 and covers the opening to the gap G. A fillet 26 composed of an underfill material is provided on a portion of the side surface 11 of the photonic chip 12 adjacent to the surface 32 of the laminate substrate 14 and adjacent to the gap G. Fillet 26 is also provided on a portion of the surface 32 and covers the other opening to the gap G.

[0021] The bottom fill material of layer 22 and fillets 24, 26 may include a bulk matrix and a filler dispersed in the bulk matrix. The bulk matrix may be composed of, for example, a curable thermoplastic resin that is an electrical insulator and is non-conductive. The filler may be small particles composed of an electrical insulator such as silicon dioxide, glass, aluminum oxide, or boron nitride. After application, the bulk matrix may be hardened by a curing process to form a cohesive solidified mass. The filler may be used to improve the mechanical properties of the cured bottom fill material and / or increase the thermal conductivity of the cured bottom fill material.

[0022] The layer 22 and the fillets 24, 26 may be formed by a molding process, wherein the flip-chip assembly including the photonic chip 12 and the laminate substrate 14 is arranged inside a cavity of a mold, and a fluid bottom fill material is injected into the mold cavity under high pressure and temperature. The shape of the fillets 24, 26 will follow the shape of the mold. The photonic chip 12 may include a groove adjacent to the fillet 24, which is configured to accommodate an optical fiber as a light source for the photonic integrated circuit of the photonic chip 12, and the photonic integrated circuit of the photonic chip 12 may include a spot-size converter that receives light (e.g., infrared light) from the optical fiber. The cover 16 is installed after the molding process.

[0023] The fillet 24 may have a height dimension H1 measured relative to the top surface 28 of the photonic chip 12 and a width dimension W1 measured relative to the edge 15 of the laminate substrate 14. In one embodiment, the ratio of the width dimension W1 to the height dimension H1 may be greater than or equal to 1.5. In one embodiment, the ratio of the width dimension W1 to the height dimension H1 may be greater than or equal to 1.5 and less than or equal to 50. Aspect ratios in one or another of these ranges may effectively reduce strain in the back-end process stack 25 of the photonic chip 12 and reduce or eliminate failures caused by stress-induced crack formation in the back-end process stack 25. In one embodiment, the minimum value of the height dimension H1 of the fillet 24 may be selected so that the fillet 24 protrudes upwardly beyond the height of the solder mask layer 30, so that the height dimension H1 is greater than the thickness of the layer 22. In one embodiment, the selection of the minimum value of the height dimension H1 may be used to derive the minimum value of the width dimension W1. For example, if the height dimension H1 of the fillet 24 is 80 microns, the width dimension W1 of the fillet 24 is greater than or equal to 120 microns. Fillet 24 has a height dimension H1 having a maximum value that may be constrained by the smaller of a height H0 of laminate substrate 14 at edge 15 and a width W0 of an exposed portion of top surface 28 of photonic chip 12 between edge 15 and side surface 13 of photonic chip 12 .

[0024] The fillet 26 (provided in the open space 21) may have a height dimension H2 measured relative to the solder mask 30 on the bottom surface 29 of the laminate substrate 14 and a width dimension W2 measured relative to the side surface 11 of the photonic chip 12. In one embodiment, the ratio of the width dimension W2 to the height dimension H2 may be greater than or equal to 1.5. In one embodiment, the ratio of the width dimension W2 to the height dimension H2 may be greater than or equal to 1.5 and less than or equal to 50. A ratio in one or another of these ranges may effectively reduce the strain of the back-end process stack 25 of the photonic chip 12 and reduce or eliminate failures caused by delamination of the fillet 26. In one embodiment, the fillet 26 may overlap with a portion of the side surface 11 along the height dimension to extend with the substrate 17 of the photonic chip 12 by a distance D1 greater than or equal to 35 microns and less than or equal to 65 microns. In one embodiment, the value of the height dimension H2 may be used to derive the value of the width dimension W2. The height dimension H2 of the fillet 26 may be greater than the thickness of the layer 22.

[0025] Fillet 26 is inverted relative to fillet 24. In one embodiment, fillet 26 may be different than fillet 24. In one embodiment, fillet 26 may be greater than fillet 24. In one embodiment, fillet 24 may be greater than fillet 26. In one embodiment, fillet 26 may be characterized by a different aspect ratio than fillet 24.

[0026] The method described above is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smart phone with a central processing unit.

[0027] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0028] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0029] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if there is at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there is at least one intermediate feature. Different features "overlap" if one feature extends over and covers a portion of another feature.

[0030] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A structure, characterized in that: include: Photonic chips; Package substrate; A plurality of electrical connections are provided in a gap between the photonic chip and the packaging substrate; as well as a first fillet comprising an underfill material, the first fillet being configured to overlap a first portion of the photonic chip adjacent the gap, the first fillet having a first width dimension and a first height dimension transverse to the first width dimension, Wherein, a ratio of the first width dimension to the first height dimension is greater than or equal to 1.

5.

2. The structure according to claim 1, characterized in that A ratio of the first width dimension to the first height dimension is less than or equal to 50.

3. The structure according to claim 1, characterized in that The packaging substrate has an edge, the photonic chip has a top surface, and the first portion of the photonic chip is a first portion of the top surface adjacent to the edge of the packaging substrate.

4. The structure according to claim 3, characterized in that The packaging substrate has a second height dimension at the edge, the first portion of the top surface has a second width dimension, the first height dimension of the first fillet is smaller than the second height dimension, and the first width dimension of the first fillet is smaller than the second width dimension.

5. The structure according to claim 3, characterized in that The first width dimension of the first fillet extends along a first direction parallel to the top surface, and the first height dimension of the first fillet extends along a second direction perpendicular to the top surface.

6. The structure according to claim 5, characterized in that The first fillet extends along the edge of the package substrate along the second direction.

7. The structure according to claim 6, characterized in that The packaging substrate has a surface adjacent to the gap, and further includes: A solder resist layer is located on the surface of the package substrate, Wherein, the first fillet extends above the solder resist layer.

8. The structure according to claim 3, characterized in that The top surface of the photonic chip includes a second portion disposed in the gap between the photonic chip and the packaging substrate.

9. The structure according to claim 1, characterized in that The packaging substrate has a surface, the photonic chip has a side surface, and the first portion of the photonic chip is a first portion of the side surface adjacent to the surface of the packaging substrate.

10. The structure according to claim 9, characterized in that The first width dimension of the first fillet extends along a first direction perpendicular to the side surface, and the first height dimension of the first fillet extends along a second direction parallel to the side surface.

11. The structure according to claim 9, characterized in that The surface of the packaging substrate includes a second portion disposed in the gap between the photonic chip and the packaging substrate.

12. The structure according to claim 9, characterized in that The photonic chip includes a substrate and a back-end process stack located on the substrate, and the first fillet and the substrate extend together by a distance greater than or equal to 35 microns and less than or equal to 65 microns.

13. The structure according to claim 1, characterized in that Also includes: A second fillet includes the bottom filling material, the second fillet is configured to overlap with a second portion of the photonic chip, the second fillet has a second width dimension and a second height dimension transverse to the second width dimension, and the ratio of the second width dimension to the second height dimension is greater than or equal to 1.

5.

14. The structure according to claim 13, characterized in that The packaging substrate has an edge, the photonic chip has a top surface, and the first portion of the photonic chip is a first portion of the top surface adjacent to the edge of the packaging substrate.

15. The structure according to claim 14, characterized in that The packaging substrate has a surface, the photonic chip has a side surface, and the second portion of the photonic chip is a portion of the side surface adjacent to the surface of the packaging substrate.

16. The structure according to claim 14, characterized in that The first fillet is different from the second fillet.

17. The structure according to claim 1, characterized in that Also includes: The cover includes a first portion adjacent to the photonic chip and a second portion adjacent to the packaging substrate.

18. The structure according to claim 17, characterized in that The cover body includes a third portion located between the first portion and the second portion. The third portion of the cover body is separated from the package substrate to define an open space, and the first fillet is arranged in the open space.

19. The structure according to claim 17, characterized in that The packaging substrate has an edge, the photonic chip has a top surface and a bottom surface opposite to the top surface, the first portion of the photonic chip is the first portion of the top surface of the photonic chip adjacent to the edge of the packaging substrate, and the first portion of the cover body is adjacent to the bottom surface of the photonic chip.

20. A method, characterized in that include: attaching the photonic chip to the packaging substrate via a plurality of electrical connections, wherein the plurality of electrical connections are provided in a gap between the photonic chip and the packaging substrate; and A fillet is formed including an underfill material, wherein the fillet is configured to overlap a portion of the photonic chip adjacent the gap, the fillet having a width dimension and a height dimension transverse to the width dimension, and a ratio of the width dimension to the height dimension is greater than or equal to 1.5.

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