Electrostatic discharge protection circuit

Abstract

An electrostatic discharge protection circuit is coupled to a first bonding pad, and includes an electrostatic discharge detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs on the first bonding pad to generate a detection signal on the first node. The P-type transistor has a source coupled to the first bonding pad, a drain coupled to the second node, and a gate coupled to the first node to receive a detection signal. The N-type transistor has a drain coupled to the second node, a source coupled to ground, and a gate coupled to the second bonding pad. The discharge circuit is coupled between the first bonding pad and the ground, and is controlled by a driving signal on the second node. When the electrostatic discharge protection circuit is in an operation mode, the first bonding pad receives a first voltage, and the second bonding pad receives a second voltage.

Description

Technical Field

[0001] The invention relates to an electrostatic discharge protection circuit, in particular to an electrostatic discharge protection circuit capable of withstanding high voltage. Background Art

[0002] With the development of semiconductor technology for integrated circuits, the size of semiconductor components has been reduced to the sub-micron stage to improve the performance and computing speed of integrated circuits. However, the reduction in component size has caused some reliability problems, especially the protection ability of integrated circuits against electrostatic discharge (ESD). When the size of components is reduced due to advanced process technology, the protection ability against electrostatic discharge is also reduced a lot, resulting in a significant reduction in the ESD tolerance of components. Therefore, an electrostatic discharge protection circuit is needed to protect components from damage by electrostatic discharge. Summary of the invention

[0003] In view of this, the present invention proposes an electrostatic discharge protection circuit, which is coupled to a first bonding pad. This electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a P-type transistor, a first N-type transistor, and a discharge circuit. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs on the first bonding pad to generate a detection signal on a first node. The P-type transistor has a source coupled to the first bonding pad, a drain coupled to a second node, and a gate coupled to the first node to receive the detection signal. The first N-type transistor has a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second bonding pad. The discharge circuit is coupled between the first bonding pad and the ground, and is controlled by a drive signal on the second node. When the electrostatic discharge protection circuit is in an operating mode, the first bonding pad receives a first voltage, and the second bonding pad receives a second voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 FIG. 4 shows an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0005] Figure 2A express Figure 1 Schematic diagram of the operation of the electrostatic discharge protection circuit during normal operation.

[0006] Figure 2B express Figure 1 Schematic diagram of the operation of the electrostatic discharge protection circuit when encountering an electrostatic discharge event.

[0007] Figure 3 FIG. 4 shows an electrostatic discharge protection circuit according to another embodiment of the present invention.

[0008] Figure 4FIG. 4 shows an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0009] Figure 5 FIG. 2 shows an electrostatic discharge protection circuit according to another embodiment of the present invention.

[0010]

Explanation of symbols

[0011] 1: Electrostatic discharge protection circuit

[0012] 10: Electrostatic discharge detection circuit

[0013] 11: Driving circuit

[0014] 12: Discharge circuit

[0015] 13,30: Voltage clamp circuit

[0016] 100: Resistor

[0017] 101: Capacitors

[0018] 110:PMOS transistor

[0019] 111:NMOS transistor

[0020] 120:NMOS transistor

[0021] 130: Zener diode

[0022] 110A,111A,120A: Gate

[0023] 110B,111B,120B: Drain

[0024] 110C, 111C, 120C: Source

[0025] 110D,111D,120D: Base

[0026] 300: Zener diode

[0027] 400:NMOS transistor

[0028] 400A: Gate

[0029] 400B: Drain

[0030] 400C: Source

[0031] 400D: Base

[0032] 500:NMOS transistor

[0033] 500A: Gate

[0034] 500B: Drain

[0035] 500C: Source

[0036] 500D: Base

[0037] GND: Ground

[0038] N10, N11: common nodes

[0039] P10, P11: Bonding pads

[0040] VCC,VCCH: voltage DETAILED DESCRIPTION

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, a preferred embodiment is given below and described in detail with reference to the accompanying drawings.

[0042] Figure 1 2 shows an electrostatic discharge (ESD) protection circuit according to an embodiment of the present invention. Figure 1 The electrostatic discharge protection circuit 1 includes an electrostatic discharge detection circuit 10, a driving circuit 11, a discharge circuit 12, and a voltage clamping circuit 13. The electrostatic discharge protection circuit 1 is coupled to the bonding pads P10 and P11. When the electrostatic discharge protection circuit 1 operates in an operation mode, the bonding pads P10 and P11 can receive respective voltages. When the electrostatic discharge protection circuit 1 is not in the operation mode, when an electrostatic discharge event occurs on the bonding pad P10, the electrostatic discharge protection circuit 1 provides a discharge path between the bonding pad P10 and the ground GND to protect the element or device coupled to the bonding pad P10 from being damaged by the large current caused by the electrostatic discharge event.

[0043] See also Figure 1 , the electrostatic discharge detection circuit 10 is coupled between the bonding pad P10 and the ground GND. The electrostatic discharge detection circuit 10 includes a resistor 100 and a capacitor 101. The resistor 100 is coupled between the bonding pad P10 and the common node N10, and the capacitor 101 is coupled between the common node N10 and the ground GND. According to the connection of the resistor 100 and the capacitor 101, the resistor 100 and the capacitor 101 form a resistor-capacitor (RC) circuit architecture. The electrostatic discharge detection circuit 10 detects whether an electrostatic discharge event occurs on the bonding pad P10 to generate a detection signal on the common node N10.

[0044] The driving circuit 11 is coupled between the bonding pad P10 and the ground GND, and includes a P-type Metal-Oxide-Semiconductor (PMOS) transistor 110 and an N-type Metal-Oxide-Semiconductor (NMOS) transistor 111. In addition, the discharge circuit 12 is coupled between the bonding pad P10 and the ground GND, and includes an NMOS transistor 120. In this embodiment, the MOS transistors 110, 111, and 120 each have a gate, a drain, a source, and a base. In one embodiment, the MOS transistors 110, 111, and 120 are implemented by transistors with a source-to-source withstand voltage greater than 5 (V).

[0045] like Figure 1 As shown, the source 110C and the base 110D of the PMOS transistor 110 are coupled to the bonding pad P10, the drain 110B thereof is coupled to the common node N11, and the gate 110A thereof is coupled to the common node N10. The drain 111B of the NMOS transistor 111 is coupled to the common node N11, the source 111C and the base 111D thereof are coupled to the ground GND, and the gate 111A thereof is coupled to the bonding pad P11. According to the connection structure of the transistors 110 and 111, the driving circuit 11 generates a driving signal at the common node N11 according to the detection signal on the common node N10 and the voltage on the bonding pad P11. The drain 120B of the NMOS transistor 120 is coupled to the bonding pad P10, the source 120C and the base 120D thereof are coupled to the ground GND, and the gate 120A thereof is coupled to the common node N11. According to the circuit structure of the discharge circuit 12 , when an electrostatic discharge event occurs on the bonding pad P10 , the NMOS transistor 120 of the discharge circuit 12 is gate-triggered and turned on to provide a discharge path.

[0046] See also Figure 1, the voltage clamping circuit 13 is coupled between the source 110C and the gate 110A of the PMOS transistor 110, that is, coupled between the bonding pad P10 and the common node N10. When the electrostatic discharge protection circuit 1 is in the operation mode, the voltage clamping circuit 13 is used to clamp the gate-source voltage (Vgs) between the gate 110A and the source 110C of the PMOS transistor 110 within a voltage range. In this embodiment, the voltage clamping circuit 13 includes a zener diode 130. The cathode of the zener diode 130 is coupled to the source 110C of the PMOS transistor 110 (that is, coupled to the bonding pad P10), and the anode thereof is coupled to the gate 110A of the PMOS transistor 110 (that is, coupled to the common node N10). In the operation mode, based on the constant voltage characteristic of the Zener diode 130, the gate-source voltage (Vgs) of the PMOS transistor 110 can be clamped at a gate-source withstand voltage determined based on the parameters of the PMOS transistor 110 or below the aforementioned gate-source withstand voltage, so as to avoid the gate-source voltage (Vgs) of the PMOS transistor 110 being too large due to the high voltage on the bonding pad P10, thereby damaging the PMOS transistor 110.

[0047] The following will be passed Figure 2A-2B The operation of the electrostatic discharge protection circuit 1 will be described in detail.

[0048] See also Figure 2A When the electrostatic discharge protection circuit 1 is in the operation mode, a voltage VCCH is provided to the bonding pad P10, a voltage VCC is provided to the bonding pad P11, and the ground GND has a ground voltage (e.g., 0 volts (V)). For example, when the MOS transistors 110, 111, and 120 are implemented as transistors with a gate-source withstand voltage of 5 (V), the voltage VCCH is greater than or equal to 5V, and the voltage VCC is less than or equal to 5V, such as 5V, 3.3V, or 1.8V. In the operation mode, the voltage VCCH charges the capacitor 101 through the resistor 100, so that the detection signal on the common node N10 has a high voltage level, that is, the common node N10 has a high voltage close to the voltage VCCH (greater than or equal to 5V). The high voltage on the common node N10 (i.e., the detection signal of the high voltage level) turns off (OFF) the PMOS transistor 110. In addition, the NMOS transistor 111 is turned on (ON) according to the voltage VCC on the bonding pad P11. Therefore, based on the ground voltage of the ground GND, the driving signal on the common node N11 has a low voltage level, that is, the common node N11 has a low voltage (ground voltage (0V)) to turn off the NMOS transistor 120. At this time, the discharge circuit 12 does not provide a discharge path for ESD protection.

[0049] In the case where the electrostatic discharge protection circuit 1 of the present application does not have the voltage clamping circuit 13, if the charging speed of the voltage VCCH to the capacitor 101 is too slow in the operation mode, or if noise occurs on the bonding pad P10 and causes a voltage overshoot on the bonding pad P10, the gate-source voltage (Vgs) between the gate 110A and the source 110C of the PMOS transistor 110 is greater than the gate-source withstand voltage of the PMOS transistor 110, resulting in damage to the PMOS transistor 110, and further making the electrostatic discharge protection circuit 1 unable to perform its function.

[0050] like Figure 2A As shown, the electrostatic discharge protection circuit 1 of the present application has a voltage clamping circuit 13. If the charging speed of the voltage VCCH to the capacitor 101 is too slow in the operation mode, or if noise occurs on the bonding pad P10 and causes the voltage on the bonding pad P10 to overshoot, based on the constant voltage characteristic of the Zener diode 130, the gate-source voltage (Vgs) of the PMOS transistor 110 can be clamped at the gate-source withstand voltage (5V) of the PMOS transistor 110 or below the gate-source withstand voltage (5V), thereby preventing the PMOS transistor 110 from being damaged.

[0051] See also Figure 2B , when the electrostatic discharge protection circuit 1 is not in the normal operation mode, the voltage VCCH is not provided to the bonding pad P10, and the voltage VCC is not provided to the bonding pad P11. Therefore, the bonding pads P10 and P11 are in a floating state. When an electrostatic discharge event (e.g., a positive electrostatic discharge event) occurs on the bonding pad P10, the voltage on the bonding pad P10 increases instantaneously. At this time, based on the component characteristics of the capacitor 101, the detection signal on the common node N10 has a low voltage level, that is, the common node N10 has a low voltage. The low voltage on the common node N10 turns on (ON) the PMOS transistor 110, and the NMOS transistor 111 is turned off (OFF) based on the floating state on the bonding pad P11. Therefore, as the voltage on the bonding pad P10 increases instantaneously, the drive signal on the common node N11 has a high voltage level, that is, the common node N11 has a high voltage to turn on (ON) the NMOS transistor 120. Since the NMOS transistor 120 is turned on, a discharge path is formed between the bonding pad P10 and the ground GND, so that the electrostatic charge on the bonding pad P10 is conducted to the ground GND through the discharge path, thereby protecting the element or device coupled to the bonding pad P10 from being damaged by the large current caused by the electrostatic discharge event.

[0052] According to the above embodiment, the electrostatic discharge protection circuit 1 of the present application is provided with a voltage clamping circuit 13, which can clamp the gate-source voltage (Vgs) of the PMOS transistor 110 at the gate-source withstand voltage or below the gate-source withstand voltage, so as to prevent the high voltage caused by the electrostatic discharge event on the bonding pad P10 from damaging the PMOS transistor 110. In addition, even if the present application realizes the protection of the PMOS transistor 110 by setting the voltage clamping circuit 13, the protection trigger voltage of the electrostatic discharge protection circuit 1 will not be increased. In an embodiment of the present invention, the protection trigger voltage of the electrostatic discharge protection circuit 1 is as low as about 2.5V, which can quickly provide a discharge path when an electrostatic discharge event occurs. Furthermore, the ESD tolerance of the electrostatic discharge protection circuit 1 in the human body model (HBM) of the electrostatic discharge test is increased to 7-7.5kV, and the ESD tolerance of the machine model (MM) is increased to 250V.

[0053] exist Figure 1 In the embodiment of the present invention, the voltage clamping circuit 13 is provided to protect the PMOS transistor 110. In other embodiments, as Figure 3 As shown, a voltage clamping circuit 13 may be additionally provided to protect the NMOS transistor 111 . Figure 3 The electrostatic discharge protection circuit is similar to Figure 1 Electrostatic discharge protection circuit. Figure 3 Electrostatic discharge protection circuit and Figure 1 The electrostatic discharge protection circuit is different in that: Figure 3 The electrostatic discharge protection circuit further includes a voltage clamping circuit 30. The following only describes the voltage clamping circuit 30. For descriptions of other components, please refer to Figure 1 , Figure 2A to Figure 2B The relevant description is omitted here.

[0054] See also Figure 3, the voltage clamping circuit 30 is coupled between the gate 111A and the source 111C of the NMOS transistor 111, that is, coupled between the bonding pad P11 and the ground GND. When the electrostatic discharge protection circuit 1 is in the operation mode, the voltage clamping circuit 30 is used to clamp the gate-source voltage (Vgs) between the gate 111A and the source 111C of the NMOS transistor 111 within a voltage range. In this embodiment, the voltage clamping circuit 30 includes a Zener diode 300. The cathode of the Zener diode 300 is coupled to the gate 111A of the NMOS transistor 111 (that is, coupled to the bonding pad P11), and the anode thereof is coupled to the source 111C of the NMOS transistor 111 (that is, coupled to the ground GND). In the operation mode, based on the constant voltage characteristic of the Zener diode 300, the gate-source voltage (Vgs) of the NMOS transistor 111 can be clamped at or below the gate-source withstand voltage determined by the parameters of the NMOS transistor 111 to avoid the gate-source voltage (Vgs) of the NMOS transistor 111 being too large due to the high voltage on the bonding pad P11, thereby damaging the NMOS transistor 111.

[0055] exist Figure 1 In the embodiment of FIG. 1 , when an electrostatic discharge event occurs on the bonding pad P10, the NMOS transistor 120 of the discharge circuit 12 is gate-triggered and turned on to provide a discharge path. In other embodiments, such as Figure 4 As shown, the NMOS transistor 400 of the discharge circuit 12 is turned on by substrate triggering to provide a discharge path. Figure 4 The electrostatic discharge protection circuit is similar to Figure 1 Electrostatic discharge protection circuit. Figure 4 Electrostatic discharge protection circuit and Figure 1 The electrostatic discharge protection circuit is different in that: Figure 4 The NMOS transistor 400 of the discharge circuit 12 is turned on by the substrate trigger to provide a discharge path. The following is only an explanation of the NMOS transistor 400. For the description of other components, please refer to Figure 1 , Figure 2A to Figure 2B The relevant description is omitted here.

[0056] See also Figure 4 , the NMOS transistor 400 has a gate 400A, a drain 400B, a source 400C, and a base 400D. The drain 400B of the NMOS transistor 400 is coupled to the bonding pad P10, the source 400C and the gate 400A are coupled to the ground GND, and the base 400D is coupled to the common node N11. Figure 4It can be seen from the circuit architecture of the discharge circuit 12 that when an electrostatic discharge event occurs on the bonding pad P10, the NMOS transistor 400 is turned on by substrate triggering to provide a discharge path. In detail, when the electrostatic discharge protection circuit 1 is not in the normal operation mode and an electrostatic discharge event occurs on the bonding pad P10, the voltage on the bonding pad P10 increases instantly. At this time, based on the component characteristics of the capacitor 101, the detection signal on the common node N10 has a low voltage level, that is, the common node N10 has a low voltage. The low voltage on the common node N10 turns on the PMOS transistor 110, and the NMOS transistor 111 is turned off based on the floating state on the bonding pad P11. Therefore, as the voltage on the bonding pad P10 increases instantly, the drive signal on the common node N11 has a high voltage level, that is, the common node N11 has a high voltage. At this time, the base 400D and the drain 400B of the NMOS transistor 400 have a high potential, and the gate 400A and the source 400C are coupled to the ground GND, so the NMOS transistor 400 is turned on, which realizes substrate triggering. The turned-on NMOS transistor 400 provides a discharge path. The electrostatic charge on the bonding pad P10 can be conducted to the ground GND through the NMOS transistor 400 and along this discharge path.

[0057] exist Figure 3 In the embodiment of FIG. 1 , when an electrostatic discharge event occurs on the bonding pad P10, the NMOS transistor 120 of the discharge circuit 12 is gate-triggered and turned on to provide a discharge path. In other embodiments, such as Figure 5 As shown, the NMOS transistor 500 of the discharge circuit 12 is turned on by substrate triggering to provide a discharge path. Figure 5 The electrostatic discharge protection circuit is similar to Figure 3 Electrostatic discharge protection circuit. Figure 5 Electrostatic discharge protection circuit and Figure 3 The electrostatic discharge protection circuit is different in that: Figure 5 The NMOS transistor 500 of the discharge circuit 12 is turned on by the substrate trigger to provide a discharge path. The following is only an explanation of the NMOS transistor 500. For the description of other components, please refer to Figure 1 to Figure 3 The relevant description is omitted here.

[0058] See also Figure 5 , the NMOS transistor 500 has a gate 500A, a drain 500B, a source 500C, and a base 500D. The drain 500B of the NMOS transistor 500 is coupled to the bonding pad P10, the source 500C and the gate 500A are coupled to the ground GND, and the base 500D is coupled to the common node N11. Figure 5It can be seen from the circuit architecture of the discharge circuit 12 that when an electrostatic discharge event occurs on the bonding pad P10, the NMOS transistor 500 is turned on by substrate triggering to provide a discharge path. In detail, when the electrostatic discharge protection circuit 1 is not in the normal operation mode and an electrostatic discharge event occurs on the bonding pad P10, the voltage on the bonding pad P10 increases instantly. At this time, based on the component characteristics of the capacitor 101, the detection signal on the common node N10 has a low voltage level, that is, the common node N10 has a low voltage. The low voltage on the common node N10 turns on the PMOS transistor 110, and the NMOS transistor 111 is turned off based on the floating state on the bonding pad P11. Therefore, as the voltage on the bonding pad P10 increases instantly, the drive signal on the common node N11 has a high voltage level, that is, the common node N11 has a high voltage. At this time, the base 500D and the drain 500B of the NMOS transistor 500 have a high potential, and the gate 500A and the source 500C are coupled to the ground GND, so the NMOS transistor 500 is turned on, which realizes substrate triggering. The turned-on NMOS transistor 500 provides a discharge path. The electrostatic charge on the bonding pad P10 can be conducted to the ground GND through the NMOS transistor 500 and along this discharge path.

[0059] Although the present invention has been disclosed as above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that: coupled to a first bonding pad, comprising: an electrostatic discharge detection circuit, detecting whether an electrostatic discharge event occurs on the first bonding pad to generate a detection signal on a first node; a P-type transistor having a source coupled to the first bonding pad, a drain coupled to a second node, and a gate coupled to the first node to receive the detection signal; a first N-type transistor having a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second bonding pad; and a discharge circuit coupled between the first bonding pad and the ground and controlled by a driving signal on the second node; When the electrostatic discharge protection circuit is in an operation mode, the first bonding pad receives a first voltage, and the second bonding pad receives a second voltage.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that: When the electrostatic discharge protection circuit is in the operation mode, the first voltage is greater than the second voltage.

3. The electrostatic discharge protection circuit according to claim 1, characterized in that: The electrostatic discharge detection circuit comprises: a resistor coupled between the first bonding pad and the first node; and A capacitor is coupled between the first node and the ground.

4. The electrostatic discharge protection circuit according to claim 1, characterized in that: Also includes: a first voltage clamping circuit coupled between the gate and the source of the P-type transistor; Wherein, when the electrostatic discharge protection circuit is in the operation mode, the first voltage clamping circuit is used to clamp a first gate-source voltage between the gate and the source of the P-type transistor within a first voltage range.

5. The electrostatic discharge protection circuit according to claim 4, characterized in that: The first voltage clamping circuit comprises: A Zener diode has a cathode coupled to the source of the P-type transistor and an anode coupled to the gate of the P-type transistor.

6. The electrostatic discharge protection circuit according to claim 4, characterized in that: Also includes: a second voltage clamping circuit coupled between the gate and the source of the first N-type transistor; Wherein, when the electrostatic discharge protection circuit is in the operation mode, the second voltage clamping circuit is used to clamp a second gate-source voltage between the gate and the source of the first N-type transistor within a second voltage range.

7. The electrostatic discharge protection circuit according to claim 6, characterized in that: The second voltage clamping circuit comprises: A Zener diode has a cathode coupled to the gate of the first N-type transistor and an anode coupled to the source of the first N-type transistor.

8. The electrostatic discharge protection circuit according to claim 6, characterized in that: The discharge circuit comprises: A second N-type transistor has a drain coupled to the first bonding pad, a source coupled to the ground, and a gate coupled to the second node.

9. The electrostatic discharge protection circuit according to claim 6, characterized in that: The discharge circuit comprises: A second N-type transistor has a drain coupled to the first bonding pad, a source and a gate coupled to the ground, and a base coupled to the second node.

10. The electrostatic discharge protection circuit according to claim 1, wherein: When the electrostatic discharge event occurs on the first bonding pad, the discharge circuit provides a discharge path between the first bonding pad and the ground according to the driving signal.

11. The electrostatic discharge protection circuit according to claim 1, characterized in that: The discharge circuit comprises: A second N-type transistor has a drain coupled to the first bonding pad, a source coupled to the ground, and a gate coupled to the second node.

12. The electrostatic discharge protection circuit according to claim 1, characterized in that: The discharge circuit comprises: A second N-type transistor has a drain coupled to the first bonding pad, a source and a gate coupled to the ground, and a base coupled to the second node.

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