Power factor correction circuit

Abstract

The invention relates to an electrical device (1) comprising an input interface (T1) to be connected to an AC voltage source, an output interface (T2) to be connected to an electrical energy storage unit, a totem-pole power factor correction circuit (10) comprising at least a high-frequency power switching half-bridge (11) and a low-frequency switching half-bridge (12), the invention relates to a power factor correction circuit (10) comprising at least one high-frequency power switching half-bridge (11), each comprising at least two switches (S1, S2, D3, D4), the high-frequency power switching half-bridge (11) further comprising an inductor (L1), a control system (20) for said power factor correction circuit (10), designed to generate control signals (P1, P2) for the switches of the at least one high-frequency power switching half-bridge (11).

Description

Technical Field

[0001] The invention relates to a power factor correction circuit, an electrical device and a vehicle charger for an electric energy storage unit comprising the electrical device. Background Art

[0002] The present invention relates to an electrical device, comprising:

[0003] Input interface, which will be connected to the AC voltage source,

[0004] Output interface, which will be connected to the electrical energy storage unit,

[0005] A totem pole power factor correction circuit includes at least one high-frequency power switch half-bridge and a low-frequency switch half-bridge, wherein the half-bridges include at least two switches, and the high-frequency power switch half-bridge also includes an inductor.

[0006] A control system for the power factor correction circuit is designed to generate control signals for switches of the at least one high-frequency power switch half-bridge.

[0007] This device is used to convert, by means of a power factor correction circuit, an AC voltage applied to an input interface of the device into a DC voltage intended to charge an electrical energy storage unit connected to an output interface.

[0008] During this transition, the device can apply a phase margin to the input current. This phase correction makes it possible to compensate for the angular offset between the voltage and the input current, which can generate harmonic distortion.

[0009] During this same transition period, the device can also apply gain margin to the input current.

[0010] Such devices are integrated, for example, in an on-board charger for the vehicle's electrical energy storage unit.

[0011] The totem pole power factor correction circuit is a known variant of the power factor correction circuit. Compared to other popular solutions of power factor correction circuits, the totem pole power factor correction circuit is an advantageous circuit due to its good efficiency and its reduced number of components.

[0012] However, it is known that for such devices comprising a totem-pole power factor correction circuit, when a zero crossing of the AC current applied to the input interface occurs, a distortion is observed in this same current.

[0013] These distortions can take the form of positive and negative current peaks around the zero crossings.

[0014] These current peaks are due to the fact that when the AC voltage at the input of the device transitions from a positive half-cycle to a negative half-cycle or vice versa, the duty cycle of the control signal for one switch in the at least one high-frequency power switch half-bridge suddenly transitions from a value close to 100% to a value close to 0%, and the duty cycle of the control signal for the other switch of the same half-bridge suddenly transitions from a value close to 0% to a value close to 100%. After these sudden changes in duty cycle, a voltage equal to the output voltage is applied to the inductance of the at least one high-frequency power switch half-bridge due to the parasitic capacitance and slow reverse recovery of the parasitic diodes in the transistor switches.

[0015] In the same manner, it is known that after the zero crossing of the AC voltage, the control system does not have sufficient bandwidth to track the sudden change in duty cycle and track the distribution of the input voltage to calculate the gain margin and phase margin to be applied to the input current. This results in a period of time when the control system cannot properly generate the control signal for the at least one high frequency power switch half-bridge in the same way as the current peak generated around the zero crossing.

[0016] This distortion produces undesirable effects in the electrical equipment and these effects may disrupt the correct operation of the electrical components connected to the interface, in particular increasing the harmonic distortion rate and common mode interference.

[0017] These distortions need to be eliminated. Summary of the invention

[0018] The object of the present invention is to meet this need using an electrical device comprising:

[0019] Input interface, which is connected to an AC voltage source,

[0020] an output interface connected to an electrical energy storage unit,

[0021] A totem pole power factor correction circuit includes at least one high-frequency power switch half-bridge and a low-frequency switch half-bridge, wherein the half-bridges include at least two switches, and the high-frequency power switch half-bridge also includes an inductor.

[0022] a control system for the power factor correction circuit, the control system being designed to generate control signals for switches of the at least one high-frequency power switching half-bridge,

[0023] In which, the control system includes at least one positive branch and a negative branch, the at least one positive branch is designed to generate a first set of duty cycle values ​​for these control signals starting from the positive half-cycle of the AC voltage at the input end of the device, and the negative branch is designed to generate a second set of duty cycle values ​​for these control signals starting from the negative half-cycle of the AC voltage at the input end of the device.

[0024] The presence of the positive branch and the negative branch within the control system makes it possible to independently generate sets of duty cycles for the control signals so that they are respectively adapted to the positive half-cycle and the negative half-cycle of the AC voltage at the input of the device. This results in the control system more successfully managing the transition from the positive half-cycle to the negative half-cycle and from the negative half-cycle to the positive half-cycle of the AC voltage applied to the input interface, and thus results in a reduction in current oscillations when zero crossings of the AC voltage occur, and ultimately results in a reduction in undesirable effects in the electrical device.

[0025] According to one embodiment, the control system comprises a phase-locked loop module designed to generate an AC reference voltage that is in phase with the AC voltage at the input interface of the device.

[0026] In all the above cases, the control system may include a separation module which receives the AC reference voltage at an input and is designed to generate a positive voltage corresponding to a positive half-cycle of the AC reference voltage and a negative voltage corresponding to a negative half-cycle of the AC reference voltage.

[0027] In all the above cases, the separation module is designed to provide a selection signal indicating the current half-cycle, ie the positive or negative half-cycle, of the AC voltage at the input of the device.

[0028] In all of the above cases, the positive branch and the negative branch can each include a current multiplication module and a current control module, and the branches are designed to receive the positive voltage or negative voltage of the separation module and the current at the input end of the device, respectively, and are designed to each provide a set of duty cycle values ​​of the control signal to be applied to the switch of the at least one high-frequency power switch half-bridge.

[0029] According to one embodiment, each current multiplication module is designed to receive the voltage of the separation module respectively and to multiply the voltage with the current at the input of the device and to provide an instantaneous power signal at the output.

[0030] According to one embodiment, each current control module is designed to receive the instantaneous power value at the output of the multiplication module and generate a set of duty cycle values ​​based on the gain margin and phase margin of the AC current to be applied to the input of the power factor correction circuit.

[0031] The generation of the duty cycle can be achieved, for example, by inputting a correspondence table or by one or more equations, taking the corresponding instantaneous power value at the input.

[0032] In all of the above cases, the control system may include a duty cycle selection module designed to provide a set of duty cycle values ​​corresponding to a set of duty cycle values ​​of the positive branch during the positive half cycle of the AC voltage at the input terminal of the device or a set of duty cycle values ​​of the negative branch during the negative half cycle of the AC voltage at the input terminal of the device.

[0033] In all the above cases, the control system may comprise a pulse width modulated signal generator designed to generate control signals for switches of the at least one high frequency power switch half-bridge according to the set of duty cycles at the output of the selection module.

[0034] According to one embodiment, the at least one high frequency power switching half-bridge comprises an inductor and two transistor switches.

[0035] According to one embodiment, the transistor switches of the at least one high-frequency power switch half-bridge are composed of a transistor (eg, a MOSFET transistor) and a freewheeling diode, which may be an intrinsic diode of the MOSFET transistor.

[0036] According to one embodiment, the switches of the low-frequency switching half-bridge are diodes. For example, two diodes are provided.

[0037] As a variant, the switches of the low-frequency switching half-bridge are controllable switches, such as transistors, each switch using, for example, an IGBT or a MOSFET. In this variant, two controllable switches are provided. Still in this variant, the power factor correction circuit is bidirectional and therefore has an operating mode in which the electrical energy storage unit connected to the output interface of the device is discharged to provide an AC voltage source in the input interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] It will be possible to better understand the present invention by reading the following description of non-limiting exemplary embodiments of the present invention:

[0039] Figure 1 An electrical device according to an exemplary embodiment of the present invention is shown,

[0040] Figure 2 Shown integrated in Figure 1 A control system for a power factor correction circuit according to an exemplary embodiment of the present invention in an electrical device of

[0041] Figure 3a , Figure 3b and Figure 3c These curves make it possible to demonstrate the effect of the invention, corresponding to the voltage curve and the current curve. DETAILED DESCRIPTION

[0042] like Figure 1 The device 1 shown comprises an input interface T1 and an output interface T2. The device 1 also comprises a power factor correction circuit 10 and a control system 20 for the power factor correction circuit.

[0043] according to Figure 1 The power factor correction circuit 10 includes a switching half-bridge 11. The half-bridge 11 is connected to the positive terminal T1 of the input interface T1 through its middle branch. + The half bridge 11 includes an inductor L1 in its middle branch. The middle branch, the upper branch and the lower branch of the half bridge 11 are connected at a common point of the three branches. The lower branch includes a lower switch S1 and the upper branch includes an upper switch S2. The upper branch is connected to the positive terminal T2 of the output interface T2. + The lower branch is connected to the negative terminal T2 of the interface T2 - .

[0044] like Figure 1 The illustrated switches S1 and S2 each include a MOSFET transistor Q1 and Q2, respectively, and include a freewheeling diode D1 and D2, respectively.

[0045] Due to the presence of the inductor L1 , the switching half-bridge 11 is referred to as a power switching half-bridge. The presence of this inductor makes it possible to apply a gain to the input current of the power factor correction circuit 10 .

[0046] The switching half bridge 11 is also called a high-frequency switching half bridge because the switches S1 and S2 are controlled by control signals P1 and P2, respectively, and the frequency of the control signals is higher than the frequency of the current applied to the input interface T1. For example, the voltage V applied to the input interface T1 in The frequency may be at 50 Hz or 60 Hz, and the control signals P1 and P2 may be at a frequency between 50 kHz and 100 kHz.

[0047] Figure 1 The power factor correction circuit 10 shown also includes a switching half-bridge 12. The half-bridge 12 is connected to the negative terminal T1 of the input interface T1 through its middle branch. - The middle branch is connected to the upper branch and the lower branch of the half bridge 12 at a common point. The lower branch includes a lower diode D3 and the upper branch includes an upper diode D4. The upper diode D4 is connected to the positive terminal T2 of the output interface T2. + , and the lower diode D3 is connected to the negative terminal T2 of the output interface T2 - .

[0048] The switching half-bridge 12 is referred to as a low-frequency switching half-bridge, since the diodes D3 and D4 change from blocking to conducting, and vice versa, depending on the frequency of the current applied to the input interface T1 .

[0049] The power factor correction circuit 10 further includes a filter capacitor C1 connected between a positive terminal T2+ and a negative terminal T2 − of the output interface T2 .

[0050] This power factor correction circuit 10 is called a totem pole power factor correction circuit. Figure 1 As shown, there are a high-frequency power switching half-bridge 11 and a low-frequency switching half-bridge 12 .

[0051] Figure 1 The device 1 shown also includes a power factor correction circuit control system 20, which is designed to generate control signals P1 and P2 for switches S1 and S2 of the high-frequency power switch half-bridge 11 of the power factor correction circuit 10. The control system 20 receives at its input an AC voltage V applied at the input of the device 1. in (t) and AC current I in (t).

[0052] The power factor correction circuit control system 20 may be a computer (eg, a microcontroller) or an integrated circuit (eg, an FPGA or an ASIC).

[0053] The power factor correction circuit control system 20 will refer to Figure 2 Give a description.

[0054] like Figure 2 The control system 20 described comprises a phase-locked loop module 21. This module is designed to operate according to the voltage V drawn at the input of the device 1. in Generate AC reference voltage V PLL (t). The reference voltage V PLL (t) is designed to be proportional to the input voltage V in (t) In phase.

[0055] The AC reference voltage V PLL (t) is supplied to the separation module 22, which is designed to generate a reference AC voltage V PLL The positive voltage V corresponding to the positive half cycle of (t) PLL+ (t) and V PLL The negative voltage V corresponding to the negative half cycle of (t) PLL- (t).

[0056] The separation module 22 is also designed to generate an indication reference voltage V PLL (t) The selection signal Sel of the current half cycle.

[0057] like Figure 2 The depicted control system 20 comprises a positive branch 30 and a negative branch 31 .

[0058] The positive branch 30 is designed to receive the positive reference voltage VPLL+ (t) and the current I at the input of device 1 in (t), and is designed to generate a signal α + Signal α + Corresponding to the duty cycle values ​​of the control signals P1 and P2 to be applied to the switches S1 and S2 for the high frequency power switch half bridge 11, respectively, to apply the desired phase margin and gain margin to the input current I in (t).

[0059] The negative branch 31 is designed to receive the negative reference voltage V PLL- (t) and the current I at the input of device 1 in (t), and is designed to provide a signal α - Signal α - Corresponding to the duty cycle values ​​of the control signals P1 and P2 to be applied to the switches S1 and S2 for the high frequency power switch half bridge 11, respectively, to apply the desired phase margin and gain margin to the input current I in (t).

[0060] As an example, the desired values ​​of phase margin and gain margin may be 45° and 12 dB, respectively.

[0061] like Figure 2 The positive branch 30 shown comprises a multiplication module 23a, which is designed to convert the positive reference voltage V at the output of the separation module 22 into PLL+ (t) and the current I drawn at the input of device 1 in The result of the multiplication operation is the instantaneous power value P + (t), the instantaneous power value is expressed in V PLL The instantaneous power at the input of device 1 during the positive half-cycle of (t).

[0062] The positive branch 30 also includes a current control module 24a. This module is designed to generate a set of duty cycle values ​​α of the control signals P1 and P2 for the switches S1 and S2 of the high-frequency power switch half-bridge 11. + The duty cycle value of this group is α + is the instantaneous power P at the output of the multiplication module 23a + (t) generated.

[0063] Similarly, in Figure 2 In the example shown, the negative branch 31 comprises a multiplication module 23b which takes a negative reference voltage V PLL- (t) and input current I in (t), and generates instantaneous power P - (t), the instantaneous power is expressed in VPLL The instantaneous power at the input of device 1 during the negative half cycle of (t). The instantaneous power P - (t) is transmitted to the current control module 24b, which is designed to generate a set of duty cycle values ​​α of the control signals P1 and P2 for the switches S1 and S2 of the high-frequency power switch half-bridge 11. - .

[0064] exist Figure 2 In the example shown, a set of duty cycle values ​​α at the output end of the positive branch 30 is + and a set of duty cycle values ​​α at the output end of the negative branch 31 - is supplied to the selection module 25. With the aid of the selection signal Sel at the output of the separation module 22, the selection module 25 determines α for the positive half-cycle + or α for the negative half cycle - Which set of values ​​in has to be used for controlling the switches S1 and S2 of the high-frequency power switching half-bridge 11. The set of duty cycle values ​​selected at the output of the selection module 25 is denoted as α.

[0065] Figure 2 The control system shown also includes a pulse width modulation signal generator 26. The signals P1 and P2 generated by this generator 26 are control signals for the switches S1 and S2 of the high frequency power switch half bridge 11. The control signals P1 and P2 are generated by the generator 26 with a duty cycle according to a set of duty cycle values ​​α provided by the selection module 25.

[0066] Figure 3a Shown with exactly the same time scale on the X-axis:

[0067] - a graph 40 showing the current in amperes flowing through the diode D3,

[0068] - a graph 41 showing the current in amperes flowing through the diode D4,

[0069] - a graph 42 showing the voltage of the control signal P2 in volts,

[0070] - a graph 43 showing the voltage of the control signal P1 in volts, and

[0071] - Graph 44 showing the input current I in (t), the unit is ampere.

[0072] Figure 3b The same time scale as Figure 3a The same graph, with the focus on the 0pn Time I inThe transition from the positive half cycle to the negative half cycle.

[0073] Figure 3c The same time scale as Figure 3a The same graph, with the focus on the 0np Time I in The transition from the negative half cycle to the positive half cycle.

[0074] In this example, the input current I in (t) has a frequency of 50 Hz, which can be Figure 3a 40, 41 and 44.

[0075] In this example, the frequency of the control signals P1 and P2 is 80kHz, which can be Figure 3b and Figure 3c 42 and 43.

[0076] exist Figure 3a , Figure 3b and Figure 3c It can be observed from the graphs 40 and 41 that the diodes D3 and D4 in each case are connected at the input current I in It conducts during the negative half cycle and the positive half cycle.

[0077] exist Figure 3a , Figure 3b and Figure 3c It can be observed that on the graph 44, the input current I in (t) does not include any significant distortion when the zero crossing occurs, such as during the transition from the positive half-cycle to the negative half-cycle, Figure 3b As shown, or during the transition from the negative half cycle to the positive half cycle, as Figure 3c shown.

[0078] exist Figure 3b In the example shown, at time t 0pn When the current I in (t) Before the transition from the positive half cycle to the negative half cycle, the control signal P2 has a duty cycle of 0% as can be seen on graph 42, and the control signal P1 has a duty cycle of nearly 100% as can be seen on graph 43. This zero duty cycle of the control signal P2 allows the parasitic capacitance of the switch S2 to be fully discharged before the zero crossing and makes it possible to avoid current peaks.

[0079] exist Figure 3c In the example shown, at time t 0np When the current I in(t) Before the transition from the negative half cycle to the positive half cycle, it can be seen on graph 42 that the control signal P2 has a duty cycle close to 100%, and it can be seen on graph 43 that the control signal P1 has a zero duty cycle. This zero duty cycle of the control signal P1 allows the parasitic capacitance of the switch S1 to be fully discharged before the zero crossing and makes it possible to avoid current peaks.

[0080] exist Figure 3b In the example shown, at time t 0pn When the current I in (t) After the transition from the positive half cycle to the negative half cycle, control signal P2 has a duty cycle of nearly 100% as can be seen in graph 42, and control signal P1 has a duty cycle of zero as can be seen in graph 43. This zero duty cycle of control signal P1 makes it possible to wait for diode D3 to begin conducting before closing switch S1 and conducting current, as can be seen in graph 40. Thus, the current I in The current peak occurs after the zero crossing of (t).

[0081] exist Figure 3c In the example shown, at time t 0np When the current I in (t) After the transition from the negative half cycle to the positive half cycle, control signal P2 has a zero duty cycle as can be seen on graph 42, and control signal P1 has a duty cycle close to 100% as can be seen on graph 43. This zero duty cycle of control signal P2 makes it possible to wait for diode D4 to begin conducting before closing switch S2 and conducting current, as can be seen on graph 41. Thus, a short circuit in current I is prevented. in The current peak occurs after the zero crossing of (t).

[0082] These duty cycle values ​​of the control signals P1 and P2 are generated due to the division of the control system into two branches (positive branch 30 and negative branch 31), which makes it possible to prevent the input current I in The current peaks occur before and after the zero crossing of (t). The positive branch 30 and the negative branch 31 only see positive voltage or zero voltage and negative voltage or zero voltage, respectively, and the input voltage V in The half-cycle variation of the input voltage V is not managed by the current control modules 24a and 24b that generate the duty cycle of the control signal. in The zero crossing point of the AC current I in (t) is reduced.

[0083] The invention is not limited to the exemplary embodiments that have just been described.

[0084] Specifically, the power factor correction circuit 10 may include more than one high frequency power switch half bridge. In this case, the number of control signals generated by the control system 20 increases according to the number of switches in the high frequency power switch half bridge.

[0085] In particular, the low-frequency switching half-bridge 12 may include controllable switches (e.g. transistor switches) instead of diodes. In this case, these controllable switches may be controlled by control signals having a frequency that is ideally equal to the frequency of the AC voltage at the input of the device. These controllable switches may be, for example, IGBT transistors or MOSFET transistors.

[0086] In this case, the power factor correction circuit 10 can be a bidirectional circuit and thus has an operation mode in which an AC voltage source is present at interface T2 to supply an AC voltage to interface T1. For example, an electrical energy storage unit connected to interface T2 is discharged to supply an AC voltage to input interface T1.

Claims

1. An electrical device (1), comprising: An input interface (T1) connected to an AC voltage source, an output interface (T2), the output interface being connected to an electrical energy storage unit, A totem pole power factor correction circuit (10), the totem pole power factor correction circuit comprising at least one high-frequency power switch half bridge (11) and a low-frequency switch half bridge (12), the half bridges (11, 12) each comprising at least two switches (S1, S2, D3, D4), the high-frequency power switch half bridge (11) further comprising an inductor (L1), A control system (20) for the power factor correction circuit (10), the control system being designed to generate control signals (P1, P2) for switches of the at least one high-frequency power switching half-bridge (11), The control system (20) comprises at least one positive branch (30) and a negative branch, wherein the at least one positive branch is designed to generate a first set of duty cycle values ​​(α ) for the control signal (P1, P2) starting from a positive half-cycle of the AC voltage at the input of the device. + ), the negative branch being designed to generate a second set of duty cycle values ​​(α ) for the control signal (P1, P2) starting from the negative half-cycle of the AC voltage at the input of the device - ).

2. Electrical device according to the preceding claim, wherein The control system (20) includes a circuit designed to generate an AC reference voltage (V PLL ) of the phase-locked loop module (21), the AC reference voltage and the AC voltage (V in ) are in phase.

3. Electrical device according to the preceding claim, wherein The control system (20) includes a separation module (22) which receives the AC reference voltage (V PLL ) and is designed to generate a positive voltage (V PLL+ ) and a negative voltage (V PLL- ).

4. Electrical device according to the preceding claim, wherein The separation module (22) is designed to provide a selection signal (Sel) indicating the AC voltage (V in ) of the current half cycle, that is, the positive or negative half cycle.

5. The device according to claim 3 or 4, wherein: The positive branch (30) and the negative branch (31) each include a current multiplication module (23a, 23b) and a current control module (24a, 24b), and the branches are designed to receive the positive voltage (V PLL+ ) or negative voltage (V PLL- ) and the current at the input of the device (I in ), and are designed to each provide a set of duty cycle values ​​(α+, α) applied to the control signals (P1, P2) for the switches of the at least one high-frequency power switching half-bridge (11) - ).

6. Device according to the preceding claim, wherein Each current multiplication module (23a, 23b) is designed to receive the voltage of the separation module (22) and to multiply the voltage by the input current (I in ) and is designed to provide an instantaneous power signal (P + , P - ).

7. Device according to the preceding claim, wherein Each current control module (24a, 24b) is designed to receive an instantaneous power value (P + , P - ), and according to the AC current (I in ) to generate a set of duty cycles (α + , α - ).

8. The electrical device according to any one of claims 5 to 7, wherein: The control system (20) comprises a duty cycle selection module (25) designed to provide an AC voltage (V in ) during the positive half cycle (α + ) or a set of duty cycles (α ) of the negative branch during the negative half cycle of the AC voltage at the input of the device - ) corresponds to a set of duty cycles (α).

9. An electrical device according to any preceding claim, wherein: The control system (20) comprises a pulse width modulation signal generator (26) which is designed to generate control signals for switches (P1, P2) of the at least one high-frequency power switch half-bridge (11) according to the set of duty cycles (α) at ​​the output of the selection module (25).

10. An on-board charger for an electrical energy storage unit, comprising an electrical device (1) according to any one of the preceding claims.

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