Common-mode voltage suppression method and device

Abstract

The invention discloses a common-mode voltage suppression method and device. The method comprises the following steps: creating nine virtual voltage vectors on an original voltage vector to reduce a common-mode voltage; assuming that any virtual voltage vector is VXY and a # imgabs0 # virtual voltage vector V12 is equal to 1 / 2 (V1 + V2), and obtaining virtual voltage vectors V12, V23, V34, V45, V56, V61, V14, V25 and V36; the a-beta two-phase static coordinate system plane is divided into six sectors by the nine newly synthesized virtual vectors; approaching from a hexagonal rotating voltage to a circular rotating voltage is realized through combination of six non-zero virtual vectors and three zero virtual vectors, a sector where a required voltage vector is located is judged, and the sector is synthesized by three nearest virtual voltage vectors; the problem that the service life of the motor is shortened due to the fact that the inverter driving system outputs high common-mode voltage when the SVPWM algorithm is adopted is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of inverter control and relates to a common mode voltage suppression method and device. Background Art

[0002] With the rapid development of new energy vehicle technology, the selection of drive motors usually focuses on synchronous motors or asynchronous motors. Among them, permanent magnet synchronous motors have been widely used in new energy vehicles with their excellent energy efficiency and significant power density advantages. At present, the powertrain systems in many pure electric and hybrid vehicles generally adopt space vector pulse width modulation (SVPWM) algorithms to optimize the power conversion efficiency and improve the torque control accuracy. However, when the SVPWM algorithm is adopted, the inverter drive system will output a higher common mode voltage. Due to the high-frequency change of the common mode voltage, shaft currents will be generated. These shaft currents will induce shaft voltages on the motor shaft and form bearing currents. This bearing current will increase the mechanical wear between the bearings, causing the motor bearings to be damaged in a short period of time, significantly shortening the service life of the motor. Therefore, in order to avoid the influence of high-frequency and high-amplitude common mode voltages on the motor bearings, corresponding measures need to be taken to suppress the generation of common mode voltages. At present, the common mode voltage can be eliminated by adding a feedforward active filter, which can suppress the generation of common mode voltages, but the structure is complex, additional equipment needs to be added, and the system cost and complexity are increased.

[0003] Patent document CN 118214324 A discloses a motor driving method and device based on a novel SVPWM algorithm. Different from the technical solution of the present application, the present application reduces the common mode voltage by synthesizing a virtual voltage vector when adopting the SVPWM algorithm.

[0004] Patent document CN113114032B discloses a method for suppressing common-mode voltage based on SVPWM under synthetic mode changes. This patent document obtains switch on-time by voltage vector synthesis and adjusts the on-order of switch units to suppress common-mode voltage at high and low frequencies. This is different from the technical solution of this application.

[0005] Patent document CN105356805A discloses a method for predicting common-mode voltage suppression using a permanent magnet synchronous motor model. The technical solution of this patent document performs optimization operations through four voltage vectors for each control cycle to achieve common-mode voltage suppression, but the amount of calculation is large, which is different from the technical solution of this application. Summary of the invention

[0006] The technical problem to be solved by the present invention is to overcome the above-mentioned problems existing in the prior art and provide a common mode voltage suppression method and device.

[0007] In order to solve the problem that when using the SVPWM algorithm, the inverter drive system outputs a higher common-mode voltage, thereby shortening the service life of the motor, and considering that adding additional hardware equipment will increase the cost and complexity of the system, this application proposes an equivalent vector regulation method to reduce the common-mode voltage.

[0008] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0009] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions:

[0010] A common-mode voltage suppression method creates nine virtual voltage vectors on the original voltage vector to reduce the common-mode voltage; assuming that any virtual voltage vector is V XY , V XY The voltage vector V X With V Y Synthesis, that is Virtual voltage vector V 12 =1 / 2(V1+V2), and the virtual voltage vector V is obtained. 12 、V 23 、V 34 、V 45 、V 56 、V 61 、V 14 、V 25 、V 36 , where V 14 、V 25 、V 36 is the zero vector, and the nine newly synthesized virtual vectors divide the a-β two-phase stationary coordinate system plane into six sectors;

[0011] The approach from hexagonal to circular rotating voltage is achieved through the combination of six non-zero virtual vectors and three zero virtual vectors. The sector where the required voltage vector is located is determined and synthesized by its three nearest virtual voltage vectors, thereby reducing the higher common-mode voltage output by the inverter drive system.

[0012] Furthermore, V 12 Composed of V1 and V2, the common mode voltage of V1 is -U dc / 6, the common mode voltage of V2 is U dc / 6, V 12 The common mode voltage also includes U dc / 6 and -U dc / 6, this is V 12 The instantaneous value, V 12 The average value is:

[0013] U AV_12 =(U AV_1 +U AV_2 ) / 2=(-U dc / 6+U dc / 6) / 2=0;

[0014] V 12 The average common-mode voltage is 0.

[0015] Furthermore, V 12 The common-mode voltage is opposite in magnitude, forming V 12 The proportions of the vectors are the same, and the remaining virtual vectors and the average common-mode voltages are derived in a similar way, and the average common-mode voltages of the remaining virtual vectors are all 0.

[0016] Furthermore, the virtual vector V 12 、V 23 、V 34 、V 45 、V 56 、V 61 The angles are 30°, 90°, 150°, 210°, 270°, 330°, V 14 、V 25 、V 36 are all zero vectors.

[0017] Furthermore, the virtual vector V 12 、V 23 、V 34 、V 45 、V 56 、V 61 The size of

[0018] A common mode voltage suppression device, comprising:

[0019] An acquisition module, used for acquiring nine virtual voltage vectors;

[0020] A sector determination module, used for dividing the a-β two-phase stationary coordinate system plane into six sectors according to the voltage vector acquired by the acquisition unit;

[0021] The vector combination module is used for combining six non-zero virtual vectors and three zero virtual vectors to realize the approximation of the rotating voltage from hexagon to circle.

[0022] Furthermore, the vector combination module includes a sector determination unit and a synthesis unit;

[0023] The sector determination unit is used to determine the sector where the required voltage vector is located;

[0024] The synthesis unit is used for synthesizing the three nearest virtual voltage vector sectors.

[0025] A processor is used to run a program, wherein the program executes the common mode voltage suppression method as described above when running.

[0026] A storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the common mode voltage suppression method as described above.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention solves the problem that when the SVPWM algorithm is adopted, the inverter drive system outputs a higher common mode voltage, thereby shortening the service life of the motor.

[0029] The present invention avoids the influence of high-frequency and high-amplitude common-mode voltage on motor bearings. The present invention has a simple structure, does not require additional equipment, and reduces system cost and complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be further described below in conjunction with the accompanying drawings:

[0031] Figure 1 It is the schematic diagram of a two-level three-phase inverter;

[0032] Figure 2 It is a schematic diagram of SVPWM voltage vector distribution;

[0033] Figure 3 To create nine virtual voltage vector schematics on the original voltage vector;

[0034] Figure 4 This is a flow chart of a common-mode voltage suppression method described in the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the implementation of the present invention clearer, the technical scheme in the embodiment of the present invention will be described in more detail below in conjunction with the drawings in the embodiment of the present invention. In the drawings, the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The described embodiments are part of the embodiments of the present invention, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limitations on the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The embodiments of the present invention are described in detail below in conjunction with the drawings.

[0036] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the scope of protection of the present invention.

[0037] The present invention is described in detail below in conjunction with the accompanying drawings:

[0038] 1. The mechanism of common mode voltage generation:

[0039] Assuming that the three-phase stator winding of the permanent magnet synchronous motor is completely symmetrical, that is, RA=RB=RC=Rs, LA=LB=LC=Ls, according to Kirchhoff's voltage law, we can get:

[0040]

[0041] Where V A 、V B 、V C is the voltage at the input terminal of the permanent magnet synchronous motor to the neutral point M on the DC side (reference ground), Rs and Ls are the resistance and inductance of the single-phase stator winding of the induction motor, respectively, i A 、i B 、i C is the three-phase transient current of the permanent magnet synchronous motor, d / dt is the differential operator, V MN It is the voltage between the neutral point of the permanent magnet motor stator winding and the neutral point of the power supply.

[0042] According to Kirchhoff's current law, we can get:

[0043] i A +i B +i C=0

[0044] Simplifying the addition of the three-phase voltages, we can get:

[0045]

[0046] Since the sum of the three-phase currents is 0, the magnitude of the common-mode voltage is:

[0047]

[0048] 2. The influence of the switching state of the inverter on the common mode voltage:

[0049] Define the state of the permanent magnet synchronous motor (PMSM) inverter: 1 means that the upper bridge arm is turned on and the corresponding lower bridge arm is turned off, and 0 means that the upper bridge arm is turned off and the corresponding lower bridge arm is turned on; therefore, when using the SVPWM algorithm, the 8 working states of the inverter can be defined as V0 (000), V1 (100), V2 (110), V3 (010), V4 (011), V5 (001), V6 (101), and V7 (111), where V0 (000) and V7 (111) represent zero vectors. Therefore, it can be seen that V0 (000) indicates that the upper bridge arm of the three bridge arms is disconnected and the lower bridge arm is turned on, V1 (100) indicates that the first bridge arm is the upper bridge arm turned on and the lower bridge arm is turned off, and the next two bridge arms are the upper bridge arm turned off and the lower bridge arm turned on, and the subsequent states can be deduced in the same way.

[0050] When using the SVPWM algorithm, such as Figure 1 The schematic diagram of the two-level three-phase inverter is shown in the figure.

[0051] Assume that Ka, Kb, Kc, K ’ a. K ’ b. K ’ c represents the different switch states of the device, 1 represents on, 0 represents off, it can be seen that the above 8 switch states correspond to 8 different voltage vectors, and the phase voltage U AN , U BN , U CN The relationship with the switch side is

[0052]

[0053] The common mode voltage is the voltage between the neutral point of the permanent magnet synchronous motor and the reference ground. Figure 1 Medium V MN That is, the common mode voltage is expressed by the common mode voltage formula

[0054] And the phase voltage U on the AC side AN , U BN , U CN Relationship with the switch side

[0055]

[0056] The common-mode voltage corresponding to different switch states can be obtained, as shown in Table 1 below.

[0057]

[0058]

[0059] Table 1 shows the common-mode voltage corresponding to different switch states.

[0060] 3. The traditional permanent magnet synchronous motor vector control system generally uses space vector pulse width modulation (SVPWM) for modulation. The common mode voltage amplitude is ±Udc / 2 under the action of zero vector, which is relatively large. When the non-zero voltage vector is in effect, the common mode voltage amplitude is ±Udc / 6, which is relatively small. The common mode voltage amplitude changes 6 times in one pulse width modulation cycle, with a large frequency of change. Each change amplitude is ±Udc / 3. Therefore, the common mode voltage can be suppressed by avoiding the use of zero vector. Therefore, a new voltage vector synthesis method based on the voltage synthesis method of space vector pulse width modulation (SVPWM) is proposed to reduce the common mode voltage.

[0061] Depend on Figure 2 From the schematic diagram of SVPWM voltage vector distribution shown in the figure, it can be seen that the eight basic space voltage vectors divide the a-β two-phase stationary coordinate plane into six sectors. The principle of SVPWM implementation is to achieve the approximation from hexagonal to circular rotating voltage through the combination of six non-zero vectors and two zero vectors. Taking sector 1 in the figure as an example, its voltage Us can be synthesized by space vectors V1, V2, and V0.

[0062] As can be seen from Table 1, when the common-mode voltages corresponding to different switch states are substituted into the SVPWM modulation algorithm, the common-mode voltage cannot be eliminated. Therefore, the present invention provides an embodiment, a common-mode voltage suppression method, which is a new voltage vector synthesis method for reducing the common-mode voltage: by creating 9 virtual voltage vectors on the original voltage vector to reduce the common-mode voltage. Assuming that any virtual voltage vector is V XY , which is represented by the voltage vector V X With V Y Synthesis, that is So the virtual voltage vector V 12 =1 / 2(V1+V2), from which we can get the virtual voltage vector V 12 、V 23 、V 34 、V 45 、V 56 、V 61 、V14 、V 25 、V 36 , where V 14 、V 25 、V 36 is the zero vector, whose magnitude and angle are as follows Figure 3 shown.

[0063] The “original voltage vector” refers to the voltage vector realized by the different switching states of the inverter. Figure 2 The six voltage vectors V1-V6 shown are of the same magnitude but different directions;

[0064] Depend on It can be seen that V 12 For example, it is composed of V1 and V2. The common mode voltage of V1 is -Udc / 6, and the common mode voltage of V2 is Udc / 6, so V 12 The common mode voltage includes both Udc / 6 and -Udc / 6, which are its instantaneous values, and its average value is:

[0065] U AV_12 =(U AV_1 +U AV_2 ) / 2 = (-Udc / 6 + Udc / 6) / 2 = 0;

[0066] "This" means that the common mode voltage of V12 mentioned above includes both Udc / 6 and -Udc / 6, that is, the instantaneous value of V12 includes Udc / 6 and -Udc / 6;

[0067] like Figure 1 As shown, Udc is the bus voltage, which is the amplitude of the synthesized V12.

[0068] From the above, we can see that V 12 The average common mode voltage is 0, because the common mode voltages of V1 and V2 are opposite in magnitude, but they have the same proportion when forming the V12 vector, so other virtual vectors and their average common mode voltages can be derived in a similar way. "Others" specifically represent the synthesized virtual voltage vectors such as V23, V34, V45, V56, etc.; as shown in Table 2:

[0069] Table 2

[0070]

[0071] Depend on Figure 3 It can be seen that the virtual vector V 12 、V 23 、V 34 、V 45 、V 56 、V 61 The angles are 30°, 90°, 150°, 210°, 270°, and 330°, and the sizes are V 14 、V 25 、V 36 are zero vectors. Figure 4 , the newly synthesized 9 virtual vectors also divide the a-β two-phase stationary coordinate system plane into six sectors. Therefore, the implementation of SVPWM can achieve the approximation from hexagonal to circular rotating voltage through the combination of six non-zero virtual vectors and three zero virtual vectors, that is, first determine the sector where the required voltage vector is located, and then synthesize it with its three nearest virtual voltage vectors. "The required voltage vector" specifically refers to the voltage vectors of various amplitudes and angles required during motor control. The control system needs the voltage vector of this angle and amplitude, and controls the output of the voltage vector of this angle and amplitude. "Its" refers to the "required voltage vector". "Nearest" means to use the virtual vector of the sector boundary when determining which sector the required voltage vector is in (the newly synthesized virtual voltage vector divides the plane into six sectors). For example, if the required voltage vector amplitude is an arbitrary number and the angle is 45 degrees, then the required voltage vector is in Figure 3 Sector II in the equation is composed of V12, V23 and zero vector V25. "a-β two-phase stationary coordinate plane": can be understood as a rectangular coordinate system with the α axis and Figure 3 The V1 in the figure coincides, and the β axis is 90° counterclockwise rotated by the α axis. For the "a-β two-phase stationary coordinate plane": the α-β coordinate system is to create a coordinate system that converts the three-phase signal into a two-phase signal, making many calculations more intuitive and simple.

[0072] The combination of six non-zero virtual vectors and three zero virtual vectors can realize the change of rotating voltage from hexagon to circle: through vector operation, there are now six voltage vectors of the same size and different directions, and a zero voltage vector. Through vector synthesis, voltage vectors of various sizes and directions can be formed on this coordinate plane. The voltage vector with the largest amplitude forms a similar circle. According to the SVPWM algorithm principle, the six basic voltage vectors are formed by different switching states. Due to the dead time of the switch, the circle can only be achieved as much as possible. The required voltage vector is synthesized by the generated virtual voltage vector to reduce the common mode voltage. The step flow is: the sector where the required voltage vector is located-select the nearest three virtual voltage vectors for synthesis-thereby reducing the high common mode voltage output by the inverter drive system.

[0073] The present invention proposes a novel voltage vector synthesis method to reduce the common mode voltage: the common mode voltage is reduced by creating nine virtual voltage vectors on the original voltage vector. Assuming that any virtual voltage vector is V XY , which is represented by the voltage vector V X With VY Synthesis, that is Therefore, the virtual voltage vector V12 = 1 / 2 (V1 + V2), from which we can get the virtual voltage vector V 12 、V 23 、V 34 、V 45 、V 56 、V 61 、V 14 、V 25 、V 36 , where V 14 、V 25 、V 36 The 9 newly synthesized virtual vectors also divide the a-β two-phase stationary coordinate plane into six sectors. Therefore, the implementation of SVPWM can achieve the approximation from hexagonal to circular rotating voltage through the combination of six non-zero virtual vectors and three zero virtual vectors, that is, first determine the sector where the required voltage vector is located, and then synthesize it with its three nearest virtual voltage vectors. This can reduce the problem of the inverter drive system outputting a higher common mode voltage when using the SVPWM algorithm, thereby shortening the service life of the motor.

[0074] The present invention provides another embodiment, a common mode voltage suppression device, the device comprising:

[0075] An acquisition module, used for acquiring nine virtual voltage vectors;

[0076] A sector determination module, used for dividing the a-β two-phase stationary coordinate system plane into six sectors according to the voltage vector acquired by the acquisition unit;

[0077] The vector combination module is used for combining six non-zero virtual vectors and three zero virtual vectors to realize the approximation of the rotating voltage from hexagon to circle.

[0078] The vector combination module includes a sector determination unit and a synthesis unit;

[0079] The sector determination unit is used to determine the sector where the required voltage vector is located;

[0080] The synthesis unit is used to synthesize the nearest three virtual voltage vector sectors.

[0081] Based on the above common mode voltage suppression method, the present invention provides another processor.

[0082] The memory, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions corresponding to the common-mode voltage suppression method in the embodiment of the present invention. The processor executes various functional applications and data processing of the vehicle by running the software programs, instructions and modules stored in the memory, that is, implementing the above-mentioned common-mode voltage suppression method.

[0083] The memory may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices.

[0084] The present invention also provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, a common-mode voltage suppression method is implemented. The common-mode voltage suppression method includes:

[0085] The nine newly synthesized virtual vectors divide the a-β two-phase stationary coordinate system plane into six sectors; the approximation from hexagonal to circular rotating voltage is achieved through the combination of six non-zero virtual vectors and three zero virtual vectors, and the sector where the required voltage vector is located is judged and synthesized by its three nearest virtual voltage vectors, thereby reducing the higher common-mode voltage output by the inverter drive system.

[0086] The computer-readable storage medium provided by the present invention has computer-executable instructions that are not limited to the method operations described above, but can also execute related operations in the common-mode voltage suppression method provided by any embodiment of the present invention.

[0087] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0088] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (for example, coaxial cable, optical fiber, digital subscriber line DSL) or wireless (for example, infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid-state hard disk SolidState Disk, SSD), etc.

[0089] The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any modification, equivalent replacement and improvement made by any person skilled in the art within the technical scope disclosed by the present invention and within the spirit and principle of the present invention shall be covered within the protection scope of the present invention. At the same time, the contents not described in detail in this specification belong to the prior art known to those skilled in the art.

Claims

1. A common mode voltage suppression method, characterized in that: Nine virtual voltage vectors are created on the original voltage vector to reduce the common-mode voltage; assuming that any virtual voltage vector is V XY , V XY The voltage vector V X With V Y Synthesis, that is Virtual voltage vector V 12 =1 / 2(V1+V2), and the virtual voltage vector V is obtained. 12 、V 23 、V 34 、V 45 、V 56 、V 61 、V 14 、V 25 、V 36 , where V 14 、V 25 、V 36 is the zero vector, and the nine newly synthesized virtual vectors divide the a-β two-phase stationary coordinate system plane into six sectors; The approach from hexagonal to circular rotating voltage is achieved through the combination of six non-zero virtual vectors and three zero virtual vectors. The sector where the required voltage vector is located is determined and synthesized by its three nearest virtual voltage vectors, thereby reducing the higher common-mode voltage output by the inverter drive system.

2. A common mode voltage suppression method according to claim 1, characterized in that: V 12 Composed of V1 and V2, the common mode voltage of V1 is -U dc / 6, the common mode voltage of V2 is U dc / 6, V 12 The common mode voltage also includes U dc / 6 and -U dc / 6, this is V 12 The instantaneous value, V 12 The average value is: IN AV_12 =(U AV_1 +U AN_2 ) / 2=(-U dc / 6+U dc / 6) / 2=0; V 12 The average common-mode voltage is 0.

3. A common mode voltage suppression method according to claim 2, characterized in that: V 12 The common-mode voltage is opposite in magnitude, forming V 12 The proportions of the vectors are the same, and the remaining virtual vectors and the average common-mode voltages are derived in a similar way, and the average common-mode voltages of the remaining virtual vectors are all 0.

4. A common mode voltage suppression method according to claim 2, characterized in that: Virtual Vector V 12 、V 23 、V 34 、V 45 、V 56 、V 61 The angles are 30°, 90°, 150°, 210°, 270°, 330°, V 14 、V 25 、V 36 are all zero vectors.

5. A common mode voltage suppression method according to claim 4, characterized in that: Virtual Vector V 12 、V 23 、V 34 、V 45 、V 56 、V 61 The size of 6. A common mode voltage suppression device, characterized in that: The device comprises: An acquisition module, used for acquiring nine virtual voltage vectors; A sector determination module, used for dividing the a-β two-phase stationary coordinate system plane into six sectors according to the voltage vector acquired by the acquisition unit; The vector combination module is used for combining six non-zero virtual vectors and three zero virtual vectors to realize the approximation of the rotating voltage from hexagon to circle.

7. The common mode voltage suppression device according to claim 6, characterized in that: The vector combination module includes a sector determination unit and a synthesis unit; The sector determination unit is used to determine the sector where the required voltage vector is located; The synthesis unit is used for synthesizing the three nearest virtual voltage vector sectors.

8. A processor, characterized in that: The processor is used to run a program, wherein the program executes the common mode voltage suppression method according to any one of claims 1 to 5 when running.

9. A storage medium, characterized in that: The storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the common mode voltage suppression method according to any one of claims 1 to 5.

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