Boost power supply circuit, power amplification device, and signal processing system

Abstract

The embodiment of the invention provides a boost power supply circuit, a power amplification device and a signal processing system. The boost power supply circuit comprises: a detection circuit for detecting an input signal of an output stage circuit of a power amplifier; the power supply circuit is used for converting power supply input voltage into power supply output voltage, and the power supply output voltage is used for supplying power to the output stage circuit; the control circuit is used for determining a truncation margin according to the amplitude difference between the amplitude upper limit of the input signal and the power supply output voltage, and determining a boost amplitude inversely related to the truncation margin and a switch clock frequency inversely related to the truncation margin; and controlling the power supply circuit according to the boost amplitude and the switching clock frequency. According to the scheme of each embodiment of the invention, the power efficiency and the driving capability of the boost power supply circuit are considered.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of electronic circuits, and in particular to a boost power supply circuit, a power amplifier device, and a signal processing system. Background Art

[0002] In order to increase the output power of a power amplifier, a boost power supply circuit such as a DC conversion circuit is often used to boost the power input voltage from a power supply and then supply power to the output stage circuit of the power amplifier.

[0003] The larger output power of the power amplifier requires the boost power supply circuit to have a greater driving capability, which results in the boost power supply circuit requiring a larger switch size or a higher switching clock frequency. As the boost power supply circuit is a switching circuit, the increase in area size or frequency will undoubtedly cause more switching losses, increase the dynamic current of the boost power supply circuit, thereby increasing the overall current of the power amplifier and affecting the overall efficiency of the power amplifier.

[0004] That is to say, when the driving capability provided by the power amplifier is large enough relative to the driving capability required by the current signal, the excess driving capability will only cause unnecessary power loss, and the power efficiency of the boost power supply circuit is poor, and it is impossible to take into account both the power efficiency and driving capability of the boost power supply circuit. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a boost power supply circuit, a power amplifier device, and a signal processing system to solve the above problems.

[0006] According to a first aspect of an embodiment of the present invention, a boost power supply circuit is provided, comprising: a detection circuit, detecting an input signal of an output stage circuit of a power amplifier; a power supply circuit, converting a power supply input voltage into a power supply output voltage, wherein the power supply output voltage is used to power the output stage circuit; a control circuit, determining a truncation margin according to an amplitude difference between an amplitude upper limit of the input signal and an amplitude of the power supply output voltage, determining a boost amplitude that is inversely correlated with the truncation margin and a switching clock frequency that is inversely correlated with the truncation margin, and controlling the power supply circuit according to the boost amplitude and the switching clock frequency.

[0007] According to a second aspect of an embodiment of the present invention, there is provided a power amplification device, comprising: the boost power supply circuit according to the first aspect, and a power amplifier.

[0008] According to a third aspect of an embodiment of the present invention, there is provided a signal processing system, comprising: a signal processing device; a speaker; and a power amplification device according to the second aspect, wherein the power amplifier is connected between the signal processing device and the speaker.

[0009] In the scheme of the embodiment of the present invention, the control circuit can determine the truncation margin according to the amplitude difference between the upper limit of the amplitude of the input signal and the power supply output voltage, and determine the boost amplitude that is inversely correlated with the truncation margin and the switching clock frequency that is inversely correlated with the truncation margin. In other words, a certain truncation margin avoids the distortion of the input signal. When the upper limit of the amplitude of the input signal is small, the truncation margin is large. Accordingly, the switching clock frequency of the power supply circuit is small and the boost amplitude is small. Therefore, the switching loss of the power supply circuit is small, and the power efficiency of the boost power supply circuit is improved. When the upper limit of the amplitude of the input signal is large, the truncation margin is small. Accordingly, the switching clock frequency of the power supply circuit is large and the boost amplitude is large. Therefore, the driving ability of the boost power supply circuit is improved, thereby taking into account both the power efficiency and the driving ability of the boost power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0011] Figure 1 A schematic structural diagram of a signal processing system applicable to some embodiments of the present invention.

[0012] Figure 2 It is a structural block diagram of a boost power supply circuit according to some embodiments of the present invention.

[0013] Figure 3 for Figure 2 A structural block diagram of a further example of an embodiment of the present invention.

[0014] Figure 4 and Figure 5 Shows Figure 2 The relationship between the power supply input voltage and the upper amplitude limit threshold of the embodiment.

[0015] Figure 6 Shows Figure 2 Schematic circuit diagrams of detection circuits of some examples of embodiments.

[0016] Fig. 7A and Figure 7B Shows Figure 2 A schematic circuit diagram of a voltage generating circuit of an embodiment.

[0017] Figure 7C Shows Figure 2 Quantitative relationship of a circuit physical model of a voltage generating circuit of an embodiment.

[0018] Fig.7D Shows Figure 2 Schematic circuit diagrams of detection circuits of other examples of embodiments.

[0019] [AW20230150ICN1][HS2410483CCN] DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0021] The specific implementation of the embodiment of the present invention is further described below in conjunction with the accompanying drawings of the embodiment of the present invention.

[0022] Figure 1 The signal processing system 100 of some embodiments of the present invention is shown. The signal processing system 100 includes a signal processing device 110, a power amplifier 120 and a speaker 130. The signal processing system 100 can be configured in an electronic device, specifically, the electronic device can be a portable device such as a mobile phone, an MP3 player, an iPod, etc. carrying the signal processing system 100.

[0023] For example, the signal processing device 110 can monitor a voltage signal such as an audio signal, perform signal processing according to the monitored signal voltage signal, and output the processed signal (e.g., a mixed song signal) to the power amplifier 120. The signal processing device 110 can be configured as a processor such as a digital signal processor (DSP), an application processor (AP), or a digital circuit such as an FPGA or an ASIC.

[0024] The power amplifier 120 amplifies the signal amplitude based on the power amplification gain to obtain an output signal, and inputs the output signal to the speaker 130. Furthermore, the speaker 130 converts the electrical energy of the output signal into mechanical energy through its own coil and diaphragm based on the principle of electromagnetic induction, so that it can be heard by human ears.

[0025] Furthermore, the boost power supply circuit 140 obtains a power supply output voltage after a boost conversion from the power supply input voltage and provides it to the power amplifier 120 (for example, an output stage circuit). The driving capability of the boost power supply circuit 140 is positively correlated with the dynamic current of the boost power supply circuit 140 during operation. For a signal of a certain size, an excessive driving capability will not be used to drive the signal, but will lead to a larger dynamic current, which will cause power loss of the boost power supply circuit 140. Therefore, the technical solutions provided by various embodiments of the present invention can take into account both the power efficiency and driving capability of the boost power supply circuit.

[0026] Figure 2 A boost power supply circuit 300 according to some embodiments of the present invention is shown. Figure 2 Boost power supply

[0027] [AW20230150ICN1][HS2410483CCN] The circuit 300 includes a detection circuit 310 , a control circuit 320 , and a power supply circuit 340 .

[0028] Specifically, the detection circuit 310 is electrically connected between the power amplifier and the control circuit 320, and is used to detect the input signal of the output stage circuit of the power amplifier. The power supply circuit 340 converts the power supply input voltage into the power supply output voltage, and the power supply output voltage is used to power the output stage circuit.

[0029] It should be understood that the input signal can be an input signal or an analog signal in other forms. The detection performed by the detection circuit on the input signal can be an amplitude detection based on parameters such as voltage and / or current, that is, the detection current performs amplitude detection on the input signal. That is, the change in signal amplitude can represent the signal change before and after the gain processing of the signal.

[0030] In addition, the control circuit 320 is electrically connected to the power supply circuit 340, and the control circuit 320 is used to determine the truncation margin according to the amplitude difference between the upper limit of the amplitude of the input signal and the amplitude of the power supply output voltage, determine the boost amplitude that is inversely correlated with the truncation margin and the switching clock frequency that is inversely correlated with the truncation margin, and control the power supply circuit according to the boost amplitude and the switching clock frequency.

[0031] It should be understood that a certain truncation margin avoids signal distortion, and the truncation margin changes with the change of the upper limit of the amplitude of the input signal. For example, the upper limit of the amplitude of the input signal increases, and the truncation margin will decrease accordingly. Further, the control circuit 320 directly uses the boost amplitude to control the power supply circuit 340. The boost power supply circuit 300 may also include a clock circuit 330, and the control circuit 320 may be electrically connected to the clock circuit 330, and the clock circuit 330 is controlled by the switching clock frequency, and the clock circuit 330 uses the switching clock frequency to control the power supply circuit 340. For example, the control circuit 320 can determine the boost amplitude and the switching clock frequency through fitting functions such as linear fitting and nonlinear fitting. In a further example, the fitting function can be a piecewise function, and the corresponding relationship between the function of each segment in the piecewise function and the function value can be implemented using a data table, as described in the following embodiments.

[0032] In addition, the power supply circuit 340 is electrically connected to the input stage circuit of the power amplifier, converts the power supply input voltage into the power supply output voltage, and supplies power to the output stage circuit. For example, the power supply circuit 340 can be implemented as a DC conversion circuit (i.e., a DC-DC circuit) such as a boost circuit, in which a switching device such as a transistor or a MOS tube is provided, and the boost operation of the boost power supply unit is performed by the switching operation of each switching device. For example, the power supply circuit 340 determines the dynamic duty cycle according to the boost amplitude, and performs the boost conversion according to the action duty cycle.

[0033] In the scheme of the embodiment of the present invention, the control circuit can determine the truncation margin according to the amplitude difference between the upper limit of the amplitude of the input signal and the power supply output voltage, and determine the boost amplitude that is inversely correlated with the truncation margin and the switching clock frequency that is inversely correlated with the truncation margin. In other words, a certain truncation margin avoids the distortion of the input signal. When the upper limit of the amplitude of the input signal is small, the truncation margin is large. Accordingly, the switching clock frequency of the power supply circuit is small and the boost amplitude is small. Therefore, the switching loss of the power supply circuit is small, and the power efficiency of the boost power supply circuit is improved. When the upper limit of the amplitude of the input signal is large, the truncation margin is small. Accordingly, the switching clock frequency of the power supply circuit is large and the boost amplitude is large. Therefore, the driving ability of the boost power supply circuit is improved, thereby taking into account both the power efficiency and the driving ability of the boost power supply circuit.

[0034] In some further embodiments, Figure 3As shown, the power amplifier 30 includes a preamplifier stage circuit such as a first-stage amplifier circuit 31 and a second-stage amplifier circuit 32, and an output stage circuit 33. The first-stage amplifier circuit 31 includes a positive input terminal IN+ and an inverting input terminal IN-. The power supply input voltage VDD is electrically connected to the preamplifier stage circuit such as the first-stage amplifier circuit 31 and the second-stage amplifier circuit 32, so that the power supply input voltage VDD is used to power each stage of the amplifier circuit, and the power supply input voltage VDD can also be provided to the voltage generating circuit 350. The power supply input voltage VDD is processed by the boost power supply circuit 300 to obtain the power supply output voltage PVDD, which is provided to the output stage circuit 33.

[0035] The detection circuit 310 can receive the non-phase output terminal VOP1 and the inverting output terminal VON1 of any amplifier circuit (eg, the first amplifier circuit 31 ) among the amplifier circuits of each stage.

[0036] In some other embodiments, the detection circuit 310 is further used to: obtain an upper amplitude threshold value that is positively correlated with the power supply input voltage, and determine an upper amplitude threshold value that is greater than the upper amplitude value by comparing the upper amplitude value of the input signal with the upper amplitude threshold value. The control circuit 320 is specifically used to: determine the amplitude difference between the upper limit of the current hysteresis interval and the power supply output voltage as the truncation margin corresponding to the power supply input voltage.

[0037] Since the upper amplitude threshold of the input signal is positively correlated with the power supply input voltage, for a given power supply output voltage, the larger the power supply input voltage, the larger the upper amplitude threshold, and the smaller the truncation margin between the power supply output voltage, thereby improving the power efficiency of the boost power supply circuit.

[0038] Some embodiments of the present invention can meet the output signal power requirements while taking into account the efficiency under small signal conditions. That is, when the input signal is small, the boost power supply circuit operates at a lower frequency, and as the input signal increases, the switching clock frequency of the boost power supply circuit is increased, thereby improving the load driving capability of the boost power supply circuit. In addition, some embodiments of the present invention can make the power supply output voltage PVDD close to the signal value without distorting the input signal, and the switching clock frequency of the boost power supply circuit with multiple gears can be set according to the amplitude of the input signal.

[0039] In addition, the power supply output voltage is directly related to the power supply input voltage provided by the battery. As the battery power decreases, the power supply input voltage gradually decreases, and the corresponding load driving capability will also decrease accordingly. Therefore, some embodiments of the present invention can meet the normal operation of the battery in all power ranges. That is, when a lower power supply input voltage is required, the corresponding load driving capability can meet the output power requirement, and when a higher power supply input voltage is required, the corresponding efficiency can be optimized.

[0040] In some embodiments, the larger the power supply input voltage, the larger the power supply output voltage, which improves the driving capability of the boost power supply circuit. Compared with a given power supply output voltage, the truncation margin between the power supply output voltage increases, thereby reducing the switching clock frequency of the power supply circuit and improving the power efficiency of the boost power supply circuit.

[0041] That is to say, when the amplitude of the input signal is small, the proportion of the truncation margin to the power supply output voltage is large, and a larger switching clock frequency can be obtained by reducing the truncation margin to improve the driving ability of the boost power supply circuit. When the amplitude of the input signal is large, the proportion of the truncation margin to the power supply output voltage is relatively small, and the driving ability of the boost power supply circuit can also be improved by increasing the power supply output voltage.

[0042] In addition, when the power supply input voltage is small, the power supply output voltage is also small, and the truncation margin can be fully utilized by reducing the upper amplitude threshold, thereby improving the power efficiency of the boost power supply circuit. When the power supply input voltage is large, the power supply output voltage is also large, and the proportion of the truncation margin to the power supply output voltage is small, so a smaller switching clock frequency can be used to improve the power efficiency of the boost power supply circuit.

[0043] like Figure 4 As shown, when the power supply input voltage VDD is small (for example, the power supply input voltage can be VDD_min, which is the lowest operating voltage of the system when the battery is low), when the input signal is less than the upper amplitude threshold Vth, the switching clock frequency is Fsw_L, and there is a truncation margin Headroom1 between the input signal and the power supply output voltage PVDD; when the input signal is greater than the upper amplitude threshold Vth, the switching clock frequency is Fsw_H, and there is a truncation margin Headroom2 between the input signal and the power supply output voltage PVDD. It can be seen that the truncation margin Headroom1> the truncation margin Headroom2.

[0044] [AW20230150ICN1][HS2410483CCN]

[0045] like Figure 5As shown, when the power supply input voltage VDD is relatively large (for example, the power supply input voltage VDD_max is the highest operating voltage of the system when the battery is at a high level), the ordinate of point b represents the upper amplitude threshold value Vth. When the input signal is less than the upper amplitude threshold value Vth, the switching clock frequency is Fsw_L, and there is a truncation margin Headroom1 between the input signal and the power supply output voltage PVDD; when the input signal is greater than the upper amplitude threshold value Vth, the switching clock frequency is Fsw_H, and there is a truncation margin Headroom2 between the input signal and the power supply output voltage PVDD. It can be seen that the truncation margin Headroom1> the truncation margin Headroom2.

[0046] That is to say, Figure 4 In the example, the Headroom2 that will not distort the signal under this voltage can be calculated based on the architecture and on-resistance of the boost power supply circuit, and the frequency switching threshold Vth is designed in combination with the signal response speed. At this time, Vth is relatively low (as shown in point a in the figure). Figure 5 In the example, the driving capability of the boost power supply circuit is improved, and the new Headroom2 corresponding to the power supply input voltage can be calculated. It can be seen that the boost power supply circuit can drive a larger signal at the same switching clock frequency, and Vth is increased to point b in the figure. Therefore, the boost power supply circuit can switch the frequency at a larger signal, which can improve the efficiency of the signal between point a and point b. That is, the amplitude upper limit threshold of the boost power supply circuit changes synchronously with the power supply input voltage, so that the most suitable amplitude upper limit threshold can be obtained under different battery power levels, thereby maximizing chip efficiency.

[0047] In some embodiments, the boost power supply circuit 300 further includes a voltage generating circuit 350. The voltage generating circuit 350 generates an upper amplitude threshold value that is positively correlated with the power supply input voltage. Figure 6 As shown, the voltage generating circuit 350 can generate upper and lower thresholds of a plurality of hysteresis intervals and provide them to the detecting circuit 310. The detecting circuit 310 determines the hysteresis interval corresponding to the input signal and outputs a signal Po indicating the corresponding hysteresis interval.

[0048] Further, the detection circuit 310 is specifically used to: determine whether the input signal is within the current hysteresis interval among the multiple hysteresis intervals, the power supply input voltage corresponding to each hysteresis interval is less than the power supply input voltage corresponding to the next hysteresis interval, and the power supply input voltage corresponding to each hysteresis interval is greater than the power supply input voltage corresponding to the previous hysteresis interval; if yes, the upper limit of the current hysteresis interval is determined as the amplitude upper limit threshold. It should be understood that multiple hysteresis intervals are conducive to improving the judgment accuracy of the input signal, obtaining the accuracy of the truncation margin, and thus improving the switching accuracy of the switching clock frequency.

[0049] Further, the upper threshold of each hysteresis interval is less than the upper threshold of the next hysteresis interval, the lower threshold of each hysteresis interval is less than the lower threshold of the next hysteresis interval, the upper threshold of each hysteresis interval is greater than the upper threshold of the previous hysteresis interval, and the lower threshold of each hysteresis interval is greater than the lower threshold of the previous hysteresis interval. In other words, the upper threshold and the lower threshold of the hysteresis interval where the input signal is located are both positively correlated with the power supply input voltage, and the switching clock frequency is also positively correlated with the power supply input voltage, which greatly takes into account the power efficiency and driving capability of the boost power supply circuit. It should be understood that the previous hysteresis interval and the next hysteresis interval of the current hysteresis interval are adjacent hysteresis intervals of the current hysteresis interval. When the input signal is not in the current hysteresis interval, the adjacent hysteresis interval can accurately determine the hysteresis interval where the input signal is located.

[0050] Further, if the peak value and valley value of the input signal are respectively less than the upper threshold value and the lower threshold value of the current hysteresis interval, the control circuit controls the voltage generating circuit, and after recording the current hysteresis interval, updates the previous hysteresis interval to the current hysteresis interval, and when the peak value of the input signal is greater than the upper threshold value of the current hysteresis interval or the valley value of the input signal is greater than the lower threshold value of the current hysteresis interval, the control circuit determines the recorded hysteresis interval as the hysteresis interval where the input signal is located. If the peak value and valley value of the input signal are respectively greater than the upper threshold value and the lower threshold value of the current hysteresis interval, the control circuit controls the voltage generating circuit to update the next hysteresis interval to the current hysteresis interval. It should be understood that by comparing the peak value and valley value of the input signal with the upper threshold value and the lower threshold value of the hysteresis interval, it is possible to reliably determine whether the input signal belongs to a hysteresis interval. In addition, when the input signal is not in the current hysteresis interval, the hysteresis interval where the input signal is located can be accurately determined by the adjacent hysteresis interval, so as to perform switching of the switching clock frequency according to the truncation margin corresponding to the upper threshold value of different hysteresis intervals.

[0051] In some examples, such as Figure 6 As shown, the detection circuit 310 includes a first comparator (COMP1) 311, a second comparator (COMP2) 312 and a first logic circuit 313.

[0052] Specifically, the input signal is a differential signal output by a preamplifier stage circuit of the power amplifier, the positive phase output terminal of the preamplifier stage circuit outputs a positive phase signal of the differential signal, and the negative phase output terminal outputs a negative phase signal of the differential signal. The preamplifier stage circuit may include a first stage amplifier circuit, or both a first stage amplifier circuit and a second stage amplifier circuit.

[0053] The first output terminal of the first comparator 311 is connected to the positive phase output terminal VOP1 of the input signal, and the second output terminal of the first comparator 311 receives the first hysteresis threshold. The first output terminal of the second comparator 312 is connected to the negative phase output terminal VON1 of the input signal, and the second output terminal of the second comparator 312 receives the second hysteresis threshold. The output terminal of the first comparator 311 and the output terminal of the second comparator 312 are both connected to the input terminal of the first logic circuit 313, and the indication signal Po of the judgment result between the first comparison result and the second comparison result is output from the output terminal of the first logic circuit 313, and the indication signal Po is used to indicate whether the input signal is in the current hysteresis interval. For example, when the positive phase signal meets the first hysteresis threshold and the negative phase signal meets the second hysteresis threshold, the indication signal indicates that the input signal is in the current hysteresis interval. It should be understood that the second output terminal of the first comparator receives the first hysteresis threshold, and the second output terminal of the second comparator receives the second hysteresis threshold. In other words, only when the peak value and the valley value of the input signal are respectively less than the upper limit threshold and the lower limit threshold of the current hysteresis interval, the indication signal Po indicates that the hysteresis interval is an alternative hysteresis interval. When the current hysteresis interval is not an alternative hysteresis interval, the next hysteresis interval is updated as the current hysteresis interval to determine whether the hysteresis interval with a threshold greater than the current hysteresis interval is an alternative hysteresis interval. When the current hysteresis interval is an alternative hysteresis interval, the hysteresis interval with the minimum threshold is determined by updating the previous hysteresis interval as the current hysteresis interval.

[0054] In some examples, multiple hysteresis intervals correspond to a detection circuit. When the detection circuit updates the previous hysteresis interval to the current hysteresis interval, or when the detection circuit updates the next hysteresis interval to the current hysteresis interval, the control circuit can control the voltage generating circuit to update the current hysteresis interval. Through the dynamic upper and lower thresholds, the first comparator and the second comparator can be reused for different hysteresis intervals to determine the hysteresis interval in which the input signal is located.

[0055] Alternatively, in some other examples, multiple hysteresis intervals correspond to multiple detection circuits, respectively, and each detection circuit can output an indication signal Po of the judgment result to the control circuit according to the hysteresis interval corresponding to the detection circuit. The control circuit can determine the hysteresis interval where the input signal is located by comparing the various judgment results, and determine the amplitude difference between the upper limit of the hysteresis interval where the input signal is located and the power supply output voltage as the truncation margin corresponding to the power supply input voltage. Specifically, if the detection circuit corresponding to a hysteresis interval detects that the peak value and valley value of the input signal are respectively less than the upper threshold value and the lower threshold value of the hysteresis interval, and the detection circuit corresponding to the previous hysteresis interval of the hysteresis interval detects that the peak value of the input signal is greater than the upper threshold value of the previous hysteresis interval or the valley value of the input signal is greater than the lower threshold value of the previous hysteresis interval, then a hysteresis interval is the hysteresis interval where the input signal is located. Without loss of generality, the hysteresis interval with the smallest threshold value in the candidate hysteresis interval among the various judgment results output by the multiple detection circuits corresponding to the multiple hysteresis intervals.

[0056] Alternatively, as some examples of determining whether the amplitude of the input signal is within the current hysteresis interval, Fig.7D As shown, the detection circuit includes an analog-to-digital conversion circuit 315 and a second logic circuit 314. The analog-to-digital conversion circuit 315 can be an analog-to-digital converter (ADC). The second logic circuit 314 can be a digital circuit for performing digital operations. The positive input terminal of the analog-to-digital conversion circuit 315 is connected to the positive output terminal of the input signal, the negative input terminal of the analog-to-digital conversion circuit 315 is connected to the negative output terminal of the input signal, the output terminal of the analog-to-digital conversion circuit 315 is connected to the input terminal of the second logic circuit 314, and the output terminal of the second logic circuit 314 is connected to the control circuit.

[0057] Specifically, the analog-to-digital conversion circuit 315 is used to convert the input signal into a digital signal, the input end of the logic circuit is also used to receive the characterization value of the current hysteresis interval, the logic circuit is used to compare the characterization value CODE_TTH / CODE_VTH_HYS of the current hysteresis interval with the characterization value CODE_Signal of the digital signal, and output an indication signal of the comparison result from the output end of the second logic circuit, the indication signal is used to indicate whether the amplitude of the input signal is in the current hysteresis interval. That is to say, if the digital signal and the characterization value are within the characterization value of the current hysteresis interval, the amplitude of the input signal is within the current hysteresis interval; if the digital signal and the characterization value are not within the characterization value of the current hysteresis interval, the amplitude of the input signal is not within the current hysteresis interval.

[0058] Furthermore, the voltage generation circuit 350 includes a voltage dividing circuit. The voltage dividing circuit includes N voltage dividing resistors connected in series. One end of the first voltage dividing resistor is connected to the bias low voltage, the other end of the nth voltage dividing resistor is connected to one end of the (n + 1)th voltage dividing resistor, and the other end of the Nth voltage dividing resistor is connected to the bias high voltage. A power supply input voltage VDD is formed between the bias high voltage and the bias low voltage. The nth voltage dividing resistor outputs an amplitude upper limit threshold, where 0 < n < N and n is an integer. It should be understood that through the N voltage dividing resistors in the voltage dividing circuit, (N - 1) series nodes can output amplitude upper limit thresholds with different positive correlation ratios to the power supply input voltage, so as to improve the driving ability of the boost power supply circuit by flexibly increasing the power supply input voltage.

[0059] As Fig. 7A shown, when the bias low voltage is the ground voltage, the bias high voltage is VDD. As VDD increases, the output power of the boost power supply circuit will gradually increase, so that at a lower voltage, the signal will not be clipped due to an excessive upper limit threshold, and at a higher voltage, the power efficiency will not be reduced due to a too small upper limit threshold. Correspondingly, the relationship between VDD and the upper limit threshold is Vth = Y(VDD), and the relationship between VDD and the lower limit threshold is Vth_HYS = Y(VDD) - b. Since the driving ability of the boost power supply circuit is positively correlated with the value of VDD, Vth is also a value positively correlated with VDD. Considering the circuit implementation complexity, it can be simply expressed as a linear relationship or a piecewise function relationship, and the threshold can be expressed in the form of k times VDD, i.e., Vth = k*VDD + b, where k is a positive number greater than 0, and b can be any constant or a variable related to VDD. As Fig. 7A shown, when b = 0, the sum of the resistances of the N voltage dividing resistors is R, the sum of the resistances from the (n + 1)th voltage dividing resistor to the Nth voltage dividing resistor is (1 - k)*R, and the sum of the resistances from the first voltage dividing resistor to the nth voltage dividing resistor is k*R.

[0060] Alternatively, as Figure 7B shown, Vth can be expressed as a piecewise function relationship, and the piecewise function relationship is as follows:

[0061] Vth = A1(0 < VDD < a1); A2(a1 < VDD < a2); An(an - 1 < VDD < an), where an represents the piecewise interval value of the power supply voltage VDD. The sum of the resistances of the N voltage dividing resistors is R, and the resistance of the nth voltage dividing resistor is ((an) - (an - 1))*R / VDD.

[0062] In some embodiments, the value of n is negatively correlated with the power supply input voltage. It should be understood that the amplitude upper limit threshold value with different positive correlation ratios with the power supply input voltage can be output through the nth series node. The larger the power supply input voltage, the smaller the value of n, and the smaller the switching clock frequency, thereby improving the power efficiency of the boost power supply circuit. In addition, the smaller the power supply input voltage, the larger the value of n, and the larger the switching clock frequency, thereby improving the driving capability of the boost power supply circuit.

[0063] Alternatively, in some other embodiments, the upper threshold and the lower threshold may be calculated based on a circuit physical model, such as Figure 7C As shown in the Headroom, the fluctuation range of the power supply output voltage caused by power losses such as conduction loss and switching loss of the boost power supply circuit can be characterized. Among them, the conduction loss can be characterized as the product of the total conduction impedance Rdson of the current generated after the output passes through the load and the power loss such as parasitic loss of the output driver tube, and the switching loss can be characterized as the amplitude of the power supply ripple caused by the repeated switching of the boost power supply circuit at a certain frequency, and the repeated charging and discharging of the power supply mounting capacitor through the output load and power supply charging.

[0064] Further, in Figure 7C In the coordinate system shown, the vertical axis represents the power supply output voltage, and the horizontal axis represents the phase of the input signal. After the switching clock frequency of the boost power supply circuit is switched, the power supply output voltage often does not change suddenly immediately. The power supply output voltage is related to the driving capability of the boost power supply circuit. After a certain boost time, it gradually stabilizes. The transition line from truncated headroom1 to truncated headroom2 represents the gradual change process of the truncated headroom after the switching clock frequency of the boost power supply circuit is switched, as shown in the following y1 expression:

[0065] [AW20230150ICN1][HS2410483CCN]

[0066] y1=(PVDD2-PVDD1) / Trise*x+PVDD1

[0067] Wherein Trise is the time required for the boost power supply circuit to stabilize the boost; x is the phase of the input signal.

[0068] In the process of increasing load current, in order to ensure that the output driving capability of the boost power supply circuit is sufficient to prevent truncation of the input signal, it is usually necessary to calculate the phase advance of the upper amplitude threshold according to the frequency and amplitude of the signal and the driving capability of the boost power supply circuit. The corresponding expression of the input signal y2 is as follows:

[0069] y2=Asin((x+a) / Tsin*2π)

[0070] Among them, x is the phase of the input signal; A is the peak value of the input sine wave; Tsin represents the period of the input signal, that is, 1 / Tsin represents the frequency of the input signal; a is the phase advance of the waveform; according to the intersection of a and the y-axis, the amplitude upper limit threshold of the boost power supply circuit can be obtained.

[0071] That is, for a given boost time Trise, signal frequency 1 / Tsin, truncation margin Headroom, and power supply input voltage VDD, a truncation threshold that prevents the input signal y2 from switching during the switching process of the power supply output voltage PVDD at the switching clock frequency can be calculated.

[0072] Thus far, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0073] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0074] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present application can take the form of one or more computer-usable storage media (including but not limited to disk storage,

[0075] [AW20230150ICN1][HS2410483CCN] is in the form of a computer program product implemented on CD-ROM, optical storage, etc.

[0076] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0077] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A boost power supply circuit, characterized in that: include: A detection circuit, detecting an input signal of an output stage circuit of the power amplifier; A power supply circuit converts a power supply input voltage into a power supply output voltage, wherein the power supply output voltage is used to supply power to the output stage circuit; A control circuit determines a truncation margin according to an amplitude difference between an upper amplitude limit of the input signal and an amplitude difference between the power supply output voltage, determines a boost amplitude inversely correlated with the truncation margin and a switching clock frequency inversely correlated with the truncation margin, and controls the power supply circuit according to the boost amplitude and the switching clock frequency.

2. The boost power supply circuit according to claim 1, characterized in that: The detection circuit is also used to: obtain an upper amplitude limit threshold value that is positively correlated with the power supply input voltage, and determine an upper amplitude limit threshold value that is greater than the upper amplitude limit by comparing the upper amplitude limit of the input signal with the upper amplitude limit threshold value.

3. The boost power supply circuit according to claim 2, characterized in that: The detection circuit is specifically used for: Determine whether the input signal is within a current hysteresis interval among a plurality of hysteresis intervals, the power supply input voltage corresponding to each hysteresis interval is less than the power supply input voltage corresponding to the next hysteresis interval, and the power supply input voltage corresponding to each hysteresis interval is greater than the power supply input voltage corresponding to the previous hysteresis interval; If yes, the control circuit determines the upper limit of the current hysteresis interval as the amplitude upper limit threshold.

4. The boost power supply circuit according to claim 3, characterized in that: The upper threshold of each hysteresis interval is less than the upper threshold of the next hysteresis interval, the lower threshold of each hysteresis interval is less than the lower threshold of the next hysteresis interval, the upper threshold of each hysteresis interval is greater than the upper threshold of the previous hysteresis interval, and the lower threshold of each hysteresis interval is greater than the lower threshold of the previous hysteresis interval.

5. The boost power supply circuit according to claim 4, characterized in that: The control circuit is also used for: If the peak value and the valley value of the input signal are respectively smaller than the upper threshold and the lower threshold of the current hysteresis interval, the current hysteresis interval is recorded as an alternative hysteresis interval, and the previous hysteresis interval is updated as the current hysteresis interval; If the peak value of the input signal is greater than the upper threshold of the current hysteresis interval or the valley value of the input signal is greater than the lower threshold of the current hysteresis interval, the upper limit of the recorded candidate hysteresis interval is determined as the amplitude upper limit threshold.

6. The boost power supply circuit according to claim 5, characterized in that: The control circuit is further configured to update the candidate hysteresis interval to the current hysteresis interval if the peak value and the valley value of the input signal are respectively smaller than the upper threshold and the lower threshold of the current hysteresis interval.

7. The boost power supply circuit according to claim 5, characterized in that: The control circuit is also used for: If the peak value and the valley value of the input signal are respectively greater than the upper threshold and the lower threshold of the current hysteresis interval, it is determined that the current hysteresis interval is not a candidate hysteresis interval, and the next hysteresis interval is updated to the current hysteresis interval.

8. The boost power supply circuit according to claim 5, characterized in that The input signal is a differential signal output by the preamplifier stage circuit of the power amplifier; The detection circuit includes a first comparator, a second comparator and a first logic circuit; The first output terminal of the first comparator is connected to the non-phase output terminal of the preamplifier stage circuit, the second output terminal of the first comparator receives a first hysteresis threshold, and outputs a first comparison result indicating whether the non-phase signal of the differential signal satisfies the first hysteresis threshold; The first output terminal of the second comparator is connected to the inverting output terminal of the preamplifier stage circuit. The second output terminal of the second comparator receives a second hysteresis threshold and outputs a second comparison result indicating whether the inverting signal of the differential signal satisfies the first hysteresis threshold. Wherein, the output terminals of the first comparator and the second comparator are both connected to the input terminal of the first logic circuit, and an indication signal of the judgment result between the first comparison result and the second comparison result is output from the output terminal of the first logic circuit. When the non-inverting signal satisfies the first hysteresis threshold and the inverting signal satisfies the second hysteresis threshold, the indication signal indicates that the input signal is within the current hysteresis interval.

9. The boost power supply circuit according to claim 5, characterized in that: The detection circuit includes an analog-to-digital conversion circuit and a second logic circuit. The non-inverting input terminal of the analog-to-digital conversion circuit is connected to the non-inverting output terminal of the input signal, the inverting input terminal of the analog-to-digital conversion circuit is connected to the inverting output terminal of the input signal, the output terminal of the analog-to-digital conversion circuit is connected to the input terminal of the second logic circuit, and the output terminal of the second logic circuit is connected to the control circuit. Wherein, the analog-to-digital conversion circuit is configured to convert the input signal into a digital signal. The input terminal of the second logic circuit is further configured to receive a characterization value of the current hysteresis interval. The second logic circuit is configured to compare the current hysteresis interval with the characterization value of the digital signal and output an indication signal of the comparison result from the output terminal of the second logic circuit. The indication signal is used to indicate whether the amplitude of the input signal is within the current hysteresis interval.

10. The boost power supply circuit according to claim 2, characterized in that: The boost power supply circuit further includes: a voltage generation circuit configured to generate an amplitude upper limit threshold that is positively correlated with the power supply input voltage.

11. The boost power supply circuit according to claim 10, characterized in that: The voltage generation circuit includes a voltage division circuit. The voltage division circuit includes N voltage division resistors connected in series. One end of the first voltage division resistor is connected to a bias low voltage, the other end of the nth voltage division resistor is connected to one end of the (n + 1)th voltage division resistor, and the other end of the Nth voltage division resistor is connected to a bias high voltage. The power supply input voltage is formed between the bias high voltage and the bias low voltage. Wherein, the nth voltage division resistor outputs the amplitude upper limit threshold, 0 < n < N, and n is an integer.

12. The boost power supply circuit according to claim 11, characterized in that: The value of n is negatively correlated with the power supply input voltage.

13. A power amplifier device, characterized in that: Comprising: The boost power supply circuit according to any one of claims 1-12, and a power amplifier.

14. A signal processing system, characterized in that: Comprising: A signal processing device; A speaker; The power amplification device according to claim 13, wherein the power amplifier is connected between the signal processing device and the speaker.

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