Amplifier circuit and analog closed-loop circuit

Abstract

The invention discloses an amplifier circuit and an analog closed-loop circuit. The amplifier circuit comprises an amplification unit, a first mirror image branch, a second mirror image branch, a pull-up switch, a pull-down switch and a control unit. The pull-up switch is configured to pull up the output voltage when closed. The pull-down switch is configured to pull down the output voltage when closed. And the control unit is configured to control the on-off of the pull-up switch and the pull-down switch according to the third reference voltage and the fourth reference voltage, so that the response speed of the off of the pull-up switch and the pull-down switch is higher than the response speed of the output voltage, and the response speed of the on of the pull-up switch and the pull-down switch is lower than the response speed of the output voltage. The response speed of closing the pull-up switch and the pull-down switch is lower than the response speed of the output voltage, and the response speed of disconnecting the pull-up switch and the pull-down switch is higher than the response speed of the output voltage, so that the pull-up switch and the pull-down switch can be ensured to be disconnected for a period of time when the amplification unit just recovers a steady state, and large signal oscillation is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of amplifiers, and more specifically, to an amplifier circuit and a switching power supply. Background Art

[0002] The slew rate (slew rate / SR) is one of the most important indicators of the amplifier. In most cases, it is limited by the charging and discharging speed of the amplifier to the capacitor. The capacitor that needs to be charged and discharged is determined by the specific external application scenario and cannot be changed. To optimize the amplifier slew rate, we generally try to increase the saturation pull-up and pull-down currents of the amplifier itself. The most direct way to increase the slew rate is to increase the static bias current of the op amp, but this will increase the static power consumption of the amplifier, so the slew rate enhancement technology has been developed.

[0003] In the related art, the slew rate enhancement effect of the amplifier is limited by the pull-up switch and the pull-down switch connected to the output end. When the input voltage difference detected by the amplifier is small, the pull-up switch and the pull-down switch connected to the output end are turned off. When the input voltage difference detected by the amplifier is large, the pull-up switch or the pull-down switch is turned on, and the corresponding feedback loop is started to increase the effective slew rate.

[0004] However, when the pull-up switch is turned on, the feedback loop increases the falling flip speed of the input signal. When the pull-up switch is just turned off, the input voltage difference detected by the amplifier triggers the pull-down switch to turn on, and large signal oscillation occurs in the loop. Summary of the invention

[0005] Embodiments of the present application provide an amplifier circuit and an analog closed-loop circuit.

[0006] The embodiment of the present application provides an amplifier circuit, including an amplifier unit, a first mirror branch, a second mirror branch, a pull-up switch, a pull-down switch and a control unit. The amplifier unit includes a first branch and a second branch, the first branch is configured to generate a first reference voltage according to a voltage difference between a first input voltage and a second input voltage, the second branch is configured to generate a second reference voltage according to a voltage difference between the first input voltage and the second input voltage, and the amplifier unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch is configured to generate a third reference voltage according to the first input voltage, the pull-up speed of the third reference voltage is higher than the pull-up speed of the first reference voltage, and the pull-down speed of the third reference voltage is lower than the pull-down speed of the first reference voltage. The second mirror branch is configured to generate a fourth reference voltage according to the second input voltage, the pull-up speed of the fourth reference voltage is higher than the pull-up speed of the second reference voltage, and the pull-down speed of the fourth reference voltage is lower than the pull-down speed of the second reference voltage. The pull-up switch is configured to pull up the output voltage when closed. The pull-down switch is configured to pull down the output voltage when closed. The control unit is configured to control the on and off of the pull-up switch and the pull-down switch according to the third reference voltage and the fourth reference voltage, so that the response speed of the pull-up switch and the pull-down switch being disconnected is higher than the response speed of the output voltage, and the response speed of the pull-up switch and the pull-down switch being closed is lower than the response speed of the output voltage.

[0007] In the amplifier circuit of the implementation mode of the present application, the response speed of closing the pull-up switch and the pull-down switch is lower than the response speed of the output voltage, while the response speed of opening the pull-up switch and the pull-down switch is higher than the response speed of the output voltage. This ensures that when the amplifying unit just returns to a steady state, the pull-up switch and the pull-down switch are disconnected for a period of time to avoid large signal oscillations in the main loop.

[0008] In some embodiments, the first branch is configured to generate a first current according to the first input voltage and a first reference voltage according to the first current, the second branch is configured to generate a second current according to the second input voltage and a second reference voltage according to the second current, and the amplification unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch is configured to copy the first current to obtain a first mirror current and provide a third reference voltage according to the first mirror current. The second mirror branch is configured to copy the second current to obtain a second mirror current and provide a fourth reference voltage according to the second mirror current.

[0009] In some embodiments, the output voltage is positively correlated with a voltage difference between the first input voltage and the second input voltage, and when the first input voltage is consistent with the second input voltage, the output voltage reaches a steady-state value.

[0010] In some embodiments, when the voltage difference is less than or equal to the dead zone voltage threshold, the control unit is configured to control the pull-up switch and the pull-down switch to be disconnected. When the voltage difference is greater than the dead zone voltage threshold, the control unit is configured to control the pull-up switch to be closed, or control the pull-down switch to be closed, so as to adjust the output voltage to the steady-state value.

[0011] In some embodiments, the dead zone voltage threshold is positively correlated with pull-up speeds of the third reference voltage and the fourth reference voltage, and the dead zone voltage threshold is negatively correlated with pull-down speeds of the third reference voltage and the fourth reference voltage.

[0012] In certain embodiments, when the voltage difference is greater than the dead zone voltage threshold and the first input voltage is higher than the second input voltage, the third reference voltage is lower than the first voltage threshold, and the control unit is configured to control the pull-down switch to be disconnected and the pull-up switch to be closed. When the voltage difference is greater than the dead zone voltage threshold and the first input voltage is lower than the second input voltage, the fourth reference voltage is lower than the second voltage threshold, and the control unit is configured to control the pull-up switch to be disconnected and the pull-down switch to be closed. When the voltage difference is less than or equal to the dead zone voltage threshold, the third reference voltage is higher than or equal to the first voltage threshold, and the fourth reference voltage is higher than or equal to the second voltage threshold, and the control unit is configured to control the pull-up switch and the pull-down switch to be disconnected.

[0013] In some embodiments, the first branch includes a first transistor and a second transistor, the voltage source of the amplifier circuit is grounded through the first transistor and the second transistor, the control electrode of the first transistor is configured to access the first input voltage, the current flowing through the first transistor and the second transistor is the first current, the first transistor and the second transistor are connected to a first node, and the voltage written to the first node is the first reference voltage. The first mirror branch includes a first mirror transistor and a second mirror transistor, the voltage source is grounded through the first mirror transistor and the second mirror transistor, the control electrode of the first mirror transistor is connected to the control electrode of the first transistor, the control electrode of the second mirror transistor is connected to the control electrode of the second transistor, the current flowing through the first mirror transistor and the second mirror transistor is the first mirror current, the first mirror transistor and the second mirror transistor are connected to a third node, and the voltage written to the third node is the third reference voltage. The width-to-length ratio of the first mirror transistor is greater than that of the first transistor, and the width-to-length ratio of the second mirror transistor is less than that of the second transistor.

[0014] In some embodiments, the second branch includes a third transistor and a fourth transistor, the voltage source of the amplifier circuit is grounded through the third transistor and the fourth transistor, the control electrode of the third transistor is configured to access the second input voltage, the current flowing through the third transistor and the fourth transistor is the second current, the third transistor and the fourth transistor are connected to a second node, and the voltage written to the second node is the second reference voltage. The second mirror branch includes a third mirror transistor and a fourth mirror transistor, the voltage source is grounded through the third mirror transistor and the fourth mirror transistor, the control electrode of the third mirror transistor is connected to the control electrode of the third transistor, the control electrode of the fourth mirror transistor is connected to the control electrode of the fourth transistor, the current flowing through the third mirror transistor and the fourth mirror transistor is the second mirror current, the third mirror transistor and the fourth mirror transistor are connected to a fourth node, and the voltage written to the fourth node is the fourth reference voltage. The width-to-length ratio of the third mirror transistor is greater than that of the third transistor, and the width-to-length ratio of the fourth mirror transistor is less than that of the fourth transistor.

[0015] In some embodiments, the amplifying unit includes a third branch and a fourth branch, the third branch is configured to generate a third current based on the first reference voltage, the fourth branch is configured to generate a fourth current based on the second reference voltage, and the amplifying unit is configured to provide the output voltage based on a current difference between the third current and the fourth current.

[0016] In some embodiments, the third branch includes a first input transistor and a first load, the voltage written into the first node of the first branch is the first reference voltage, and the first node is connected to the voltage source of the amplifier circuit through the first input transistor and the first load. The fourth branch includes a second input transistor and a second load, the voltage written into the second node of the second branch is the second reference voltage, and the second node is connected to the voltage source of the amplifier circuit through the second input transistor and the second load, and the output end of the amplifying unit is connected between the second input transistor and the second load.

[0017] In some embodiments, the amplifier circuit includes a bias transistor, a voltage source of the amplifier circuit is connected to a first electrode of the bias transistor, and a second electrode of the bias transistor is connected to the first branch, the second branch, the first mirror branch, and the second mirror branch. The bias voltage provided by the second electrode of the bias transistor is smaller than the voltage of the first electrode of the bias transistor, and the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage are all smaller than the bias voltage.

[0018] In some embodiments, the output end of the amplifier circuit includes a single-ended output end and a differential output end, the single-ended output end is configured to output a single-ended amplified signal, and the differential output end is configured to output a differential amplified signal.

[0019] The analog closed-loop circuit provided in the embodiments of the present application includes the amplifier circuit of any one of the above embodiments.

[0020] The embodiment of the present application provides an amplifier circuit and an analog closed-loop circuit, wherein the amplifier circuit includes an amplifier unit, a first mirror branch, a second mirror branch, a pull-up switch, a pull-down switch, and a control unit. The amplifier unit includes a first branch and a second branch, wherein the first branch is configured to generate a first reference voltage according to a voltage difference between a first input voltage and a second input voltage, and the second branch is configured to generate a second reference voltage according to a voltage difference between the first input voltage and the second input voltage, and the amplifier unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch is configured to generate a third reference voltage according to the first input voltage, wherein the pull-up speed of the third reference voltage is higher than the pull-up speed of the first reference voltage, and the pull-down speed of the third reference voltage is lower than the pull-down speed of the first reference voltage. The second mirror branch is configured to generate a fourth reference voltage according to the second input voltage, wherein the pull-up speed of the fourth reference voltage is higher than the pull-up speed of the second reference voltage, and the pull-down speed of the fourth reference voltage is lower than the pull-down speed of the second reference voltage. The pull-up switch is configured to pull up the output voltage when closed. The pull-down switch is configured to pull down the output voltage when closed. The control unit is configured to control the on and off of the pull-up switch and the pull-down switch according to the third reference voltage and the fourth reference voltage, so that the response speed of the pull-up switch and the pull-down switch being disconnected is higher than the response speed of the output voltage, and the response speed of the pull-up switch and the pull-down switch being closed is lower than the response speed of the output voltage.

[0021] In the amplifier circuit of the implementation mode of the present application, the response speed of closing the pull-up switch and the pull-down switch is lower than the response speed of the output voltage, while the response speed of opening the pull-up switch and the pull-down switch is higher than the response speed of the output voltage. This ensures that when the amplifying unit just returns to a steady state, the pull-up switch and the pull-down switch are disconnected for a period of time to avoid large signal oscillations in the main loop.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 is a schematic diagram of an amplifier circuit according to an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of an amplifier circuit of certain embodiments of the present application;

[0026] Figure 3 is a circuit diagram of some amplifier circuits in the related art;

[0027] Figure 4 is a circuit diagram of some amplifier circuits in the related art;

[0028] Figure 5 is a circuit diagram of some amplifier circuits in the related art;

[0029] Figure 6 is a schematic diagram of an amplifier circuit of certain embodiments of the present application;

[0030] Figure 7 is a schematic diagram of an amplifier circuit of certain embodiments of the present application;

[0031] Figure 8 is a schematic diagram of an amplifier circuit according to some embodiments of the present application.

[0032] Figure numerals: amplifier circuit 100, amplifying unit 10, first branch 11, second branch 12, first mirror branch 13, second mirror branch 14, third branch 15, fourth branch 16, pull-up switch 20, pull-down switch 30, control unit 40, bias transistor 17, first transistor 111, second transistor 112, third transistor 121, fourth transistor 122, first mirror transistor 131, second mirror transistor 132, third mirror transistor 141, fourth mirror transistor 142, first input transistor 151, first load 152, second input transistor 161, second load 162. DETAILED DESCRIPTION

[0033] The embodiments of the present application are described in detail below, and the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0034] Reference Figure 1 as well as Figure 2The embodiment of the present application provides an amplifier circuit 100, including an amplifier unit 10, a first mirror branch 13, a second mirror branch 14, a pull-up switch 20, a pull-down switch 30 and a control unit 40. The amplifier unit 10 includes a first branch 11 and a second branch 12, the first branch 11 is configured to generate a first reference voltage according to a voltage difference between a first input voltage and a second input voltage, the second branch 12 is configured to generate a second reference voltage according to a voltage difference between the first input voltage and the second input voltage, and the amplifier unit 10 is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch 13 is configured to generate a third reference voltage according to the first input voltage, the pull-up speed of the third reference voltage is higher than the pull-up speed of the first reference voltage, and the pull-down speed of the third reference voltage is lower than the pull-down speed of the first reference voltage. The second mirror branch 14 is configured to generate a fourth reference voltage according to the second input voltage, the pull-up speed of the fourth reference voltage is higher than the pull-up speed of the second reference voltage, and the pull-down speed of the fourth reference voltage is lower than the pull-down speed of the second reference voltage. The pull-up switch 20 is configured to pull up the output voltage when closed. The pull-down switch 30 is configured to pull down the output voltage when closed. The control unit 40 is configured to control the on and off of the pull-up switch 20 and the pull-down switch 30 according to the third reference voltage and the fourth reference voltage, so that the response speed of the pull-up switch 20 and the pull-down switch 30 being disconnected is higher than the response speed of the output voltage, and the response speed of the pull-up switch 20 and the pull-down switch 30 being closed is lower than the response speed of the output voltage.

[0035] In the related art, the slew rate enhancement effect of the amplifier is limited by the pull-up switch 20 and the pull-down switch 30 connected to the output end. When the input voltage difference detected by the amplifier is small, the pull-up switch 20 and the pull-down switch 30 connected to the output end are turned off. When the input voltage difference detected by the amplifier is large, the pull-up switch 20 or the pull-down switch 30 is turned on, and the corresponding feedback loop is started to increase the effective slew rate. However, when the pull-up switch 20 is turned on, the feedback loop will increase the falling flip speed of the input signal. When the pull-up switch 20 is just disconnected, the input voltage difference detected by the amplifier triggers the pull-down switch 30 to turn on, and a large signal oscillation occurs in the loop.

[0036] by Figure 3 For example, an upper comparator and a lower comparator may be provided, the upper comparator controls the transistor M12, and the lower comparator controls the transistor M11. When the voltage difference between the INP terminal and the INN terminal is small, the transistor M11 and the transistor M12 connected to the OUT terminal are turned off. When the voltage difference between the INP terminal and the INN terminal is large, the transistor M11 connected to the OUT terminal is turned on or the transistor M12 is turned on, increasing the effective slew rate.

[0037] Assuming that the voltage difference between the INP terminal and the INN terminal exceeds the dead zone threshold of the upper comparator, causing the transistor M12 to turn on, the voltage output at the OUT terminal is pulled up, and the feedback loop causes the voltage connected to the INN terminal to be pulled down. If the upper comparator responds quickly, when the transistor M12 is turned off, when the voltage difference between the INP terminal and the INN terminal is already less than the dead zone threshold of the lower comparator, causing the transistor M11 to turn on, the transistor M12 and the transistor M11 are intermittently turned on in this way, and large signal oscillation occurs in the loop, which has a negative impact on the stability of the main loop.

[0038] In the related art, there are other solutions for enhancing the slew rate of the amplifier, but these solutions still have the problem of insufficient stability of the main loop.

[0039] by Figure 4 For example, when the voltage difference between the INP terminal and the INN terminal is small, the voltage difference between node A and node C is small, and transistors M15 and M16 still work near the static bias point. The average current flowing through transistors M15 and M16 will not deviate too much from the current flowing through transistor M14, which can ensure that transistor M19 is turned off, and the first-stage bias current of the amplifier is determined by the current flowing through transistor M0. When the voltage difference between the INP terminal and the INN terminal is large, the voltage difference between node A and node C is large, and transistors M15 and M16 deviate from the static bias point, causing transistor M19 to turn on, increasing the first-stage bias current of the amplifier; thereby increasing the transient slew rate of the amplifier. This solution requires that the amplifier must have a structure for connecting the load, which consumes additional power consumption, and because the amplifier body is embedded, it has a negative impact on the stability of the main loop.

[0040] by Figure 5 For example, the RFC (re-used folded cascode) structure can be used to improve both bandwidth and slew rate. Compared with the traditional folded cascode operational amplifier, the RFC structure has higher gain bandwidth, low-frequency gain and slew rate, while not increasing power consumption and design area. However, this solution increases the complexity of the signal path, introduces more poles in the main loop, increases system complexity, and has a negative impact on the stability of the main loop. In addition, RFC amplifies the current through the NMOS current mirror below, so it cannot be directly applied to the fully differential amplifier.

[0041] Compared with the above-mentioned related technologies, the amplifier circuit 100 of the embodiment of the present application can ensure that the pull-up switch 20 and the pull-down switch 30 are disconnected for a period of time when the amplifying unit 10 just recovers the steady state, so as to avoid large signal oscillation in the main loop.

[0042] Specifically, the voltage source VDD is the voltage source of the amplifier circuit 100 , and the amplifier circuit 100 may include an INP terminal and an INN terminal. The first input voltage may be a voltage connected to the INP terminal, the second input voltage may be a voltage connected to the INN terminal, and the OUT terminal may be the output terminal of the amplification unit 10 .

[0043] The first branch 11 may include a node N1, the first mirror branch 13 may include a node N3, the second branch 12 may include a node N2, and the second mirror branch 14 may include a node N4. The voltage written to the node N1 may be a first reference voltage, the voltage written to the node N2 may be a second reference voltage, the voltage written to the node N3 may be a third reference voltage, and the voltage written to the node N4 may be a fourth reference voltage.

[0044] When the first input voltage and the second input voltage are the same, the first branch 11, the second branch 12, the first mirror branch 13 and the second mirror branch 14 operate in a steady state. When the first input voltage is greater than the second input voltage, the greater the voltage difference between the first input voltage and the second input voltage, the voltage written into the nodes N1 and N3 is pulled down to a voltage value lower than the steady state. When the second input voltage is greater than the first input voltage, the greater the voltage difference between the first input voltage and the second input voltage, the voltage written into the nodes N2 and N4 is pulled down to a voltage value lower than the steady state.

[0045] When the voltage written to the node N1 is pulled up, the voltage written to the node N3 follows the voltage written to the node N1 being pulled up; when the voltage written to the node N1 is pulled down, the voltage written to the node N3 follows the voltage written to the node N1 being pulled down; the speed at which the voltage written to the node N3 is pulled up is higher than the speed at which the voltage written to the node N1 is pulled up, and the speed at which the voltage written to the node N3 is pulled down is lower than the speed at which the voltage written to the node N1 is pulled down.

[0046] When the voltage written to the node N2 is pulled up, the voltage written to the node N4 follows the voltage written to the node N2 being pulled up; when the voltage written to the node N2 is pulled down, the voltage written to the node N4 follows the voltage written to the node N2 being pulled down; the speed at which the voltage written to the node N4 is pulled up is higher than the speed at which the voltage written to the node N2 is pulled up, and the speed at which the voltage written to the node N4 is pulled down is lower than the speed at which the voltage written to the node N2 is pulled down.

[0047] The pull-up switch 20 may be a transistor M12, and the pull-down switch 30 may be a transistor M11. The amplifying unit 10 provides an output voltage at the OUT terminal according to the voltages written into the nodes N1 and N2, and the control unit 40 controls the on and off of the transistors M11 and M12 according to the voltages written into the nodes N3 and N4.

[0048] Since the pull-up speed of the third reference voltage is higher than the pull-up speed of the first reference voltage, and the pull-down speed of the third reference voltage is lower than the pull-down speed of the first reference voltage, the corresponding response speed of the pull-up switch 20 when closed is lower than the response speed of the output voltage, and the response speed when open is higher than the response speed of the output voltage.

[0049] Since the pull-up speed of the fourth reference voltage is higher than the pull-up speed of the second reference voltage, and the pull-down speed of the fourth reference voltage is lower than the pull-down speed of the second reference voltage, the corresponding response speed of the pull-down switch 30 when closed is lower than the response speed of the output voltage, and the response speed when open is higher than the response speed of the output voltage.

[0050] The response speed of closing the pull-up switch 20 and the pull-down switch 30 is lower than the response speed of the output voltage, while the response speed of opening the pull-up switch 20 and the pull-down switch 30 is higher than the response speed of the output voltage. This ensures that when the amplifier unit 10 just returns to a steady state, the pull-up switch 20 and the pull-down switch 30 are disconnected for a period of time to avoid large signal oscillation in the main loop.

[0051] In addition, the amplifier circuit 100 provided in the embodiment of the present application also has the following technical effects: the improvement of the circuit structure is based on the comparator, and has little effect on the main loop after stabilization; the slew rate enhancement effect is only limited by the pull-up and pull-down switch 30 connected to OUT; a single comparator is used, and the dead zone function is integrated to minimize the increased power consumption; the comparator output swing is reduced, and the comparator speed is indirectly improved; at the same time, through current multiplexing, when a large signal is input, the comparator increases the flipping speed by grabbing the amplifier differential pair current; the single comparator has its own asymmetric rise / fall flipping speed, which naturally avoids the risk of large signal oscillation.

[0052] In some embodiments, the first branch 11 is configured to generate a first current according to a first input voltage and a first reference voltage according to the first current, the second branch 12 is configured to generate a second current according to a second input voltage and a second reference voltage according to the second current, and the amplification unit 10 is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch 13 is configured to copy the first current to obtain a first mirror current and provide a third reference voltage according to the first mirror current. The second mirror branch 14 is configured to copy the second current to obtain a second mirror current and provide a fourth reference voltage according to the second mirror current.

[0053] Specifically, the first mirror branch 13 is a current mirror branch of the first branch 11. If the current flowing through the first branch 11 is I1, the current flowing through the first mirror branch 13 is I1, (K1 is determined according to the electronic device parameters of the first mirror branch 13 and the first branch 11). The second mirror branch 14 is a current mirror branch of the second branch 12. If the current flowing through the second branch 12 is I2, the current flowing through the second mirror branch 14 is K2*I2, (K2 is determined according to the electronic device parameters of the second mirror branch 14 and the second branch 12).

[0054] The speed at which the first mirror current increases is higher than the speed at which the first current increases, and the speed at which the first mirror current decreases is lower than the speed at which the first current decreases, which in turn causes the third reference voltage to be pulled up at a higher speed than the first reference voltage, and the third reference voltage to be pulled down at a lower speed than the first reference voltage.

[0055] The speed at which the second mirror current increases is higher than the speed at which the second current increases, and the speed at which the second mirror current decreases is lower than the speed at which the second current decreases, which in turn causes the fourth reference voltage to be pulled up at a higher speed than the second reference voltage, and the fourth reference voltage to be pulled down at a lower speed than the second reference voltage.

[0056] The improvement of the first mirror branch 13 and the second mirror branch 14 is based on the comparator, which has little effect on the main loop after stabilization. In addition, through current multiplexing, when a large signal is input, the comparator increases the pull-up speed of the third reference voltage and the fourth reference voltage by preempting the amplifier differential pair current, thereby indirectly increasing the response speed of the control unit 40. The third reference voltage and the fourth reference voltage have asymmetric rising / falling flip speeds, so that the single-channel comparator has asymmetric rising / falling flip speeds, which naturally avoids the risk of large signal oscillation.

[0057] In some embodiments, the output voltage is positively correlated with the voltage difference between the first input voltage and the second input voltage, and when the first input voltage is consistent with the second input voltage, the output voltage reaches a steady-state value.

[0058] Specifically, the amplification unit 10 is a differential amplifier, and the greater the voltage difference between the first input voltage and the second input voltage, the greater the output voltage at the OUT terminal. When the first input voltage and the second input voltage are substantially the same, the output voltage is substantially close to zero, at which point the output voltage reaches a steady-state value, and the loop of the amplifier circuit 100 is maintained in a steady state.

[0059] In some embodiments, when the voltage difference is less than or equal to the dead zone voltage threshold, the control unit 40 is configured to control the pull-up switch 20 and the pull-down switch 30 to be disconnected. When the voltage difference is greater than the dead zone voltage threshold, the control unit 40 is configured to control the pull-up switch 20 to be closed, or to control the pull-down switch 30 to be closed, so as to adjust the output voltage to a steady-state value.

[0060] Specifically, the amplification unit 10 is provided with a corresponding dead zone voltage threshold. If the voltage difference between the first input voltage and the second input voltage is less than or equal to the dead zone voltage threshold, it can be considered that the first input voltage and the second input voltage are basically consistent at this time, and the transistor M11 and the transistor M12 are maintained in the off state. At this time, the feedback loop is disconnected and has no effect on the main loop.

[0061] If the voltage difference between the first input voltage and the second input voltage is greater than the dead zone voltage threshold, it can be considered that the corresponding feedback loop needs to be started at this time to pull up the output voltage of the OUT terminal or pull down the output voltage of the OUT terminal so that the output voltage of the OUT terminal can be restored to a steady state. When the first input voltage is greater than the second input voltage and the voltage difference is greater than the dead zone voltage threshold, the pull-down switch 30 is closed and the pull-up switch 20 is disconnected to pull up the output voltage of the OUT terminal. When the first input voltage is less than the second input voltage and the voltage difference is greater than the dead zone voltage threshold, the pull-up switch 20 is closed and the pull-down switch 30 is disconnected to pull down the output voltage of the OUT terminal.

[0062] In certain embodiments, when the voltage difference is greater than the dead zone voltage threshold and the first input voltage is higher than the second input voltage, the third reference voltage is lower than the first voltage threshold, and the control unit 40 is configured to control the pull-down switch 30 to be disconnected and the pull-up switch 20 to be closed. When the voltage difference is greater than the dead zone voltage threshold and the first input voltage is lower than the second input voltage, the fourth reference voltage is lower than the second voltage threshold, and the control unit 40 is configured to control the pull-up switch 20 to be disconnected and the pull-down switch 30 to be closed. When the voltage difference is less than or equal to the dead zone voltage threshold, the third reference voltage is higher than or equal to the first voltage threshold, the fourth reference voltage is higher than or equal to the second voltage threshold, and the control unit 40 is configured to control the pull-up switch 20 and the pull-down switch 30 to be disconnected.

[0063] Specifically, the control unit 40 can determine the on / off of the pull-down switch 30 according to the third reference voltage (the voltage written to the node N3 ) and the on / off of the pull-down switch 30 according to the fourth reference voltage (the voltage written to the node N4 ).

[0064] When the first input voltage is greater than the second input voltage and the voltage difference is greater than the dead zone voltage threshold, the third reference voltage is lower than the first voltage threshold, and the control unit 40 controls the pull-down switch 30 to close and the pull-up switch 20 to open, so as to pull up the output voltage of the OUT terminal. When the first input voltage is less than the second input voltage and the voltage difference is greater than the dead zone voltage threshold, the fourth reference voltage is lower than the voltage threshold, and the control unit 40 controls the pull-up switch 20 to close and the pull-down switch 30 to open, so as to pull down the output voltage of the OUT terminal.

[0065] The control unit 40 can be used as a single comparator (comparing the first voltage threshold with the third reference voltage, or comparing the first voltage threshold with the fourth reference voltage), and at the same time integrates a dead zone function, which is beneficial to reducing power consumption.

[0066] In some embodiments, the dead zone voltage threshold is positively correlated with the pull-up speed of the third reference voltage and the fourth reference voltage, and the dead zone voltage threshold is negatively correlated with the pull-down speed of the third reference voltage and the fourth reference voltage.

[0067] Specifically, the faster the third reference voltage and the fourth reference voltage are pulled up, the easier it is for the third reference voltage and the fourth reference voltage to reach a level higher than the first voltage threshold, and the corresponding control unit 40 is less likely to trigger the pull-up switch 20 to close or trigger the pull-down switch 30 to close, that is, the corresponding dead zone voltage threshold is larger.

[0068] The faster the third reference voltage and the fourth reference voltage are pulled down, the easier it is for the third reference voltage and the fourth reference voltage to reach a level lower than the first voltage threshold, and the easier it is for the corresponding control unit 40 to trigger the control of the pull-up switch 20 to close or trigger the control of the pull-down switch 30 to close, that is, the corresponding dead zone voltage threshold is smaller.

[0069] Reference Figure 6In some embodiments, the first branch 11 includes a first transistor 111 and a second transistor 112, the voltage source of the amplifier circuit 100 is grounded through the first transistor 111 and the second transistor 112, the control electrode of the first transistor 111 is configured to access the first input voltage, the current flowing through the first transistor 111 and the second transistor 112 is the first current, the first transistor 111 and the second transistor 112 are connected to a first node, and the voltage written to the first node is the first reference voltage. The first mirror branch 13 includes a first mirror transistor 131 and a second mirror transistor 132, the voltage source is grounded through the first mirror transistor 131 and the second mirror transistor 132, the control electrode of the first mirror transistor 131 is connected to the control electrode of the first transistor 111, the control electrode of the second mirror transistor 132 is connected to the control electrode of the second transistor 112, the current flowing through the first mirror transistor 131 and the second mirror transistor 132 is the first mirror current, the first mirror transistor 131 and the second mirror transistor 132 are connected to a third node, and the voltage written to the third node is the third reference voltage. The width-to-length ratio of the first mirror transistor 131 is greater than that of the first transistor 111 , and the width-to-length ratio of the second mirror transistor 132 is less than that of the second transistor 112 .

[0070] Specifically, the first transistor 111 may be a transistor M1, the second transistor 112 may be a transistor M2, the first mirror transistor 131 may be a transistor M1_cmp, and the second mirror transistor 132 may be a transistor M2_cmp. The transistor M2 and the transistor M2_cmp are in a normally-on state. The control electrodes of the transistor M1 and the transistor M1_cmp are connected to the INP terminal.

[0071] The first electrode of transistor M1 can be connected to voltage source VDD, the second electrode of transistor M1 can be connected to the second electrode of transistor M2 at node N1, and the first electrode of transistor M2 can be grounded. The first electrode of transistor M1_cmp can be connected to voltage source VDD, the second electrode of transistor M1_cmp can be connected to the second electrode of transistor M2 at node N2, and the first electrode of transistor M2_cmp can be grounded.

[0072] Since the width-to-length ratio of the first mirror transistor 131 is greater than that of the first transistor 111, the speed at which the first mirror current increases is higher than that at which the first current increases, thereby causing the speed at which the third reference voltage is pulled up to be higher than that at which the first reference voltage is pulled up. Since the width-to-length ratio of the first mirror transistor 131 is greater than that of the first transistor 111, the speed at which the first mirror current decreases is lower than that at which the first current decreases, thereby causing the speed at which the third reference voltage is pulled down to be higher than that at which the first reference voltage is pulled down.

[0073] Reference Figure 6In some embodiments, the second branch 12 includes a third transistor 121 and a fourth transistor 122, the voltage source of the amplifier circuit 100 is grounded through the third transistor 121 and the fourth transistor 122, the control electrode of the third transistor 121 is configured to access the second input voltage, the current flowing through the third transistor 121 and the fourth transistor 122 is the second current, the third transistor 121 and the fourth transistor 122 are connected to the second node, and the voltage written to the second node is the second reference voltage. The second mirror branch 14 includes a third mirror transistor 141 and a fourth mirror transistor 142, the voltage source is grounded through the third mirror transistor 141 and the fourth mirror transistor 142, the control electrode of the third mirror transistor 141 is connected to the control electrode of the third transistor 121, the control electrode of the fourth mirror transistor 142 is connected to the control electrode of the fourth transistor 122, the current flowing through the third mirror transistor 141 and the fourth mirror transistor 142 is the second mirror current, the third mirror transistor 141 and the fourth mirror transistor 142 are connected to the fourth node, and the voltage written to the fourth node is the fourth reference voltage. The width-to-length ratio of the third mirror transistor 141 is greater than that of the third transistor 121 , and the width-to-length ratio of the fourth mirror transistor 142 is less than that of the fourth transistor 122 .

[0074] Specifically, the third transistor 121 may be a transistor M3, the fourth transistor 122 may be a transistor M4, the third mirror transistor 141 may be a transistor M3_cmp, and the fourth mirror transistor 142 may be a transistor M4_cmp. The transistor M4 and the transistor M4_cmp are in a normally-on state. The control electrodes of the transistor M3 and the transistor M3_cmp are connected to the INN terminal.

[0075] The first electrode of transistor M3 can be connected to voltage source VDD, the second electrode of transistor M3 can be connected to the second electrode of transistor M4 at node N3, and the first electrode of transistor M4 can be grounded. The first electrode of transistor M3_cmp can be connected to voltage source VDD, the second electrode of transistor M3_cmp can be connected to the second electrode of transistor M4 at node N4, and the first electrode of transistor M4_cmp can be grounded.

[0076] Since the width-to-length ratio of the second mirror transistor 132 is greater than that of the second transistor 112, the speed at which the second mirror current increases is higher than that at which the second current increases, thereby causing the speed at which the fourth reference voltage is pulled up to be higher than that at which the second reference voltage is pulled up. Since the width-to-length ratio of the second mirror transistor 132 is greater than that of the second transistor 112, the speed at which the second mirror current decreases is lower than that at which the second current decreases, thereby causing the speed at which the fourth reference voltage is pulled down to be higher than that at which the second reference voltage is pulled down.

[0077] Reference Figure 6In some embodiments, the amplifier circuit 100 includes a bias transistor 17, a voltage source of the amplifier circuit 100 is connected to a first electrode of the bias transistor 17, and a second electrode of the bias transistor 17 is connected to the first branch 11, the second branch 12, the first mirror branch 13, and the second mirror branch 14. The bias voltage provided by the second electrode of the bias transistor 17 is less than the voltage of the first electrode of the bias transistor 17, and the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage are all less than the bias voltage.

[0078] Specifically, the bias transistor 17 can be a transistor M0, and the transistor M0 can be in a normally-on state. The first electrode of the transistor M0 is connected to the voltage source VDD, and the second electrode of the transistor can be connected to the first branch 11, the second branch 12, the first mirror branch 13 and the second mirror branch 14 to connect to the node vs, and provide a bias voltage through the node vs. The voltage of the second electrode of the transistor M0 is lower than the voltage of the first electrode, and the bias voltage is lower than the voltage provided by the voltage source VDD. Since the voltage of the second electrode of the transistor M1, the transistor M1_cmp, the transistor M3 and the transistor M3_cmp is lower than the voltage of the first electrode, the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage are all lower than the bias voltage.

[0079] The output swing of the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage is from 0 to the bias voltage, which is beneficial to increase the flip speed of the amplifier.

[0080] Reference Figure 1 In some embodiments, the amplifier circuit 100 may include a transistor M13, a voltage source VDD is connected to a first electrode of the transistor M13, a control electrode of the transistor M13 is connected to a node vs, a second electrode of the transistor M13 is grounded via a capacitor C1, and provides a voltage Vdd-f to the control unit 40, and the voltage Vdd-f may be used as a first voltage threshold. The voltage of the second electrode of the transistor M13 is lower than the voltage of the first electrode, that is, the first voltage threshold is lower than the bias voltage.

[0081] The first voltage threshold is lower than the bias voltage, and the output swings of the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage are from 0 to the bias voltage. When the voltage value of the third reference voltage is less than the first voltage threshold, the control unit 40 controls the pull-down switch 30 to be closed, and when the voltage value of the third reference voltage is greater than the first voltage threshold, the control unit 40 controls the pull-down switch 30 to be opened. When the voltage value of the fourth reference voltage is less than the first voltage threshold, the control unit 40 controls the pull-up switch 20 to be closed, and when the voltage value of the fourth reference voltage is greater than the first voltage threshold, the control unit 40 controls the pull-up switch 20 to be opened.

[0082] Reference Figure 2In some embodiments, the amplifying unit 10 includes a third branch 15 and a fourth branch 16, the third branch 15 is configured to generate a third current according to the first reference voltage, the fourth branch 16 is configured to generate a fourth current according to the second reference voltage, and the amplifying unit 10 is configured to provide an output voltage according to the current difference between the third current and the fourth current.

[0083] Specifically, the third branch 15 is connected to the first branch 11 at the node N1, and generates a third current according to the first reference voltage written into the node N1, and the third current may be a current flowing through the transistor M5, the transistor M7 and the transistor M9. The fourth branch 16 is connected to the second branch 12 at the node N2, and generates a fourth current according to the second reference voltage written into the node N2, and the fourth current may be a current flowing through the transistor M6, the transistor M8 and the transistor M10.

[0084] When the voltage value of the first input voltage is basically consistent with the voltage value of the second input voltage, the voltage value of the first reference voltage is basically consistent with the voltage value of the second reference voltage, the current value of the third current is basically consistent with the current value of the fourth current, and the output voltage provided by the OUT terminal is close to zero.

[0085] The greater the voltage difference between the first input voltage and the second input voltage, the greater the voltage difference between the first reference voltage and the second reference voltage, the greater the current difference between the third current and the fourth current, and the greater the amplitude of the output voltage provided by the OUT terminal.

[0086] In some embodiments, when the first input voltage is greater than the second input voltage, the value of the output voltage is a positive number, and when the first input voltage is less than the second input voltage, the value of the output voltage is a negative number.

[0087] Reference Figure 7 In some embodiments, the third branch 15 includes a first input transistor 151 and a first load 152, the voltage written into the first node of the first branch 11 is the first reference voltage, and the first node is connected to the voltage source of the amplifier circuit 100 through the first input transistor 151 and the first load 152. The fourth branch 16 includes a second input transistor 161 and a second load 162, the voltage written into the second node of the second branch 12 is the second reference voltage, and the second node is connected to the voltage source of the amplifier circuit 100 through the second input transistor 161 and the second load 162, and the output end of the amplifying unit 10 is connected between the second input transistor 161 and the second load 162.

[0088] Specifically, the first input transistor 151 may be a transistor M5 , and the first load 152 may include a transistor M7 and a transistor M9 . The transistor M5 , the transistor M7 , and the transistor M9 may be in a normally-on state.

[0089] The first electrode of the transistor M5 may be connected to the node N1, the second electrode of the transistor M5 may be connected to the second electrode of the transistor M7 and the control electrode of the transistor M9, the first electrode of the transistor M7 may be connected to the second electrode of the transistor M9, and the first electrode of the transistor M9 may be connected to the voltage source VDD. The first electrode of the transistor M6 may be connected to the node N2, the second electrode of the transistor M6 may be connected to the second electrode of the transistor M8 and the OUT terminal, the first electrode of the transistor M8 may be connected to the second electrode of the transistor M10, and the first electrode of the transistor M10 may be connected to the voltage source VDD.

[0090] In some embodiments, the output terminal of the amplifier circuit 100 includes a single-ended output terminal and a differential output terminal, the single-ended output terminal is configured to output a single-ended amplified signal, and the differential output terminal is configured to output a differential amplified signal.

[0091] In addition to being applied to the single-ended amplifier in the example, the amplifier circuit 100 can also be applied to a fully differential amplifier. The specific implementation can refer to the implementation of the single-ended amplifier in the example, and will not be described in detail here.

[0092] by Figure 1 For example, the amplifier circuit 100 can be applied to a single-ended amplifier, and the OUT terminal is used as a single-ended output terminal.

[0093] by Figure 8 For example, the amplifier circuit 100 can be applied to a differential amplifier, with the OUTA terminal and the OUTB terminal serving as differential output terminals.

[0094] The embodiment of the present application further provides an analog closed-loop circuit, which includes the amplifier circuit 100 of the above embodiment.

[0095] Specifically, the amplifier circuit 100 provided in the embodiment of the present application can be applied to analog closed-loop circuits of devices such as low-dropout linear regulators (LDOs) and DC-DC (direct current-to-direct current) amplifiers. While improving the amplifier slew rate, it can effectively avoid large signal oscillations in the loop and improve the stability of the loop.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0097] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0098] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0099] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0100] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An amplifier circuit, characterized in that: include: an amplifying unit, comprising a first branch and a second branch, wherein the first branch is configured to generate a first reference voltage according to a voltage difference between a first input voltage and a second input voltage, the second branch is configured to generate a second reference voltage according to the voltage difference between the first input voltage and the second input voltage, and the amplifying unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage; a first mirror branch, configured to generate a third reference voltage according to the first input voltage, wherein a pull-up speed of the third reference voltage is higher than a pull-up speed of the first reference voltage, and a pull-down speed of the third reference voltage is lower than a pull-down speed of the first reference voltage; a second mirror branch, configured to generate a fourth reference voltage according to the second input voltage, wherein a pull-up speed of the fourth reference voltage is higher than a pull-up speed of the second reference voltage, and a pull-down speed of the fourth reference voltage is lower than a pull-down speed of the second reference voltage; a pull-up switch configured to pull up the output voltage when closed; a pull-down switch configured to pull down the output voltage when closed; The control unit is configured to control the on and off of the pull-up switch and the pull-down switch according to the third reference voltage and the fourth reference voltage, so that the response speed of the pull-up switch and the pull-down switch being disconnected is higher than the response speed of the output voltage, and the response speed of the pull-up switch and the pull-down switch being closed is lower than the response speed of the output voltage.

2. The amplifier circuit according to claim 1, characterized in that The first branch is configured to generate a first current according to the first input voltage and a first reference voltage according to the first current, the second branch is configured to generate a second current according to the second input voltage and a second reference voltage according to the second current, and the amplification unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage; The first mirror branch is configured to copy the first current to obtain a first mirror current and provide a third reference voltage according to the first mirror current; The second mirror branch is configured to copy the second current to obtain a second mirror current and provide a fourth reference voltage according to the second mirror current.

3. The amplifier circuit according to claim 2, characterized in that The output voltage is positively correlated with a voltage difference between the first input voltage and the second input voltage, and when the first input voltage is consistent with the second input voltage, the output voltage reaches a steady-state value.

4. The amplifier circuit according to claim 3, characterized in that When the voltage difference is less than or equal to the dead zone voltage threshold, the control unit is configured to control the pull-up switch and the pull-down switch to be disconnected; When the voltage difference is greater than the dead zone voltage threshold, the control unit is configured to control the pull-up switch to be closed, or control the pull-down switch to be closed, so as to adjust the output voltage to reach the steady-state value.

5. The amplifier circuit according to claim 4, characterized in that The dead zone voltage threshold is positively correlated with pull-up speeds of the third reference voltage and the fourth reference voltage, and the dead zone voltage threshold is negatively correlated with pull-down speeds of the third reference voltage and the fourth reference voltage.

6. The amplifier circuit according to claim 4, characterized in that When the voltage difference is greater than the dead zone voltage threshold and the first input voltage is higher than the second input voltage, the third reference voltage is lower than the first voltage threshold, and the control unit is configured to control the pull-down switch to be opened and the pull-up switch to be closed; When the voltage difference is greater than the dead zone voltage threshold and the first input voltage is lower than the second input voltage, the fourth reference voltage is lower than the second voltage threshold, and the control unit is configured to control the pull-up switch to be disconnected and the pull-down switch to be closed; When the voltage difference is less than or equal to the dead zone voltage threshold, the third reference voltage is higher than or equal to the first voltage threshold, the fourth reference voltage is higher than or equal to the second voltage threshold, and the control unit is configured to control the pull-up switch and the pull-down switch to be disconnected.

7. The amplifier circuit according to claim 2, characterized in that The first branch includes a first transistor and a second transistor, the voltage source of the amplifier circuit is grounded through the first transistor and the second transistor, the control electrode of the first transistor is configured to be connected to the first input voltage, the current flowing through the first transistor and the second transistor is the first current, the first transistor and the second transistor are connected to a first node, and the voltage written to the first node is the first reference voltage; The first mirror branch includes a first mirror transistor and a second mirror transistor, the voltage source is grounded through the first mirror transistor and the second mirror transistor, the control electrode of the first mirror transistor is connected to the control electrode of the first transistor, the control electrode of the second mirror transistor is connected to the control electrode of the second transistor, the current flowing through the first mirror transistor and the second mirror transistor is the first mirror current, the first mirror transistor and the second mirror transistor are connected to a third node, and the voltage written to the third node is the third reference voltage; The width-to-length ratio of the first mirror transistor is greater than that of the first transistor, and the width-to-length ratio of the second mirror transistor is smaller than that of the second transistor.

8. The amplifier circuit according to claim 2, characterized in that The second branch includes a third transistor and a fourth transistor, the voltage source of the amplifier circuit is grounded through the third transistor and the fourth transistor, the control electrode of the third transistor is configured to be connected to the second input voltage, the current flowing through the third transistor and the fourth transistor is the second current, the third transistor and the fourth transistor are connected to a second node, and the voltage written to the second node is the second reference voltage; The second mirror branch includes a third mirror transistor and a fourth mirror transistor, the voltage source is grounded through the third mirror transistor and the fourth mirror transistor, the control electrode of the third mirror transistor is connected to the control electrode of the third transistor, the control electrode of the fourth mirror transistor is connected to the control electrode of the fourth transistor, the current flowing through the third mirror transistor and the fourth mirror transistor is the second mirror current, the third mirror transistor and the fourth mirror transistor are connected to a fourth node, and the voltage written to the fourth node is the fourth reference voltage; The width-to-length ratio of the third mirror transistor is greater than that of the third transistor, and the width-to-length ratio of the fourth mirror transistor is smaller than that of the fourth transistor.

9. The amplifier circuit according to claim 2, characterized in that The amplifying unit includes a third branch and a fourth branch, the third branch is configured to generate a third current according to the first reference voltage, the fourth branch is configured to generate a fourth current according to the second reference voltage, and the amplifying unit is configured to provide the output voltage according to the current difference between the third current and the fourth current.

10. The amplifier circuit according to claim 9, characterized in that The third branch includes a first input transistor and a first load, the voltage written into the first node of the first branch is the first reference voltage, and the first node is connected to the voltage source of the amplifier circuit through the first input transistor, the first load and the first node; The fourth branch includes a second input transistor and a second load, the voltage written into the second node of the second branch is the second reference voltage, the second node is connected to the voltage source of the amplifier circuit through the second input transistor and the second load, and the output end of the amplification unit is connected between the second input transistor and the second load.

11. The amplifier circuit according to claim 1, characterized in that The amplifier circuit includes a bias transistor, a voltage source of the amplifier circuit is connected to a first electrode of the bias transistor, and a second electrode of the bias transistor is connected to the first branch, the second branch, the first mirror branch, and the second mirror branch; The bias voltage provided by the second electrode of the bias transistor is smaller than the voltage of the first electrode of the bias transistor, and the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage are all smaller than the bias voltage.

12. The amplifier circuit according to claim 1, characterized in that The output end of the amplifier circuit includes a single-ended output end and a differential output end. The single-ended output end is configured to output a single-ended amplified signal, and the differential output end is configured to output a differential amplified signal.

13. An analog closed-loop circuit, characterized in that: The analog closed-loop circuit comprises the amplifier circuit according to any one of claims 1-12.

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