Video logarithmic amplifier bandwidth compensation circuit and video logarithmic amplifier circuit

Abstract

The invention provides a video logarithmic amplifier bandwidth compensation circuit and a video logarithmic amplification circuit, and the bandwidth compensation circuit comprises three amplification compensation sub-circuits which are sequentially connected in series, and enables an input signal to pass through each amplification compensation sub-circuit for bandwidth compensation to obtain a corresponding voltage signal; the three logarithmic units are connected with the amplification compensation sub-circuits in a one-to-one correspondence mode, and a voltage signal output by each amplification compensation sub-circuit is converted into a current signal through one logarithmic unit; the summation unit is used for receiving the current signals output by the logarithmic units and carrying out summation operation to obtain summation signals; and the operational amplifier is used for carrying out operational amplification on the summation signal to obtain an output signal. The circuit is simple in structure and can meet the requirements of different application scenes.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit applications, and in particular to a video logarithmic amplifier bandwidth compensation circuit and a video logarithmic amplifier circuit. Background Art

[0002] In system applications such as communication receivers, radars, and telemetry equipment, when the input signal is a bipolar pulse amplitude modulation signal with a large dynamic range, it is necessary to perform high-gain amplification on small signals and gain compression on large signals to obtain an output signal with a small dynamic range for processing by the subsequent modules. The processing circuit is required to have performance such as large dynamic range compression and high gain. At the same time, when the processing signal bandwidth is very wide, especially when the pulse signal is narrow and the rising edge is very small, the engineering also requires the circuit to have the characteristics of wide bandwidth so that the circuit can amplify and process the wide-band signal normally. However, the existing logarithmic discharger circuits are usually complex in structure, high in manufacturing cost, and difficult to adapt to the application environment, making it difficult to meet actual application needs. Summary of the invention

[0003] In view of the above problems existing in the prior art, the present invention proposes a video logarithmic amplifier bandwidth compensation circuit and a video logarithmic amplifier circuit, which mainly solve the problems that the bandwidth compensation structure of the existing video logarithmic amplifier is complex and the environmental adaptability is poor.

[0004] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0005] The present application provides a video logarithmic amplifier bandwidth compensation circuit, comprising: three amplification compensation sub-circuits connected in series in sequence, which enable an input signal to pass through each of the amplification compensation sub-circuits to perform bandwidth compensation to obtain a corresponding voltage signal; three logarithmic units, which are connected to the amplification compensation sub-circuits in a one-to-one correspondence, and the voltage signal output by each of the amplification compensation sub-circuits is converted into a current signal by one of the logarithmic units; a summing unit, which receives the current signals output by each of the logarithmic units and performs a summing operation to obtain a summed signal; and an operational amplifier, which performs operational amplification on the summed signal to obtain an output signal.

[0006] In one embodiment of the present application, the amplification and compensation subcircuit includes an amplifier and a compensation unit connected in series in sequence. The signal is amplified by the amplifier and then input into the compensation unit for bandwidth compensation to obtain the output of the corresponding subcircuit.

[0007] In one embodiment of the present application, a first DC blocking capacitor is provided at the same-direction input terminal of the amplifier in the amplification and compensation subcircuit, and a signal flows into the amplifier through the first DC blocking capacitor; the reverse input terminal of the amplifier is grounded through a second DC blocking capacitor; and the output terminal of the amplifier is connected to the input terminal of the corresponding compensation unit through a third DC blocking capacitor.

[0008] In an embodiment of the present application, a fourth DC blocking capacitor is disposed between each of the logarithmic units and the corresponding amplification and compensation sub-circuit.

[0009] In an embodiment of the present application, a fifth DC blocking capacitor and a seventh resistor are sequentially connected in series between the summing unit and the inverting input terminal of the operational amplifier.

[0010] In one embodiment of the present application, a fifth resistor and an eighth resistor are connected in series between the reverse input terminal and the output terminal of the operational amplifier, and the signal output port is connected through a seventeenth capacitor; the same-direction input terminal of the operational amplifier is grounded through a ninth resistor.

[0011] In one embodiment of the present application, the amplifying compensation subcircuit provided in connection with the input signal is a first amplifying compensation subcircuit, the amplifying compensation subcircuit connected to the first amplifying compensation subcircuit is a second amplifying compensation subcircuit, and the amplifying compensation subcircuit connected to the second amplifying compensation subcircuit is a third amplifying compensation subcircuit, then the circuit structure of the compensation unit in the first amplifying compensation subcircuit is the same as that in the second amplifying compensation subcircuit, the compensation unit in the first amplifying compensation subcircuit includes a first resistor and a second capacitor connected in parallel with each other; the compensation unit in the third amplifying compensation subcircuit includes a third resistor, a fourth resistor, a first inductor and a fourteenth capacitor, one end of the third resistor is respectively connected to one end of the fourteenth capacitor and one end of the fourth resistor, and the other end of the fourth resistor is grounded through the first inductor; the other ends of the fourteenth capacitor and the third resistor are connected to each other as the output end of the corresponding compensation unit.

[0012] The present application also provides a video logarithmic amplifier circuit, comprising the video logarithmic amplifier bandwidth compensation circuit.

[0013] As described above, the video logarithmic amplifier bandwidth compensation circuit and the video logarithmic amplifier circuit proposed in the present application have the following beneficial effects.

[0014] The present application linearly amplifies and compensates the bandwidth of an input signal through a three-way amplification compensation circuit, then converts the amplified voltage signal into a current signal through a logarithmic unit, sums the three-way current signals, and then amplifies the signal through an operational amplifier to obtain an output signal, thereby achieving logarithmic amplification of the input signal and bandwidth compensation at the same time, so that the bandwidth of the amplifier circuit can be adjusted according to the actual application environment, thereby enhancing the overall performance and flexibility of the amplifier; the circuit structure is simple, the cost is low, and it is more conducive to mass production, and it can also be expanded to other analog circuit fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the circuit structure of a video logarithmic amplifier bandwidth compensation circuit in one embodiment of the present application.

[0016] Figure 2 Schematic diagram of the circuit structure of a video logarithmic amplifier bandwidth compensation circuit in one embodiment of the present application.

[0017] Figure 3 Schematic diagram of the circuit structure of a compensation unit in one embodiment of the present application.

[0018] Figure 4 Schematic diagram of pre-compensation amplifier bandwidth simulation in one embodiment of the present application.

[0019] Figure 5 FIG. 1 is a schematic diagram of a simulation of a bandwidth of a compensated amplifier in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0021] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0022] See also Figure 1 , Figure 1The circuit architecture diagram of the video logarithmic amplifier bandwidth compensation circuit in one embodiment of the present application. The video logarithmic amplifier bandwidth compensation circuit provided in the embodiment of the present application includes: three amplification compensation sub-circuits connected in series, which allow the input signal to pass through each of the amplification compensation sub-circuits to perform bandwidth compensation to obtain a corresponding voltage signal; three logarithmic units, which are connected to the amplification compensation sub-circuits in a one-to-one correspondence, and the voltage signal output by each of the amplification compensation sub-circuits is converted into a current signal by one of the logarithmic units; a summing unit, which receives the current signals output by each of the logarithmic units and performs a summing operation to obtain a summed signal; and an operational amplifier, which performs an operational amplification on the summed signal to obtain an output signal.

[0023] In one embodiment, the amplification compensation subcircuit includes an amplifier and a compensation unit connected in series in sequence, and the signal is amplified by the amplifier and then input into the compensation unit for bandwidth compensation to obtain the output of the corresponding subcircuit. Specifically, the video logarithmic amplifier bandwidth compensation circuit includes a video logarithmic amplifier integrated by a first amplifier, a second amplifier, a third amplifier, a first logarithmic unit, a second logarithmic unit, a third logarithmic unit, a summing unit and an operational amplifier, and the first compensation unit, the second compensation unit, and the third compensation unit are connected to each other. The first amplifier and the first compensation unit constitute a first amplification compensation subcircuit, the second amplifier and the second compensation unit constitute a second amplification compensation subcircuit, and the third amplifier and the third unit constitute a third amplification compensation subcircuit.

[0024] In one embodiment, the same-direction input end of the amplifier in the amplification compensation subcircuit is provided with a first DC blocking capacitor (C10, C3, C11), and the signal flows into the amplifier through the first DC blocking capacitor; the reverse input end of the amplifier is grounded through a second DC blocking capacitor (C7, C5, C12); the output end of the amplifier is connected to the input end of the corresponding compensation unit through a third DC blocking capacitor (C4, C8, C13). For details, please refer to Figure 2 , Figure 2The circuit structure diagram of the video logarithmic amplifier bandwidth compensation circuit in one embodiment of the present application. The same-direction input terminal A1INP of the first amplifier A1 is connected to the input terminal of the external input signal through the first DC blocking capacitor C10; its reverse input terminal A1INN is connected to the ground through the second DC blocking capacitor C7; the output terminal of the first amplifier A1 is connected to the input terminal of the first compensation unit D1 through the third DC blocking capacitor C4. The same-direction input terminal A2INP of the second amplifier A2 is connected to the output terminal of the first compensation circuit D1 through the first DC blocking capacitor C3; its reverse input terminal A2INN is connected to the ground through the second DC blocking capacitor C5; its output terminal is connected to the input terminal of the second compensation unit D2 through the third DC blocking capacitor C8. The same-direction input terminal A3INP of the third amplifier A3 is connected to the output terminal of the second compensation unit D2 through the first DC blocking capacitor C11; its reverse input terminal A3INN is connected to the ground through the second DC blocking capacitor C12; its output terminal is connected to the input terminal of the third compensation unit D3 through the third DC blocking capacitor C13.

[0025] In one embodiment, a fourth DC blocking capacitor (C1, C9, C15) is provided between each of the logarithmic units and the corresponding amplification compensation sub-circuit. Figure 2 The input terminal A1IN_LOG of the first logarithmic unit L1 is connected to the output terminal of the first compensation unit D1 through the fourth DC blocking capacitor C1, and its output terminal is connected to the input terminal of the summing unit S1. The input terminal A2IN_LOG of the second logarithmic unit L2 is connected to the output terminal of the second compensation unit D2 through the fourth DC blocking capacitor C9, and its output terminal is connected to the input terminal of the summing unit S1. The input terminal A3IN_LOG of the third logarithmic unit L3 is connected to the output terminal of the third compensation unit D3 through the fourth DC blocking capacitor C15, and its output terminal is connected to the input terminal of the summing unit S1.

[0026] In one embodiment, a fifth DC blocking capacitor C18 and a seventh resistor R7 are sequentially connected in series between the summing unit S1 and the inverting input terminal OUTINN of the operational amplifier O1. Figure 2 The summing circuit S1 has an input end connected to the first logarithmic unit L1, the second logarithmic unit L2, and the third logarithmic unit L3, and an output end connected to the input end of the seventh resistor R7 through the fifth DC blocking capacitor C18.

[0027] In one embodiment, the fifth resistor R5 and the eighth resistor R8 are connected in series between the inverting input terminal OUTINN and the output terminal of the operational amplifier O1, and the signal output port is connected through the seventeenth capacitor C17; the non-inverting input terminal OUTINP of the operational amplifier O1 is grounded through the ninth resistor. Figure 2The inverting input terminal OUTINN of the operational amplifier circuit O1 is connected to the output terminal of the seventh resistor R7, and is also connected to the input terminals of the fifth resistor R5 and the eighth resistor R8; its inverting input terminal OUTINP is connected to the ground through the ninth resistor R9; its output terminal is connected to the output terminals of the fifth resistor R5 and the eighth resistor R8, and is also connected to the input terminal of the seventeenth capacitor C17. The output terminal of the seventeenth capacitor C17 is connected to the signal output port.

[0028] In one embodiment, the amplifying compensation subcircuit connected to the input signal is a first amplifying compensation subcircuit, the amplifying compensation subcircuit connected to the first amplifying compensation subcircuit is a second amplifying compensation subcircuit, and the amplifying compensation subcircuit connected to the second amplifying compensation subcircuit is a third amplifying compensation subcircuit. The circuit structure of the compensation unit in the first amplifying compensation subcircuit is the same as that in the second amplifying compensation subcircuit. The compensation unit D1 in the first amplifying compensation subcircuit includes a first resistor R1 and a second capacitor R2 connected in parallel with each other. The compensation unit D3 in the third amplifying compensation subcircuit includes a third resistor R3, a fourth resistor R4, a first inductor L1 and a fourteenth capacitor C14. One end of the third resistor R3 is respectively connected to one end of the fourteenth capacitor C14 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded through the first inductor L1. The other ends of the fourteenth capacitor C14 and the third resistor R3 are connected to each other as the output end of the corresponding compensation unit. For details, please refer to Figure 3 , Figure 3Schematic diagram of the circuit structure of the compensation unit in one embodiment of the present application. The first compensation unit D1 includes a first resistor R1 and a second capacitor C2. The input end of the first resistor R1 is connected to the input end of the second capacitor C2, and the output end of the first resistor R1 is connected to the output end of the second capacitor C2. The input end of the first compensation unit D1 is connected to the output of the first amplifier A1 through the first DC blocking capacitor C4; its output end is connected to the input end of the first logarithmic unit L1 through the fourth DC blocking capacitor C1, and is connected to the same-direction input end A2INP of the second amplifier A2 through the first DC blocking capacitor C3. The second compensation unit D2 includes a second resistor R2 and a sixth capacitor C6. The input end of the second resistor R2 is connected to the input end of the sixth capacitor C6, and the output end of the second resistor R2 is connected to the output end of the sixth capacitor C6. The input end of the second compensation unit D2 is connected to the output of the second amplifier A2 through the third DC blocking capacitor C8; its output end is connected to the input end of the second logarithmic unit L2 through the fourth DC blocking capacitor C9, and is connected to the same-direction input end A3INP of the third amplifier A3 through the first DC blocking capacitor C11. The third compensation unit D3 includes a third resistor R3, a fourth resistor R4, a first inductor L1 and a fourteenth capacitor C14, wherein the input end of the third resistor R3, the input end of the fourteenth capacitor C14 and the input end of the fourth resistor R4 are connected, and the output end of the third resistor R3 and the output end of the fourteenth capacitor C14 are connected. The output end of the fourth resistor R4 is connected to the input end of the first inductor L1, and the output end of the first inductor L1 is grounded. The input end of the third compensation unit D3 is connected to the output of the third amplifier A3 through the third DC blocking capacitor C13; its output end is connected to the input end of the logarithmic unit L3 through the fourth DC blocking capacitor C15.

[0029] In one embodiment, the first capacitor C1, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fifteenth capacitor C15, and the seventeenth capacitor C17 are all 1μF, the ninth resistor R9 and the seventh resistor R7 are 1kΩ, and the eighth resistor R8 is 1.2kΩ. In the first compensation unit D1, C1 is 30nF and R1 is 300Ω; in the second compensation unit D2, C6 is 30nF and R2 is 300Ω; in the third compensation unit, C14 is 10nF, R3 is 300 ohms, R4 is 430 ohms, and L1 is 3.9nH. Specifically, the values ​​of the components can be set and adjusted according to the actual application requirements, and are not limited here.

[0030] The working principle of the circuit in the embodiment of the present application is:

[0031] The input signal is amplified by the first amplifier A1 and then input into the first compensation unit D1. After the first compensation unit D1 compensates for the signal bandwidth, the signal is input into the second amplifier A2 and then into the first logarithmic unit L1. The signal after the second amplifier A2 is input into the second compensation unit D2 for bandwidth compensation, and then the signal is input into the third amplifier A3 and then into the second logarithmic unit L2. The signal after the third amplifier A3 is amplified and then input into the third compensation unit D3 for bandwidth compensation, and then input into the third logarithmic unit L3 circuit. The summing unit S1 sums the output current signals of the first logarithmic unit L1, the second logarithmic unit L2, and the third logarithmic unit L3, and the summed signal is input into the operational amplifier O1. The operational amplifier O1 amplifies the amplitude of the signal and then outputs the final signal.

[0032] The circuit structures of the first compensation unit D1 and the second compensation unit D2 are as follows: Figure 3 As shown, the working principle is as follows: If the impedance of the circuit is Zo and the impedance of the capacitor is Xc, then:

[0033] Zo=R||Xc

[0034]

[0035] (1) When f is very small, the capacitive reactance of the capacitor to the signal is very large, that is, Much larger than R, Zo=R, resistance plays a major role in the link; f is the signal frequency, c is the capacitance value.

[0036] (2) When f is very large, the capacitive reactance of the capacitor to the signal is very small, that is, Much smaller than R, Capacitors play a major role in the link. At this time, the impedance of capacitors to signals is very small, and the loss caused by high-frequency signals is very small, thus achieving compensation for high-frequency signals.

[0037] The structure of the third compensation unit D3 is as follows Figure 3 As shown, part of the resistor and capacitor are connected in parallel, and the total impedance is

[0038] When f is large, The capacitance is much smaller than R. At this time, the impedance of the capacitor to the signal is very small, and the high-frequency signal can pass through the link with little loss. The inductance and resistance connected to the ground in the compensation circuit are connected in series to form a resonant circuit with a resonant frequency of Further compensate for high frequency signals and broaden the bandwidth of the amplifier.

[0039] The bandwidth compensation result of the technical solution of the embodiment of the present application is as follows Figure 4 and 5 As shown, Figure 4 This is a schematic diagram of the simulation of the bandwidth of the pre-compensation amplifier in an embodiment of the present application. Figure 5This is a schematic diagram of the amplifier bandwidth simulation after compensation in an embodiment of the present application. As can be seen from the figure, after bandwidth compensation, the bandwidth of the circuit is compensated from 25MHz to 118MHz, and the performance of the amplifier is greatly improved.

[0040] In one embodiment, the present application also provides a video logarithmic amplifier circuit, which integrates the aforementioned video logarithmic amplifier bandwidth compensation circuit into one chip, and provides a capacitor capable of adjusting bandwidth and a resistor capable of adjusting amplitude. Specifically, the first amplifier A1, the second amplifier A2, the third amplifier A3, the first logarithmic unit circuit L1, the second logarithmic unit circuit L2, the third logarithmic unit circuit L3, the summing circuit S1, and the operational amplifier circuit O1 are integrated into the video logarithmic amplifier circuit U1. The BP port of the video logarithmic amplifier circuit U1 is connected to a -5V negative power supply, the VEE port of the video logarithmic amplifier circuit U1 is connected to a -5V negative power supply, the VCC port and the VCC2 port of the video logarithmic amplifier circuit U1 are connected to a +5V positive power supply, the GND port is grounded, the LODDADJ port is suspended, the OUTCOMP port is connected to the input end of the sixteenth capacitor C16, and the output end of the sixteenth capacitor C16 is grounded. C16 is a bandwidth adjustment capacitor, and R5 is an amplitude adjustment resistor. The device value configuration can be performed according to the actual application requirements to adjust the bandwidth and output amplitude of the amplifier circuit to meet the requirements of different application environments.

[0041] Based on the technical solution of the above embodiment of the present application, the video logarithmic amplifier bandwidth compensation circuit adopts three amplifiers, three logarithmic units, a summing unit, an operational amplifier, and three compensation units for bandwidth compensation are connected to achieve. The input signal is input from the first amplifier A1, linearly amplified by the second amplifier A2 and the third amplifier A3, and then the signal is converted into a current signal by the logarithmic unit circuit and enters the summing unit for summation. After summation, it is amplified by the operational amplifier to achieve logarithmic amplification of the input signal. The bandwidth compensation circuit is cascaded between the amplifiers to achieve the bandwidth of the compensation circuit. Thereby achieving logarithmic amplification of wide frequency signals. The circuit of the embodiment of the present application can expand the bandwidth of the video logarithmic amplifier, and at the same time, the amplifier bandwidth can be adjusted according to the actual application environment, which enhances the comprehensive performance and flexibility of the amplifier, and enriches the application scenarios of the amplifier; the circuit structure is simple, the components are few, the cost is low, it is conducive to mass production, and it can be expanded to other analog circuit fields.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A video logarithmic amplifier bandwidth compensation circuit, characterized in that: include: Three amplification and compensation sub-circuits are connected in series in sequence, so that the input signal passes through each of the amplification and compensation sub-circuits for bandwidth compensation to obtain a corresponding voltage signal; Three logarithmic units, which are connected to the amplifying and compensating sub-circuits in a one-to-one correspondence, and each voltage signal output by the amplifying and compensating sub-circuit is converted into a current signal by one of the logarithmic units; a summing unit, which receives the current signals output by the logarithmic units and performs summing operation to obtain a summing signal; and An operational amplifier performs operational amplification on the sum signal to obtain an output signal.

2. The video logarithmic amplifier bandwidth compensation circuit according to claim 1, characterized in that: The amplification and compensation subcircuit comprises an amplifier and a compensation unit connected in series in sequence. The signal is amplified by the amplifier and then input into the compensation unit for bandwidth compensation to obtain the output of the corresponding subcircuit.

3. The video logarithmic amplifier bandwidth compensation circuit according to claim 2, characterized in that: The same-direction input terminal of the amplifier in the amplification compensation subcircuit is provided with a first DC blocking capacitor, and the signal flows into the amplifier through the first DC blocking capacitor; the reverse input terminal of the amplifier is grounded through a second DC blocking capacitor; and the output terminal of the amplifier is connected to the input terminal of the corresponding compensation unit through a third DC blocking capacitor.

4. The video logarithmic amplifier bandwidth compensation circuit according to claim 1, characterized in that: A fourth DC blocking capacitor is arranged between each of the logarithmic units and the corresponding amplification and compensation sub-circuit.

5. The video logarithmic amplifier bandwidth compensation circuit according to claim 1, characterized in that: A fifth DC blocking capacitor and a seventh resistor are sequentially connected in series between the summing unit and the inverting input terminal of the operational amplifier.

6. The video logarithmic amplifier bandwidth compensation circuit according to claim 5, characterized in that: A fifth resistor and an eighth resistor are connected in series between the inverting input terminal and the output terminal of the operational amplifier in sequence, and are connected to the signal output port via a seventeenth capacitor; and the non-inverting input terminal of the operational amplifier is grounded via a ninth resistor.

7. The video logarithmic amplifier bandwidth compensation circuit according to claim 2, characterized in that: The amplifying compensation subcircuit connected to the input signal is a first amplifying compensation subcircuit, the amplifying compensation subcircuit connected to the first amplifying compensation subcircuit is a second amplifying compensation subcircuit, and the amplifying compensation subcircuit connected to the second amplifying compensation subcircuit is a third amplifying compensation subcircuit. The circuit structures of the compensation units in the first amplifying compensation subcircuit and the second amplifying compensation subcircuit are the same. The compensation unit in the first amplifying compensation subcircuit includes a first resistor and a second capacitor connected in parallel with each other. The compensation unit in the third amplifying compensation subcircuit includes a third resistor, a fourth resistor, a first inductor and a fourteenth capacitor. One end of the third resistor is respectively connected to one end of the fourteenth capacitor and one end of the fourth resistor, and the other end of the fourth resistor is grounded through the first inductor. The other ends of the fourteenth capacitor and the third resistor are connected to each other as output ends of the corresponding compensation units.

8. A video logarithmic amplifier circuit, characterized in that: It comprises the video logarithmic amplifier bandwidth compensation circuit as described in any one of claims 1-7.

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