Dynamic comparator

Abstract

The invention relates to the technical field of analog integrated circuit design, and discloses a dynamic comparator which comprises a pre-amplification module and a latch module. The pre-amplification module comprises a differential input unit, a current unit and a reset unit; the differential input unit comprises a PMOS input unit and an NMOS input unit; the PMOS input unit is used for accessing a first input signal, amplifying the first input signal through two branches in the PMOS input unit, and outputting a first P tube amplified signal and a second P tube amplified signal; the NMOS input unit is used for accessing a second input signal, respectively amplifying the second input signal through two branches in the NMOS input unit, and outputting a first N tube amplified signal and a second N tube amplified signal; the first input signal and the second input signal are differential signals; the latch module is of a double-tail dynamic latch structure and comprises a first P tube signal input end, a second P tube signal input end, a first N tube signal input end and a second N tube signal input end.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuit design, and in particular to a dynamic comparator. Background Art

[0002] Comparator is one of the important analog circuit modules in modern integrated circuit systems and is widely used in AD / DA conversion systems, automotive electronics, biomedicine and other fields. As the core module in SAR ADC, the accuracy, power consumption, speed and other indicators of comparator have an important impact on the overall performance. Dynamic comparator has the advantages of fast comparison speed, no static power consumption and rail-to-rail output, so it is widely used in high-speed and low-power SAR ADC.

[0003] Traditional dynamic comparators have a wide input range and the noise level is difficult to control, especially when the common-mode voltage changes greatly. It is difficult to maintain high speed, low noise and sensitivity at the same time. The input-referred noise increases linearly with the increase of common-mode voltage and input signal, causing the comparator to be greatly affected by the power-mode voltage.

[0004] In view of this, a dynamic comparator with a wide input swing suitable for SAR ADC is needed, which can effectively suppress the influence of common-mode voltage changes on circuit performance. Summary of the invention

[0005] In view of this, the present invention provides a dynamic comparator capable of maintaining high speed, low noise and high sensitivity under a wide range of common mode voltages.

[0006] In a first aspect, the present invention provides a dynamic comparator, comprising a pre-amplifier module and a latch module; the pre-amplifier module comprises a differential input unit, a current unit and a reset unit; the differential input unit comprises a PMOS input unit and an NMOS input unit; the PMOS input unit is used to access a first input signal, and amplify the first input signal through two branches in the PMOS input unit, and output a first P-tube amplified signal and a second P-tube amplified signal; the NMOS input unit is used to access a second input signal, and amplify the second input signal through two branches in the NMOS input unit, and output a first N-tube amplified signal and a second N-tube amplified signal; the first input signal and the second input signal are differential signals;

[0007] The latch module has a double-tail dynamic latch structure, including a first P-tube signal input terminal, a second P-tube signal input terminal, a first N-tube signal input terminal and a second N-tube signal input terminal; the first P-tube signal input terminal is connected to the first P-tube amplified signal; the second P-tube signal input terminal is connected to the second P-tube amplified signal; the first N-tube signal input terminal is connected to the first N-tube amplified signal; the second N-tube signal input terminal is connected to the second N-tube amplified signal.

[0008] Furthermore, the two branches in the PMOS input unit include a first PMOS input unit branch and a second PMOS input unit branch; the first PMOS input unit branch includes a first PMOS tube and a second PMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are connected to the first input signal; the drain of the first PMOS tube is connected to the signal input end of the first P tube; the source of the first PMOS tube is connected to the current input end of the current unit; the drain of the second PMOS tube is connected to the signal input end of the second P tube; and the source of the second PMOS tube is connected to the current output end of the current unit.

[0009] Furthermore, the two branches in the NMOS input unit include a first NMOS input unit branch and a second NMOS input unit branch; the first NMOS input unit branch includes a first NMOS tube and a second NMOS tube; the gate of the first NMOS tube and the gate of the second NMOS tube are connected to the second input signal; the drain of the first NMOS tube is connected to the signal input end of the first NMOS tube; the source of the first NMOS tube is connected to the current input end of the current unit; the drain of the second NMOS tube is connected to the signal input end of the second NMOS tube; and the source of the second NMOS tube is connected to the current output end of the current unit.

[0010] Furthermore, the current unit includes a first tail current tube; the gate of the first tail current tube is connected to the first control signal; the source of the first tail current tube is connected to the voltage signal; and the drain of the first tail current tube is connected to the current input end of the current unit.

[0011] Furthermore, the current unit also includes a second tail current tube; the gate of the second tail current tube is connected to the second control signal; the source of the second tail current tube is connected to the ground signal; the drain of the second tail current tube is connected to the current output end of the current unit; the phase of the second control signal is opposite to the phase of the first control signal.

[0012] Furthermore, the reset unit includes a P signal reset unit; the P signal reset unit includes a third PMOS tube and a fourth PMOS tube; the gate of the third PMOS tube is connected to the first control signal; the source of the third PMOS tube is connected to the ground signal; the gate of the third PMOS tube is connected to the gate of the first PMOS tube; the gate of the fourth PMOS tube is connected to the second control signal; the source of the fourth PMOS tube is connected to the voltage signal; the gate of the fourth PMOS tube is connected to the gate of the second PMOS tube.

[0013] Furthermore, the reset unit also includes an N signal reset unit; the N signal reset unit includes a third NMOS tube and a fourth NMOS tube; the gate of the third NMOS tube is connected to the first control signal; the source of the third NMOS tube is connected to the ground signal; the gate of the third NMOS tube is connected to the gate of the first NMOS tube; the gate of the fourth NMOS tube is connected to the second control signal; the source of the fourth NMOS tube is connected to the voltage signal; the gate of the fourth NMOS tube is connected to the gate of the second NMOS tube.

[0014] Further, the latch module includes an input unit; the input unit includes a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube; the gate of the fifth PMOS tube is connected to the second N tube signal input terminal; the gate of the sixth PMOS tube is connected to the first P tube signal input terminal; the source of the fifth PMOS tube is connected to the second reset node; the drain of the fifth PMOS tube is connected to the drain of the sixth PMOS tube; the gate of the fifth NMOS tube is connected to the second P tube signal input terminal; the gate of the sixth NMOS tube is connected to the first N tube signal input terminal; the source of the fifth NMOS tube is connected to the first reset node; the drain of the fifth NMOS tube is connected to the drain of the sixth NMOS tube.

[0015] Further, the latch module also includes a latch reset unit; the latch reset unit includes a seventh PMOS tube, a seventh NMOS tube, a tenth PMOS tube and a tenth NMOS tube; the gate of the seventh PMOS tube is connected to the second control signal; the source of the seventh PMOS tube is connected to the voltage signal; the gate of the seventh PMOS tube is connected to the second reset node; the gate of the seventh NMOS tube is connected to the second control signal; the source of the seventh NMOS tube is connected to the voltage signal; the gate of the seventh NMOS tube is connected to the first reset node; the gate of the tenth PMOS tube is connected to the first control signal; the source of the tenth PMOS tube is connected to the ground signal; the gate of the tenth PMOS tube is connected to the fourth reset node; the gate of the tenth NMOS tube is connected to the first control signal; the source of the tenth NMOS tube is connected to the ground signal; the gate of the tenth NMOS tube is connected to the third reset node.

[0016] Further, the latch module also includes a main unit; the main unit includes an eighth PMOS tube, a ninth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a first inverter and a second inverter; the gate of the eighth PMOS tube is connected to the gate of the eighth NMOS tube; the source of the eighth PMOS tube is connected to the voltage signal; the drain of the eighth PMOS tube is connected to the second reset node; the gate of the ninth PMOS tube is connected to the gate of the eighth PMOS tube; the source of the ninth PMOS tube is connected to the ground signal; the drain of the ninth PMOS tube is connected to the drain of the sixth PMOS tube; the input node of the first inverter is connected to the gate of the eighth PMOS tube; The output node of the first inverter outputs a P output terminal signal; the source of the eighth NMOS tube is connected to the voltage signal; the drain of the eighth NMOS tube is connected to the first reset node; the gate of the ninth NMOS tube is connected to the gate of the eighth NMOS tube; the source of the ninth NMOS tube is connected to the ground signal; the drain of the ninth NMOS tube is connected to the drain of the sixth NMOS tube; the input node of the second inverter is connected to the gate of the eighth NMOS tube; the output node of the second inverter outputs an N output terminal signal; the first inverter input node, the second inverter input node, the first reset node, the second reset node, the third reset node and the fourth reset node are connected to each other.

[0017] The technical solution provided by the present invention may include the following beneficial effects:

[0018] A differential input unit in a dynamic comparator pre-amplification module of the present invention includes a PMOS input unit and an NMOS input unit, which process differential signals respectively and amplify signals through their two branches, so that the comparator can receive and amplify input signals in a wide range, reduce noise interference, and improve comparison accuracy. The latch module adopts a double-tail dynamic latch structure to speed up the comparison process through a positive feedback mechanism. The above scheme has a larger input dynamic range through differential input and complementary amplification, effectively suppresses the influence of common mode voltage changes on comparator performance, and maintains high speed, low noise and high sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1is a circuit diagram of a dynamic comparator according to an embodiment of the present invention; DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0022] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0023] An embodiment of the present invention provides a dynamic comparator, comprising a pre-amplification module and a latch module;

[0024] The pre-amplification module includes a differential input unit, a current unit and a reset unit; the differential input unit includes a PMOS input unit and an NMOS input unit; the PMOS input unit is used to access a first input signal, and amplify the first input signal through two branches in the PMOS input unit, and output a first P-tube amplified signal and a second P-tube amplified signal; the NMOS input unit is used to access a second input signal, and amplify the second input signal through two branches in the NMOS input unit, and output a first N-tube amplified signal and a second N-tube amplified signal; the first input signal and the second input signal are differential signals;

[0025] The latch module has a double-tail dynamic latch structure, including a first P-tube signal input terminal, a second P-tube signal input terminal, a first N-tube signal input terminal and a second N-tube signal input terminal; the first P-tube signal input terminal is connected to the first P-tube amplified signal; the second P-tube signal input terminal is connected to the second P-tube amplified signal; the first N-tube signal input terminal is connected to the first N-tube amplified signal; the second N-tube signal input terminal is connected to the second N-tube amplified signal.

[0026] Based on the above structure, a differential input unit in a dynamic comparator pre-amplification module of the present invention includes a PMOS input unit and an NMOS input unit, which process differential signals respectively and amplify signals through their two branches, so that the comparator can receive and amplify input signals in a wide range, reduce noise interference, and improve comparison accuracy. The latch module adopts a double-tail dynamic latch structure to speed up the comparison process through a positive feedback mechanism. The above scheme has a larger input dynamic range through differential input and complementary amplification, effectively suppresses the influence of common-mode voltage changes on comparator performance, and maintains high speed, low noise and high sensitivity.

[0027] In the embodiment of the present invention, reference Figure 1 In part A, the two branches in the PMOS input unit include a first PMOS input unit branch and a second PMOS input unit branch; the first PMOS input unit branch includes a first PMOS tube MP1 and a second PMOS tube MP2;

[0028] The gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are connected to the first input signal IN;

[0029] The drain of the first PMOS tube MP1 is connected to the first P tube signal input terminal Vop1; the source of the first PMOS tube MP1 is connected to the current input terminal Xa of the current unit;

[0030] The drain of the second PMOS tube MP2 is connected to the second P tube signal input terminal Vop2; the source of the second PMOS tube MP2 is connected to the current output terminal Xb of the current unit.

[0031] refer to Figure 1 In the A part, the two branches in the NMOS input unit include a first NMOS input unit branch and a second NMOS input unit branch; the first NMOS input unit branch includes a first NMOS transistor MN1 and a second NMOS transistor MN2;

[0032] The gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are connected to the second input signal IP;

[0033] The drain of the first NMOS transistor MN1 is connected to the first N-tube signal input terminal Von1; the source of the first NMOS transistor MN1 is connected to the current input terminal Xa of the current unit;

[0034] The drain of the second NMOS transistor MN2 is connected to the second N-tube signal input terminal Von2; the source of the second NMOS transistor MN2 is connected to the current output terminal Xb of the current unit.

[0035] The PMOS and NMOS complementary input differential pair structure (i.e., MP1, MP2 and MN1, MN2) is adopted, which can effectively process a wide range of input signals, thereby realizing a wide input swing. At the same time, due to the complementary characteristics of the differential pair, the noise suppression capability of the circuit is enhanced. By connecting the first input signal IN and the second input signal IP to the gate of the PMOS tube and the NMOS tube respectively, the current difference generated by the differential pair can make the latch enter the positive feedback state, speed up the comparison process, and improve the comparison speed. Due to the use of a rail-to-rail wide swing input design, the comparator has a low sensitivity to changes in the input common-mode voltage. In a wider common-mode voltage range, the performance of the comparator (such as speed, noise, etc.) can remain stable, thereby improving its reliability and adaptability in practical applications.

[0036] refer to Figure 1 In the A part, the current unit includes a first tail current tube M0;

[0037] The gate of the first tail current tube M0 is connected to the first control signal CLKB; the source of the first tail current tube M0 is connected to the voltage signal VDD; the drain of the first tail current tube M0 is connected to the current input terminal Xa of the current unit.

[0038] refer to Figure 1 A part of the current unit further includes a second tail current tube M1;

[0039] The gate of the second tail current tube M1 is connected to the second control signal CLK; the source of the second tail current tube M1 is connected to the ground signal; the drain of the second tail current tube M1 is connected to the current output terminal Xb of the current unit; the phase of the second control signal CLK is opposite to that of the first control signal CLKB.

[0040] By introducing the first tail current tube M0 and the second tail current tube M1, the current input terminal Xa and the current output terminal Xb are controlled respectively, so as to ensure the normal operation of the PMOS input unit during the dynamic pre-amplification process.

[0041] refer to Figure 1 In the A part, the reset unit includes a P signal reset unit; the P signal reset unit includes a third PMOS tube MP3 and a fourth PMOS tube MP4;

[0042] The gate of the third PMOS tube MP3 is connected to the first control signal CLKB; the source of the third PMOS tube MP3 is connected to the ground signal; the gate of the third PMOS tube MP3 is connected to the gate of the first PMOS tube MP1;

[0043] The gate of the fourth PMOS transistor MP4 is connected to the second control signal CLK; the source of the fourth PMOS transistor MP4 is connected to the voltage signal VDD; the gate of the fourth PMOS transistor MP4 is connected to the gate of the second PMOS transistor MP2.

[0044] refer to Figure 1 The reset unit further comprises an N signal reset unit; the N signal reset unit comprises a third NMOS tube MN3 and a fourth NMOS tube MN4;

[0045] The gate of the third NMOS transistor MN3 is connected to the first control signal CLKB; the source of the third NMOS transistor MN3 is connected to the ground signal; the gate of the third NMOS transistor MN3 is connected to the gate of the first NMOS transistor MN1;

[0046] The gate of the fourth NMOS transistor MN4 is connected to the second control signal CLK; the source of the fourth NMOS transistor MN4 is connected to the voltage signal VDD; the gate of the fourth NMOS transistor MN4 is connected to the gate of the second NMOS transistor MN2.

[0047] By connecting the third PMOS tube MP3 and the fourth PMOS tube MP4, as well as the third NMOS tube MN3 and the fourth NMOS tube MN4 to the control signals CLKB and CLK respectively, the reset control of the PMOS and NMOS input unit branches is realized. In the reset stage, by controlling the clock signals CLK and CKLB, the MN3, MP3, MN4, and MP4 of the reset unit reset the nodes Vop1, Von1, Vop2, and Von2 to a fixed level. Since no current path is formed in the circuit, no static power consumption is generated, which helps to reduce the power consumption of the overall system. By controlling the CLKB and CLK signals, M0 and M1 can be in a proper working state.

[0048] In the embodiment of the present invention, reference Figure 1 In the B part, the latch module includes an input unit; the input unit includes a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fifth NMOS tube MN5 and a sixth NMOS tube MN6;

[0049] The gate of the fifth PMOS tube MP5 is connected to the second N-tube signal input terminal Von2; the gate of the sixth PMOS tube MP6 is connected to the first P-tube signal input terminal Vop1; the source of the fifth PMOS tube MP5 is connected to the second reset node Xd; the drain of the fifth PMOS tube MP5 is connected to the drain of the sixth PMOS tube MP6;

[0050] The gate of the fifth NMOS tube MN5 is connected to the second P tube signal input terminal Vop2; the gate of the sixth NMOS tube MN6 is connected to the first N tube signal input terminal Von1; the source of the fifth NMOS tube MN5 is connected to the first reset node Xc; the drain of the fifth NMOS tube MN5 is connected to the drain of the sixth NMOS tube MN6.

[0051] In the latch module input unit, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected to the first P tube signal input terminal and the second P tube signal input terminal Vop1, Vop2 respectively, and the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are connected to the first N tube signal input terminal and the second N tube signal input terminal Von1, Von2 respectively. The direct connection method enhances the efficiency of signal transmission. The input unit enables the latch module to quickly respond to the changes in the amplified signal output by the pre-amplification module and start the positive feedback comparison process.

[0052] refer to Figure 1 In part B, the latch module further includes a latch reset unit; the latch reset unit includes a seventh PMOS tube MP7, a seventh NMOS tube MN7, a tenth PMOS tube MP10 and a tenth NMOS tube MN10;

[0053] The gate of the seventh PMOS transistor MP7 is connected to the second control signal CLK; the source of the seventh PMOS transistor MP7 is connected to the voltage signal VDD; the gate of the seventh PMOS transistor MP7 is connected to the second reset node Xd;

[0054] The gate of the seventh NMOS transistor MN7 is connected to the second control signal CLK; the source of the seventh NMOS transistor MN7 is connected to the voltage signal VDD; and the gate of the seventh NMOS transistor MN7 is connected to the first reset node Xc.

[0055] The gate of the tenth PMOS transistor MP10 is connected to the first control signal CLKB; the source of the tenth PMOS transistor MP10 is connected to the ground signal; the gate of the tenth PMOS transistor MP10 is connected to the fourth reset node Xf;

[0056] The gate of the tenth NMOS transistor MN10 is connected to the first control signal CKLB; the source of the tenth NMOS transistor MN10 is connected to the ground signal; and the gate of the tenth NMOS transistor MN10 is connected to the third reset node Xe.

[0057] In the reset phase, the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 are turned on by the control of the second control signal CLK, and the second reset node Xd and the first reset node Xc are quickly reset to a predetermined state (such as a high level or a low level). This avoids the output voltage of the previous state from affecting the subsequent positive feedback process, and begins to form a signal path in the latching phase. This avoids the comparison offset error caused by different node voltages, and at the same time speeds up the reset speed, avoiding competition between node voltages in the reset phase.

[0058] refer to Figure 1 In part B, the latch module further includes a main unit; the main unit includes an eighth PMOS tube MP8, a ninth PMOS tube MP9, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a first inverter NOT1 and a second inverter NOT2;

[0059] The gate of the eighth PMOS tube MP8 is connected to the gate of the eighth NMOS tube MN8; the source of the eighth PMOS tube MP8 is connected to the voltage signal VDD; the drain of the eighth PMOS tube MP8 is connected to the second reset node Xd;

[0060] The gate of the ninth PMOS tube MP9 is connected to the gate of the eighth PMOS tube MP8; the source of the ninth PMOS tube MP9 is connected to the ground signal; the drain of the ninth PMOS tube MP9 is connected to the drain of the sixth PMOS tube MP6;

[0061] The input node Xp of the first inverter NOT1 is connected to the gate of the eighth PMOS transistor MP8; the output node of the first inverter NOT1 outputs the P output terminal signal OUTP;

[0062] The source of the eighth NMOS transistor MN8 is connected to the voltage signal VDD; the drain of the eighth NMOS transistor MN8 is connected to the first reset node Xc;

[0063] The gate of the ninth NMOS tube MN9 is connected to the gate of the eighth NMOS tube MN8; the source of the ninth NMOS tube MN9 is connected to the ground signal; the drain of the ninth NMOS tube MN9 is connected to the drain of the sixth NMOS tube MN6;

[0064] An input node Xn of the second inverter NOT2 is connected to the gate of the eighth NMOS transistor MN8; an output node of the second inverter NOT2 outputs a P output terminal signal OUTN.

[0065] The first inverter input node Xp, the second inverter input node Xn, the first reset node Xc, the second reset node Xd, the third reset node Xe and the fourth reset node Xf are connected to each other.

[0066] The main unit adopts a positive feedback structure. For example, at the input end, when the input differential signal is amplified by the pre-amplification module, a voltage difference will be generated at the gates of the eighth PMOS transistor MP8 and the eighth NMOS transistor MN8. This voltage difference is amplified through the positive feedback paths of MP8 and MN8, enabling the output nodes OUTP and OUTN to output high or low states accordingly. At the output end, by introducing the first inverter NOT1 and the second inverter NOT2 to shape the output signal, the signal stability can be improved.

[0067] In the embodiments of the present invention, referring to Figure 1 or Figure 1 Part B of, the basic principle of a dynamic comparator provided by the present invention is that due to the potential difference between IP and IN, the discharge speeds of Vop1, Von1, Vop2, and Von2 are different, further causing a voltage difference at the Xp and Xn nodes. Subsequently, through the positive feedback mechanism of the latch and the shaping process of the subsequent inverter, a stable comparison result is finally obtained. The specific process is as follows:

[0068] In the reset stage, when CLK is at a low level, the nodes Von1 and Vop1 are reset to a low level, Von2 and Vop2 are reset to a high level, the latch module transistors MN5, MP5, MN6, and MP6 are turned off, the Xc, Xd, Xp, and Xn nodes are reset to a high level, the Xe and Xf nodes are reset to a low level, and OUTN and OUTP are reset to a low level.

[0069] After entering the comparison stage, when CLK is at a high level, the voltage values output by the nodes Von1, Vop1, Von2, and Vop2 cause the transistors MN5, MP5, MN6, and MP6 to operate, and the latch module enters the positive feedback process, quickly outputting the comparison result:

[0070] If IP > IN, M1 and M0 are turned on, there is Von2 < Vop2, Von1 < Vop1, the latch Xn outputs a high level, Xp outputs a low level, OUTP outputs a high level, and OUTN outputs a low level, completing the comparison;

[0071] If IP < IN, M1 and M0 are turned on, there is Von2 > Vop2, Von1 > Vop1, the latch Xp outputs a high level, Xn outputs a low level, OUTN outputs a high level, and OUTP outputs a low level, completing the comparison.

[0072] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A dynamic comparator, characterized in that: It includes a pre-amplifier module and a latch module; The pre-amplification module includes a differential input unit, a current unit and a reset unit; the differential input unit includes a PMOS input unit and an NMOS input unit; the PMOS input unit is used to access a first input signal, and amplify the first input signal through two branches in the PMOS input unit, and output a first P-tube amplified signal and a second P-tube amplified signal; the NMOS input unit is used to access a second input signal, and amplify the second input signal through two branches in the NMOS input unit, and output a first N-tube amplified signal and a second N-tube amplified signal; the first input signal and the second input signal are differential signals; The latch module has a double-tail dynamic latch structure, including a first P-tube signal input terminal, a second P-tube signal input terminal, a first N-tube signal input terminal and a second N-tube signal input terminal; the first P-tube signal input terminal is connected to the first P-tube amplified signal; the second P-tube signal input terminal is connected to the second P-tube amplified signal; the first N-tube signal input terminal is connected to the first N-tube amplified signal; the second N-tube signal input terminal is connected to the second N-tube amplified signal.

2. The dynamic comparator according to claim 1, characterized in that: The two branches in the PMOS input unit include a first PMOS input unit branch and a second PMOS input unit branch; the first PMOS input unit branch includes a first PMOS tube and a second PMOS tube; The gate of the first PMOS tube and the gate of the second PMOS tube are connected to the first input signal; The drain of the first PMOS tube is connected to the signal input terminal of the first P tube; the source of the first PMOS tube is connected to the current input terminal of the current unit; The drain of the second PMOS tube is connected to the signal input terminal of the second P tube; the source of the second PMOS tube is connected to the current output terminal of the current unit.

3. The dynamic comparator according to claim 1, characterized in that: The two branches in the NMOS input unit include a first NMOS input unit branch and a second NMOS input unit branch; the first NMOS input unit branch includes a first NMOS transistor and a second NMOS transistor; The gate of the first NMOS tube and the gate of the second NMOS tube are connected to the second input signal; The drain of the first NMOS tube is connected to the signal input terminal of the first N tube; the source of the first NMOS tube is connected to the current input terminal of the current unit; The drain of the second NMOS tube is connected to the signal input terminal of the second N tube; the source of the second NMOS tube is connected to the current output terminal of the current unit.

4. The dynamic comparator according to claim 2 or 3, characterized in that: The current unit includes a first tail current tube; The gate of the first tail current tube is connected to the first control signal; the source of the first tail current tube is connected to the voltage signal; the drain of the first tail current tube is connected to the current input end of the current unit.

5. The dynamic comparator according to claim 4, characterized in that: The current unit also includes a second tail current tube; The gate of the second tail current tube is connected to the second control signal; the source of the second tail current tube is connected to the ground signal; the drain of the second tail current tube is connected to the current output end of the current unit; The phase of the second control signal is opposite to that of the first control signal.

6. The dynamic comparator according to claim 5, characterized in that: The reset unit includes a P signal reset unit; the P signal reset unit includes a third PMOS tube and a fourth PMOS tube; The gate of the third PMOS tube is connected to the first control signal; the source of the third PMOS tube is connected to the ground signal; the gate of the third PMOS tube is connected to the gate of the first PMOS tube; The gate of the fourth PMOS tube is connected to the second control signal; the source of the fourth PMOS tube is connected to the voltage signal; the gate of the fourth PMOS tube is connected to the gate of the second PMOS tube.

7. The dynamic comparator according to claim 6, characterized in that: The reset unit further includes an N signal reset unit; the N signal reset unit includes a third NMOS tube and a fourth NMOS tube; The gate of the third NMOS tube is connected to the first control signal; the source of the third NMOS tube is connected to the ground signal; the gate of the third NMOS tube is connected to the gate of the first NMOS tube; The gate of the fourth NMOS tube is connected to the second control signal; the source of the fourth NMOS tube is connected to the voltage signal; the gate of the fourth NMOS tube is connected to the gate of the second NMOS tube.

8. The dynamic comparator according to claim 1, characterized in that: The latch module includes an input unit; the input unit includes a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube; The gate of the fifth PMOS tube is connected to the signal input terminal of the second N tube; the gate of the sixth PMOS tube is connected to the signal input terminal of the first P tube; the source of the fifth PMOS tube is connected to the second reset node; the drain of the fifth PMOS tube is connected to the drain of the sixth PMOS tube; The gate of the fifth NMOS tube is connected to the signal input terminal of the second P tube; the gate of the sixth NMOS tube is connected to the signal input terminal of the first N tube; the source of the fifth NMOS tube is connected to the first reset node; the drain of the fifth NMOS tube is connected to the drain of the sixth NMOS tube.

9. The dynamic comparator according to claim 8, characterized in that: The latch module further includes a latch reset unit; the latch reset unit includes a seventh PMOS tube, a seventh NMOS tube, a tenth PMOS tube and a tenth NMOS tube; The gate of the seventh PMOS tube is connected to the second control signal; the source of the seventh PMOS tube is connected to the voltage signal; the gate of the seventh PMOS tube is connected to the second reset node; The gate of the seventh NMOS tube is connected to the second control signal; the source of the seventh NMOS tube is connected to the voltage signal; the gate of the seventh NMOS tube is connected to the first reset node; The gate of the tenth PMOS tube is connected to the first control signal; the source of the tenth PMOS tube is connected to the ground signal; the gate of the tenth PMOS tube is connected to the fourth reset node; The gate of the tenth NMOS tube is connected to the first control signal; the source of the tenth NMOS tube is connected to the ground signal; the gate of the tenth NMOS tube is connected to the third reset node.

10. The dynamic comparator according to claim 9, characterized in that: The latch module further includes a main unit; the main unit includes an eighth PMOS tube, a ninth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a first inverter and a second inverter; The gate of the eighth PMOS tube is connected to the gate of the eighth NMOS tube; the source of the eighth PMOS tube is connected to the voltage signal; the drain of the eighth PMOS tube is connected to the second reset node; The gate of the ninth PMOS tube is connected to the gate of the eighth PMOS tube; the source of the ninth PMOS tube is connected to the ground signal; the drain of the ninth PMOS tube is connected to the drain of the sixth PMOS tube; The input node of the first inverter is connected to the gate of the eighth PMOS tube; the output node of the first inverter outputs a P output terminal signal; The source of the eighth NMOS tube is connected to the voltage signal; the drain of the eighth NMOS tube is connected to the first reset node; The gate of the ninth NMOS tube is connected to the gate of the eighth NMOS tube; the source of the ninth NMOS tube is connected to the ground signal; the drain of the ninth NMOS tube is connected to the drain of the sixth NMOS tube; The input node of the second inverter is connected to the gate of the eighth NMOS tube; the output node of the second inverter outputs an N output terminal signal; The first inverter input node, the second inverter input node, the first reset node, the second reset node, the third reset node, and the fourth reset node are connected to each other.

Images