Self-calibration circuit and method for offset voltage

Abstract

The invention provides an offset voltage self-calibration circuit and method, the self-calibration circuit comprises a comparator and a logic circuit, and the comparator comprises a first stage circuit and a second stage circuit; the comparator is used for inputting differential signals in a working mode and comparing the differential signals to obtain output signals; in a calibration mode, the differential input end is short-circuited and connected to a common-mode level; the logic circuit is used for sampling the output signal and counting the code density output in a preset time; the offset voltage of the comparator is adjusted in a closed loop mode according to the code density, and the number of the MOS tube arrays is fed back and adjusted; mOS tube arrays are connected in parallel at an output stage of a second-stage circuit of the comparator, system imbalance is introduced to offset random imbalance, a logic circuit is used for sampling code density output by the comparator to detect the magnitude of imbalance voltage, and the number of the MOS tube arrays is fed back and adjusted to adjust the magnitude of the system imbalance; the structure is simple, the stability is ensured, a signal link is not influenced, and the precision of the comparator is improved and adjustable.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a self-calibration circuit and method for offset voltage. Background Art

[0002] At present, the existing offset voltage elimination circuits are as follows Figure 1 As shown, the circuit includes a comparator, a correction unit and a switch unit. The comparator is used to control the input common mode voltage and the comparison voltage according to the enable signal, and after the voltage correction is performed by connecting the common mode voltage, the comparison signal is connected to perform signal comparison output; the correction unit is used to connect the two output terminals OUTP and OUTN of the comparator, and feed back the output signal of the comparator to the input terminal according to the enable signal to offset the offset voltage; the switch unit is used to realize the switching input of the common mode voltage and the comparison voltage through the enable signal. The offset voltage of the comparator can be greatly reduced through this circuit.

[0003] In high-speed communication circuits, not only comparator accuracy but also speed is required. The comparator input is directly connected to the signal path, so the tube area should not be too large, which contradicts the high-precision requirement. The limited tube area will cause batch fluctuations in the chip production process to have a greater impact on random imbalance, so a comparator that can perform self-calibration is needed.

[0004] The current comparator self-calibration technology is to connect the output to the input through a feedback circuit to offset the offset voltage. Since the comparator input is usually connected to the signal path, there are several disadvantages:

[0005] 1) The circuit contains feedback, which introduces an additional loop, complicates the structure and affects stability;

[0006] 2) Input and output affect each other. The input of the comparator is usually a signal input and will be affected by the output load;

[0007] 3) The accuracy is not high enough. It costs a lot to obtain a comparator with higher accuracy. Summary of the invention

[0008] In view of this, the purpose of the present invention is to provide a self-calibration circuit and method for offset voltage, in which a MOS tube array is connected in parallel at the output stage of the second-stage circuit of the comparator, a system offset is introduced to offset the random offset, the code density of the comparator output is sampled by a logic circuit to detect the offset voltage size, and then the number of MOS tube arrays is adjusted by feedback to adjust the system offset size. The circuit structure of the present application is simple, no feedback loop needs to be introduced, stability is guaranteed, the signal link is not affected, the accuracy of the comparator is improved, and the accuracy is adjustable.

[0009] In a first aspect, an embodiment of the present invention provides a self-calibration circuit for offset voltage, wherein the self-calibration circuit comprises a comparator and a logic circuit, wherein the comparator comprises a first-stage circuit and a second-stage circuit, wherein the output stage of the second-stage circuit is connected in parallel to a MOS tube array; and the comparator is connected to the logic circuit;

[0010] The comparator is used to input a differential signal when in working mode, and obtain an output signal after comparing the differential signal; when in calibration mode, the differential input terminal is short-circuited and connected to a common mode level;

[0011] The logic circuit is used to sample the output signal and count the code density output within a preset time; adjust the offset voltage of the comparator in a closed loop according to the code density, and feedback-adjust the number of the MOS tube array.

[0012] Further, the self-calibration circuit further includes a switch group, wherein the switch group includes a first switch, a second switch, a third switch and a fourth switch;

[0013] One end of the first switch is connected to the inverting input terminal, and the other end of the first switch is connected to one end of the third switch and the first input terminal of the comparator respectively;

[0014] One end of the second switch is connected to the in-phase input terminal, the other end of the second switch is respectively connected to one end of the fourth switch and the second input terminal of the comparator, and the other end of the third switch and the other end of the fourth switch are connected to the common mode level.

[0015] Furthermore, the comparator is used for obtaining the differential signal according to the first signal input to the inverting input terminal and the second signal input to the non-inverting input terminal when in the working mode, wherein the first switch and the second switch are both closed, and the third switch and the fourth switch are both opened.

[0016] Furthermore, the comparator is used for, when in calibration mode, the first switch and the second switch are both disconnected, the third switch and the fourth switch are both closed; the first input terminal and the second input terminal are both short-circuited and connected to the common mode level.

[0017] Furthermore, the comparator is used to, when the second signal input to the non-inverting input terminal is greater than the first signal input to the inverting input terminal, the output signal is the power supply voltage, which is identified as a positive level in the digital signal; when the second signal input to the non-inverting input terminal is less than the first signal input to the inverting input terminal, the output signal is grounded, which is identified as a negative level in the digital signal.

[0018] Furthermore, the logic circuit is used to count the number of positive levels and the number of negative levels within the preset time; calculate the ratio of the positive level to the negative level based on the number of positive levels and the number of negative levels; when the ratio is 1, the calibration ends.

[0019] Furthermore, the amplitudes of the in-phase input terminal and the inverting input terminal are equal, and the phase difference is 180 degrees.

[0020] In a second aspect, an embodiment of the present invention provides a self-calibration method for offset voltage, which is applied to the self-calibration circuit for offset voltage as described above, wherein the self-calibration circuit includes a comparator and a logic circuit, wherein the comparator includes a first-stage circuit and a second-stage circuit, wherein the output stage of the second-stage circuit is connected in parallel to a MOS tube array; the method includes:

[0021] When in working mode, the comparator inputs a differential signal and obtains an output signal after comparing the differential signal;

[0022] When in calibration mode, the differential input terminals of the comparator are short-circuited and connected to a common-mode level;

[0023] The logic circuit samples the output signal and counts the code density output within a preset time;

[0024] The offset voltage of the comparator is closed-loop adjusted according to the code density, and the number of the MOS tube array is adjusted by feedback.

[0025] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor implements the method described above when executing the computer program.

[0026] In a fourth aspect, an embodiment of the present invention provides a computer-readable medium having a non-volatile program code executable by a processor, wherein the program code enables the processor to execute the method as described above.

[0027] The embodiment of the present invention provides a self-calibration circuit and method for offset voltage, wherein the self-calibration circuit includes a comparator and a logic circuit, wherein the comparator includes a first-stage circuit and a second-stage circuit, wherein the output stage of the second-stage circuit is connected in parallel with a MOS tube array; the comparator and the logic circuit are connected; the comparator is used to input a differential signal when in working mode, and obtain an output signal after comparing the differential signal; when in calibration mode, the differential input terminal is short-circuited and connected to a common mode level; the logic circuit is used to sample the output signal and count the code density output within a preset time; the offset voltage of the comparator is closed-loop adjusted according to the code density, and the number of MOS tube arrays is adjusted by feedback; the MOS tube array is connected in parallel at the output stage of the second-stage circuit of the comparator, a system offset is introduced to offset the random offset, the code density output by the comparator is sampled by the logic circuit to detect the offset voltage size, and then the number of MOS tube arrays is adjusted by feedback to adjust the system offset size. The circuit structure of the present application is simple, no feedback loop is required, stability is guaranteed, the signal link is not affected, the accuracy of the comparator is improved, and the accuracy is adjustable.

[0028] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A schematic diagram of the structure of an offset voltage elimination circuit provided by the prior art;

[0032] Figure 2 A schematic diagram of the structure of a self-calibration circuit for offset voltage provided in the first embodiment of the present invention;

[0033] Figure 3 A schematic diagram of another self-calibration circuit structure for offset voltage provided in the first embodiment of the present invention;

[0034] Figure 4 A schematic diagram of the circuit structure of a comparator provided in Embodiment 1 of the present invention;

[0035] Figure 5 This is a flow chart of a self-calibration method for offset voltage provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] To facilitate understanding of this embodiment, the embodiment of the present invention is described in detail below.

[0038] Embodiment 1:

[0039] Figure 2 This is a schematic diagram of the structure of a self-calibration circuit for offset voltage provided in Embodiment 1 of the present invention.

[0040] Reference Figure 2 The self-calibration circuit includes a comparator and a logic circuit, the comparator includes a first-stage circuit and a second-stage circuit, wherein the output stage of the second-stage circuit is connected in parallel with a MOS tube array; the comparator and the logic circuit are connected;

[0041] The comparator is used to input a differential signal when in working mode, and obtain an output signal after comparing the differential signal; when in calibration mode, the differential input terminal is short-circuited and connected to a common mode level;

[0042] The logic circuit is used to sample the output signal and count the code density output within a preset time; adjust the offset voltage of the comparator in a closed loop according to the code density, and feedback-adjust the number of MOS tube arrays.

[0043] In this embodiment, a MOS tube array is added to the output stage of the second stage circuit of the comparator to introduce a system offset to offset the random offset, and the offset voltage is detected by sampling the comparator output code density through a logic circuit, and then the number of MOS tube arrays is adjusted by feedback to adjust the system offset. This circuit simplifies the conventional self-calibration comparator circuit, does not introduce a feedback loop, ensures stability, does not affect the signal link, improves the accuracy of the comparator, and the accuracy is adjustable.

[0044] Further, see Figure 3 , the self-calibration circuit further includes a switch group, the switch group includes a first switch, a second switch, a third switch and a fourth switch;

[0045] One end of the first switch is connected to the inverting input terminal, and the other end of the first switch is connected to one end of the third switch and the first input terminal of the comparator respectively;

[0046] One end of the second switch is connected to the in-phase input terminal, the other end of the second switch is respectively connected to one end of the fourth switch and the second input terminal of the comparator, and the other end of the third switch and the other end of the fourth switch are connected to the common mode level.

[0047] Furthermore, the comparator is used for obtaining a differential signal according to the first signal input to the inverting input terminal and the second signal input to the non-inverting input terminal when in the working mode, the first switch and the second switch are both closed, and the third switch and the fourth switch are both opened.

[0048] Specifically, the comparator is configured to switch between the calibration mode and the working mode according to the enable signal. When in the working mode, the first switch S1 and the second switch S2 are both closed, the third switch S3 and the fourth switch S4 are both disconnected, and the input differential signal is compared by the comparator to obtain the output signal. Among them, the differential signal is that both lines of the in-phase input terminal and the inverting input terminal transmit signals, the amplitudes of the in-phase input terminal and the inverting input terminal are equal, and the phase difference is 180 degrees. However, the polarity of the in-phase input terminal and the inverting input terminal is opposite, and the signal finally input into the comparator is the difference between the signals of the two signal lines, so it is called a differential signal. VIN is the inverting input terminal of the differential signal, and VIP is the in-phase input terminal of the differential signal.

[0049] Furthermore, the comparator is used for, when in calibration mode, the first switch and the second switch are both disconnected, the third switch and the fourth switch are both closed; the first input terminal and the second input terminal are both short-circuited and connected to a common mode level.

[0050] Specifically, when in calibration mode, the first switch S1 and the second switch S2 are both disconnected, and the third switch S3 and the fourth switch S4 are both closed. At this time, the differential input terminal of the comparator is short-circuited and connected to VCM; VCM represents the common mode level, that is, the amplitude baseline of the differential signal. The polarity of the differential signal is generally relative to the common mode level, that is, VIP=VCM+V, VIN=VCM-V.

[0051] Furthermore, the comparator is used to output a power supply voltage when the second signal input to the non-inverting input terminal is greater than the first signal input to the inverting input terminal, which is recognized as a positive level in the digital signal; and to ground the output signal when the second signal input to the non-inverting input terminal is less than the first signal input to the inverting input terminal, which is recognized as a negative level in the digital signal.

[0052] Specifically, when the comparator is an ideal comparator, under the interference of random noise, the output signal VOUT should be randomly distributed between 0 and 1, that is, the output signal is sampled for a preset time, and the ratio of the positive and negative levels obtained by sampling is 1.

[0053] When VIP > VIN, VOUT = VDD, which is recognized as 1 in the digital signal (code); when VIP < VIN, VOUT = GND, which is recognized as 0 in the digital signal (code). Here, code is a multi-bit digital signal.

[0054] Furthermore, a logic circuit is used to count the number of positive levels and the number of negative levels within a preset time; calculate the ratio of the positive level to the negative level based on the number of positive levels and the number of negative levels; when the ratio is 1, the calibration ends.

[0055] Specifically, the logic circuit generally refers to a digital circuit, usually composed of various logic gates to implement algorithm functions. The code density refers to the number of 0s or 1s within a preset time. If VIP = VIN, from a statistical perspective, the probabilities of VOUT = 1 and VOUT = 0 are equal under the perturbation of random noise for an ideal comparator. For example, within a preset time (also called the sampling time), assuming it is 100s and the sampling frequency is once per second, finally 100 data are obtained. Theoretically, the ratio of 0s to 1s in these 100 data should be close to 1.

[0056] Refer to Figure 4 , in the circuit structure of the comparator, M8 and M5 are current mirrors. Based on the basic two-stage comparator with positive feedback composed of M1, M2, M3, M4, M6, M7, M8, M9, and M10, a tunable MOS transistor array MOS_ARRAY is connected in parallel at the output stage of the second-stage circuit of the comparator, and the number of MOS transistor arrays connected is controlled by a switch.

[0057] The switch is then controlled by the code density sent by the logic circuit. Increasing or decreasing the number of MOS transistor arrays can make the system offset larger or smaller. By introducing the system offset to cancel the random offset, and the precision is adjustable. The final precision of the comparator depends on the LSB of the MOS transistor array. The LSB of the MOS array can be reduced by increasing the number of bits. Therefore, the comparator precision of this application can be made very high, and adding the MOS transistor array to the output stage of the second stage will not affect the input signal.

[0058] Embodiment 2:

[0059] Figure 5 This is the flowchart of the self-calibration method for the offset voltage provided in Embodiment 2 of the present invention.

[0060] Refer to Figure 5 , applied to the self-calibration circuit for the offset voltage as described above. The self-calibration circuit includes a comparator and a logic circuit. The comparator includes a first-stage circuit and a second-stage circuit, where a MOS transistor array is connected in parallel at the output stage of the second-stage circuit; the method includes the following steps:

[0061] Step S101, when in working mode, the comparator inputs a differential signal, and obtains an output signal after comparing the differential signal;

[0062] Step S102, when in calibration mode, the differential input terminal of the comparator is short-circuited and connected to a common mode level;

[0063] Step S103, the logic circuit samples the output signal and counts the code density output within a preset time;

[0064] Step S104, adjusting the offset voltage of the comparator in a closed loop according to the code density, and feedback-adjusting the number of the MOS tube array.

[0065] An embodiment of the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the offset voltage self-calibration method provided in the above embodiment are implemented.

[0066] An embodiment of the present invention further provides a computer-readable medium having a non-volatile program code executable by a processor. The computer-readable medium stores a computer program. When the computer program is executed by the processor, the steps of the offset voltage self-calibration method of the above embodiment are executed.

[0067] The computer program product provided in the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0068] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0069] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0070] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0071] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0072] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A self-calibration circuit for offset voltage, characterized in that: The self-calibration circuit comprises a comparator and a logic circuit, wherein the comparator comprises a first-stage circuit and a second-stage circuit, wherein the output stage of the second-stage circuit is connected in parallel with a MOS tube array; the comparator is connected to the logic circuit; The comparator is used to input a differential signal when in working mode, and obtain an output signal after comparing the differential signal; when in calibration mode, the differential input terminal is short-circuited and connected to a common mode level; The logic circuit is used to sample the output signal and count the code density output within a preset time; adjust the offset voltage of the comparator in a closed loop according to the code density, and feedback-adjust the number of the MOS tube array.

2. The self-calibration circuit for offset voltage according to claim 1, characterized in that: The self-calibration circuit further includes a switch group, wherein the switch group includes a first switch, a second switch, a third switch and a fourth switch; One end of the first switch is connected to the inverting input terminal, and the other end of the first switch is connected to one end of the third switch and the first input terminal of the comparator respectively; One end of the second switch is connected to the in-phase input terminal, the other end of the second switch is respectively connected to one end of the fourth switch and the second input terminal of the comparator, and the other end of the third switch and the other end of the fourth switch are connected to the common mode level.

3. The self-calibration circuit for offset voltage according to claim 2, characterized in that: The comparator is used for obtaining the differential signal according to the first signal input to the inverting input terminal and the second signal input to the non-inverting input terminal when the first switch and the second switch are both closed and the third switch and the fourth switch are both opened in the working mode.

4. The self-calibration circuit for offset voltage according to claim 2, characterized in that: The comparator is used for, when in calibration mode, the first switch and the second switch are both disconnected, the third switch and the fourth switch are both closed; the first input terminal and the second input terminal are both short-circuited and connected to the common mode level.

5. The self-calibration circuit for offset voltage according to claim 2, characterized in that: The comparator is used for, when the second signal input to the non-inverting input terminal is greater than the first signal input to the inverting input terminal, the output signal is the power supply voltage, which is recognized as a positive level in the digital signal; when the second signal input to the non-inverting input terminal is less than the first signal input to the inverting input terminal, the output signal is grounded, which is recognized as a negative level in the digital signal.

6. The self-calibration circuit for offset voltage according to claim 1, characterized in that: The logic circuit is used to count the number of positive levels and the number of negative levels within the preset time; Calculating a ratio of the positive level to the negative level according to the number of the positive level and the number of the negative level; When the ratio is 1, the calibration is finished.

7. The self-calibration circuit for offset voltage according to claim 2, characterized in that: The amplitudes of the in-phase input terminal and the inverting input terminal are equal, and the phases thereof differ by 180 degrees.

8. A self-calibration method for offset voltage, characterized in that: A self-calibration circuit for offset voltage according to any one of claims 1 to 7, the self-calibration circuit comprising a comparator and a logic circuit, the comparator comprising a first-stage circuit and a second-stage circuit, wherein the output stage of the second-stage circuit is connected in parallel to a MOS tube array; the method comprising: When in working mode, the comparator inputs a differential signal and obtains an output signal after comparing the differential signal; When in calibration mode, the differential input terminals of the comparator are short-circuited and connected to a common-mode level; The logic circuit samples the output signal and counts the code density output within a preset time; The offset voltage of the comparator is closed-loop adjusted according to the code density, and the number of the MOS tube array is adjusted by feedback.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor executes the computer program, the method according to claim 8 is implemented.

10. A computer readable medium having a non-volatile program code executable by a processor, characterized in that: The program code causes the processor to execute the method of claim 8.

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