Readout circuit and image sensing apparatus including the same

Abstract

A readout circuit and an image sensing apparatus including the same are disclosed. The readout circuit includes: a ramp signal generator configured to generate a ramp signal having a first noise; a sampling circuit configured to generate a pixel sampling signal having a second noise by sampling the pixel signal; and a conversion circuit configured to compare the ramp signal with the pixel sampling signal and cancel the first noise and the second noise based on the comparison result.

Description

Technical Field

[0001] Techniques and implementations disclosed in the present disclosure generally relate to a readout circuit and an image sensing device including the readout circuit. Background Art

[0002] The image sensor may include an analog-to-digital converter (ADC) that converts an analog signal output from a pixel array into a digital signal. The ADC may perform cross-correlated double sampling (CDS) on an analog output voltage used as an output signal of the pixel array, and may store a voltage corresponding to a result of the CDS. The ADC may compare a voltage stored by a CDS operation with a predetermined reference voltage in response to a ramp signal generated by a ramp signal generator, and may provide a comparison signal required to generate a digital code.

[0003] In the ramp signal generator, ramp power supply noise and ramp ground noise may occur. In this case, the noise may be transmitted to the column ADC that receives the ramp signal as input, thereby causing signal distortion. Summary of the invention

[0004] Various embodiments of the disclosed technology relate to a readout circuit capable of reducing the influence of power supply noise by canceling noise to be generated in an input stage of an analog-to-digital converter (ADC), and an image sensing device including the readout circuit.

[0005] According to one embodiment of the disclosed technology, a readout circuit may include: a ramp signal generator configured to generate a ramp signal having a first noise; a sampling circuit configured to generate a pixel sampling signal having a second noise by sampling a pixel signal; and a conversion circuit configured to compare the ramp signal with the pixel sampling signal and cancel the first noise and the second noise based on the comparison result.

[0006] According to another embodiment of the disclosed technology, an image sensing device may include: a source follower transistor configured to generate a pixel bias voltage corresponding to a pixel signal; a ramp signal generator configured to generate a ramp signal including a first noise; a bias sampling circuit configured to generate a sampling voltage including a second noise by sampling the pixel bias voltage; a buffer circuit configured to generate a pixel sampling signal by buffering the sampling voltage; and a conversion circuit configured to compare the ramp signal with the pixel sampling signal including the second noise to generate a digital signal based on a result of the comparison.

[0007] It should be understood that the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further description of the claimed invention. These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating an example of an image sensing device including a readout circuit based on some implementations of the disclosed technology.

[0010] Figure 2 This is an example of some implementations based on the disclosed technology. Figure 1 A detailed circuit diagram of an example of a ramp signal generator is shown.

[0011] Figure 3 This is an example of some implementations based on the disclosed technology. Figure 1 A detailed circuit diagram of an example of a sampling circuit is shown.

[0012] Figure 4 This is an example of some implementations based on the disclosed technology. Figure 1 A detailed circuit diagram of an example of a conversion circuit is shown. DETAILED DESCRIPTION

[0013] The present disclosure provides implementations and examples of a readout circuit and an image sensing device including the readout circuit, which can be used in a configuration that substantially solves one or more technical or engineering problems and alleviates limitations or shortcomings faced in some image sensing devices in the art. Some implementations of the disclosed technology relate to a readout circuit and an image sensing device including the readout circuit, which can reduce the impact of power supply noise by offsetting the noise to be generated in the input stage of an analog-to-digital converter (ADC). Recognizing the above problems, a readout circuit based on some implementations of the disclosed technology and an image sensing device including the readout circuit can reduce the impact of noise to be generated in the ADC, thereby preventing signal distortion in the image.

[0014] Reference will now be made in detail to some embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, its specific embodiments are shown in the accompanying drawings by way of example. However, the present disclosure should not be construed as being limited by the embodiments set forth herein.

[0015] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or alternatives of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0016] Figure 1 is a block diagram illustrating an example of an image sensing device 1 including a readout circuit according to some implementations of the disclosed technology.

[0017] Reference Figure 1 An image sensing device 1 based on some implementations of the disclosed technology may include a pixel array 10 , a controller 20 , and a readout circuit 100 .

[0018] The pixel array 10 may generate a pixel signal (VPX) in response to a pixel control signal (PCON) generated by the controller 20. The pixel array 10 may include a plurality of pixels arranged in an array between a plurality of row lines and a plurality of column lines.

[0019] Each of the pixels may include a photoelectric conversion element that generates charge in response to incident light, such as a photodiode, a phototransistor, a clamped photodiode, etc. Each of the pixels may include a pixel circuit for generating a pixel signal. The pixel circuit may include a transfer transistor, a drive (source follower) transistor, a selection transistor, and a reset transistor.

[0020] The controller 20 may generate a pixel control signal (PCON) to control the operation of the pixel array 10. In addition, the controller 20 may generate a control signal (CON) to control the operation of the readout circuit 100.

[0021] The readout circuit 100 may convert a pixel signal (VPX) generated from the pixel array 10 into a digital signal based on a control signal (CON), and may output image data (IDATA). Figure 1 As shown, the readout circuit 100 may include a ramp signal generator 110 , a sampling circuit 120 , a conversion circuit 130 , and a column driver 140 .

[0022] The ramp signal generator 110 may generate a ramp signal (VRAMP) that changes with a slope of a predetermined magnitude based on the control signal (CON). In one embodiment, the ramp signal (VRAMP) may be a signal having a voltage level that increases periodically over time. In another embodiment, the ramp signal (VRAMP) may be a signal having a voltage level that decreases periodically over time.

[0023] The sampling circuit 120 may generate a sampling voltage by sampling the pixel signal (VPX) based on the bias voltage (VBIAS). The sampling circuit 120 may generate a pixel sampling signal (VPX_OUT) by adding sampling noise to the sampling voltage. In one embodiment, the bias voltage (VBIAS) may be a voltage generated by the controller 20.

[0024] The conversion circuit 130 may generate a digital signal (ADC_OUT) based on the ramp signal (VRAMP) and the pixel sampling signal (VPX_OUT). The image sensing device 1 may require an operation of converting an analog signal (e.g., pixel signal VPX) output from the pixel array 10 into a digital signal. For example, the conversion circuit 130 may compare the pixel sampling signal (VPX_OUT) with the ramp signal (VRAMP) and may output a digital signal (ADC_OUT) required to generate a digital code. In one embodiment, the conversion circuit 130 may include an analog-to-digital converter (ADC) that converts an analog signal into a digital signal.

[0025] The column driver 140 may output image data (IDATA) by processing the digital signal (ADC_OUT) received from the conversion circuit 130. The column driver 140 may include a latch or a buffer capable of temporarily storing the digital signal (ADC_OUT). The image data (IDATA) output from the column driver 140 may be provided to a digital signal processor, etc.

[0026] In the readout circuit 100 having the above-mentioned elements, the conversion circuit 130 may receive a ramp signal (VRAMP) and a pixel sampling signal (VPX_OUT) as input signals. However, when the ramp signal (VRAMP) having ramp noise is applied to the conversion circuit 130, signal distortion may occur. Therefore, the sampling circuit 120 based on some implementations of the disclosed technology may add sampling noise to the pixel sampling signal (VPX_OUT), and may transmit the resulting pixel sampling signal (VPX_OUT) having sampling noise to the conversion circuit 130. The sampling circuit 120 may receive the pixel signal (VPX) from the pixel array 10 as input and may add sampling noise to the received signal. According to one embodiment of the disclosed technology, the ramp noise of the ramp signal (VRAMP) and the sampling noise of the pixel sampling signal (VPX_OUT) cancel each other at the input terminal of the conversion circuit 130, thereby removing the noise generated in the conversion circuit 130.

[0027] Figure 2 This is an example of some implementations based on the disclosed technology. Figure 1 A detailed circuit diagram of an example of the ramp signal generator 110 is shown.

[0028] Reference Figure 2 , the ramp signal generator 110 may include a current generator 111 and a load circuit 112 .

[0029] In the illustrated embodiment, the current generator 111 may be connected between the power supply voltage (VDD) input terminal and the load circuit 112. The current generator 111 may generate a current (I1) that increases at a constant speed during an activation period when the control signal (CON) is activated. The ramp signal generator 110 may output a ramp signal (VRAMP) from a node to which the load circuit 112 and the current generator 111 are connected.

[0030] The current generator 111 may include a plurality of transistors (P1-PN) connected between a power supply voltage (VDD) input terminal and a load circuit 112 to receive a plurality of current control signals (PG1-PGN) through gate terminals of the plurality of transistors (P1-PN), respectively. For example, the plurality of transistors (P1-PN) may include PMOS transistors. The current generator 111 may selectively turn on or off the plurality of transistors (P1-PN) based on the plurality of current control signals (PG1-PGN) and thus may adjust the magnitude of the current (I1) flowing in the load circuit 112. In one embodiment, the plurality of current control signals (PG1-PGN) may be included in the control signal (CON).

[0031] The load circuit 112 may control the loading of the ramp signal (VRAMP) and may output the result of such control. The load circuit 112 may include a resistor (R1) connected between the current generator 111 and the ground voltage (VGND) input terminal. In one embodiment, the resistor R1 may have a resistance value of a predetermined size.

[0032] In this way, the voltage of the ramp signal (VRAMP) in the ramp signal generator 110 can be determined based on the power supply voltage (VDD), the ground voltage (VGND), the current (I1), and the value of the resistor (R1). That is, the ramp signal generator 110 can generate a ramp signal (or ramp voltage) (VRAMP) based on the power supply voltage (VDD) or the ground voltage (VGND).

[0033] However, in the ramp signal generator 110, power supply noise caused by the power supply voltage (VDD) or ground noise caused by the ground voltage (VGND) may be included in the ramp signal (VRAMP), so that the resulting ramp signal (VRAMP) including the power supply noise and the ground noise may be output to the conversion circuit 130. In addition, noise generated by the ramp signal generator 110 itself may also be included in the ramp signal (VRAMP), so that the resulting ramp signal (VRAMP) with noise may be output to the conversion circuit 130.

[0034] In this way, the noise of the ramp signal (VRAMP) may include not only the noise generated by the ramp signal generator 110 itself, but also any one of the power supply noise or the ground noise, which will be collectively referred to as the ramp noise (ie, the first noise) hereinafter. Figure 2 , the ramp noise (ie, the first noise) is exemplified by (A).

[0035] The ramp noise may increase the horizontal noise in the image sensing device 1. That is, the ramp noise included in the ramp signal (VRAMP) of the ramp signal generator 110 may be transmitted to the input terminal of the conversion circuit 130 without change. When the ramp noise is transmitted to the input terminal of the conversion circuit 130, signal distortion may occur due to the ramp noise.

[0036] Figure 3 This is an example of some implementations based on the disclosed technology. Figure 1 A detailed circuit diagram of an example of sampling circuit 120 is shown.

[0037] Reference Figure 3 The sampling circuit 120 may include a source follower circuit 121 , a bias sampling circuit 122 and a buffer circuit 123 .

[0038] In one embodiment, the source follower circuit 121 may supply a pixel bias voltage (PBV) to the bias sampling circuit 122 based on the bias voltage (VBIAS). The pixel bias voltage (PBV) may correspond to the pixel signal (VPX) received from the pixel array 10.

[0039] The source follower circuit 121 may include a plurality of transistors (N1, N2). In one embodiment, the plurality of transistors (N1, N2) may be implemented as NMOS transistors.

[0040] In one embodiment, transistor N1 (also referred to as a "source follower transistor") may be connected between a power supply voltage (VDD) input terminal and a node (ND1) such that transistor N1 may receive a pixel signal (VPX) through a gate terminal of transistor N1. Upon receiving the pixel signal (VPX), transistor N1 may supply a pixel bias voltage (PBV) corresponding to a gate-source voltage to node ND1. Transistor N1 may include Figure 1 In the pixel array 10 shown in FIG. 1 , the scope or concept of the disclosed technology is not limited thereto. The following embodiments of the disclosed technology illustrate that the transistor N1 is included in Figure 3 In the source follower circuit 121.

[0041] In one embodiment, transistor N2 (also referred to as a "bias transistor") can be connected between node (ND1) and a ground voltage (VGND) input terminal so that transistor N2 can receive a bias voltage (VBIAS) through a gate terminal of transistor N2. Transistor N2 can bias the voltage of node (ND1) based on the bias voltage (VBIAS). Upon receiving the bias voltage (VBIAS), transistor N2 can supply a pixel bias voltage (PBV) corresponding to the gate-source voltage to node (ND1).

[0042] The pixel bias voltage (PBV) output to the node ND1 may correspond to a value obtained by subtracting the gate-source voltage of the transistor N1 from the voltage of the pixel signal (VPX). That is, when the current flowing through the transistors (N1, N2) is constant, the pixel bias voltage (PBV) corresponds to the gate-source voltage of the transistors (N1, N2), so that the pixel bias voltage (PBV) may not be affected by the ground noise. Therefore, the sampling circuit 120 based on some implementations of the disclosed technology may randomly generate ground noise through the bias sampling circuit 122 to be described later and may transmit the ground noise to the buffer circuit 123.

[0043] The bias sampling circuit 122 may sample the pixel bias voltage (PBV) of the node (ND1) and may transmit the sampled voltage (SPV) to the buffer circuit 123. When the bias sampling circuit 122 transmits the sampled voltage (SPV) to the buffer circuit 123, sampling noise (ground noise) caused by the ground voltage (VGND) may also be transmitted to the buffer circuit 123.

[0044] The bias sampling circuit 122 may include a sampling switch (SW1) and a sampling capacitor (C1). The sampling switch (SW1) may be connected between the node (ND1) and the node (ND2) so that the switching operation may be controlled by a switch control signal (SWC1). In one embodiment, the switch control signal (SWC1) may be included in the control signal (CON). The sampling capacitor C1 may be connected between the node (ND2) and the ground voltage (VGND) input terminal.

[0045] In the bias sampling circuit 122 , when the switch control signal ( SWC1 ) is activated and the sampling switch ( SW1 ) is turned on (connected), the pixel bias voltage (PBV) of the node ( ND1 ) may be transferred to the buffer circuit 123 without change.

[0046] When the switch control signal (SWC1) is disabled and the sampling switch (SW1) changes from the ON state to the OFF state (open circuit), the voltage level of the node (ND2) can be increased through the sampling capacitor (C1). That is, when the sampling switch SW1 is turned off, the sampling noise caused by the ground voltage (VGND) can be transmitted to the node (ND2) through the sampling capacitor (C1). Therefore, if Figure 3 As shown in (B) of , a sampling voltage (SPV) in which sampling noise is added to a pixel bias voltage (PBV) applied to a node (ND2) may be transmitted to the buffer circuit 123.

[0047] In one embodiment, the buffer circuit 123 may generate a pixel sampling signal (VPX_OUT) based on the sampling voltage (SPV) of the bias sampling circuit 122 and may output the pixel sampling signal (VPX_OUT) to the conversion circuit 130. Figure 4 As shown, the conversion circuit 130 to be described later may include capacitors (C2, C3) at the input terminals of the conversion circuit 130. Therefore, the buffer circuit 123 may provide the conversion circuit 130 with a pixel sampling signal (VPX_OUT) buffered with the sampling voltage (SPV), thereby preventing coupling noise from being generated by the capacitors (C2, C3). The buffer circuit 123 may include a constant current source (CC) and a transistor (P3).

[0048] In one embodiment, a constant current source (CC) may be connected between a power supply voltage (VDD) input terminal and the node (ND3). The constant current source (CC) may supply a constant current to the node (ND3).

[0049] Transistor P3 (also referred to as a "load transistor") may be connected between node (ND3) and a ground voltage terminal such that transistor P3 may be connected to node (ND2) through a gate terminal of transistor P3. Transistor P3 may be implemented as a PMOS transistor. Transistor P3 may provide a pixel sampling signal (VPX_OUT) corresponding to a gate-source voltage to conversion circuit 130 based on an output voltage of node (ND2).

[0050] For example, when the sampling voltage (SPV) is at a high level, the transistor P3 may be turned off. When the sampling voltage (SPV) is at a low level, the transistor P3 may be turned on and thus may output a pixel sampling signal (VPX_OUT) at a low level. When the current of the constant current source CC is constant, the transistor P3 may output the pixel sampling signal (VPX_OUT) as a voltage value corresponding to the gate-source voltage. That is, since the pixel sampling signal (VPX_OUT) corresponds to the gate-source voltage of the transistor P3, the noise (referred to as "sampling noise", i.e., the second noise) added to the sampling voltage (SPV) in the bias sampling circuit 122 may be transmitted to the pixel sampling signal (VPX_OUT) (e.g., Figure 3 ).

[0051] Figure 4 This is an example of some implementations based on the disclosed technology. Figure 1 A detailed circuit diagram of an example of the conversion circuit 130 is shown.

[0052] Reference Figure 4 , the conversion circuit 130 may include a first comparison block 131 and a second comparison block 132. In some embodiments, the conversion circuit 130 includes two comparison blocks 131 and 132. However, the scope or concept of the embodiments of the disclosed technology is not limited thereto. Alternatively, each of the comparison blocks may include one level or three or more levels.

[0053] In one embodiment, the first comparison block 131 may compare the ramp signal (VRAMP) with the pixel sampling signal (VPX_OUT), and may output a comparison signal corresponding to the result of the comparison. The first comparison block 131 may include a plurality of capacitors (C2, C3), a plurality of switch elements (SW2, SW3), and a comparator (AMP1).

[0054] The capacitor C2 may be connected to the ramp signal generator 110 and may receive the ramp signal (VRAMP). The capacitor C2 may be connected between an input terminal of the ramp signal (VRAMP) and a first input terminal (IN1) of the comparator (AMP1).

[0055] Capacitor C2 can correct the offset of the comparator (AMP1) and the change of the ramp level. For example, capacitor C2 can perform direct current (DC) blocking on the received ramp signal (VRAMP) and can output the resulting signal to the comparator (AMP1). Here, the expression "DC blocking" can mean an operation of removing the DC component of the signal.

[0056] The capacitor C3 may be connected to the sampling circuit 120 and may receive the pixel sampling signal (VPX_OUT). The capacitor C3 may be connected between an input terminal of the pixel sampling signal (VPX_OUT) and a second input terminal (IN2) of the comparator (AMP1).

[0057] The capacitor C3 can correct the offset of the comparator (AMP1) and the variation of the pixel reset level. For example, the capacitor C3 can perform DC blocking on the received pixel sampling signal (VPX_OUT) and can output the resulting signal to the comparator (AMP1).

[0058] The switch element SW2 may be connected between the first input terminal (IN1) of the comparator (AMP1) and the first output terminal (OUT1) of the comparator (AMP1). The switching operation of the switch element SW2 may be controlled by a switch control signal (SWC2). For example, when the switch element (SW2) is turned on and the first input terminal (IN1) of the comparator (AMP1) is connected to the first output terminal (OUT1), the capacitor C2 and the comparison signal may have the same level, so that the offset of the comparator (AMP1) may be removed.

[0059] The switch element SW3 may be connected between the second input terminal (IN2) of the comparator (AMP1) and the second output terminal (OUT2) of the comparator (AMP1). The switching operation of the switch element SW3 may be controlled by a switch control signal (SWC3).

[0060] The comparator (AMP1) may include a differential operational amplifier (OP-AMP) having a 2-input terminal (IN1, IN2) / 2-output terminal (OUT1, OUT2) structure. For example, the comparator (AMP1) may compare a ramp signal (VRAMP) applied to the first input terminal (IN1) through the capacitor C2 with a pixel sampling signal (VPX_OUT) applied to the second input terminal (IN2) through the capacitor C3 and may output a comparison signal corresponding to the comparison result to the first output terminal (OUT1).

[0061] The second comparison block 132 may compare the comparison signal received from the first comparison block 131 with the ground voltage (VGND) and may output a digital signal (ADC_OUT) corresponding to the result of the comparison. The second comparison block 132 may include a plurality of capacitors (C4, C5), a plurality of switch elements (SW4, SW5) and a comparator (AMP2).

[0062] The capacitor C4 may be connected between the first output terminal (OUT1) of the comparator (AMP1) and the third input terminal (IN3) of the comparator (AMP2). The capacitor C5 may be connected between the ground voltage (VGND) input terminal and the fourth input terminal (IN4) of the comparator (AMP2).

[0063] The switch element SW4 can be connected between the third input terminal (IN3) of the comparator (AMP2) and the third output terminal (OUT3) of the comparator (AMP2). The switching operation of the switch element (SW4) can be controlled by the switch control signal (SWC4). When the switch element SW4 is turned on and the third input terminal (IN3) of the comparator (AMP2) is connected to the third output terminal (OUT3), the output signal of the capacitor C4 and the comparator (AMP2) can have the same level, so that the offset of the comparator (AMP2) can be removed.

[0064] The switch element SW5 may be connected between the fourth input terminal (IN4) of the comparator (AMP2) and the fourth output terminal (OUT4) of the comparator (AMP2). The switching operation of the switch element SW5 may be controlled by a switch control signal (SWC5).

[0065] The comparator (AMP2) may include a differential operational amplifier (OP-AMP) having a 2-input terminal (IN3, IN4) / 2-output terminal (OUT3, OUT4) structure. For example, the comparator (AMP2) may compare a comparison signal applied to the third input terminal (IN3) through the capacitor C4 with a ground voltage (VGND) applied to the fourth input terminal (IN4) through the capacitor C5, and may output a digital signal (ADC_OUT) corresponding to the comparison result to the third output terminal (OUT3).

[0066] The switch control signals (SWC2 to SWC5) may be included in Figure 1 For example, the controller 20 may generate switch control signals (SWC2 ˜ SWC5 ) to control the switching operations of the switch elements ( SW2 ˜ SW5 ) included in the comparison blocks ( 131 , 132 ).

[0067] For example, the controller 20 may selectively activate the switch control signals (SWC2 to SWC5) during the auto-zero period to perform the auto-zero operation. In addition, the controller 20 may selectively activate the switch control signals (SWC2 to SWC5) during the comparison operation period to perform the comparison operation. In one embodiment, the switch control signals (SWC2 to SWC5) may have the same phase. Alternatively, the switch control signals (SWC2 to SWC5) may be signals with opposite phases or may be signals with different phases.

[0068] In the conversion circuit 130 having the above-mentioned elements, the input terminal of the capacitor C2 can be connected to the output terminal of the ramp signal generator 110, so that the ramp noise included in the ramp signal (VRAMP) can be input to one terminal of the capacitor C2 without change. In addition, since the input terminal of the capacitor C3 in the conversion circuit 130 is connected to the output terminal of the sampling circuit 120, the sampling noise included in the pixel sampling signal (VPX_OUT) can be input to one terminal of the capacitor C3 without change. In this case, as Figure 4 As shown in (D), when the first comparison block 121 performs a differential operation, the ramp noise and the sampling noise can cancel each other.

[0069] That is to say, as mentioned above Figure 2 , when ramp noise is transmitted to one terminal of the conversion circuit 130 (i.e., the input terminal of the capacitor C2), signal distortion may occur due to the ramp noise. According to one embodiment of the disclosed technology, sampling noise may be generated by the sampling circuit 120 and transmitted to the other terminal of the conversion circuit 130 (i.e., the input terminal of the capacitor C3), so that the noise levels of the two input terminals of the conversion circuit 130 may be maintained at the same level, thereby canceling the noise to be input to the conversion circuit 130.

[0070] According to one embodiment of the disclosed technology, when ground noise is added to the ramp signal (VRAMP) of the ramp signal generator 110, the sampling circuit 120 may sample the ground noise and add the sampled result to the pixel sampling signal (VPX_OUT). However, the scope or concept of the embodiments of the disclosed technology is not limited thereto, and as another example, when power supply noise is added to the ramp signal (VRAMP) of the ramp signal generator 110, the sampling circuit 120 may add power supply noise to the pixel sampling signal (VPX_OUT) as needed.

[0071] As is apparent from the above description, a readout circuit based on some implementations of the disclosed technology and an image sensing device including the readout circuit can reduce the influence of noise to be generated in an ADC, thereby preventing signal distortion from occurring in an image.

[0072] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the present disclosure.

[0073] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be designed based on what is described and / or illustrated in this disclosure. In addition, the embodiments may be combined to form additional embodiments.

[0074] CROSS-REFERENCE TO RELATED APPLICATIONS

[0075] This patent application claims priority to and the benefit of Korean Patent Application No. 10-2023-0111033, filed on August 24, 2023, which is hereby incorporated by reference in its entirety as a part of this disclosure.

Claims

1. A readout circuit, the readout circuit comprising: a ramp signal generator, the ramp signal generator generating a ramp signal having a first noise; a sampling circuit, wherein the sampling circuit generates a pixel sampling signal having a second noise by sampling the pixel signal; as well as A conversion circuit compares the ramp signal with the pixel sampling signal and cancels the first noise and the second noise based on a result of the comparison.

2. The readout circuit according to claim 1, wherein: The ramp signal generator comprises: a current generator that generates a current based on a control signal; and a load circuit, the load circuit controlling the loading of the current generator, The ramp signal generator outputs the ramp signal to a first node to which the current generator and the load circuit are connected.

3. The readout circuit according to claim 2, wherein: The current generator comprises: A plurality of transistors are connected to the load circuit and a power supply voltage input terminal and are selectively turned on or off based on the control signal.

4. The readout circuit according to claim 2, wherein: The load circuit comprises: A resistor is connected between the first node and a ground voltage input terminal.

5. The readout circuit according to claim 4, wherein: The ramp signal generator adds the first noise generated from the ground voltage input terminal to the ramp signal through the resistor.

6. The readout circuit according to claim 1, wherein: The sampling circuit comprises: a source follower circuit, wherein the source follower circuit generates a pixel bias voltage corresponding to the pixel signal based on a bias voltage; a bias sampling circuit that samples the pixel bias voltage and generates a sampled voltage to which the second noise is added; and A buffer circuit is provided to generate the pixel sampling signal based on the sampling voltage.

7. The readout circuit according to claim 6, wherein: The source follower circuit comprises: a source follower transistor connected between a power supply voltage input terminal and a second node and receiving the pixel signal through a gate terminal of the source follower transistor; and a bias transistor connected between the second node and a ground voltage input terminal and receiving the bias voltage through a gate terminal of the bias transistor, The source follower circuit outputs the pixel bias voltage through the second node.

8. The readout circuit according to claim 6, wherein: The bias sampling circuit comprises: a sampling switch connected between an input terminal for receiving the pixel bias voltage and a third node to control a switching operation by a first switch control signal; and A sampling capacitor is connected between the third node and a ground voltage input terminal.

9. The readout circuit according to claim 8, wherein: The bias sampling circuit: transmitting the pixel bias voltage to the buffer circuit when the sampling switch is turned on based on the first switch control signal; and When the sampling switch is turned off based on the first switch control signal, the second noise is added to the sampling voltage through the sampling capacitor.

10. The readout circuit according to claim 6, wherein: The buffer circuit comprises: a constant current source connected between the power supply voltage input terminal and the fourth node; and A load transistor is connected between the fourth node and a ground voltage input terminal to receive the sampling voltage through a gate terminal of the load transistor.

11. The readout circuit according to claim 1, wherein: The conversion circuit comprises: An analog-to-digital converter ADC compares the ramp signal with the pixel sampling signal and generates a digital signal based on a result of the comparison.

12. The readout circuit according to claim 1, wherein: The conversion circuit comprises: A first comparison block is provided, wherein the first comparison block compares the ramp signal including the first noise with the pixel sampling signal including the second noise.

13. The readout circuit according to claim 12, wherein: The first comparison block further includes: a first capacitor connected between an input terminal for receiving the ramp signal and a first input terminal; a second capacitor connected between an input terminal for the pixel sampling signal and a second input terminal; and A first comparator generates a comparison signal by comparing a signal on the first input terminal with a signal on the second input terminal.

14. The readout circuit according to claim 13, wherein: The first comparison block further includes: a first switching element connected between the first input terminal and a first output terminal of the first comparator to control a switching operation by a second switching control signal; and A second switching element is connected between the second input terminal and a second output terminal of the first comparator to control a switching operation by a third switching control signal.

15. The readout circuit according to claim 12, wherein: The conversion circuit also includes: A second comparison block compares the output signal of the first comparison block with a ground voltage and generates a digital signal based on a result of the comparison.

16. The readout circuit according to claim 15, wherein: The second comparison block includes: a third capacitor connected between the third input terminal and the first output terminal of the first comparison block; a fourth capacitor connected between the ground voltage input terminal and the fourth input terminal; and A second comparator generates the digital signal by comparing the signal on the third input terminal with the signal on the fourth input terminal.

17. The readout circuit according to claim 16, wherein: The second comparison block further includes: a third switching element connected between the third input terminal and a third output terminal of the second comparator to control a switching operation by a fourth switching control signal; and A fourth switching element is connected between the fourth input terminal and a fourth output terminal of the second comparator to control a switching operation by a fifth switching control signal.

18. An image sensing device, comprising: A source follower transistor, wherein the source follower transistor generates a pixel bias voltage corresponding to a pixel signal; a ramp signal generator, the ramp signal generator generating a ramp signal including a first noise; a bias sampling circuit, wherein the bias sampling circuit generates a sampling voltage including a second noise by sampling the pixel bias voltage; a buffer circuit, wherein the buffer circuit generates a pixel sampling signal by buffering the sampling voltage; as well as A conversion circuit compares the ramp signal with the pixel sampling signal including the second noise to generate a digital signal based on a result of the comparison.

19. The image sensing device according to claim 18, wherein: The conversion circuit: receiving the ramp signal including the first noise through a first input terminal; receiving the pixel sampling signal including the second noise through a second input terminal; and The ramp signal is compared with the pixel sampling signal, thereby canceling the first noise and the second noise through a result of the comparison.

20. The image sensing device according to claim 18, wherein: The bias sampling circuit comprises: a sampling switch connected between an input terminal for receiving the pixel bias voltage and a first node to control a switching operation by a switch control signal; and A sampling capacitor is connected between the first node and a ground voltage input terminal.

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