Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method of the semiconductor structure, and the semiconductor structure comprises a substrate which is internally provided with a word line groove extending from the top surface of the substrate to the interior of the substrate, the word line groove also extends along a first direction, and the first direction is parallel to a plane where the top surface of the substrate is located; the embedded word line structure is located in the word line groove, the word line structure comprises a gate dielectric layer, a gate conductive layer and an insulating cover layer which are stacked in sequence, and the gate dielectric layer covers the bottom and at least part of the side wall of the word line groove; the gate conducting layer covers the bottom of the word line groove and the surface of the gate dielectric layer on the partial side wall area in contact with the bottom, and the insulating cover layer is located on the top surface of the gate conducting layer; wherein the gate conducting layer comprises a metal material conducting layer, a semiconductor material conducting layer and an air gap, and the semiconductor material conducting layer and the air gap are embedded into and occupy part of the side wall of the metal material conducting layer. The semiconductor structure has good electrical performance.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] A dynamic random access memory device (DRAM) is a type of volatile memory. DRAM devices generally include a memory array region consisting of memory cells, and a peripheral region consisting of logic control circuits. A typical memory cell includes a switch structure (such as a transistor) and a storage structure (such as a capacitor). The logic control circuit in the peripheral region can address each memory cell in the memory array region through multiple word lines (word lines) and multiple bit lines (bit lines) that pass through the memory array region, and open the switch structure to electrically connect the storage structure to perform data reading, writing, or access.

[0003] However, due to the demand for large-capacity storage and high integration, the size of memory devices has shrunk dramatically. How to ensure and improve the electrical performance of the word line structure in the memory array area has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate, wherein the substrate has a word line groove extending from the top surface of the substrate toward the inside of the substrate, and the word line groove also extends along a first direction, and the first direction is parallel to the plane where the top surface of the substrate is located; a word line structure, located in the word line groove, the word line structure comprising a gate dielectric layer, a gate conductive layer and an insulating cap layer stacked in sequence, the gate dielectric layer covers the bottom and at least a portion of the sidewalls of the word line groove, the gate conductive layer covers the surface of the gate dielectric layer located at the bottom of the word line groove and the portion of the sidewalls in contact with the bottom, and the insulating cap layer is located on the top surface of the gate conductive layer; the gate conductive layer also includes a metal material conductive layer and a semiconductor material conductive layer, and the word line structure also includes an air gap, wherein the semiconductor material conductive layer and the air gap are embedded in and occupy a portion of the sidewalls of the metal material conductive layer.

[0005] In some embodiments, the air gap is located on top of the conductive layer of semiconductor material and is in direct contact with the top of the conductive layer of semiconductor material.

[0006] In some embodiments, the ratio of the height of the air gap to the height of the semiconductor material conductive layer is 1:3, and the height direction is a direction perpendicular to the substrate surface.

[0007] In some embodiments, the sum of the height of the air gap and the height of the semiconductor material conductive layer is in the range of 30 to 45 nm.

[0008] In some embodiments, the thickness of the air gap is greater than or equal to the thickness of the conductive layer of the semiconductor material, the thickness ranges from 2.5 to 4.5 nm, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

[0009] In some embodiments, in the same word line groove, the number of the air gap and the semiconductor material conductive layer is two, which are respectively located on two opposite side walls of the metal material conductive layer, and are mirror-symmetrically arranged about the central axis plane of the metal material conductive layer, and the central axis plane is perpendicular to the top surface of the substrate and extends along the first direction.

[0010] In some embodiments, the portion of the sidewall of the metal material conductive layer embedded and occupied by the semiconductor material conductive layer and the air gap is located in a region close to the top of the metal material conductive layer.

[0011] In some embodiments, the conductive layer of metal material includes a first sub-part and a second sub-part, the second sub-part is located on the top of the first sub-part, and the conductive layer of semiconductor material and the air gap are located on both sides of the second sub-part; wherein the sum of the heights of the conductive layer of semiconductor material and the air gap is less than or equal to the height of the second sub-part, the height direction is a direction perpendicular to the surface of the substrate, the average thickness of the second sub-part is less than the maximum thickness of the first sub-part, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

[0012] In some embodiments, a ratio of the height of the second sub-portion to that of the first sub-portion ranges from 1:2 to 1:1; and a ratio of the average thickness of the second sub-portion to the maximum thickness of the first sub-portion ranges from 1:3 to 2:3.

[0013] In some embodiments, the substrate further includes an active region and an isolation structure, a plurality of the active regions are distributed in an array, the isolation structure is located between adjacent active regions, and the word line structure passes through the plurality of active regions and the isolation structure.

[0014] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a word line groove on the surface of the substrate extending from the top surface of the substrate toward the inside of the substrate, and the word line groove also extends along a first direction, and the first direction is parallel to the plane where the top surface of the substrate is located; forming a word line structure in the word line groove, comprising forming a gate dielectric layer, a gate conductive layer and an insulating cap layer stacked in sequence in the word line groove, the gate dielectric layer covers the bottom and at least part of the sidewall of the word line groove, the gate conductive layer covers the surface of the gate dielectric layer located at the bottom of the word line groove and the part of the sidewall area contacting the bottom, and the insulating cap layer is formed on the top surface of the gate conductive layer; the gate conductive layer also includes a metal material conductive layer and a semiconductor material conductive layer, and the word line structure also includes an air gap, wherein the semiconductor material conductive layer and the air gap are embedded in and occupy part of the sidewall of the metal material conductive layer.

[0015] In some embodiments, a gate dielectric layer, a gate conductive layer, and an insulating cap layer are sequentially stacked in the word line groove, including: forming the gate dielectric layer at the bottom and at least a portion of the sidewalls of the word line groove; forming the metal material conductive layer on the surface of the gate dielectric layer; forming the semiconductor material conductive layer on a portion of the sidewalls of the metal material conductive layer; forming the insulating cap layer on the top surface of the metal material conductive layer, forming the air gap between the insulating cap layer and the semiconductor material conductive layer, the air gap is located on the top of the semiconductor material conductive layer, and the air gap is in direct contact with the top of the semiconductor material conductive layer.

[0016] In some embodiments, the metal material conductive layer is formed on the surface of the gate dielectric layer, and the semiconductor material conductive layer is formed on a portion of the side wall of the metal material conductive layer, including: forming a first sub-portion of the metal material conductive layer on the surface of the gate dielectric layer; forming the semiconductor material conductive layer and a second sub-portion of the metal material conductive layer on the top of the first sub-portion, and the semiconductor material conductive layer and the air gap are located on both sides of the second sub-portion; wherein the sum of the heights of the semiconductor material conductive layer and the air gap is less than or equal to the height of the second sub-portion, the height direction is a direction perpendicular to the substrate surface, the average thickness of the second sub-portion is less than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

[0017] In some embodiments, the metal material conductive layer is formed on the surface of the gate dielectric layer, and the semiconductor material conductive layer is formed on a portion of the sidewall of the metal material conductive layer, including: forming an initial metal material conductive layer on the surface of the gate dielectric layer; etching a portion of the sidewall of the initial metal material conductive layer to form the metal material conductive layer including a first sub-portion and a second sub-portion, the second sub-portion being located on the top of the first sub-portion; forming the semiconductor material conductive layer on the sidewall of the second sub-portion; wherein the sum of the heights of the semiconductor material conductive layer and the air gap is less than or equal to the height of the second sub-portion, the height direction is a direction perpendicular to the substrate surface, the average thickness of the second sub-portion is less than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

[0018] In some embodiments, before forming the word line groove, it also includes: forming an active area and an isolation structure on the surface of the substrate, a plurality of the active areas are distributed in an array, and the isolation structure is located between adjacent active areas; after forming the word line groove, the word line groove passes through the plurality of the active areas and the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0020] Figure 2 is a schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0021] Figure 3 is a schematic diagram showing providing a substrate according to an exemplary embodiment;

[0022] Figure 4 is a schematic diagram showing the formation of an isolation structure and an active region according to an exemplary embodiment;

[0023] Figure 5 is a schematic diagram showing a method of forming a word line structure according to an exemplary embodiment;

[0024] Figure 6 is a schematic diagram of specific steps of forming a word line structure according to an exemplary embodiment 1;

[0025] Figure 7 is a schematic diagram of specific steps of forming a word line structure according to a second exemplary embodiment;

[0026] Figure 8 is a schematic diagram of specific steps of forming a word line structure according to a third exemplary embodiment;

[0027] Fig. 9is a schematic diagram showing a memory structure according to an exemplary embodiment. DETAILED DESCRIPTION

[0028] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0029] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0030] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0031] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0032] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0033] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0034] In the related art, the process flow of the dynamic random access memory (DRAM) structure usually requires the formation of storage cell related structures in the storage array area, such as storage transistors, storage capacitors, bit lines, word lines and other structures. The inventors of the present application have found that: with the continuous demand for large-capacity storage and high integration, the related electrical performance of the word line structure has seriously declined after the size is further reduced, such as the increase of gate-induced drain leakage (GIDL), the decrease of saturation current (IDR), the increase of word line impedance and other problems, which seriously affect the transistor switch, the memory cannot work normally, and the device reliability is reduced.

[0035] In view of the above technical problems, the present disclosure provides a semiconductor structure and a method for preparing the same. Figures 1 to 9 A semiconductor structure and a method for preparing the semiconductor structure exemplarily provided by the present disclosure are specifically introduced. Figure 1 to Figure 2 is a schematic diagram of a semiconductor structure according to multiple exemplary embodiments of the present disclosure. Figures 3 to 8 is a schematic diagram of a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure. Fig. 9 It is a schematic diagram of a memory structure according to an exemplary embodiment of the present disclosure.

[0036] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, referring to Figure 1 , Figure 2 or Figure 5 As shown, Figure 1 or Figure 2 It is a schematic cross-sectional view along the plane of the third direction Z and the second direction Y. Figure 5 (a) is a top view showing the top surface of the substrate 1 in the opposite direction of the third direction Z, Figure 5 (b) along Figure 5 (a) Schematic diagram of the cross section along the A-A' direction. The semiconductor structure comprises: a substrate 1, wherein the substrate 1 has a word line groove 100 extending from the top surface of the substrate 1 toward the inside of the substrate 1, and the word line groove 100 also extends along a first direction X, and the first direction X is parallel to the plane where the top surface of the substrate 1 is located; a word line structure 10, located in the word line groove 100, the word line structure 10 comprises a gate dielectric layer 101, a gate conductive layer 102 and an insulating cap layer 103 stacked in sequence, the gate dielectric layer 101 covers the bottom and at least part of the sidewall of the word line groove 100, the gate conductive layer 102 covers the surface of the gate dielectric layer 101 located at the bottom of the word line groove 100 and on part of the sidewall in contact with the bottom, and the insulating cap layer 103 is located on the top surface of the gate conductive layer 102; the word line structure 10 also comprises an air gap 104, the gate conductive layer 102 comprises a metal material conductive layer 1021 and a semiconductor material conductive layer 1022, wherein the semiconductor material conductive layer 1022 and the air gap 104 are embedded in and occupy part of the sidewall of the metal material conductive layer 1021.

[0037] The material of the substrate 1 may be at least one of the following materials: semiconductor materials or III-V materials such as silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In an exemplary embodiment of the present disclosure, the material of the substrate 1 is single crystal silicon.

[0038] The word line groove 100 is located in the substrate 1, extending from the top surface of the substrate 1 toward the inside of the substrate 1, that is, the opening of the word line groove 100 is on the top surface of the substrate 1, and the depth direction of the groove is perpendicular to the plane where the top surface of the substrate 1 is located and faces the inside of the substrate 1, which is opposite to the third direction Z. On the plane parallel to the top surface of the substrate 1, the word line groove 100 also extends along the first direction X, which can be referred to Figure 5 As shown in (a), the word line structure 10 located in the word line trench 100 extends along a first direction X. In some embodiments, Figure 1 or Figure 2 As shown, the cross-sectional schematic diagram of the word line trench 100 is rectangular, that is, the opening size and the bottom size of the word line trench 100 are substantially consistent. In other embodiments, the cross-sectional schematic diagram of the word line trench 100 is trapezoidal, for example, the opening size of the word line trench 100 is larger than the bottom size, or the bottom size of the word line trench 100 is larger than the opening size.

[0039] The gate dielectric layer 101 covers the bottom and at least a portion of the sidewalls of the word line trench 100. Figure 1 or Figure 2 As shown, the gate dielectric layer 101 covers the bottom and all sidewalls of the word line trench 100. In other embodiments, the gate dielectric layer 101 only covers the bottom of the word line trench 100 and the sidewalls of the portion of the height that contacts the bottom (not shown). The material of the gate dielectric layer 101 can be any one or more combinations of silicon oxide, hafnium oxide, zirconium oxide, and aluminum oxide. In an exemplary embodiment of the present disclosure, the material of the gate dielectric layer 101 is silicon oxide.

[0040] The gate conductive layer 102 covers the surface of the gate dielectric layer 101 located at the bottom of the word line trench 100 and on the portion of the sidewall in contact with the bottom. In some embodiments, the gate conductive layer 102 fills the bottom of the word line trench 100 and covers the gate dielectric layer 101 on the portion of the sidewall from the bottom to the depth of 1 / 3 to 2 / 3 of the word line trench 100. Specifically, in the word line trench 100, the top surface of the gate dielectric layer 101 is higher than the gate conductive layer 102.

[0041] The gate conductive layer 102 includes a metal conductive layer 1021 and a semiconductor conductive layer 1022. In some embodiments, the metal conductive layer 1021 occupies a main portion of the gate conductive layer 1021, and the semiconductor conductive layer 1022 is embedded in and occupies a portion of the sidewall of the metal conductive layer 1021.

[0042] In some embodiments, the metal material conductive layer 1021 includes a first sub-portion 1021a and a second sub-portion 1021b, and the second sub-portion 1021b is located on top of the first sub-portion 1021a. In some embodiments, in the same word line trench 100, there are two semiconductor material conductive layers 1022, which are located on both sides of the second sub-portion 1021b, and are arranged in a mirror-symmetrical manner with respect to the central axis of the metal material conductive layer 1021.

[0043] In some embodiments, the average thickness of the second sub-portion 1021b is less than the maximum thickness of the first sub-portion 1021a. In some embodiments, the ratio of the height of the second sub-portion 1021b to the height of the first sub-portion 1021a is in the range of 1:2 to 1:1; the ratio of the average thickness of the second sub-portion 1021b to the maximum thickness of the first sub-portion 1021a is in the range of 1:3 to 2:3. It should be noted that the thickness direction is parallel to the plane where the top surface of the substrate 1 is located and is perpendicular to the first direction X, and the height direction is perpendicular to the surface of the substrate 1, that is, the same direction as the third direction Z.

[0044] In some embodiments, the material of the metal material conductive layer 1021 can be any one or more combinations of tungsten, titanium, molybdenum, ruthenium, tungsten nitride, titanium nitride, molybdenum nitride, and ruthenium nitride, and the material of the semiconductor material conductive layer 1022 can be any one or more combinations of doped polysilicon, polycrystalline germanium, or polycrystalline silicon germanium. In an exemplary embodiment of the present disclosure, the material of the metal material conductive layer 1021 is titanium nitride, and the semiconductor material conductive layer is doped polysilicon.

[0045] In some embodiments, the second sub-portion 1021b and the first sub-portion 1021a may be made of the same material, for example, both are titanium nitride. In other embodiments, the second sub-portion 1021b and the first sub-portion 1021a may be made of different materials, for example, the first sub-portion 1021a may be made of titanium nitride and the second sub-portion 1021b may be made of tungsten.

[0046] In some embodiments, Figure 1 As shown in FIG. 1 , the second sub-portion 1021b and the first sub-portion 1021a may be formed as two independent parts. In other embodiments, such as Figure 2 As shown, the second sub-portion 1021b and the first sub-portion 1021a are integrally formed. It should be noted that, Figure 2The dotted line is only used to schematically distinguish the first sub-portion 1021a from the second sub-portion 1021b. In the actual structure, since it is integrally formed, there is no substantial dividing line or interface.

[0047] The insulating capping layer 103 is located on the top surface of the gate conductive layer 102. Specifically, the insulating capping layer 103 fills the word line trench 100 located above the top surface of the second sub-portion 1021b of the metal material conductive layer 1021 of the gate conductive layer 102, and the lowest bottom surface of the insulating capping layer 103 is flush with the top surface of the second sub-portion 1021b, or slightly lower than the top surface of the second sub-portion 1021b. In some embodiments, the gate dielectric layer 101 covers the bottom and all sidewalls of the word line trench 100, and the insulating capping layer 103 covers the surface of the gate dielectric layer 101 located on the sidewalls of the top region of the word line trench 100. In other embodiments, the gate dielectric layer 101 covers the bottom and part of the sidewalls of the word line trench 100, that is, the sidewalls except the sidewalls of the top region of the word line trench 100, and the insulating capping layer 103 directly covers the sidewalls located on the top region of the word line trench 100, and is located on the top surface of the gate dielectric layer 101 and directly contacts the top surface of the gate dielectric layer 101. In some embodiments, the insulating cap layer 103 may be made of at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride. In an exemplary embodiment of the present disclosure, the insulating cap layer 103 is made of silicon nitride.

[0048] The word line structure 10 further includes an air gap 104, which is embedded in and occupies a portion of the sidewall of the metal material conductive layer 1021. Specifically, the air gap 104 is surrounded by the top surface of the semiconductor material conductive layer 1022, a portion of the side surface of the second sub-portion 1021b, a portion of the surface of the gate dielectric layer 101, and the bottom surface of the insulating cap layer 103. In some embodiments, the air gap 104 is located on the top of the semiconductor material conductive layer 1022 and is in direct contact with the top of the semiconductor material conductive layer 1022.

[0049] In some embodiments, the ratio of the height of the air gap 104 to the height of the semiconductor material conductive layer 1022 is 1:3. In an exemplary embodiment of the present disclosure, the sum of the height of the air gap 104 and the height of the semiconductor material conductive layer 1022 is in the range of 30 to 45 nm, for example, 30 nm, 35 nm, 40 nm, 45 nm. In an exemplary embodiment of the present disclosure, the thickness of the air gap 104 is greater than or equal to the thickness of the semiconductor material conductive layer 1022, and the thickness ranges from 2.5 to 4.5 nm, for example, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm. It should be noted that the above-mentioned height direction is a direction perpendicular to the surface of the substrate 1, that is, in the same direction as the third direction Z, and the above-mentioned thickness direction is parallel to the plane where the top surface of the substrate 1 is located and perpendicular to the first direction X.

[0050] In some embodiments, Figure 5 As shown, the substrate 1 further includes an active region 11 and an isolation structure 12. The multiple active regions 11 are distributed in an array. The isolation structure 12 is located between adjacent active regions 11. The word line structure 10 passes through the multiple active regions 11 and the isolation structure 12. Figure 5 As shown in (a) and 5(b), the isolation structure 12 is a shallow trench isolation structure (STI), which divides a portion of the surface area of ​​the substrate 1 into a plurality of active areas 11; the plurality of active areas 11 are arranged in a staggered array, and are used to subsequently form source, drain and channel areas of transistors; a plurality of word line structures 10 extend along a first direction X and are arranged at equal intervals along a second direction Y, and pass through the plurality of active areas 11 and the isolation structure 12; wherein the depth of the word line structure 10 or the word line trench 100 is less than the depth of the isolation structure 12. In some embodiments, the same active area 11 is passed through by two adjacent word line structures 11, so that two transistors sharing one of the source and drain areas are subsequently formed in the active area 11.

[0051] In some embodiments, the material of the isolation structure 12 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of the present disclosure, the material of the isolation structure 12 is silicon oxide. In some embodiments, the active region 11 may be doped with N-type or P-type elements, specifically, the N-type elements include group V elements, such as phosphorus, arsenic, antimony, or bismuth, and the P-type elements include group III elements, such as boron, aluminum, gallium, or indium.

[0052] The semiconductor structure provided by the present invention has a word line structure including a gate dielectric layer, a gate conductive layer, an insulating cap layer and an air gap stacked in sequence, the gate conductive layer is a metal material conductive layer and a semiconductor material conductive layer, the semiconductor material conductive layer and the air gap are embedded in and occupy part of the side wall of the metal material conductive layer, and only a suitably thin thickness is required to allow the metal material conductive layer to maintain a larger conduction area to reduce the word line impedance. On the one hand, the semiconductor material conductive layer has a lower work function than the metal material conductive layer, and the semiconductor material conductive layer is embedded in part of the sidewall of the metal material conductive layer and is located at the end of the channel region in the transistor to be formed subsequently, which can effectively reduce the gate induced drain leakage (GIDL) problem, and the higher height can also effectively increase the drain saturation current (IDR); on the other hand, the air gap has a lower dielectric constant and is configured to be embedded in part of the sidewall of the metal material conductive layer, which can effectively reduce the coupling effect between adjacent word line structures or between the word line structure and other subsequently formed devices (for example: bit line structure, storage contact structure, etc.), and avoid crosstalk between adjacent structures; in addition, the air gap is located on the top of the semiconductor material conductive layer and is in direct contact with the top of the semiconductor material conductive layer, and the higher height of the air gap further reduces the gate induced drain leakage (GIDL). Based on the above characteristics, the word line structure with the height and thickness of the semiconductor material conductive layer and the air gap is appropriately adjusted, taking into account the characteristics of high drain saturation current (IDR), low gate induced drain leakage (GIDL), and low word line impedance, thereby improving the working performance of the storage device.

[0053] Based on the above semiconductor structure, the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a substrate 1, such as Figure 3 As shown, Figure 3 (a) is a top view toward the substrate in the opposite direction of the third direction Z, Figure 3 (b) along Figure 3 (a) is a schematic cross-sectional view along the dotted line AA', where the cross-section along the dotted line AA' is perpendicular to the top surface of the substrate 1.

[0054] The material of the substrate 1 may be at least one of the following materials: semiconductor materials or III-V materials such as silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In an exemplary embodiment of the present disclosure, the material of the substrate 1 is single crystal silicon.

[0055] Next, an active region 11 and an isolation structure 12 are formed on the surface of the substrate 1. The multiple active regions 11 are distributed in an array, and the isolation structure 12 is located between adjacent active regions 11. Figure 4 As shown, Figure 4(a) is a top view toward the substrate in the opposite direction of the third direction Z, Figure 4 (b) along Figure 4 (a) is a schematic cross-sectional view along the dotted line A-A', wherein the cross-section along the dotted line A-A' is perpendicular to the top surface of the substrate 1. Specifically, a shallow trench isolation structure (STI) is formed on the surface of the substrate 1 as an isolation structure 12 to divide a portion of the surface area of ​​the substrate 1 into a plurality of active areas 11 arranged in an array. More specifically, the substrate 1 can be etched to form shallow trenches, which divide the surface of the substrate 1 into a plurality of active areas 11 arranged in an array, and then an isolation material is filled in the shallow trenches to form an isolation structure 12. Before or after forming the isolation structure 12, the first active area 11 can be doped with an N-type or P-type element. In an exemplary embodiment of the present disclosure, from Figure 4 As can be seen in (a), the top view of the active region 11 is in the shape of a long strip with rounded ends, and adjacent active regions 11 are arranged in a staggered manner. In other embodiments, the top view of the active region 11 may also be in the shape of a parallelogram strip or a rectangular strip, and adjacent active regions 11 may also be arranged in a non-staggered manner.

[0056] In some embodiments, the surface of the substrate 1 may be etched by a photolithography process to form a shallow groove. Specifically, a photoresist mask layer may be formed on the surface of the substrate 1, and a pattern of the active area 11 may be formed in the photoresist mask layer by exposure and development, and then dry etching is performed to etch the substrate 1 along the pattern to form a shallow groove. In some embodiments, before applying the photoresist mask layer, an anti-reflective layer and a hard mask layer (not shown) are formed on the surface of the substrate 1, and both are removed after the shallow groove is formed.

[0057] In some embodiments, the material of the isolation structure 12 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon nitride. In an exemplary embodiment of the present disclosure, the material of the isolation structure 12 is silicon oxide. In some embodiments, the deposition method of the isolation material in the isolation structure 12 may be at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), thermal oxidation growth method.

[0058] In some embodiments, the active region 11 may be doped with N-type or P-type elements, specifically, the N-type elements include Group V elements, such as phosphorus, arsenic, antimony or bismuth, and the P-type elements include Group III elements, such as boron, aluminum, gallium or indium. In some embodiments, the doping method in the active region 11 may include ion implantation.

[0059] Then, refer to Figure 5 As shown, Figure 5 (a) is a top view toward the substrate in the opposite direction of the third direction Z, Figure 5 (b) along Figure 5 (a) is a schematic cross-sectional view along the dotted line A-A' direction, wherein the cross-sectional view along the dotted line A-A' direction is perpendicular to the top surface of the substrate 1, a word line groove 100 extending from the top surface of the substrate 1 toward the inside of the substrate 1 is formed on the surface of the substrate 1, and the word line groove 100 also extends along a first direction X, and the first direction X is parallel to the plane where the top surface of the substrate 1 is located, and a word line structure 10 is formed in the word line groove 100, including a gate dielectric layer 101, a gate conductive layer 102 and an insulating cap layer 103 stacked in sequence formed in the word line groove 100, and the gate dielectric layer 101 covers the word line groove 100. The bottom and at least part of the sidewall of the groove 100, the gate conductive layer 102 covers the surface of the gate dielectric layer 101 located at the bottom of the word line groove 100 and the part of the sidewall area in contact with the bottom, and the insulating cap layer 103 is located on the top surface of the gate conductive layer 102; the gate conductive layer 102 also includes a metal material conductive layer 1021 and a semiconductor material conductive layer 1022, and the word line structure 10 also includes an air gap 104, wherein the semiconductor material conductive layer 1022 and the air gap 104 are embedded in and occupy part of the sidewall of the metal material conductive layer 1021.

[0060] In some embodiments, the surface of the substrate 1 may be etched by a photolithography process to form the word line groove 100. Specifically, a photoresist mask layer may be formed on the surface of the substrate 1, and a pattern of the word line structure 10 may be formed in the photoresist mask layer by exposure and development, and then dry etching is performed to etch the substrate 1 (including the active area 11 and the isolation structure 12) along the pattern to form the word line groove 100, and the depth of the word line groove 100 is less than the depth of the isolation structure 12. In some embodiments, before applying the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are formed on the surface of the substrate 1, and both are removed after the word line groove 100 is formed.

[0061] In some embodiments, the material of the gate dielectric layer 101 may be a combination of at least one or more of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of the present disclosure, the material of the gate dielectric layer 101 is silicon oxide. In some embodiments, the material of the gate conductive layer 102 may be a combination of at least one or more of doped polysilicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN). In other embodiments, the material of the gate conductive layer 102 may also be a combination of at least one or more of molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and their nitrides. In an exemplary embodiment of the present disclosure, the material of the metal material conductive layer 1021 is titanium nitride, and the semiconductor material conductive layer 1022 is doped polysilicon. In some embodiments, the material of the insulating cap layer 103 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride oxide. In an exemplary embodiment of the present disclosure, the material of the insulating cap layer 103 is silicon nitride.

[0062] In some embodiments, the gate dielectric layer 101, the gate conductive layer 102, and the insulating cap layer 103 may be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth (ISSG), thermal oxidation growth. It should be noted that the gate dielectric layer 101 in the word line structure 10 can also be selectively formed only in the first active area 11.

[0063] In some embodiments, before forming the word line structure 10, the active area 11 is doped with N-type or P-type. After the word line structure 10 is formed, the doped part of the active area 11 located on both sides of the word line structure 10 is used as two source and drain electrodes, the doped part of the active area 11 located below the word line structure 10 is used as a channel region, and the gate conductive layer 102 in the word line structure 10 itself is used as a gate to form a transistor structure. The gate conductive layer 102 serves as the gate of the transistor structure and is used to provide a gate signal to control the on or off of the storage transistor structure. In an exemplary embodiment of the present disclosure, a single active area 11 is crossed by two adjacent word line structures 10 to form two transistor structures, and the two transistor structures share one of the source and drain electrodes.

[0064] In an exemplary embodiment of the present disclosure, Figure 6 As shown, Figure 6 (a) to 6(h) are schematic diagrams of specific steps of sequentially forming the word line structure 10, and are all schematic cross-sectional diagrams along any plane intersecting the word line structure 10. They include:

[0065] First, if Figure 6 As shown in (a), a word line groove 100 extending from the top surface of the substrate 1 toward the inside of the substrate 1 is formed on the surface of the substrate 1, and the surface of the substrate 1 can be etched by a photolithography method. In some embodiments, the cross-sectional schematic diagram of the word line groove 100 is rectangular, that is, the opening size and the bottom size of the word line groove 100 are substantially consistent. In other embodiments, the cross-sectional schematic diagram of the word line groove 100 is trapezoidal, for example, the opening size of the word line groove 100 is larger than the bottom size, or the bottom size of the word line groove 100 is larger than the opening size.

[0066] Then, if Figure 6 As shown in (b), a gate dielectric layer 101 is formed at the bottom and at least a portion of the sidewalls of the word line trench 100, and any method for forming the gate dielectric layer 101 in the aforementioned embodiments may be used. In some embodiments, the gate dielectric layer 101 covers the bottom and all the sidewalls of the word line trench 100. In some embodiments, the gate dielectric layer 101 covers the bottom of the word line trench 100 and a portion of the sidewalls that are in contact with the bottom.

[0067] Then Figure 6As shown in (c), a first sub-portion 1021a of the metal material conductive layer 1021 is formed in the word line groove 100. The first sub-portion 1021a is located on the surface of the gate dielectric layer 101 and fills the bottom of the word line groove 100 and has a target height. It can be formed by any method for forming the gate conductive layer 102 in the above-mentioned embodiment. In some embodiments, the first sub-portion 1021a of the target height can be formed by first depositing and then etching back. In other embodiments, the target height or thickness of the deposition can also be controlled by controlling the deposition time.

[0068] Next, refer to Figure 6 (d) An initial semiconductor material conductive layer 1022'' is formed in the word line groove 100. The initial semiconductor material conductive layer 1022'' covers at least the top surface of the first sub-portion 1021a and the remaining uncovered surface of the gate dielectric layer 101 in the word line groove 100. The gate conductive layer 102 may be formed by any of the methods for forming the gate conductive layer 102 in the aforementioned embodiments. The thickness of the initial semiconductor material conductive layer 1022'' is in the range of 2.5 to 4.5 nm.

[0069] Next, refer to Figure 6 (e) The initial semiconductor material conductive layer 1022" is etched back to obtain a temporary semiconductor material conductive layer 1022' of a temporary height, so that the temporary semiconductor material conductive layer 1022' is present on the top surface of the first sub-portion 1021a only in the area near the side wall in contact with the gate dielectric layer 101, and the area on the top surface of the first sub-portion 1021a away from the side wall (near the middle) is exposed, and the etching back can be performed by plasma dry etching, vapor chemical etching or wet chemical etching. In some embodiments, the area on the top surface of the first sub-portion 1021a away from the side wall (near the middle) will have a depression caused by over-etching.

[0070] Then, refer to Figure 6 As shown in (f), an initial second sub-portion 1021b' of the metal material conductive layer 1021 is formed in the word line groove 100, and the initial second sub-portion 1021b' fills the remaining space in the word line groove 100 and covers the first sub-portion 1021a, the temporary semiconductor material conductive layer 1022' and the exposed surface of the gate dielectric layer 101, and can be formed by any formation method of the gate conductive layer 102 in the aforementioned embodiments.

[0071] Then, if Figure 6As shown in (g), the initial second sub-portion 1021b' is etched back to obtain the second sub-portion 1021b of the target height, and the temporary semiconductor material conductive layer 1022' is etched back to obtain the semiconductor material conductive layer 1022 of the target height. The etching back can be performed by plasma dry etching, vapor phase chemical etching or wet chemical etching. In some embodiments, the ratio of the height of the second sub-portion 1021b to the first sub-portion 1021a is in the range of 1:2 to 1:1; the ratio of the average thickness of the second sub-portion 1021b to the maximum thickness of the first sub-portion 1021a is in the range of 1:3 to 2:3. In some embodiments, wet chemical etching can be used to reduce the thickness of the sidewall gate dielectric layer 101, and finally the thickness of the air gap 104 is greater than or equal to the thickness of the semiconductor material conductive layer 1022.

[0072] Finally, reference Figure 6 As shown in (h), an insulating cap layer 103 is formed in the word line trench 100, and the insulating cap layer 103 covers the top surface of the second sub-portion 1021b of the metal material conductive layer 1021, and an air gap 104 is formed between the semiconductor material conductive layer 1022, and the top surface of the insulating cap layer 103 is flush with the top surface of the substrate 1. In some embodiments, the air gap 104 is located on the top of the semiconductor material conductive layer 1022 and is in direct contact with the top of the semiconductor material conductive layer 1022. The ratio of the height of the air gap 104 to the height of the semiconductor material conductive layer 1022 is 1:3, and the sum of the height of the air gap 104 and the height of the semiconductor material conductive layer 1033 is in the range of 30 to 45 nm. In some embodiments, the thickness of the air gap 104 is greater than or equal to the thickness of the semiconductor material conductive layer 1022. It should be noted that the height direction is perpendicular to the surface of the substrate 1, and the thickness direction is parallel to the plane where the top surface of the substrate 1 is located and perpendicular to the first direction X.

[0073] In the second exemplary embodiment of the present disclosure, Figure 7 As shown, Figure 7 (a) to 7(h) are schematic diagrams of specific steps of sequentially forming the word line structure 10, and are all schematic cross-sectional diagrams along any plane intersecting the word line structure 10. They include:

[0074] first, Figure 7 (a) with Figure 7 The steps shown in (b) are basically the same as steps 6(a) and 6(b) in the aforementioned embodiment and are not repeated here.

[0075] Then as Figure 7As shown in (c), a first sub-portion 1021a of the metal material conductive layer 1021 and an initial semiconductor material conductive layer 1022" are formed in the word line groove 100. The first sub-portion 1021a is located on the surface of the gate dielectric layer 101 and fills the bottom of the word line groove 100 and has a target height. The initial semiconductor material conductive layer 1022" is located on the top surface of the first sub-portion 1021a and fills the middle of the word line groove 100 and has an initial height. It can be formed by any formation method of the gate conductive layer 102 in the aforementioned embodiments. In some embodiments, the first sub-portion 1021a and the initial semiconductor material conductive layer 1022" of the target height can be formed by first depositing and then etching back. In other embodiments, the target height or thickness of the deposition can also be controlled by controlling the deposition time.

[0076] Next, refer to Figure 7 (d) forming an initial first mask layer 105' in the word line trench 100, wherein the initial first mask layer 105' at least covers the top surface of the initial semiconductor material conductive layer 1022" and the remaining uncovered surface of the gate dielectric layer 101 in the word line trench 100, and the thickness of the initial first mask layer 105' ranges from 2.5 to 4.5 nm. In some embodiments, the material of the initial first mask layer 105' may be at least one or any combination of the following materials: amorphous carbon carbon), polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon carbonitride, and silicon oxynitride. In an exemplary embodiment of the present disclosure, the material of the initial first mask layer 105' is amorphous carbon. In some embodiments, the formation method of the initial first mask layer 105' can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth method (ISSG), thermal oxidation growth method.

[0077] Then, if Figure 7As shown in (e), the initial semiconductor material conductive layer 1022" is self-aligned etched with the initial first mask layer 105' as a mask to obtain a temporary semiconductor material conductive layer 1022', and the temporary semiconductor material conductive layer 1022' is provided on the top surface of the first sub-portion 1021a only in the area near the side wall in contact with the gate dielectric layer 101, and the area on the top surface of the first sub-portion 1021a away from the side wall (near the middle) is exposed, and the self-aligned etching can be performed by plasma dry etching, gas phase chemical etching or wet chemical etching. In some embodiments, the area on the top surface of the first sub-portion 1021a away from the side wall (near the middle) will have a depression caused by over-etching. In some embodiments, the initial first mask layer 105' is not completely etched and consumed, and the first mask layer 105 will be retained as being located on the top surface of the temporary semiconductor material conductive layer 1022' and covering a portion of the surface of the gate dielectric layer 101. In other embodiments, the initial first mask layer 105' is completely consumed.

[0078] Next, when executing Figure 7 Before step (f), the first mask layer 105 is removed, and Figure 7 (f) to Figure 7 (h) The subsequent steps shown are as in the above embodiment Figure 6 The steps shown in (f) to 6(h) are basically the same and will not be repeated here.

[0079] In the third exemplary embodiment of the present disclosure, Figure 8 As shown, Figure 8 (a) to 8(j) are schematic diagrams of specific steps of sequentially forming the word line structure 10, and are all schematic cross-sectional diagrams along any plane intersecting the word line structure 10. They include:

[0080] first, Figure 8 (a) with Figure 8 The steps shown in (b) are basically the same as steps 6(a) and 6(b) in the aforementioned embodiment and are not repeated here.

[0081] Then, if Figure 8 As shown in (c), an initial metal material conductive layer 1021' is formed in the word line trench 100. The initial metal material conductive layer 1021' is located on the surface of the gate dielectric layer 101 and fills the bottom of the word line trench 100 and has a target height. It can be formed by any method for forming the gate conductive layer 102 in the above-mentioned embodiment. In some embodiments, the initial metal material conductive layer 1021' of the target height can be formed by first depositing and then etching back. In other embodiments, the target height or thickness of the deposition can also be controlled by controlling the deposition time.

[0082] Then, refer to Figure 8(d) An initial first mask layer 105' is formed in the word line trench 100, the initial first mask layer 105' at least covers the top surface of the initial metal material conductive layer 1021' and the remaining uncovered surface of the gate dielectric layer 101 in the word line trench 100, and the thickness of the initial first mask layer 105' ranges from 2.5 to 4.5 nm. Figure 8 The step of forming the initial first mask layer 105' in (d) is similar to that in the above-mentioned embodiment. Figure 7 The steps of (d) are basically the same and will not be repeated here.

[0083] Next, refer to Figure 8 (e) Self-aligned etching is performed using the initial first mask layer 105' as a mask to obtain the first mask layer 105, and the first mask layer 105 is provided on the top surface of the initial metal material conductive layer 1021' only in the area near the side wall in contact with the gate dielectric layer 101, and the area on the top surface of the initial metal material conductive layer 1021' away from the side wall (near the middle) is exposed. The self-aligned etching can be performed by plasma dry etching, vapor chemical etching or wet chemical etching.

[0084] Then, if Figure 8 As shown in (f), an initial second mask layer 106' is formed in the word line trench 100, and the initial second mask layer 106' fills the remaining space in the word line trench 100 and covers the exposed surface of the initial metal material conductive layer 1021', the first mask layer 105 and the gate dielectric layer 101. In some embodiments, the material and formation method of the initial second mask layer 106' can be the same as the description of the initial first mask layer 105' in the above-mentioned embodiment, but the material of the initial second mask layer 106' and the material of the initial first mask layer 105' need to be different to ensure that the two have different etching selectivity ratios when etching later. In an exemplary embodiment of the present disclosure, the material of the initial first mask layer 105' is amorphous carbon, and the material of the initial second mask layer 106' is silicon nitride.

[0085] Next, refer to Figure 8(g) Self-aligned etching is performed using the initial second mask layer 106' and the first mask layer 105 as masks. The etching rate of the first mask layer 105 is higher than that of the initial second mask layer 106', so that the sidewall portion of the initial metal material conductive layer 1021' close to the top is etched away to form a gap, and the remaining initial second mask layer 106' acts as the second mask layer 106 to protect the top of the initial metal material conductive layer 1021' from being etched, thereby obtaining the metal material conductive layer 1021. The self-aligned etching can be performed by plasma dry etching, gas phase chemical etching or wet chemical etching. The metal material conductive layer 1021 includes a first sub-portion 1021a and a second sub-portion 1021b located on the top surface of the first sub-portion 1021a.

[0086] Then, if Figure 8 As shown in (h), the second mask layer 106 located on the top of the metal material conductive layer 1021 is removed by selective dry etching, reactive ion etching, vapor phase chemical etching or wet chemical etching.

[0087] Then, refer to Figure 8 (i) A semiconductor material conductive layer 1022 is formed in the gap formed in the aforementioned step 8(g). The semiconductor material conductive layer 1022 has a target height and can be formed by any of the methods for forming the gate conductive layer 102 in the aforementioned embodiments. In some embodiments, the semiconductor material conductive layer 1022 of the target height can be formed by first depositing and then etching back. In other embodiments, the target height or thickness of the deposition can also be controlled by controlling the deposition time. In some embodiments, wet chemical etching can be used to reduce the thickness of the sidewall gate dielectric layer 101, and finally the thickness of the air gap 104 is greater than or equal to the thickness of the semiconductor material conductive layer 1022.

[0088] Finally, if Figure 8 As shown in (j), an insulating capping layer 103 is formed in the word line trench 100. The insulating capping layer 103 covers the top surface of the second sub-portion 1021b of the metal material conductive layer 1021, and an air gap 104 is formed between the insulating capping layer 103 and the semiconductor material conductive layer 1022. The top surface of the insulating capping layer 103 is flush with the top surface of the substrate 1. The description of forming the insulating capping layer 103 and the air gap 104 is basically the same as the description in the step shown in 6 (h) of the aforementioned embodiment, and will not be repeated here. The metal material conductive layer 1021 includes a first sub-portion 1021a and a second sub-portion 1021b located on the top surface of the first sub-portion 1021a. Figure 8In (j), the description of the first sub-portion 1021a and the second sub-portion 1021b and their relationship with the semiconductor material conductive layer 1022 and the air gap 104 are basically consistent with the description in the aforementioned embodiment, and will not be repeated here.

[0089] In an exemplary embodiment of the present disclosure, a memory structure is also provided. Fig. 9 As shown, it includes a memory cell array region and a peripheral device region with a dotted line CC' as a dividing line / plane, wherein the memory cell array region includes, in addition to the substrate 1, the word line structure 10, the active region 11, and the isolation structure 12 in the above-mentioned embodiment, a subsequently formed bit line structure 14 (including a first bit line conductive layer 141, a second bit line conductive layer 142, and a bit line insulating layer 143) connected to a source and drain in the active region 11, a capacitor contact structure 15 (including a contact plug 151 and a landing pad 152) connected to another source and drain in the active region 11, The capacitor structure 17 (including a first electrode layer 171, a capacitor dielectric layer 172 and a second electrode layer 172) is connected to the capacitor contact structure 15, and the support layer 161 / 162 / 163 is used to support the capacitor structure 17; the peripheral area includes a peripheral active area 21, a peripheral isolation structure 22 and a peripheral device 23; the memory structure also includes some interconnect structures, such as contact plugs 19 / 241 / 243, interconnect lines 242, conductive plates 18, etc., and some dielectric layer structures, such as interlayer dielectric layers 20 / 251 / 252, interlayer isolation layers 26, etc.

[0090] It should be noted that the semiconductor structure or memory structure in the embodiments of the present disclosure can be used to manufacture DRAM devices, and can also be used to manufacture other devices that require capacitor structures or conductive plates to be formed in different regions, and no excessive restrictions are made here.

[0091] The various semiconductor structures shown in this specific embodiment can be used for electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM).

[0092] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a word line groove extending from the top surface of the substrate toward the inside of the substrate, and the word line groove also extends along a first direction, and the first direction is parallel to the plane where the top surface of the substrate is located; A word line structure is located in the word line trench, the word line structure comprises a gate dielectric layer, a gate conductive layer and an insulating cap layer stacked in sequence, the gate dielectric layer covers the bottom and at least a portion of the sidewall of the word line trench, the gate conductive layer covers the surface of the gate dielectric layer located at the bottom of the word line trench and a portion of the sidewall contacting the bottom, and the insulating cap layer is located on the top surface of the gate conductive layer; The gate conductive layer further includes a metal material conductive layer and a semiconductor material conductive layer, and the word line structure further includes an air gap, wherein the semiconductor material conductive layer and the air gap are embedded in and occupy a portion of the sidewall of the metal material conductive layer.

2. The semiconductor structure according to claim 1, characterized in that: The air gap is located on the top of the semiconductor material conductive layer and is in direct contact with the top of the semiconductor material conductive layer.

3. The semiconductor structure according to claim 1, characterized in that: The ratio of the height of the air gap to the height of the semiconductor material conductive layer is 1:3, and the height direction is a direction perpendicular to the substrate surface.

4. The semiconductor structure according to claim 3, characterized in that: The sum of the height of the air gap and the height of the semiconductor material conductive layer is in the range of 30 to 45 nm.

5. The semiconductor structure according to claim 1, characterized in that: The thickness of the air gap is greater than or equal to the thickness of the semiconductor material conductive layer, the thickness ranges from 2.5 to 4.5 nm, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

6. The semiconductor structure according to claim 1, characterized in that In the same word line groove, the number of the air gap and the semiconductor material conductive layer is two, which are respectively located on two opposite side walls of the metal material conductive layer and are mirror-symmetrically arranged about the central axis plane of the metal material conductive layer, and the central axis plane is perpendicular to the top surface of the substrate and extends along the first direction.

7. The semiconductor structure according to claim 1, characterized in that: The portion of the sidewall of the metal material conductive layer embedded and occupied by the semiconductor material conductive layer and the air gap is located in a region close to the top of the metal material conductive layer.

8. The semiconductor structure according to claim 1, characterized in that: The metal material conductive layer includes a first sub-portion and a second sub-portion, the second sub-portion is located on the top of the first sub-portion, and the semiconductor material conductive layer and the air gap are located on both sides of the second sub-portion; Among them, the sum of the heights of the semiconductor material conductive layer and the air gap is less than or equal to the height of the second sub-portion, the height direction is a direction perpendicular to the substrate surface, the average thickness of the second sub-portion is less than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

9. The semiconductor structure according to claim 8, characterized in that: The ratio of the height of the second sub-portion to the height of the first sub-portion is in the range of 1:2 to 1:1; the ratio of the average thickness of the second sub-portion to the maximum thickness of the first sub-portion is in the range of 1:3 to 2:

3.

10. The semiconductor structure according to claim 1, wherein: The substrate further comprises an active region and an isolation structure. The multiple active regions are distributed in an array. The isolation structure is located between adjacent active regions. The word line structure passes through the multiple active regions and the isolation structure.

11. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; A word line groove is formed on the surface of the substrate and extends from the top surface of the substrate toward the inside of the substrate, and the word line groove also extends along a first direction, and the first direction is parallel to the plane where the top surface of the substrate is located; forming a word line structure in the word line trench, comprising forming a gate dielectric layer, a gate conductive layer and an insulating cap layer stacked in sequence in the word line trench, wherein the gate dielectric layer covers the bottom and at least a portion of the sidewall of the word line trench, the gate conductive layer covers the surface of the gate dielectric layer located at the bottom of the word line trench and a portion of the sidewall region contacting the bottom, and the insulating cap layer is formed on the top surface of the gate conductive layer; The gate conductive layer further includes a metal material conductive layer and a semiconductor material conductive layer, and the word line structure further includes an air gap, wherein the semiconductor material conductive layer and the air gap are embedded in and occupy a portion of the sidewall of the metal material conductive layer.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: A gate dielectric layer, a gate conductive layer and an insulating cap layer are sequentially stacked in the word line trench, including: forming the gate dielectric layer at the bottom and at least a portion of the sidewall of the word line trench; forming the metal material conductive layer on the surface of the gate dielectric layer; forming the semiconductor material conductive layer on a portion of the sidewall of the metal material conductive layer; The insulating cap layer is formed on the top surface of the metal material conductive layer, and the air gap is formed between the insulating cap layer and the semiconductor material conductive layer. The air gap is located on the top of the semiconductor material conductive layer, and the air gap is in direct contact with the top of the semiconductor material conductive layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: Forming the metal material conductive layer on the surface of the gate dielectric layer, and forming the semiconductor material conductive layer on part of the sidewall of the metal material conductive layer, comprises: forming a first sub-portion of the metal material conductive layer on the surface of the gate dielectric layer; forming a second sub-portion of the semiconductor material conductive layer and the metal material conductive layer on the top of the first sub-portion, wherein the semiconductor material conductive layer and the air gap are located on both sides of the second sub-portion; Among them, the sum of the heights of the conductive layer of semiconductor material and the air gap is less than or equal to the height of the second sub-portion, the height direction is a direction perpendicular to the surface of the substrate, the thickness of the air gap is greater than or equal to the thickness of the conductive layer of semiconductor material, the average thickness of the second sub-portion is less than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

14. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: Forming the metal material conductive layer on the surface of the gate dielectric layer, and forming the semiconductor material conductive layer on part of the sidewall of the metal material conductive layer, comprises: forming an initial metal material conductive layer on the surface of the gate dielectric layer; Etching a portion of the sidewall of the initial metal material conductive layer to form the metal material conductive layer including a first sub-portion and a second sub-portion, wherein the second sub-portion is located on top of the first sub-portion; forming the conductive layer of semiconductor material on the sidewalls of the second sub-portion; Among them, the sum of the heights of the conductive layer of semiconductor material and the air gap is less than or equal to the height of the second sub-portion, the height direction is a direction perpendicular to the surface of the substrate, the thickness of the air gap is greater than or equal to the thickness of the conductive layer of semiconductor material, the average thickness of the second sub-portion is less than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane where the top surface of the substrate is located and perpendicular to the first direction.

15. The method for manufacturing a semiconductor structure according to any one of claims 11 to 14, characterized in that: Before forming the word line trench, the method further includes: forming active regions and isolation structures on the surface of the substrate, wherein a plurality of the active regions are distributed in an array, and the isolation structures are located between adjacent active regions; After the word line trench is formed, the word line trench passes through the plurality of active regions and the isolation structure.

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