Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a method of forming the same. The semiconductor structure includes depositing a gate dielectric layer on a first nanostructure over a first region of a substrate and depositing a second nanostructure on a second region of the substrate; depositing a first work function metal (WFM) layer over the first nanostructure and the second nanostructure, and depositing a second work function metal (WFM) layer over the first nanostructure and the second nanostructure; depositing a first hard mask (HM) layer on the first WFM layer; selectively removing the first HM layer and the first WFM layer above the first region; selectively removing the first HM layer over the second region; depositing a second WFM layer on the substrate; depositing a second HM layer on the second WFM layer; selectively removing the second HM layer and the second WFM layer above the first region; selectively removing the second HM layer over the second region; and depositing a third WFM layer on the substrate.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor technology, and more particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. In the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or circuit) that can be formed using a manufacturing process) has decreased. This process of miniaturization often provides benefits by increasing production efficiency and reducing associated costs. This miniaturization also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors (both also referred to as non-planar transistors) are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. A fin field effect transistor (FinFET) has an ascending channel surrounded by a gate on more than one side (e.g., a gate surrounds the top and sidewalls of a "fin" extending from a substrate and composed of semiconductor material). This configuration allows for better channel control and significantly reduced short channel effects (SCE) compared to planar transistors (particularly by reducing sub-threshold leakage (i.e., coupling between the source and drain of a FinFET in the "off" state)). A gate-all-around (GAA) transistor has a gate structure that extends partially or completely around a channel region to provide access to two or more sides of the channel region. Due to this configuration, a gate-all-around (GAA) transistor may also be referred to as a surrounding-gate transistor (SGT) or a multi-bridge-channel (MBC) transistor. The channel region of a gate-all-around (GAA) transistor may be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. These shapes of the channel region also give different names to gate-all-around (GAA) transistors. For example, a gate-all-around (GAA) transistor with a nanosheet channel region may be referred to as a nanosheet transistor.

[0004] When gate-all-around (GAA) transistors of different conductivity types or different threshold voltages are required, the gate formation process may involve depositing more than one work function metal layer in different device regions. As device dimensions continue to decrease, it becomes increasingly challenging to satisfactorily and selectively deposit several work function metal layers in one region and several other work function metal layers in another region. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor structure and a method for forming the same to solve at least one of the above problems.

[0006] In some embodiments, a method for forming a semiconductor structure is provided, comprising: receiving a working component, which includes a plurality of first nanostructures located above a first region of a substrate and a plurality of second nanostructures located above a second region of the substrate; depositing a gate dielectric layer on a surface of each of the plurality of first nanostructures and on a surface of each of the plurality of second nanostructures; depositing a first work function metal layer on the plurality of first nanostructures above the first region and on the plurality of second nanostructures above the second region; depositing a first hard mask layer on the first work function metal layer; selectively removing the first hard mask layer located above the first region; The present invention relates to a method for depositing a first work function metal layer on a plurality of first nanostructures above the first region and a plurality of second nanostructures above the second region after selectively removing the first hard mask layer above the second region; depositing a second hard mask layer on the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer above the first region; and depositing a third work function metal layer on the plurality of first nanostructures above the first region and the plurality of second nanostructures above the second region.

[0007] In some embodiments, a method for forming a semiconductor structure is provided, comprising: receiving a working component, which includes a plurality of first nanostructures located on a first substrate fin and a plurality of second nanostructures located on a second substrate fin separated from the first substrate fin by an isolation feature; depositing a gate dielectric layer on a surface of each of the plurality of first nanostructures and a surface of each of the plurality of second nanostructures; depositing a first work function metal layer over the plurality of first nanostructures and the plurality of second nanostructures and contacting the gate dielectric layer; depositing a first hard mask layer over the first work function metal layer, such that the first hard mask layer passes through the first work function metal layer; The method comprises the steps of: separating the work function metal layer from the gate dielectric layer; selectively removing the first hard mask layer and the first work function metal layer between the plurality of first nanostructures; selectively removing the first hard mask layer between the plurality of second nanostructures; depositing a second work function metal layer over the plurality of first nanostructures and the plurality of second nanostructures; depositing a second hard mask layer over the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer between the plurality of first nanostructures; and depositing a third work function metal layer to surround each of the plurality of first nanostructures and the second work function metal layer over the plurality of second nanostructures.

[0008] In some embodiments, a semiconductor structure is provided, comprising: a first base fin and a second base fin, located above a substrate; an isolation component, located above the substrate and directly disposed between the first base fin and the second base fin; a plurality of first nanostructures, disposed above the first base fin; a plurality of second nanostructures, disposed above the second base fin; a gate dielectric layer, surrounding each of the plurality of first nanostructures, each of the plurality of second nanostructures, and disposed on the first base fin, the second base fin, and the upper surface of the isolation feature; a first work function layer surrounding each of the plurality of second nanostructures, and disposed above the second base fin; a second work function layer surrounding each of the plurality of second nanostructures and filling the space between the plurality of second nanostructures; a third work function layer surrounding each of the plurality of first nanostructures, and located on the second work function layer surrounding the plurality of second nanostructures; a glue layer, disposed on the third work function layer; and a gate cap layer, located on the glue layer. There is an interface between the first work function layer and the second work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure is shown.

[0010] Figure 2-Figure 26 Shown according to Figure 1 Schematic diagram of the non-complete cross-section of the first region and the second region of the working component at different manufacturing stages in the method.

[0011] The reference numerals are as follows:

[0012] 100: Method

[0013] 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130: Step Block

[0014] 200: Working parts; Semiconductor devices

[0015] 202: Base

[0016] 202N: n-type well area

[0017] 202P: p-type well area

[0018] 204: Stack

[0019] 206: Sacrificial layer

[0020] 208: Channel layer

[0021] 210: Hard mask layer

[0022] 212: Fin-shaped structure

[0023] 212C: Channel area

[0024] 212NB: Second base fin

[0025] 212PB: First base fin

[0026] 212SD: Source / Drain Region

[0027] 214: Isolation feature component; shallow trench isolation (STI) component

[0028] 216: Virtual dielectric layer

[0029] 218: dummy electrode layer

[0030] 220: Virtual Gate Stack

[0031] 222: Gate top hard mask layer

[0032] 223: Silicon oxide layer

[0033] 224: Silicon nitride layer

[0034] 226: (at least one) gate spacer layer

[0035] 226-1: First spacer layer

[0036] 226-2: Second spacer layer

[0037] 230: Internal spacing feature

[0038] 232N: First source / drain feature component

[0039] 232P: Second source / drain feature

[0040] 236: Contact Etch Stop Layer (CESL)

[0041] 238: Interlayer dielectric (ILD) layer

[0042] 240: Interface layer

[0043] 242: Gate dielectric layer

[0044] 244: first work function metal (WFM) layer

[0045] 246: first hard mask layer

[0046] 248: First bottom anti-reflection (BARC) layer

[0047] 250: second work function metal (WFM) layer

[0048] 252: second hard mask layer

[0049] 254: Second bottom anti-reflection (BARC) layer

[0050] 256: third work function metal (WFM) layer

[0051] 258: Adhesive layer

[0052] 260: Gate cap layer

[0053] 300: Stepped feature parts

[0054] 400: Encapsulate step feature

[0055] 1000: First Area

[0056] 2000: Second Region

[0057] 2080: first nanostructure; second nanostructure DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present invention. The following disclosure is a specific example describing each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which an additional characteristic component can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in each different example. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0059] Spatially related terms such as "under", "below", "lower", "over", "upper", etc. are used herein to easily express the relationship between an element or feature in the drawings shown in this specification and another element or feature. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device during use or operation. The device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used herein are also interpreted accordingly.

[0060] Furthermore, when "about," "approximately," etc. are used to describe a value or range of values, the term includes values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having features associated with the values, the magnitude or range of values ​​includes a reasonable range of the values, such as within + / - 10% of the values. For example, a material layer having a thickness of "about 5 nm" may cover a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers is known to those skilled in the art to be + / - 15%.

[0061] Multi-gate devices, such as gate-all-around (GAA) transistors, have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCE). A gate-all-around (GAA) transistor has a gate structure that partially or completely extends around a channel region to provide access to the channel region on two or more sides. The channel region of a gate-all-around (GAA) transistor may include multiple sheet-like or linear nano-sized channel components that are stacked or placed side by side on each other. As device dimensions continue to shrink, it is very challenging to form a gate structure that satisfactorily surrounds each channel component. Furthermore, in order to form a gate-all-around (GAA) transistor with different threshold voltages, different work function metal (WFM) layers must be deposited on different regions to surround each channel component. In order to successfully deposit different work function metal (WFM) layers on different regions, the work function metal (WFM) layer needs to fill the space between the channel components, and the gate trench that exposes the channel component must be large enough to accommodate the patterned material. Some processes aim to increase the pitch of patterned material, however, too much patterned material may result in incomplete removal of patterned material and unsatisfactory filling of the work function metal (WFM) layer.

[0062] The present disclosure relates to forming a gate structure for a p-type gate all-around (GAA) transistor and an n-type gate all-around (GAA) transistor on a substrate. The working part includes a first nanostructure located above a first region and a second nanostructure located above a second region. After forming an interface layer and a gate dielectric layer on the surface of the first nanostructure and the second nanostructure, a first work function metal (WFM) layer is deposited above the first region and the second region. After depositing the first work function metal (WFM) layer, a first hard mask layer is deposited above the first work function metal (WFM) layer. After trimming the first hard mask layer, the first hard mask layer and the first work function metal (WFM) layer above the first region are selectively removed. Then the first hard mask layer above the second region is selectively removed. A second work function metal (WFM) layer is deposited above the first region and the second region, and a second hard mask layer is deposited above the second work function metal (WFM) layer. After trimming the second hard mask layer, the second hard mask layer and the work function metal (WFM) layer are selectively removed from the first region. Then, a third work function metal (WFM) layer is deposited over the first region and the second region. By using two separate hard masks to deposit the first work function metal (WFM) layer and the second work function metal (WFM) layer over the second region, the process window of the gate filling process is relaxed.

[0063] The various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 A flow chart of a method 100 for forming a gate structure of a stacked multi-gate device in various forms according to the present disclosure is shown. The method 100 is merely an example and does not limit the present disclosure to the contents explicitly indicated in the method 100. In additional embodiments of the method, additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, removed, or moved. For the sake of simplicity, not all steps are described in detail herein. The method 100 is described below in conjunction with Figures 2-26, which are schematic diagrams of incomplete cross-sections of a working component 200 at different manufacturing stages according to an embodiment of the method 100. Because the working component 200 will be manufactured into a semiconductor device 200 at the end of the manufacturing process, the working component 200 may be referred to as a semiconductor device 200 as required by the context. In addition, throughout the present application and in different embodiments, unless otherwise specified, similar reference numerals represent similar feature components having similar structures and compositions. Depending on the context, the source / drain region may be referred to as a source region or a drain region individually or collectively.

[0064] Please refer to Figure 1-Figure 9The method 100 includes a step block 102, wherein a plurality of first nanostructures 2080 are formed between two first source / drain features 232N above a first region 1000 of a substrate 202, and a plurality of second nanostructures 2080 are formed between two second source / drain features 232P above a second region 2000. The operation of step block 102 includes forming a stack 204 above the substrate 202 (e.g., Figure 2 As shown in FIG. 1 ), the stack 204 and a portion of the substrate 202 are patterned to form a fin structure 212 (as shown in FIG. 1 ). Figure 3 ), forming a dummy gate stack 220 in the channel region of the fin structure 212 (as shown in Figure 4 and Figure 5 ) above, forming a gate spacer 226 and a source / drain region 212SD (as shown in FIG. Figure 6 As shown), forming a first source / drain feature component 232N and a second source / drain feature component 232P (as shown Figure 7 ), depositing a contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 (as shown in FIG. Figure 8 ) and removing the dummy gate stack 220 and releasing the first nanostructure 2080 and the second nanostructure 2080 in the first region 1000 and the second region 2000 (as shown in FIG. Fig. 9 shown).

[0065] Please refer to Figure 2, substrate 202 is a portion of working component 200 (which undergoes various operations of method 100). In some embodiments, substrate 202 can be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 can also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe) or diamond. Alternatively, substrate 202 can include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 202 can optionally include an epitaxial layer (epi-layer), can be strained to enhance performance, can include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or can have other suitable enhanced feature components. As is known in the art, substrate 202 can include various doping configurations depending on design requirements. In the illustrated embodiment, substrate 202 includes a first region 1000 and a second region 2000. The substrate 202 includes a p-type well region 202P (i.e., p-type doping profile distribution) above the first region 1000 and an n-type well region 202N (i.e., n-type doping profile distribution) located above the second region 2000. In some embodiments, the n-type dopant used to form the n-type well region 202N may include phosphorus (P) or arsenic (As), and the p-type dopant may include phosphorus (P) or arsenic (As). The dopant used to form the p-type well region 202P may include boron (B). Suitable doping for the n-type well region 202N or the p-type well region 202P may include ion implantation and / or diffusion processes of the dopant.

[0066] Please refer to Figure 2 , the stack 204 includes sacrificial layers 206 having a first semiconductor composition interleaved with channel layers 208 having a second semiconductor composition. The first and second semiconductor compositions may be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) and the channel layers 208 include silicon (Si). Figure 2 As shown, three (3) sacrificial layers 206 and three (3) channel layers 208 are alternately arranged, which is for illustrative purposes only and does not limit the scope of the invention beyond the specific description of the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of epitaxial layers depends on the number of channel components required for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0067] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness of about 5 nm to 10 nm, and all channel layers 208 may have a substantially uniform first thickness of about 2 nm to 8 nm. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion of the channel layer 208 may be used as a channel component of a subsequently formed multi-gate device, and the thickness of each channel layer 208 is selected based on device performance considerations. The sacrificial layer 206 in the channel region may eventually be removed and used to define the vertical distance between adjacent channel regions of a subsequently formed multi-gate device, and the thickness of each sacrificial layer 206 is selected based on device performance considerations.

[0068] The layers in stack 204 may be deposited at a temperature between about 600° C. and 800° C. using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least some examples, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants (i.e., have a thickness of about 0 cm -3 Up to 1x10 17 cm -3 The concentration of extrinsic dopants may be determined by measuring the dopant concentration of the epitaxial growth layer 204, wherein, for example, no deliberate doping is performed during the epitaxial growth process of the stack 204.

[0069] Please refer to Figure 3 A fin-shaped structure 212 is formed by the stack 204 and a portion of the substrate 202. To pattern the stack 204, a hard mask layer 210 (shown in FIG. 2 ) may be deposited thereon. Figure 2 ) to form an etching mask. The hard mask layer 210 can be a single layer or a multilayer. For example, the hard mask layer 210 can include a pad oxide layer and a pad nitride layer located on the pad oxide layer. The fin structure 212 can be patterned from the stack 204 and a portion of the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable process lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching and / or other etching methods. As Figure 3 As shown, the etching process forms a trench extending through the stack 204 and a portion of the substrate 202. The trench defines a fin structure 212, including a plurality of base fins (eg, Figure 3 212 NB). In some embodiments, a double patterning or multiple patterning process can be used to define a fin structure having, for example, a smaller pitch than can be obtained using a single direct lithography process. For example, in one embodiment, a material layer is formed above the substrate and patterned using a lithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching the stack 204 and a portion of the substrate 202. Figure 3 As shown, the fin structure 212 may be used to pattern the fin structure 212. The fin structure 212 together with the sacrificial layer 206 and the channel layer 208 therein extend vertically along the Z direction and longitudinally along the X direction.

[0070] An isolation feature 214 is formed adjacent to the fin structure 212. In some embodiments, the isolation feature 214 can be formed in a trench to isolate the fin structure 212 from an adjacent active area (which may be another fin structure). The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, a combination thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a chemical vapor deposition (CVD) process, a subatmospheric CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form a shallow trench isolation (STI) feature 214. Figure 3 As shown, when the base fin (including the first base fin 212PB and the second base fin 212NB) is set in the shallow trench isolation (STI) part 214 or surrounded by the shallow trench isolation (STI) part 214, the rest of the fin-shaped structure 212 (formed by the stack 204) rises above the shallow trench isolation (STI) part 214 after the recess.

[0071] Now please refer to Figure 4 and Figure 5 A dummy gate stack 220 is formed above the channel region 212C of the fin structure 212. In some embodiments, a gate replacement process (or gate last process) is used, wherein the dummy gate stack 220 is used as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown, the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 in the first region 1000 and the second region 2000 can be divided into a channel region 212C located below the gate stack 212 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown, the channel region 212C is disposed between the two source / drain regions 212SD along the X direction.

[0072] The fabrication of the dummy gate stack 220 may include deposition of film layers in the dummy gate stack 220 and patterning of the film layers. Figure 4 , a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be deposited over the working component 200. In some embodiments, the dummy dielectric layer 216 may be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, a thermal oxidation process, or other suitable process. In some cases, the dummy dielectric layer 216 may include silicon oxide. When the dummy dielectric layer 216 is formed using an oxidation process, it may be selectively formed on the exposed surface of the fin structure 212, such as Figure 4 As shown. Thereafter, a dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or other suitable process. In some cases, the dummy electrode layer 218 may include polysilicon. For patterning purposes, a gate top hard mask layer 222 may be deposited over the dummy electrode layer 218 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or other suitable process. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 may then be patterned to form a dummy gate stack 220, as shown. Figure 5As shown. For example, the patterning process may include a photolithography process (e.g., optical lithography or electron beam lithography), which also includes photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 located above the silicon oxide layer 223. As shown in FIG. Figure 5 As shown, no dummy gate stack 220 is disposed above the source / drain region 212SD of the fin structure 212 .

[0073] Now please refer to Figure 6 , depositing at least one gate spacer layer 226 above the dummy gate stack 220 in the first region 1000 and the second region 2000. In some embodiments, at least one gate spacer layer 226 is conformally deposited above the working part 200, including on the upper surface and sidewalls of the dummy gate stack 220. The term "conformity" may be used herein to facilitate describing a film layer having a substantially uniform thickness in various regions. The at least one gate spacer layer 226 may be a single layer or multiple layers. In the illustrated embodiment, the at least one gate spacer layer 226 includes a first spacer layer 226-1 and a second spacer layer 226-2 disposed above the first spacer layer 226-1. The composition of the first spacer layer 226-1 may be different from the composition of the second spacer layer 226-2. In some embodiments, the dielectric constant of the first spacer layer 226-1 is greater than the dielectric constant of the second spacer layer 226-2. The at least one gate spacer layer 226 including the first spacer layer 226-1 and the second spacer layer 226-2 may include silicon oxide, silicon carbonitride, silicon oxycarbon, silicon carbon oxynitride or silicon nitride. The at least one gate spacer layer 226 may be deposited on the dummy gate stack 220 using a chemical vapor deposition (CVD) process, a low pressure chemical vapor deposition (SACVD) process, an atomic layer deposition (ALD) process or other suitable processes. For the convenience of comparison, the at least one gate spacer layer 226 may also be simply referred to as the gate spacer layer 226.

[0074] Please still refer to Figure 6, the source / drain region 212SD of the fin-shaped structure 212 is recessed to form a source / drain trench 228. In some embodiments, the source / drain region 212SD not covered by the dummy gate is etched by dry etching or an appropriate etching process to etch the stack 220 and the gate spacer 226 to form a source / drain trench 228. For example, the dry etching process can be implemented with oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. Figure 6 In some embodiments shown, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the source / drain trench 228 extends below the stack 204 and into the substrate 202.

[0075] Please refer to Figure 7, forming an inner spacer feature 230. After forming the source / drain trenches 228, the sacrificial layer 206 located in the channel region 212C is selectively and partially recessed to form an inner spacer groove, while the exposed channel layer 208 is substantially unetched. In an embodiment where the channel layer 208 is mainly composed of silicon (Si) and the sacrificial layer 206 is mainly composed of silicon germanium (SiGe), the selective and local recessing of the sacrificial layer 206 may include a SiGe oxidation process and then remove the SiGe oxide. In this embodiment, the SiGe oxidation process may include the use of ozone (O3). In some other embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 206 is controlled by the duration of the etching process. The selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbon. The selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). After forming the inner spacer groove, an inner spacer material layer is deposited over the working part 200, including the inner spacer groove. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbon nitride, silicon carbonitride, metal nitride, or a suitable dielectric material, and may be deposited using chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), low pressure chemical vapor deposition (SACVD), atomic layer deposition (ALD), or other suitable methods. Afterwards, the deposited inner spacer material layer is etched back to remove the excess inner spacer material layer over the sidewalls of the gate spacer layer 226 and the channel layer 208, and form the inner spacer feature 230. In some embodiments, the back etching process to form the inner spacer feature 230 may be a dry etching process, including using an oxygen-containing gas, hydrogen (H2), nitrogen (N2), a fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas (e.g., CF3I), other suitable gases and / or plasma and / or combinations thereof. Although not explicitly shown, a cleaning process may be performed after the back etching process to remove native oxide and debris from the surface of the channel layer 208.

[0076] Please still refer to Figure 7. A first source / drain feature 232N is formed over the source / drain region 212SD in the first region 1000, and a second source / drain feature 232P is formed over the source / drain region 212SD in the second region. Each of the first source / drain feature 232N and the second source / drain feature 232P may be selectively epitaxially formed from the exposed sidewalls of the channel layer 208 and the exposed surface of the substrate 202, while the sidewalls of the sacrificial layer 206 remain covered by the inner spacer feature 230. Suitable epitaxial processes for forming the first source / drain feature 232N and the second source / drain feature 232P include vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (ultra-high vacuum CVD, UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use a gaseous precursor that interacts with the composition of the substrate 202 and the channel layer 208. In some embodiments, the parameters of the epitaxial growth process are selected such that the first source / drain feature 232N and the second source / drain feature 232P are not epitaxially deposited on the inner spacer feature 230. That is, the overgrowth of the first source / drain feature 232N and the second source / drain feature 232P may be merged over some of the inner spacer feature 230.

[0077] The first source / drain feature 232N and the second source / drain feature 232P may have different conductivity types and may each include more than one epitaxial layer. Figure 7In some of the illustrated embodiments, the first source / drain feature 232N above the first region 1000 may be an n-type source / drain feature, which includes silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenic (As). The second source / drain feature 232P above the second region 2000 may include silicon germanium (SiGe) doped with a p-type dopant, such as boron (B). When each first source / drain feature 232N includes multiple epitaxial layers, the epitaxial layer close to the channel layer 208 and the substrate 202 may include a lower n-type dopant concentration, while the epitaxial layer away from the channel layer 208 and the substrate 202 may include a higher n-type dopant concentration. Similarly, when each second source / drain feature 232P includes multiple epitaxial layers, the epitaxial layer close to the channel layer 208 and the substrate 202 may include a lower p-type dopant concentration and the epitaxial layer away from the channel layer 208 and the substrate 202 may include a higher p-type dopant concentration. In addition, when each first source / drain feature 232N includes multiple epitaxial layers, the epitaxial layer close to the channel layer 208 and the substrate 202 may include a lower germanium (Ge) content, while the epitaxial layer away from the channel layer 208 and the substrate 202 may include a higher germanium (Ge) content. Since the first source / drain feature 232N and the second source / drain feature 232P have different compositions and are formed in different regions, they are formed separately. In one embodiment, a patterned mask layer (e.g., a photoresist layer or a bottom antireflective coating (BARC) layer) may be formed to cover the second region 2000, while the first source / drain feature 232N is formed in the first region 1000. Then, another patterned mask layer may be formed to cover the first region 1000, while the second source / drain feature 232P is formed in the second region 2000. In another embodiment, the order can be exchanged, and the second source / drain feature 232P is first formed in the second region 2000. Although not explicitly shown in the drawings, an annealing process can be performed to obtain the desired electron contribution of the dopant in the semiconductor host (e.g., silicon germanium (SiGe) or silicon (Si)). The annealing process can include a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. The annealing process can include a peak annealing temperature between about 900°C and 1000°C. In these embodiments, the peak annealing temperature can be maintained for a duration measured in seconds or microseconds.

[0078] Please refer to Figure 8A contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 are deposited over the first source / drain feature 232N and the second source / drain feature 232P. The contact etch stop layer (CESL) 236 may include silicon nitride, silicon oxynitride, and / or other known materials. The ILD layer 238 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or a dielectric material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass BPSG, fused silica glass (FSG), phosphosilicate glass PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, the ILD layer 238 is deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or the like. The contact etch stop layer (CESL) 236 is first conformally deposited on the first region 1000 and the second region 2000 by using a PECVD (Polyethylene glycol deposition) process and / or other appropriate deposition or oxidation process, and an interlayer dielectric (ILD) layer 238 is deposited on the contact etch stop layer (CESL) 236 by using spin coating, flow chemical vapor deposition (FCVD), chemical vapor deposition (CVD) or other appropriate deposition techniques. In some embodiments, after the interlayer dielectric (ILD) layer 238 is formed, the working component 200 may be annealed to improve the integrity of the interlayer dielectric (ILD) layer 238. Figure 8 As shown, after depositing the contact etch stop layer (CESL) 236 and the interlayer dielectric (ILD) layer 238, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to remove excess materials. Figure 8 As shown, the planarization process also exposes the dummy electrode layer 218 of the dummy gate stack 220 in the first region 1000 and the second region 2000 .

[0079] Now please refer to Fig. 9, remove the exposed dummy gate stack 220, and selectively remove the sacrificial layer 206 in the channel region 210C to release the first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000. The removal of the dummy gate stack 220 may include one or more etching processes that are selective to the material in the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 210C are exposed. Thereafter, the sacrificial layer 206 in the channel region 210C is selectively removed to release the first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000. The first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000 may also be referred to as a channel component. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching includes APM etching (e.g., ammonium hydroxide-hydrogen peroxide-water mixture). In some other embodiments, the selective removal includes SiGe oxidation followed by removal of the silicon germanium oxide. For example, oxidation can be provided by ozone cleaning, followed by removal of the silicon germanium oxide by an etchant, such as NH4OH.

[0080] Please refer to Figure 1 and Fig.10 The method 100 includes step block 104, wherein an interface layer 240 is formed above the first nanostructure 2080 and the second nanostructure 2080. Fig.10 As shown, the first nanostructure 2080 is disposed above the first base fin 212PB in the first region 1000, and the second nanostructure 2080 is disposed above the second base fin 212NB in ​​the second region 2000. Because the first base fin 212PB is patterned from the p-type well region 202P, the first base fin 212PB includes the same composition as the p-type well region 202P. Because the second base fin 212NB is patterned from the n-type well region 202N, the second base fin 212NB includes the same composition as the n-type well region 202N. Fig.10, the first region 1000 may be adjacent to the second region 2000. In this way, the p-type well region 202P may be connected to the n-type well region 202N. The interface layer 240 may include silicon oxide or silicon oxynitride or other appropriate materials. In some embodiments, the interface layer 240 may be deposited on the surface of the first nanostructure 2080, the surface of the second nanostructure 2080, and the upper surface of the first base fin 212PB and the second base fin 212NB using an appropriate method (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), ozone oxidation, thermal oxidation, or other appropriate methods). The function of the interface layer 240 is to control and reduce gate leakage current and to increase the gate dielectric layer 242 (shown in FIG. Fig.11 ) and the interfacial adhesion between the nanostructures (including the first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000). In the illustrated embodiment, thermal oxidation is used to form the interfacial layer 240, and the interfacial layer 240 is selectively deposited on the semiconductor surface but not on the dielectric layer surface (e.g., the top surface of the isolation feature 214).

[0081] Please refer to Figure 1 and Fig.11 , the method 100 includes step block 106, wherein a gate dielectric layer 242 is deposited over the interfacial layer 240. In some embodiments, the gate dielectric layer 242 is a high-k dielectric layer because its dielectric constant is greater than the dielectric constant of silicon dioxide (~3.9). In some embodiments, the gate dielectric layer 242 may include doped or undoped hafnium oxide (HfO2), doped or undoped zirconium oxide (ZrO2), doped or undoped titanium oxide (TiO2), or doped or undoped aluminum oxide (Al2O3). For example, the gate dielectric layer 242 may include hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), or hafnium aluminum oxide (HfAlO), hafnium tantalum oxide (HfTaO), hafnium zirconium oxide (HfZrO), zirconium silicon oxide (ZrSiO2), hafnium titanium oxide (HfTiO), or a combination thereof. When the operation of step block 106 is completed, each of the first nanostructure 2080 of the first region 1000 and the second nanostructure 2080 of the second region 2000 is surrounded by the interface layer 240 and the gate dielectric layer 242. Fig.11 As shown, the deposition of the gate dielectric layer 242 may not be selective, and the gate dielectric layer 242 may be deposited over the isolation features 214 .

[0082] Please refer to Figure 1 and Fig.12, the method 100 includes a step block 108, wherein a first work function metal (WFM) layer 244 is deposited over the first region 1000 and the second region 2000. In some embodiments, the first work function metal (WFM) layer 244 may be a p-type work function metal (WFM) layer and may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), molybdenum (Mo), or other suitable p-type work function materials. The first work function metal (WFM) layer 244 may be deposited using atomic layer deposition (ALD). Fig.12 As shown, the thickness of the first work function metal (WFM) layer 244 is such that the space between two adjacent first nanostructures 2080 or second nanostructures 2080 is not completely filled.

[0083] Please refer to Figure 1 and Fig.13 , the method 100 includes step block 110, in which a first hard mask layer 246 is deposited over the first work function metal (WFM) layer 244. The first hard mask layer 246 is formed of a material that can be selectively removed without substantially damaging the first work function metal (WFM) layer 244. In some embodiments, the first hard mask layer 246 is formed of a dielectric material (e.g., silicon oxide, aluminum oxide) or a semiconductor material (e.g., silicon (Si) or germanium (Ge) or silicon germanium (SiGe)). In one embodiment, the first hard mask layer 246 includes aluminum oxide. The first hard mask layer 246 can be deposited using atomic layer deposition (ALD) or other suitable methods. As Fig.13 As shown, the first hard mask layer 246 is formed to a thickness such that it completely fills the space between two adjacent first nanostructures 2080 or two adjacent second nanostructures 2080 .

[0084] Please refer to Figure 1 and Fig.14, the method 100 includes a step block 112, in which the first hard mask layer 246 is trimmed. In the step block 112, a dry etching process or a wet etching process may be performed to remove the first hard mask layer 246 above the working part 200, but excluding the portion disposed between two adjacent first nanostructures 2080 or two adjacent second nanostructures 2080. A suitable etching process may be selected according to the composition of the first hard mask layer 246. For example, when the first hard mask layer 246 includes aluminum oxide, ammonium hydroxide may be used to selectively etch the first hard mask layer 246. In other words, the operation in the step block 112 may remove the first hard mask layer 246 on the uppermost surface and side surfaces of the first nanostructure 2080, on the uppermost surface and side surfaces of the second nanostructure 2080, and on the gate dielectric layer 242 above the isolation feature 214 to expose the first work function metal (WFM) layer 244 deposited thereon.

[0085] Please refer to Figure 1 , Fig.15 and Fig.16 The method 100 includes a step block 114, wherein the first hard mask layer 246 and the first work function metal (WFM) layer 244 are selectively removed over the first region 1000. To selectively remove the first hard mask layer 246 and the first work function metal (WFM) layer 244 over the first region 1000, a first bottom anti-reflective (BARC) layer 248 is formed over the second region 2000 while exposing the first region 1000. In an exemplary process, a blanket bottom anti-reflective (BARC) layer is deposited over the first region 1000 and the second region 2000, and then a photoresist layer is deposited over the blanket bottom anti-reflective (BARC) layer. The photoresist layer is pre-baked, patterned by contacting the photoresist layer with patterned radiation that passes through a photomask or is reflected from the photomask, the photoresist layer is post-baked, and the photoresist layer is developed using a developer in a development process to form a patterned photoresist layer. The patterned photoresist layer is used as an etching mask to pattern the blanket bottom anti-reflective (BARC) layer to form a first bottom anti-reflective (BARC) layer 248, such as Fig.15As shown. The second region 2000 is covered with a first bottom anti-reflective (BARC) layer 248, and the first hard mask layer 246 and the first work function metal (WFM) layer 244 above the first region 1000 are removed. The first hard mask layer 246 and the first work function metal (WFM) layer 244 can be removed using one or more etching processes. For example, the first hard mask layer 246 can be removed using a wet etching process using ammonium hydroxide or a dry etching process using a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3). The first work function metal (WFM) layer 244 can be removed using a wet etching process, and the wet etching process includes a sulfuric acid hydrogen peroxide mixture (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC1), or a mixture of hydrochloric acid and hydrogen peroxide (SC2). Alternatively, a dry etching process may be used, wherein the dry etching process uses a plasma composed of a chlorine gas (e.g., Cl2 and / or BCl3) and an argon gas (Ar). After removing the first hard mask layer 246 and the first work function metal (WFM) layer 244 from the first region 1000, the first bottom anti-reflective (BARC) layer 248 may be removed from the second region 2000 using an ashing or selective etching process, such as Fig.16 shown.

[0086] Please refer to Figure 1 and Fig.17 , the method 100 includes step block 116, wherein the first hard mask layer 246 over the second region 2000 is selectively removed. After the first bottom anti-reflective (BARC) layer 248 is removed from the second region 2000, the first hard mask layer 246 remaining in the second region 2000 is exposed and can be removed using a wet etching process using ammonium hydroxide. Fig.17 As shown, after performing the operation of step block 116 , each first nanostructure 2080 in the first region 1000 is surrounded by the interface layer 240 and the gate dielectric layer 242 , and each second nanostructure 2080 in the second region 2000 is surrounded by the interface layer 240 , the gate dielectric layer 242 and the first work function metal (WFM) layer 244 .

[0087] Please refer to Figure 1 and Fig.18, the method 100 includes step block 118, wherein a second work function metal (WFM) layer 250 is deposited over the first region 1000 and the second region 2000. In some embodiments, the second work function metal (WFM) layer 250 can have the same composition as the first work function metal (WFM) layer 244. In these embodiments, the second work function metal (WFM) layer 250 is actually a second layer of the first work function metal (WFM) layer 244. In some other embodiments, the composition of the second work function metal (WFM) layer 250 is different from the composition of the first work function metal (WFM) layer 244. In these embodiments, the second work function metal (WFM) layer 250 can be used as a diffusion barrier to prevent unwanted species (e.g., aluminum) from diffusing into the first work function metal (WFM) layer 244. In some embodiments, the second work function metal (WFM) layer 250 may be a p-type work function metal (WFM) layer and may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), molybdenum (Mo), or other suitable p-type work function materials. The second work function metal (WFM) layer 250 may be deposited using atomic layer deposition (ALD). Fig.18 As shown, the thickness of the second work function metal (WFM) layer 250 is such that the space between two adjacent first nanostructures 2080 or two adjacent second nanostructures 2080 is completely filled.

[0088] Please refer to Figure 1 and Fig.19 , the method 100 includes step block 120, wherein a second hard mask layer 252 is deposited over the first region 1000 and the second region 2000. The material forming the second hard mask layer 252 is a second work function metal (WFM) layer 250 that can be selectively removed without substantially damaging the first region. In some embodiments, the second hard mask layer 252 is formed of a dielectric material (e.g., silicon oxide, aluminum oxide) or a semiconductor material (e.g., silicon or germanium or SiGe). In one embodiment, the second hard mask layer 252 includes aluminum oxide. The second hard mask layer 252 may be deposited using atomic layer deposition (ALD) or other suitable methods. As Fig.19 As shown, the second hard mask layer 252 is formed to a thickness that enables it to completely fill the space between two adjacent first nanostructures 2080 in the first region 1000. Because the second work function metal (WFM) layer 250 fills the space between two adjacent second nanostructures, the second hard mask layer 252 does not vertically extend between the two adjacent second nanostructures 2080.

[0089] Please refer to Figure 1 and Fig. 20, the method 100 includes a step block 122, in which the second hard mask layer 252 is trimmed. In the step block 122, a dry etching process or a wet etching process may be performed to remove the second hard mask layer 252 above the working part 200, except for a portion disposed between two adjacent first nanostructures 2080 in the first region 1000. A suitable etching process in the step block 122 may be selected according to the composition of the second hard mask layer 252. For example, when the second hard mask layer 252 includes aluminum oxide, ammonium hydroxide may be used to selectively etch the second hard mask layer 252. In other words, the operation in the step block 122 may remove the second hard mask layer 252 above the uppermost surface and the side surface of the first nanostructure 2080 to expose the second work function metal (WFM) layer 250 deposited thereon.

[0090] Please refer to Figure 1 , Fig.21 and Fig. 22 , the method 100 includes a step block 124, wherein the second hard mask layer 252 and the second work function metal (WFM) layer 250 are selectively removed over the first region 1000. To selectively remove the second hard mask layer 252 and the second work function metal (WFM) layer 250 from the first region 1000, a second bottom anti-reflective (BARC) layer 254 is formed over the second region 2000 while exposing the first region 1000. In an exemplary process, a blanket bottom anti-reflective (BARC) layer is deposited over the first region 1000 and the second region 2000, and then a photoresist layer is deposited over the blanket bottom anti-reflective (BARC) layer. The photoresist layer is pre-baked, patterned by contacting the photoresist layer with patterned radiation that passes through a photomask or is reflected from the photomask, the photoresist layer is post-baked, and the photoresist layer is developed using a developer in a development process to form a patterned photoresist layer. The patterned photoresist layer is used as an etching mask to pattern the blanket bottom anti-reflective (BARC) layer to form a second bottom anti-reflective (BARC) layer 254, such as Fig.21As shown. The second region 2000 is covered with a second bottom anti-reflective (BARC) layer 254, and the second hard mask layer 252 and the second work function metal (WFM) layer 250 above the first region 1000 are removed. The second hard mask layer 252 and the second work function metal (WFM) layer 250 can be removed using one or more etching processes. For example, the second hard mask layer 252 can be removed using a wet etching process using ammonium hydroxide or a dry etching process using a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3). The second work function metal (WFM) layer 250 can be removed using a wet etching process including a sulfuric acid hydrogen peroxide mixture (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC1), or a mixture of hydrochloric acid and hydrogen peroxide (SC2) or using a dry etching process, which uses a plasma composed of a chlorine gas (e.g., Cl2 and / or BCl3) and argon (Ar). After removing the second hard mask layer 252 and the second work function metal (WFM) layer 250 from the first region 1000, the second bottom anti-reflective (BARC) layer 254 may be removed from the second region 2000 using an ashing or selective etching process, such as Fig. 22 shown.

[0091] Still referring to No. 22, because the first work function metal (WFM) layer 244 and the second work function metal (WFM) layer 250 are deposited and patterned in different process groups, a step feature 300 can be formed around the interface region between the first work function metal (WFM) layer 244 and the second work function metal (WFM) layer 250 (or between the n-type well region 202N and the p-type well region 202P). The second work function metal (WFM) layer 250 cannot cover the edge portion of the first work function metal (WFM) layer 244, thus leaving the upper surface of a small edge portion of the first work function metal (WFM) layer 244 uncovered. As will be shown in subsequent figures and descriptions, additional film layers can be conformally deposited on the step feature 300 to continue the step shape.

[0092] Please refer to Figure 1 and Fig.23, the method 100 includes step block 126, wherein a third work function metal (WFM) layer 256 is deposited over the first region 1000 and the second region 2000. The third work function metal (WFM) layer 256 may have a different conductivity type than the first work function metal (WFM) layer 244 or the second work function metal (WFM) layer. In some embodiments, the third work function metal (WFM) layer 256 may be an n-type work function metal (WFM) layer and may include aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), hafnium carbide (HfC), other n-type work function materials, or combinations thereof. The third work function metal (WFM) layer 256 may be deposited using atomic layer deposition (ALD). Fig.23 As shown, the thickness of the third work function metal (WFM) layer 256 is such that the space between two adjacent first nanostructures 2080 in the first region 1000 is not completely filled.

[0093] Please refer to Figure 1 and Fig.24 , the method 100 includes step block 128, wherein a glue layer 258 is deposited over the third work function metal (WFM) layer 256. In some embodiments, the glue layer 258 may include titanium nitride. In these embodiments, the composition of the glue layer 258 may be the same as the composition of the first work function metal (WFM) layer 244 or the second work function metal (WFM) layer 250. In some embodiments, the glue layer 258 may be formed by atomic layer deposition (ALD). In some cases, the deposition of the glue layer 258 causes the space between two adjacent first nanostructures 2080 in the first region 1000 to be truncated, resulting in that subsequent film layers cannot be deposited between the two adjacent first nanostructures 2080.

[0094] Please refer to Figure 1 and Fig.25 , the method 100 includes step block 130, wherein a gate cap layer 260 is deposited over the first region 1000 and the second region 2000. In some embodiments, the gate cap layer 260 may include tungsten (W) and may be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Fig.25 As shown, each of the third work function metal (WFM) layer 256 , the glue layer 258 and the gate cap layer 260 extends and crosses the first region 1000 and the second region 2000 , thereby forming a common gate structure that joins the nanostructure 2080 above the first region 1000 and the second nanostructure 2080 in the second region 2000 .

[0095] Please still refer to Fig.25, the conformal deposition of the third work function metal (WFM) layer 256 and the glue layer 258 can maintain the step shape of the step-shaped feature 300, which is caused by the individual patterning of the first work function metal (WFM) layer 244 and the second work function metal (WFM) layer 250. Fig.26 In some other embodiments shown, the individually patterned first work function metal (WFM) layer 244 and second work function metal (WFM) layer 250 may also form an enclosure step feature 400 where the second work function metal (WFM) layer 250 surrounds the edge of the first work function metal (WFM) layer 244. Similar to the step feature 300, the subsequent conformal deposition of the third work function metal (WFM) layer 256 and the glue layer 258 may maintain the step-like shape.

[0096] The present disclosure provides a process embodiment for forming a gate structure of a multi-gate device. In one embodiment, a method for forming a semiconductor structure is provided. The method includes: receiving a working component, which includes a plurality of first nanostructures located above a first region of a substrate and a plurality of second nanostructures located above a second region of the substrate; depositing a gate dielectric layer on the surface of each of the plurality of first nanostructures and on the surface of each of the plurality of second nanostructures; depositing a first work function metal layer on the plurality of first nanostructures above the first region and on the plurality of second nanostructures above the second region; depositing a first hard mask layer on the first work function metal layer; selectively removing the first hard mask layer and the first work function metal layer located above the first region; selectively removing the first hard mask layer located above the second region; after selectively removing the first hard mask layer located above the second region, depositing a second work function metal layer on the plurality of first nanostructures above the first region and on the plurality of second nanostructures above the second region; depositing a second hard mask layer on the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer located above the first region; and depositing a third work function metal layer on the plurality of first nanostructures above the first region and on the plurality of second nanostructures above the second region.

[0097] In some embodiments, the first work function metal layer and the second work function metal layer include titanium nitride (TiN), titanium silicon nitride (TiSiN or TSN), or tungsten carbonitride (WCN). In some embodiments, the composition of the first work function metal layer is the same as the composition of the second work function metal layer. In some embodiments, the first hard mask layer and the second hard mask layer include aluminum oxide. In some embodiments, the third work function metal layer includes aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), or hafnium carbide (HfC). In some embodiments, the above method further includes trimming the first hard mask layer before selectively removing the first hard mask layer and the first work function metal layer located above the first region; and trimming the second hard mask layer before selectively removing the second hard mask layer and the second work function metal layer located above the first region. In some embodiments, the method further comprises depositing a glue layer on the third work function metal layer; and depositing a gate cap layer on the glue layer. In some cases, the glue layer comprises titanium nitride. In some embodiments, the gate cap layer comprises tungsten (W).

[0098] In another embodiment, a method for forming a semiconductor structure is provided. The method includes: receiving a working component, which includes a plurality of first nanostructures located on a first substrate fin and a plurality of second nanostructures located on a second substrate fin separated from the first substrate fin by an isolation feature; depositing a gate dielectric layer on the surface of each of the plurality of first nanostructures and on the surface of each of the plurality of second nanostructures; depositing a first work function metal layer over the plurality of first nanostructures and the plurality of second nanostructures and in contact with the gate dielectric layer; depositing a first hard mask layer over the first work function metal layer, so that the first hard mask layer is connected to the gate dielectric layer through the first work function metal layer. The present invention relates to a method for separating the first nanostructures from the second nanostructures by an electrical layer; selectively removing the first hard mask layer and the first work function metal layer between the plurality of first nanostructures; selectively removing the first hard mask layer between the plurality of second nanostructures; depositing a second work function metal layer over the plurality of first nanostructures and the plurality of second nanostructures; depositing a second hard mask layer over the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer between the plurality of first nanostructures; and depositing a third work function metal layer to surround each of the plurality of first nanostructures and the second work function metal layer over the plurality of second nanostructures.

[0099] In some embodiments, after depositing the gate dielectric layer, a portion of the gate dielectric layer extends continuously from above the first substrate fin to above the second substrate fin. In some embodiments, after depositing the first work function metal layer, a portion of the first work function metal layer extends continuously from above the first substrate fin to above the second substrate fin. In some embodiments, selectively removing the first hard mask layer and the first work function metal layer between the plurality of first nanostructures comprises: trimming the first hard mask layer to expose portions of the first work function metal layer located on the top surfaces and sidewalls of the plurality of first nanostructures, on the top surfaces and sidewalls of the plurality of second nanostructures, and on the isolation feature; depositing a first patterned film layer to cover the plurality of second nanostructures and the second substrate fin; removing the first hard mask layer between the plurality of first nanostructures; and removing the first patterned film layer. In some embodiments, the first hard mask layer comprises aluminum oxide, and the trimming comprises isotropic wet etching using ammonium hydroxide. In some embodiments, selectively removing the second hard mask layer and the second work function metal layer between multiple first nanostructures includes: trimming the second hard mask layer to expose portions of the second work function metal layer located on the top surfaces and side walls of the multiple first nanostructures, on the top surfaces and side walls of the multiple second nanostructures, and on the isolation feature components; depositing a second patterned film layer to cover the multiple second nanostructures and the second base fins; removing the second hard mask layer between the multiple first nanostructures; removing the second work function metal layer between the multiple first nanostructures; and removing the second patterned film layer.

[0100] In another embodiment, a semiconductor structure is provided. The semiconductor structure includes: a first base fin and a second base fin, located above a substrate; an isolation component, located above the substrate and directly disposed between the first base fin and the second base fin; a plurality of first nanostructures, disposed above the first base fin; a plurality of second nanostructures, disposed above the second base fin; a gate dielectric layer, surrounding each of the plurality of first nanostructures, each of the plurality of second nanostructures, and disposed on the first base fin, the second base fin, and the upper surface of the isolation feature component; a first work function layer surrounding each of the plurality of second nanostructures, and disposed above the second base fin; a second work function layer surrounding each of the plurality of second nanostructures and filling the space between the plurality of second nanostructures; a third work function layer surrounding each of the plurality of first nanostructures, and located on the second work function layer surrounding the plurality of second nanostructures; a glue layer, disposed on the third work function layer; and a gate cap layer, located on the glue layer. There is an interface between the first work function layer and the second work function layer.

[0101] In some embodiments, the first work function layer and the second work function layer include p-type work function materials. In some embodiments, the third work function layer includes n-type work function materials. In some embodiments, the composition of the first work function layer is the same as the composition of the second work function layer. In some embodiments, the interface includes an oxide form of a metal component in the first work function layer.

[0102] The above briefly describes the characteristic components of several embodiments of the present invention, so that those skilled in the art can more easily understand the types of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A working component is received, comprising: A plurality of first nanostructures are located above a first region of a substrate; and A plurality of second nanostructures are located above a second region of the substrate; Depositing a gate dielectric layer on a surface of each of the plurality of first nanostructures and on a surface of each of the plurality of second nanostructures; Depositing a first work function metal layer on the first nanostructures above the first region and on the second nanostructures above the second region; Depositing a first hard mask layer over the first work function metal layer; Selectively removing the first hard mask layer and the first work function metal layer located above the first region; Selectively removing the first hard mask layer located above the second region; After selectively removing the first hard mask layer located above the second region, depositing a second work function metal layer above the plurality of first nanostructures above the first region and above the plurality of second nanostructures above the second region; Depositing a second hard mask layer over the second work function metal layer; Selectively removing the second hard mask layer and the second work function metal layer located above the first region; and A third work function metal layer is deposited on the first nanostructures above the first region and on the second nanostructures above the second region. 2 . The method for forming a semiconductor structure as claimed in claim 1 , wherein a composition of the first work function metal layer is the same as a composition of the second work function metal layer.

3. The method for forming a semiconductor structure according to claim 1, further comprising: Before selectively removing the first hard mask layer and the first work function metal layer located above the first region, trimming the first hard mask layer; as well as Before selectively removing the second hard mask layer and the second work function metal layer located above the first region, the second hard mask layer is trimmed.

4. The method for forming a semiconductor structure according to claim 1, further comprising: Depositing a glue layer on the third work function metal layer; as well as A gate cap layer is deposited on the glue layer.

5. A method for forming a semiconductor structure, comprising: A working component is received, comprising: A plurality of first nanostructures are located on a first base fin; and a plurality of second nanostructures located on a second substrate fin separated from the first substrate fin by an isolation feature; Depositing a gate dielectric layer on a surface of each of the plurality of first nanostructures and on a surface of each of the plurality of second nanostructures; Depositing a first work function metal layer over the first nanostructures and the second nanostructures and contacting the gate dielectric layer; Depositing a first hard mask layer over the first work function metal layer such that the first hard mask layer is separated from the gate dielectric layer by the first work function metal layer; Selectively removing the first hard mask layer and the first work function metal layer located between the first nanostructures; Selectively removing the first hard mask layer between the plurality of the second nanostructures; Depositing a second work function metal layer on the plurality of the first nanostructures and the plurality of the second nanostructures; Depositing a second hard mask layer over the second work function metal layer; selectively removing the second hard mask layer and the second work function metal layer between the plurality of the first nanostructures; and A third work function metal layer is deposited to surround each of the first nanostructures and is located on the second work function metal layer above the second nanostructure. 6 . The method for forming a semiconductor structure as claimed in claim 5 , wherein after depositing the gate dielectric layer, a portion of the gate dielectric layer continuously extends from above the first base fin portion to above the second base fin portion. 7 . The method for forming a semiconductor structure as claimed in claim 5 , wherein after depositing the first work function metal layer, a portion of the first work function metal layer continuously extends from above the first base fin to above the second base fin.

8. A semiconductor structure comprising: A first base fin and a second base fin are located above a substrate; an isolation member located above the substrate and disposed directly between the first substrate fin and the second substrate fin; A plurality of first nanostructures are disposed above the first substrate fin; A plurality of second nanostructures are disposed above the second substrate fin; a gate dielectric layer surrounding each of the plurality of the first nanostructures, each of the plurality of the second nanostructures, and disposed on the upper surfaces of the first base fin, the second base fin, and the isolation feature; a first work function layer, surrounding each of the plurality of the second nanostructures and disposed above the second substrate fin; a second work function layer, surrounding each of the plurality of the second nanostructures and filling spaces between the plurality of the second nanostructures; a third work function layer surrounding each of the plurality of the first nanostructures and located on the second work function layer surrounding the plurality of the second nanostructures; a glue layer, disposed on the third work function layer; as well as a gate cap layer, located on the glue layer, An interface exists between the first work function layer and the second work function layer. 9 . The semiconductor structure of claim 8 , wherein the first work function layer and the second work function layer comprise p-type work function materials.

10. The semiconductor structure of claim 8, wherein the interface comprises an oxide form of a metal component in the first work function layer.

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