Formation method of semiconductor structure, semiconductor structure, device and electronic device

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure forming method, a semiconductor structure, a device and an electronic device. The forming method of the semiconductor structure comprises the following steps: providing a substrate structure with a first groove; the substrate structure comprises a base layer, an epitaxial layer, a first oxide layer, a hard mask layer and a second oxide layer which are arranged in sequence; the first trench penetrates through the first oxide layer, the hard mask layer and the second oxide layer, and the bottom of the first trench is located on the epitaxial layer; performing back etching on the hard mask layer of the substrate structure with the first groove twice, and forming an isolation oxide layer on the surface of the first groove by adopting a thermal oxidation process between the two times of back etching on the hard mask layer; and subsequently forming an interlayer dielectric layer in the first groove to obtain a target semiconductor structure. Therefore, not only can the formed isolation oxide layer not generate film stress, but also the beak effect and the influence of a hard mask eave on the filling quality of the subsequently formed interlayer dielectric layer can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure, a semiconductor structure, a device and an electronic apparatus. Background Art

[0002] The forming process of semiconductor devices usually involves the formation of grooves. After the grooves, in order to isolate the influence between the layers in the previous and subsequent processes, an oxide layer is first formed on the side walls of the grooves as an isolation layer. The isolation layer is a necessary forming step in semiconductor devices. The quality of its formation will affect the film quality of subsequent layers and ultimately affect the performance of semiconductor devices. This makes it a research hotspot for relevant personnel.

[0003] In the prior art, one solution is to use a combination of thermal oxidation and deposition processes to form a composite oxide layer on the sidewalls of the groove. Although the formed oxide layer is not prone to the bird's beak effect, the process of forming the oxide layer is relatively complicated and is also prone to film stress. Another solution is to use direct thermal oxidation to form an oxide layer on the sidewalls of the groove. The molding process is simple and can also improve film stress, but this solution is prone to produce a bird's beak effect and a hard mask eaves, causing quality defects in the subsequently formed material layer (such as the presence of filled gaps), thereby affecting the performance of the device. Therefore, how to provide a semiconductor manufacturing solution that can avoid the film stress of the oxide layer and reduce the impact of the bird's beak effect and the hard mask eaves problem on subsequent processes has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present application discloses, on one hand, a method for forming a semiconductor structure, which comprises:

[0005] A substrate structure having a first trench is provided; the substrate structure comprises a base layer, an epitaxial layer, a first oxide layer, a hard mask layer and a second oxide layer arranged in sequence; the first trench penetrates the first oxide layer, the hard mask layer and the second oxide layer, and the bottom of the first trench is located in the epitaxial layer;

[0006] Performing a first etching back process on the hard mask layer to remove a portion of the hard mask layer adjacent to an opening of the first trench;

[0007] forming an isolation oxide layer on the surface of the first trench based on a thermal oxidation process;

[0008] Performing a second etching back process on the substrate structure having the isolation oxide layer to remove the second oxide layer, a portion of the first oxide layer and a portion of the isolation oxide layer, and making the side edge of the hard mask layer flush with the side wall of the first trench;

[0009] An interlayer dielectric layer is formed in the first trench to obtain a target semiconductor structure.

[0010] In an exemplary embodiment, the first etch-back process etches back the hard mask layer less than the second etch-back process etches back the hard mask layer.

[0011] In an exemplary embodiment, after the first back etching process, the first side edge of the hard mask layer and the second side edge of the first oxide layer are recessed inward relative to the inner wall of the first trench to expose a local area of ​​the top of the epitaxial layer; the first side edge and the second side edge are the side edges of the hard mask layer and the first oxide layer close to the inner wall of the first trench, respectively.

[0012] In an exemplary embodiment, before performing a second etching back process on the substrate structure having the isolation oxide layer, the method further includes:

[0013] A third etching back process is performed on the substrate structure having the isolation oxide layer to expose an end portion of the hard mask layer.

[0014] In an exemplary embodiment, the thickness of the second oxide layer after the third etching back process is less than the thickness of the second oxide layer after the first etching back process.

[0015] In an exemplary embodiment, after the third etching back process, the thickness of the second oxide layer is greater than or equal to a first preset thickness, and the first preset thickness is 450 to 550 angstroms.

[0016] In an exemplary embodiment, forming an isolation oxide layer on the surface of the first trench based on a thermal oxidation process includes:

[0017] forming an isolation oxide layer on the surface of the first trench based on a thermal oxidation process, thereby obtaining a second trench formed by the isolation oxide layer surrounding the first trench;

[0018] A source conductor is formed in the second trench; a top of the source conductor is lower than a top of the epitaxial layer.

[0019] In an exemplary embodiment, the step of forming an interlayer dielectric layer in the first trench to obtain a target semiconductor structure includes:

[0020] forming an interlayer dielectric layer in the first trench and on the surface of the hard mask layer;

[0021] performing a planarization process on the surface of the substrate structure formed with the interlayer dielectric layer to remove the interlayer dielectric layer and a portion of the hard mask layer located on the hard mask layer;

[0022] The hard mask layer, the first oxide layer and a portion of the interlayer dielectric layer are removed so that a top of the interlayer dielectric layer is lower than a top of the epitaxial layer and the interlayer dielectric layer covers an end of the source conductor.

[0023] In an exemplary embodiment, in the target semiconductor structure, an angle between a top of the isolation oxide layer and an inner wall of the first trench is an obtuse angle.

[0024] In an exemplary embodiment, the isolation oxide layer has a thickness of 4000 to 9000 angstroms.

[0025] On the other hand, the present application further discloses a semiconductor structure, which is prepared based on the above-mentioned formation method.

[0026] The present application further discloses a method for forming a semiconductor device, which comprises:

[0027] After forming the target semiconductor structure, a gate is formed; the target semiconductor structure is prepared based on the above-mentioned formation method.

[0028] On the other hand, the present application further discloses a semiconductor device, which is prepared based on the above-mentioned formation method.

[0029] In another aspect, the present application further discloses an electronic device, which includes the above-mentioned semiconductor device.

[0030] A method for forming a semiconductor structure provided in an embodiment of the present application is specifically performed by etching back a hard mask layer of a substrate structure having a first groove twice, and between the two etchings of the hard mask layer, a thermal oxidation process is used to form an isolation oxide layer on the surface of the first groove. This method of directly using a molding process to form the isolation oxide layer makes the formed film layer uniform, and is less likely to generate film stress compared to the existing method of using a composite process to form the isolation oxide layer. In addition, by etching back the hard mask layer twice, that is, etching back once before forming the isolation oxide layer, the width of the hard mask layer is reduced, thereby reducing the bird's beak effect of the isolation oxide layer formed subsequently, and etching back the hard mask layer again after forming the isolation oxide layer, the side of the hard mask layer can be made flush with the side wall of the first groove, thereby reducing the influence of the eaves structure of the hard mask layer on the filling quality of subsequent materials (such as the interlayer dielectric layer). BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A scanning electron microscope image of a conventional semiconductor device exemplified in this application;

[0033] Figure 2 A schematic diagram of a process for forming a semiconductor structure exemplified in the present application;

[0034] Figure 3 A cross-sectional view of a substrate structure having a first trench according to an exemplary embodiment of the present application;

[0035] Figure 4 This is a cross-sectional view of a substrate structure after a first back-etching process exemplified in the present application;

[0036] Figure 5 This is a cross-sectional view of a substrate structure after forming a source conductor according to an exemplary embodiment of the present application;

[0037] Figure 6 This is a cross-sectional view of a substrate structure after a third back etching process exemplified in the present application;

[0038] Figure 7 This is a cross-sectional view of a substrate structure after a second etching back process exemplified in the present application;

[0039] Figure 8 A cross-sectional view of an exemplary target semiconductor structure of the present application;

[0040] Fig. 9 This is a cross-sectional view of a substrate structure after an interlayer dielectric layer is etched back as an example of the present application;

[0041] Fig.10 This is a scanning electron microscope image corresponding to a comparative example 2 of the present application;

[0042] Fig.11 This is a scanning electron microscope image corresponding to a comparative example 3 of the present application;

[0043] Fig.12 This is a scanning electron microscope image of an exemplary target semiconductor structure of the present application.

[0044] The following is a supplementary description of the attached drawings:

[0045] 1-base layer; 2-epitaxial layer; 3-first oxide layer; 4-hard mask layer; 5-second oxide layer; 6-first trench; 7-isolation oxide layer; 8-concave structure; 9-second trench; 10-source conductor; 11-interlayer dielectric layer. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0048] When a numerical range is disclosed herein, the above range is deemed to be continuous and includes the minimum and maximum values ​​of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all sub-ranges included therein. For example, a specified range from "1 to 10" should be deemed to include any and all sub-ranges between a minimum of 1 and a maximum of 10. Exemplary sub-ranges of ranges 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0049] The manufacturing process of semiconductor integrated circuits usually involves the processing and forming of multiple types of semiconductor devices or multiple devices of the same type. Since the functions of these semiconductor devices may be different, in order to avoid crosstalk between devices, it is usually necessary to set grooves between the devices. Alternatively, in a semiconductor device, in order to avoid the influence between different structures (such as side-by-side structures or structures stacked up and down), grooves are also set and isolation materials are formed in the grooves as isolation layers. Such isolation materials can usually be silicon oxide or silicon oxide derivatives, such as silicon nitride, silicon oxynitride, silicon oxycarbide, amorphous carbon and silicon oxycarbonitride. Among them, the commonly used molding process is to first use a high-temperature thermal oxidation process to form a silicon oxide layer, which can be called a thermal oxide layer (Pad OX, POX). However, in order to ensure the isolation effect, when a thicker thermal oxide layer is formed, a bird's beak effect is easily generated, and there will also be a hard mask eaves problem, resulting in quality defects in the subsequent material layer (such as the presence of filled gaps), thereby affecting the performance of the device.

[0050] The bird's beak effect is a phenomenon in the local oxidation (LOCOS) process. It occurs at the edge of the oxide layer formed on the silicon wafer. In the LOCOS process, in order to isolate different devices, a layer of silicon dioxide needs to be grown on the silicon wafer. The oxidation process will cause volume expansion at the interface between the oxide layer and the silicon wafer. When silicon is oxidized to silicon dioxide, the volume will increase. This volume expansion causes the edge of the oxide layer to push outward, forming a shape similar to a bird's beak, which is the so-called "bird's beak effect". The bird's beak effect will cause the actual isolation area to be larger than expected, which limits the further reduction of the device size, affects the integration and performance of the integrated circuit, and may also cause uneven electric field strength, affecting the reliability and long-term stability of the device.

[0051] In order to avoid the above defects, the existing scheme usually adopts a combination of thermal oxidation process and other deposition processes to make the thickness of the thermal oxide layer thinner (such as less than 2000 angstroms), and then uses chemical vapor deposition (Chemical Vapor Deposition, CVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vaper Deposition, PECVD) to form an oxide layer, thereby forming a composite oxide layer formed by thermal oxidation process + deposition process. But obviously, the forming steps of this scheme are more complicated, and this composite material layer is also prone to membrane stress, affecting the performance of semiconductor devices.

[0052] In order to explain the above problem more clearly, the manufacturing process of a shielded gate trench power MOS device (shield gate trench-Metal-Oxide-Semiconductor Field-Effect Transistor, SGT-MOSFET), i.e., an SGT-MOS device, will be taken as an example for explanation below.

[0053] As a power device, SGT-MOS devices have the characteristics of high breakdown voltage, low on-resistance, and fast switching speed. They can be used in power circuits, motor drives, home appliances and other application fields. SGT-MOS devices usually include a gate located in the upper half of the trench and a source located in the lower half of the trench, and an isolation oxide layer 7 is provided between the gate and the source. The manufacturing process of SGT-MOS devices mainly involves the formation of trenches, sources, gates, and isolation oxide layers 7. For details, please refer to Figure 1 , which is a scanning electron microscope image of an exemplary existing semiconductor device of the present application. A mask layer can be formed on a substrate (specifically including a base layer and an epitaxial layer 2 located on the base layer) first. The mask layer is specifically a composite layer structure, such as a three-layer composite structure of an oxide layer-hard mask layer-oxide layer. The material of the hard mask layer 4 can be silicon nitride, and the mask layer can be a SiO2-SiN-SiO2 structure, which can also be called an ONO structure. Next, a layer of photoresist is formed on the mask layer, and the mask layer is patterned using a photolithography process, and then the photoresist is removed, and the substrate is etched with the pattern defined by the mask layer to form a groove. Subsequently, a thermal oxidation process or a composite process can be directly used to form an isolation oxide layer 7 in the groove, and the first layer of polysilicon is filled in the groove, and back etching is performed to form a source conductor 10 (i.e., a source electrode), and then an isolation oxide layer 7 is deposited, polysilicon is deposited and etched to form a gate, and finally subsequent processes such as body ion implantation and source ion implantation are performed. When the isolation oxide layer 7 is formed directly in the trench by a thermal oxidation process, the following will be formed: Figure 1 The bird's beak effect shown in the dotted box will also produce the eaves of the hard mask layer 4, which will further affect the quality defects of the subsequently formed material layer (such as the presence of filled gaps). When the composite process is used to form the isolation oxide layer 7, although the influence of the above defects can be reduced, the molding steps are relatively complicated, and this composite material layer is also prone to membrane stress, affecting the performance of the semiconductor device.

[0054] To do this, see Figure 2 , which is a schematic flow chart of an exemplary method for forming a semiconductor structure of the present application. The method for forming a semiconductor structure provided in an embodiment of the present application may include the following steps:

[0055] S201: Provide a substrate structure having a first groove; the substrate structure includes a base layer, an epitaxial layer, a first oxide layer, a hard mask layer, and a second oxide layer arranged in sequence; the first groove penetrates the first oxide layer, the hard mask layer, and the second oxide layer, and the bottom of the first groove is located in the epitaxial layer.

[0056] Exemplarily, step S201 may specifically include: providing a base layer 1 (see Figure 3 ), the material of the base layer 1 may specifically be at least one of silicon or silicon on insulator (SOI), etc. In the embodiment of the present application, the base layer 1 may be a single crystal silicon substrate.

[0057] An epitaxial layer 2 is formed on the substrate layer 1. Optionally, the epitaxial layer 2 is specifically formed by an epitaxial growth process, and can be a homogeneous epitaxial layer, such as being able to continue to grow along the lattice direction of the substrate layer 1 to form the epitaxial layer 2, or a heterogeneous epitaxial layer, and the specific growth temperature can be the same as the existing process, or can be adaptively adjusted. Optionally, the epitaxial layer 2 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0058] A first oxide layer 3, a hard mask layer 4, and a second oxide layer 5 are sequentially deposited on the epitaxial layer 2. Optionally, the first oxide layer 3 and the second oxide layer 5 may both be silicon oxide, the first oxide layer 3 may be formed by a thermal oxidation process, and the second oxide layer 5 may be formed by a plasma chemical vapor deposition process, the hard mask layer 4 may specifically be silicon nitride, and a chemical vapor deposition (Chemical Vapor Deposition, CVD) may be used, such as plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD), high density plasma chemical vapor deposition (High Density Plasma CVD, HDPCVD), sub atmospheric pressure chemical vapor deposition (Sub Atmospheric CVD, SACVD), low pressure chemical vapor deposition (Low Pressure CVD, LPCVD), atomic layer deposition (Atomic Layer Deposition, ALD), plasma enhanced atomic layer deposition (Plasma Enhanced Atomic Layer Deposition, PEALD), or other types of chemical vapor deposition processes to form a hard mask. In the embodiment of the present application, a PECVD process may be used to form a silicon nitride material on the first oxide layer 3 as the hard mask layer 4 .

[0059] The thickness of the second oxide layer 5 is greater than the thickness of the first oxide layer 3. Optionally, the thickness of the first oxide layer 3 can be 100 to 300 angstroms. An exemplary thickness of the first oxide layer 3 can be 100 angstroms, 120 angstroms, 140 angstroms, 160 angstroms, 180 angstroms, 200 angstroms, 220 angstroms, 240 angstroms, 260 angstroms, 280 angstroms or 300 angstroms. The thickness of the second oxide layer 5 can be 1700 to 3000 angstroms. An exemplary thickness of the second oxide layer 5 can be 1700 angstroms, 1900 angstroms, 2100 angstroms, 2300 angstroms, 2500 angstroms, 2700 angstroms, 2900 angstroms or 3000 angstroms. In fact, the thickness of the first oxide layer 3 and the second oxide layer 5 is not limited to the above-mentioned example thicknesses, and can be adaptively adjusted as needed.

[0060] The mask layer composed of the first oxide layer 3, the hard mask layer 4 and the second oxide layer 5 is patterned to form an etching window, and the epitaxial layer 2 is etched to a preset depth based on the etching window to form a first trench 6, so as to obtain Figure 3 The structure shown. Optionally, the specific process of patterning the mask layer can be: firstly coating a photoresist on the second oxide layer 5, and patterning the photoresist to expose a partial area of ​​the second oxide layer 5, and etching the mask layer based on the patterned photoresist to form a patterned mask layer. Optionally, the hard mask layer 4 can be etched by a wet etching process, such as a phosphoric acid wet etching process. The first oxide layer 3 and the second oxide layer 5 can also be etched by a wet etching process. Optionally, a wet etching process can be used for the epitaxial layer 2, and a dry etching process can also be used, wherein the dry etching process includes but is not limited to at least one of ion milling etching, plasma etching, reactive ion etching and laser ablation.

[0061] The first groove 6 can be a deep groove or a shallow groove, which is selected according to the performance requirements of the device to be manufactured. Generally, the width of a typical deep groove is between 65nm and 0.5um, and the depth is between 2 and 5nm. In the embodiment of the present application, the first groove 6 is a deep groove.

[0062] In the embodiment of the present application, the formation of multiple SGT-MOS devices is taken as an example for explanation. For example, two SGT-MOS devices may be formed. In fact, the present solution is also applicable to the formation of single or array SGT-MOS devices, as well as other integrated circuits that are compatible with the steps S201-S209 process.

[0063] S203: performing a first etching back process on the hard mask layer to remove a portion of the hard mask layer adjacent to the opening of the first trench.

[0064] In an exemplary embodiment, after the first etching back process, the first side edge of the hard mask layer 4 and the second side edge of the first oxide layer 3 are recessed inward relative to the inner wall of the first trench 6 to expose a local area of ​​the top of the epitaxial layer 2, and the following can be obtained: Figure 4 The structure shown in FIG. 1 ; the first side and the second side are the sides of the hard mask layer 4 and the first oxide layer 3 close to the inner wall of the first trench 6, respectively. Specifically, after the first back etching process, the bottom of the second oxide layer 5, the first side of the hard mask layer 4, the second side of the first oxide layer 3 and the top of the epitaxial layer 2 can form the following structure: Figure 4 The concave structure 8 is shown. By first etching back a small amount of the hard mask layer 4 in the mask layer, a small portion of the top area of ​​the epitaxial layer 2 can be exposed at the opening of the first trench 6, which is conducive to the formation of an unclosed trench profile when the subsequent isolation oxide layer 7 grows. Optionally, the hard mask layer 4 can be laterally etched by a wet etching process.

[0065] Exemplarily, the etching amount of the hard mask layer 4 in the first etching back process is 600 to 1500 angstroms. An exemplary etching amount of the first etching back process of the hard mask layer 4 is 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms or 1500 angstroms; the width of the exposed top of the epitaxial layer 2 is 0.03 to 0.1 microns, and the width of the exposed area of ​​the top of the epitaxial layer 2 after the first etching back process of an exemplary hard mask layer 4 is 0.03 microns, 0.035 microns, 0.04 microns, 0.045 microns, 0.05 microns, 0.055 microns, 0.06 microns, 0.07 microns, 0.08 microns, 0.09 microns or 0.1 microns. In fact, the specific etching amount and the width of the exposed area of ​​the epitaxial layer 2 are not limited to the specific values ​​of the above examples, and can be adjusted and determined according to actual processing conditions.

[0066] S205: forming an isolation oxide layer on the surface of the first trench based on a thermal oxidation process.

[0067] In an exemplary embodiment, the thickness of the isolation oxide layer 7 is 4000 to 9000 angstroms. Obviously, compared with the thickness of the thermal oxide layer in the composite process (such as less than 2000 angstroms), the thermal oxide layer formed by the direct thermal oxide process in the present application does not need to be composited with other process materials, thereby reducing the influence of film stress on subsequent processes and devices.

[0068] Exemplarily, step S205 may specifically include: forming a thermal oxide layer on the surface of the first trench 6 and the surface of the second oxide layer 5 based on a thermal oxidation process, that is, obtaining an isolation oxide layer 7 to achieve an isolation effect.

[0069] In the embodiment of the present application, when it is applied to the SGT-MOS device, after the above step S205 and before the following step S207, it also includes the formation of the source conductor 10. Therefore, the above step S205 can also be described as: forming an isolation oxide layer 7 on the surface of the first trench 6 based on a thermal oxidation process to obtain a second trench 9 formed by the isolation oxide layer 7 surrounding the first trench 6; forming a source conductor 10 in the second trench 9, and the following can be obtained. Figure 5 The structure shown; the top of the source conductor 10 is lower than the top of the epitaxial layer 2.

[0070] After forming the second trench 9 , a source material may be formed on the surface of the second trench 9 and on the top of the isolation oxide layer 7 , and a source conductor 10 may be formed in the second trench 9 by successively planarizing and etching back the source material layer.

[0071] In the embodiment of the present application, a layer of source material can be covered on the upper surface of the isolation oxide layer 7 by a vapor deposition process, and the source material includes but is not limited to polysilicon. Then, a chemical mechanical polishing process can be used to remove excess source material. Specifically, the source material can be polished to the isolation oxide layer 7 to stop, that is, the source material on the isolation oxide layer 7 is removed. The source material in the second trench 9 is etched back by a dry etching process so that the source material in the second trench 9 is lower than the top of the epitaxial layer 2.

[0072] Since the isolation oxide layer 7 is relatively thick, it takes a long time to subsequently etch back the hard mask layer 4. In order to shorten the subsequent etch back time of the hard mask layer 4, the oxide layer may be etched back appropriately to expose the end of the hard mask layer 4, thereby increasing the contact area between the hard mask layer 4 and the etching liquid and accelerating the etch back speed of the hard mask. Therefore, in an exemplary embodiment, before performing the second etch back treatment on the substrate structure having the isolation oxide layer, the method further includes: performing a third etch back treatment on the substrate structure having the isolation oxide layer 7 to expose the end of the hard mask layer 4, and obtaining the following Figure 6 The structure shown.

[0073] Exemplarily, after the third back-etching process, the thickness of the second oxide layer 5 is less than the thickness of the second oxide layer 5 after the first back-etching process, that is, during the third back-etching process, the second oxide layer 5 will also be partially etched, but a portion of the thickness of the second oxide layer 5 still needs to be retained. Optionally, after the third back-etching process, the thickness of the second oxide layer 5 is greater than or equal to a first preset thickness, the first preset thickness is 400 to 550 angstroms, and an exemplary first preset thickness can be 400 angstroms, 420 angstroms, 440 angstroms, 460 angstroms, 480 angstroms, 500 angstroms, 520 angstroms, 540 angstroms or 550 angstroms. Thus, the process window of the fluctuation of the previous layer and the fluctuation of the etching rate of the current process step can be guaranteed. The amount of the third back-etching can be adjusted according to the remaining thickness of the second oxide layer 5 of the previous layer, the exposed size of the end of the hard mask layer 4, and the size of the obtuse angle required to be formed between the isolation oxide layer 7 and the inner wall of the first groove 6, because the maximum amount of the third back-etching is determined by the remaining thickness of the second oxide layer 5 of the previous layer after the minimum remaining amount is defined, and the third back-etching amount will affect the size of the exposed area of ​​the end of the hard mask layer 4, and the exposed area will affect the amount of hard mask back-etching, and at the same time affect the size of the obtuse angle formed subsequently. Generally speaking, the larger the third back-etching amount, the larger the obtuse angle accordingly, and there is a certain adjustment relationship, which leaves enough process window for the subsequent deposition of the interlayer dielectric layer 11.

[0074] Based on the above, before the subsequent step S207, that is, before the substrate structure with the isolation oxide layer 7 is subjected to the second etching back process, the partial oxide layer in the semiconductor structure is first etched back, so that the exposed area of ​​the end of the hard mask layer 4 can be increased. If the partial oxide layer is not etched first, Figure 5 It can be seen that the hard mask layer 4 is located between two oxide layers, and the exposed area at both ends of the hard mask layer 4 is very small. It takes a long time to directly etch the hard mask layer later. Therefore, the characteristic of the second oxide layer 5 being thin at both ends and thick in the middle can be used to first perform an appropriate amount of oxide layer back etching, remove the second oxide layer 5 above the end of the hard mask layer 4 and the first oxide layer 3 below, so that more areas are exposed at the end of the hard mask layer 4. When the hard mask layer 4 is etched later, its etching speed can be greatly improved. Optionally, the etching speed ratio of the hard mask layer 4 to the oxide layer is (10-20):1.

[0075] And because the hard mask layer 4 forms an arc structure after the isolation oxide layer 7 is formed, under the blocking of the hard mask layer 4, when part of the oxide layer is etched back, the side wall of the oxide layer will form a profile with a certain inclination angle, that is, slightly higher at both ends and slightly lower in the middle. This inclined profile will be inherited by the subsequent process of etching the oxide layer, so that the thickness of the oxide layer formed at the corner is thicker, thereby increasing the breakdown voltage of the device.

[0076] In the embodiment of the present application, during the third back-etching process of the oxide layer in the structure formed in step S205, a partial area of ​​the first oxide layer 3, a partial area of ​​the second oxide layer 5, and a partial area of ​​the isolation oxide layer 7 at the opening of the second trench 9 may be etched and removed. The specific amount of etching is determined based on the area of ​​the end of the hard mask layer 4 that needs to be exposed. After the third back-etching, the top of the source conductor 10 may be exposed or not, and there is no limitation here.

[0077] S207: performing a second etching back process on the substrate structure having the isolation oxide layer to remove the second oxide layer, a portion of the first oxide layer and a portion of the isolation oxide layer, and making the side edge of the hard mask layer flush with the side wall of the first trench.

[0078] In the embodiment of the present application, the second etching back process of step S207 specifically includes etching back the hard mask layer 4 and etching back the oxide layer. Through the second etching back of the hard mask layer 4, the side of the hard mask layer 4 can be flush with the side wall of the first trench 6, and the second etching back process of the oxide layer can be specifically etching back the first oxide layer 3, the second oxide layer 5 and the isolation oxide layer 7, so as to remove the second oxide layer 5, part of the first oxide layer 3 and part of the isolation oxide layer 7.

[0079] In an exemplary embodiment, the first etching back process performs a smaller etching back amount on the hard mask layer 4 than the second etching back process, that is, by first etching back a small amount on the hard mask layer 4 and then etching back a large amount on the hard mask layer 4, the bird's beak effect can be effectively reduced, and the side wall of the hard mask layer can be flush with the inner wall of the first trench 6 by the second etching back (see Figure 7 ), the influence of the eaves of the hard mask layer 4 on the filling of subsequent material layers can be reduced.

[0080] Exemplarily, a wet etching process may be used to perform a laterally etched hard mask layer 4 , for example, a phosphoric acid wet etching process may be used to perform a second etching back process on the hard mask layer 4 .

[0081] In the embodiment of the present application, the substrate structure after the second back etching process can be as follows: Figure 7 The structure shown, after the second back-etching treatment of the oxide layer in the substrate structure having the isolation oxide layer 7, all the second oxide layers 5 will be removed, and the angle between the top of the isolation oxide layer 7 and the inner wall of the first groove 6 can be made an obtuse angle, that is, the angle between the isolation oxide layer 7 and the inner wall of the first groove 6 is θ1. The specific value of the obtuse angle is not limited here, as long as it can meet the requirements of subsequent steps.

[0082] Through step S207, the deposition window of the subsequent deposition step can be further opened, thereby ensuring the molding quality of the dielectric layer subsequently deposited in the first groove 6. Optionally, after the second back etching process, the following can be obtained: Figure 7 The substrate structure shown can further enlarge the recessed window at the end of the isolation oxide layer 7, and the aspect ratio of the recessed window (ie, W1 / D1 ) can be within 2.5:1.

[0083] S209: forming an interlayer dielectric layer in the first trench to obtain a target semiconductor structure.

[0084] In an exemplary embodiment, the device to be formed is an SGT-MOS device as an example for explanation. At this time, step S209 can be specifically explained as follows: forming an interlayer dielectric layer 11 in the first trench 6 and on the surface of the hard mask layer 4; planarizing the surface of the substrate structure formed with the interlayer dielectric layer 11 to remove the interlayer dielectric layer 11 located on the hard mask layer 4 and a portion of the hard mask layer 4; removing the hard mask layer 4, the first oxide layer 3 and a portion of the interlayer dielectric layer 11 to make the top of the interlayer dielectric layer 11 lower than the top of the epitaxial layer 2, and the interlayer dielectric layer 11 covers the end of the source conductor 10, and the following is obtained. Figure 8 The target semiconductor structure is shown.

[0085] Exemplarily, a deposition process can be used to form a layer of dielectric material on the inner surface of the first groove 6 and on the top of the hard mask layer 4. The deposition process includes but is not limited to plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD), high density plasma chemical vapor deposition (High Density Plasma CVD, HDPCVD), sub atmospheric pressure chemical vapor deposition (Sub Atmospheric CVD, SACVD), low pressure chemical vapor deposition (Low Pressure CVD, LPCVD), atomic layer deposition (Atomic Layer Deposition, ALD), plasma enhanced atomic layer deposition (Plasma Enhanced Atomic Layer Deposition, PEALD), etc. In an embodiment of the present application, HDPCVD is used to form a dielectric material, and the dielectric material includes but is not limited to silicon oxide.

[0086] The dielectric material and the hard mask layer 4 are planarized to form a Figure 8 The structure shown makes the top surfaces of the two relatively flat. Specifically, a chemical mechanical polishing process can be used to remove excess dielectric material and the warped hard mask layer 4 to form an interlayer dielectric layer 11 in the first trench 6 .

[0087] Then, the remaining hard mask layer 4 and the remaining first oxide layer 3 are removed, and the interlayer dielectric layer 11 is etched back to obtain the following: Fig. 9 The structure shown, at this time, due to the above steps, after the second back-etching treatment is performed on the oxide layer in the substrate structure having the isolation oxide layer 7, all the second oxide layer 5 will be removed, and the angle between the top of the isolation oxide layer 7 and the inner wall of the first groove 6 can be made to be an obtuse angle, that is, the top of the first isolation oxide layer 7 is an inclined structure, and this feature will be inherited when the first oxide layer 3 and the interlayer dielectric layer 11 are further back-etched, so that after the back-etching treatment is performed on the interlayer dielectric layer 11, a structure in which the angle between the isolation oxide layer 7 and the inner wall of the first groove 6 is θ2 will be formed, specifically, θ2 can be 120°, and the specific value of θ2 is related to the size of the device to be prepared, and the top of the isolation oxide layer 7 and the top of the interlayer dielectric layer 11 form a concave structure, that is, a structure that is slightly higher on both sides and slightly lower in the middle, and the specific height difference is related to the size of the device to be prepared, etc.

[0088] In the manufacturing process of the SGT-MOS device, in addition to the above process steps, it also includes gate formation, body region doping, source doping and other processes. For example, the gate formation process can be specifically performed as follows: Fig. 9 An epitaxial layer is formed on the top of the structure shown, which can be called the second epitaxial layer. The epitaxial layer in the substrate structure of the above step can be called the first epitaxial layer. The second epitaxial layer can be ion doped to form a body region. The second epitaxial layer can be homoepitaxial or heteroepitaxial, which is not limited here. The second epitaxial layer is patterned to form a through hole penetrating the second epitaxial layer. The through hole is connected to the first trench 6, and the widths of the two can be the same. Then, the surface of the second epitaxial layer and the surface of the first trench 6 are covered with a gate dielectric layer. Specifically, a thermal oxidation process can be used to form an oxide layer on the surface of the second epitaxial layer, the sidewall of the through hole, the sidewall of the first trench 6, the surface of the isolation oxide layer 7, and the surface of the interlayer dielectric layer 11. At this time, the oxide layer and the interlayer dielectric layer 11 jointly form an isolation layer for isolating the source conductor 10 and the gate. The gate dielectric layer is used to isolate the epitaxial layer (including the first epitaxial layer and the second epitaxial layer) from the gate to prevent the doping elements in the gate from diffusing into the epitaxial layer. A layer of gate material is covered on the gate dielectric layer, and the excess gate material and dielectric layer on the top of the second epitaxial layer are removed by a grinding process, so that the gate is located in the groove formed by the gate dielectric layer. The gate material can be polysilicon. The above gate formation process is only an exemplary solution, and this application does not limit the gate formation method.

[0089] The embodiment of the present application performs a second back-etching process on the oxide layer in the substrate structure having the isolation oxide layer 7, thereby opening a sufficient deposition window to allow the subsequent interlayer dielectric layer 11 to be normally filled, avoiding the occurrence of filling voids, and also enabling the top of the isolation oxide layer 7 to form an obtuse angle with the sidewall of the first trench 6. Subsequently, the interlayer dielectric layer 11 is filled in the first trench 6 and back-etched, so that the oxide layer in the first trench 6 has a contour shape that is slightly lower in the middle and slightly higher on both sides, which is beneficial to increase the thickness of the gate dielectric layer at the corner, thereby improving the source-gate leakage performance.

[0090] In order to better illustrate the technical effect of the technical solution of the present application, several comparative examples are used to illustrate the technical effect of the present application. A comparative example 1 is provided. The manufacturing method of the semiconductor device provided in comparative example 1 specifically includes the following steps: first, a substrate structure having a first groove 6 is provided; the substrate structure includes a base layer 1, an epitaxial layer 2, a first oxide layer 3, a hard mask layer 4, and a second oxide layer 5 arranged in sequence from bottom to top; the first groove 6 penetrates the first oxide layer 3, the hard mask layer 4, and the second oxide layer 5, and the bottom of the first groove 6 is located in the epitaxial layer 2; wherein the first oxide layer 3 and the second oxide layer 5 are both silicon oxide, and the hard mask layer 4 is silicon nitride. Subsequently, the hard mask layer 4 is subjected to a large amount of back etching to remove part of the hard mask layer 4 adjacent to the opening of the first trench 6; an isolation oxide layer 7 is formed on the surface of the first trench 6 based on a thermal oxidation process, and a second trench 9 is obtained by the isolation oxide layer 7 surrounding the first trench 6; a source conductor 10 is formed in the second trench 9; and the oxide layer in the structure of the aforementioned steps is subjected to back etching to remove the second oxide layer 5, part of the first oxide layer 3 and part of the isolation oxide layer 7, followed by filling the interlayer dielectric layer 11, specifically, forming the interlayer dielectric layer 11 located in the first trench 6; the source conductor 10 is located in the cavity formed by the isolation oxide layer 7 and the interlayer dielectric layer 11. In short, the manufacturing method provided in Comparative Example 1 is to perform a large amount of back etching of the hard mask layer 4 only once before the growth of the isolation oxide layer 7, and no further back etching is performed subsequently, which is equivalent to only performing the back etching of the hard mask layer 4 in step S207 of this scheme before filling the isolation oxide layer 7, and the following will be obtained. Figure 1 As shown in the target semiconductor structure, it can be seen that the structure obtained in comparative example 1 has a serious bird's beak phenomenon after the isolation oxide layer 7 is grown (eg Figure 1 The area shown by the dotted box in FIG. 1 ), and there is loss on the top of the epitaxial layer 2, the sidewall profile of the epitaxial layer 2 is poor, and there is filling anomaly of the interlayer dielectric layer 11 (such as the presence of filling gaps), which affects the subsequent semiconductor process technology.

[0091] A comparative example 2 is also provided. The manufacturing method of the semiconductor device provided in comparative example 2 specifically includes the following steps: first, a substrate structure having a first groove 6 is provided; the substrate structure includes a base layer 1, an epitaxial layer 2, a first oxide layer 3, a hard mask layer 4 and a second oxide layer 5 arranged in sequence from bottom to top; the first groove 6 penetrates the first oxide layer 3, the hard mask layer 4 and the second oxide layer 5, and the bottom of the first groove 6 is located at the epitaxial layer 2; wherein the first oxide layer 3 and the second oxide layer 5 are both silicon oxide, and the hard mask layer 4 is silicon nitride. Based on the thermal oxidation process, an isolation oxide layer 7 is formed on the surface of the first trench 6 to obtain a second trench 9 formed by the isolation oxide layer 7 surrounding the first trench 6; a source conductor 10 is formed in the second trench 9; subsequently, a large amount of back etching is performed on the hard mask layer 4 to remove part of the hard mask layer 4 adjacent to the opening of the first trench 6; the oxide layer in the structure of the aforementioned step is then back-etched to remove the second oxide layer 5, part of the first oxide layer 3 and part of the isolation oxide layer 7, and then the interlayer dielectric layer 11 is filled, specifically, an interlayer dielectric layer 11 is formed in the first trench 6; the source conductor 10 is located in the cavity formed by the isolation oxide layer 7 and the interlayer dielectric layer 11. In short, the manufacturing method provided in Comparative Example 2 is to perform a large amount of back etching of the hard mask layer 4 only once before the interlayer dielectric layer 11 is filled, which is equivalent to only performing the back etching of the hard mask layer 4 in step S207 of this scheme before the interlayer dielectric layer 11 is filled, and the following will be obtained. Fig.10 As shown in the target semiconductor structure, it can be seen that the structure obtained in comparative example 2 has a slightly narrowed opening of the first trench 6 (such as Fig.10 ), and there is filling anomaly of the interlayer dielectric layer 11 (such as the presence of filling gaps), which affects the subsequent semiconductor process technology.

[0092] A comparative example 3 is also provided. The manufacturing method of the semiconductor device provided in comparative example 3 specifically includes the following steps: first, a substrate structure having a first groove 6 is provided; the substrate structure includes a base layer 1, an epitaxial layer 2, a first oxide layer 3, a hard mask layer 4 and a second oxide layer 5 arranged in sequence from bottom to top; the first groove 6 penetrates the first oxide layer 3, the hard mask layer 4 and the second oxide layer 5, and the bottom of the first groove 6 is located at the epitaxial layer 2; wherein the first oxide layer 3 and the second oxide layer 5 are both silicon oxide, and the hard mask layer 4 is silicon nitride. Subsequently, a small amount of back-etching is performed on the hard mask layer 4 to remove a portion of the hard mask layer 4 adjacent to the opening of the first trench 6; an isolation oxide layer 7 is formed on the surface of the first trench 6 based on a thermal oxidation process, so as to obtain a second trench 9 formed by the isolation oxide layer 7 surrounding the first trench 6; a source conductor 10 is formed in the second trench 9; and the oxide layer in the structure of the aforementioned steps is back-etched to remove the second oxide layer 5, a portion of the first oxide layer 3 and a portion of the isolation oxide layer 7, followed by filling the interlayer dielectric layer 11, specifically, forming an interlayer dielectric layer 11 located in the first trench 6; the source conductor 10 is located in a cavity formed by the isolation oxide layer 7 and the interlayer dielectric layer 11. In short, the manufacturing method provided in Comparative Example 3 is to perform a small amount of back-etching of the hard mask layer 4 only once before the growth of the isolation oxide layer 7, which is equivalent to only performing the back-etching of the hard mask layer 4 in step S203 of this scheme before filling the interlayer dielectric layer 11, and no further back-etching is performed subsequently, and the following will be obtained. Fig.11 As shown in the target semiconductor structure, it can be seen that the structure obtained in comparative example 3 has filling anomalies in the interlayer dielectric layer 11 (such as the presence of filling gaps, such as Fig.11 The area shown by the dotted box in the figure affects the subsequent semiconductor process technology.

[0093] Based on the above comparative examples 1-3, it can be seen that after forming the first groove 6, only a small amount or a large amount of hard mask layer 4 is etched back once, or a large amount of hard mask layer 4 is etched back once before the isolation oxide layer 7 grows. It is not acceptable. After the first groove 6 is formed, only a small amount of hard mask layer 4 is etched back once, which will lead to serious eaves of the hard mask layer 4 after the isolation oxide layer 7 grows, and then lead to abnormal filling of the subsequent interlayer dielectric layer 11. Alternatively, only a large amount of hard mask layer 4 is etched back once, which will lead to serious bird beak phenomenon and cause loss of the top area of ​​the epitaxial layer 2, resulting in abnormal side wall profile of the epitaxial layer 2. In addition, it is not acceptable to etch back a large amount of hard mask layer 4 before etching back the isolation oxide layer 7, which will cause the opening of the first groove 6 to be slightly closed, and the filling of the interlayer dielectric layer 11 to be abnormal (such as the presence of filling gaps), affecting the subsequent semiconductor process technology.

[0094] In this solution, the hard mask layer 4 is etched back twice, and a large amount of etching and a small amount of etching are combined. That is, after forming the first trench 6, the hard mask layer 4 is first etched back with a small amount, and then the isolation oxide layer 7 is formed based on the thermal oxidation process, and then the hard mask layer 4 is etched back with a large amount, and then a part of the oxide layer in the structure is removed, so that the side wall of the hard mask layer 4 is flush with the side wall of the first trench 6, and then the interlayer dielectric layer 11 is filled, and the layer structure on the top of the epitaxial layer 2 and a part of the interlayer dielectric layer 11 are etched away, so that the interlayer dielectric layer 11 is slightly lower than the top of the epitaxial layer 2. The scanning electron microscope image of the obtained structure can be shown as follows: Fig.12 As shown, it can be seen that the semiconductor structure prepared by this method reduces the bird's beak phenomenon, and the filling of the interlayer dielectric layer 11 is normal, the profile of the epitaxial layer 2 is better, and since this scheme adopts a thermal oxidation process to directly form the isolation oxide layer 7, the film stress of the film layer will also be reduced.

[0095] The embodiment of the present application also provides a semiconductor structure, which is prepared based on the above-mentioned formation method. The semiconductor structure includes a substrate layer 1, an epitaxial layer 2, a first oxide layer 3 and a hard mask layer 4 arranged in sequence from bottom to top, and a first trench 6 penetrating the first oxide layer 3 and the hard mask layer 4, and the bottom of the first trench 6 is located in the epitaxial layer 2, and the inner wall of the first trench 6 is formed with an isolation oxide layer 7 and an interlayer dielectric layer 11. Since the semiconductor junction is manufactured by the above-mentioned semiconductor structure formation method, the hard mask layer 4 of the substrate structure with the first trench 6 is back-etched twice, and the isolation oxide layer 7 is formed on the surface of the first trench 6 by a thermal oxidation process, so that not only the formed isolation oxide layer 7 will not generate film stress, but also its bird's beak effect and the influence of the hard mask eaves on the filling quality of the interlayer dielectric layer 11 formed subsequently can be reduced.

[0096] The embodiment of the present application also provides a method for forming a semiconductor device, which includes: after forming a target semiconductor structure, forming a gate; the target semiconductor structure is prepared based on the above-mentioned formation method. The semiconductor device can be a SGT-MOS device, or other devices that need to be formed with a groove and an isolation oxide layer 7, which is not limited here. If the semiconductor device is an SGT-MOS device, it is also necessary to remove the residual hard mask layer 4, the first oxide layer 3, etc. located on the epitaxial layer 2, and form a source conductor 10 in the groove formed by the isolation oxide layer 7, and form a gate on the source conductor 10. Structures, since the target semiconductor structure is manufactured by the above-mentioned semiconductor structure formation method, that is, by etching back the hard mask layer 4 of the substrate structure with the first groove 6 twice, and using a thermal oxidation process to form an isolation oxide layer 7 on the surface of the first groove 6, not only can the isolation oxide layer 7 formed not generate film stress, but also can reduce its bird's beak effect and the influence of the hard mask eaves on the filling quality of the interlayer dielectric layer 11 formed subsequently. Therefore, the method for forming a semiconductor device including the method for forming the semiconductor structure has the same technical effect as above.

[0097] The embodiment of the present application also provides a semiconductor device, which is prepared based on the above-mentioned formation method. The semiconductor device can specifically be an SGT-MOS device, or other devices that need to be formed with grooves and an isolation oxide layer 7, which are not limited here. Since the formation of the semiconductor device includes first forming the above-mentioned semiconductor structure, the method for forming the semiconductor structure is to first back-etch the hard mask layer 4 of the substrate structure with the first groove 6 twice, and use a thermal oxidation process to form an isolation oxide layer 7 on the surface of the first groove 6, so that not only the formed isolation oxide layer 7 will not generate film stress, but also its bird's beak effect and the influence of the hard mask eaves on the filling quality of the interlayer dielectric layer 11 formed subsequently can be reduced. Therefore, the semiconductor device formed based on the formation method of the semiconductor structure has the same technical effect.

[0098] An embodiment of the present application further provides an electronic device, which includes the above-mentioned semiconductor device.

[0099] Specifically, the electronic device includes a semiconductor device and an electronic component connected to the semiconductor device. Since the formation of the semiconductor device includes first forming the semiconductor structure, the method for forming the semiconductor structure is to first etch back the hard mask layer 4 of the substrate structure with the first groove 6 twice, and form an isolation oxide layer 7 on the surface of the first groove 6 using a thermal oxidation process, so that not only the formed isolation oxide layer 7 will not generate film stress, but also its bird's beak effect and the influence of the hard mask eaves on the filling quality of the interlayer dielectric layer 11 formed subsequently can be reduced, so that the semiconductor device formed based on the method for forming the semiconductor structure has the same technical effect. The electronic component can be any electronic component such as a transistor.

[0100] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., and can also be any intermediate product including the above-mentioned semiconductor device.

[0101] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0102] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0103] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0104] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: A substrate structure having a first trench is provided; the substrate structure comprises a base layer, an epitaxial layer, a first oxide layer, a hard mask layer and a second oxide layer arranged in sequence; the first trench penetrates the first oxide layer, the hard mask layer and the second oxide layer, and the bottom of the first trench is located in the epitaxial layer; Performing a first etching back process on the hard mask layer to remove a portion of the hard mask layer adjacent to an opening of the first trench; forming an isolation oxide layer on the surface of the first trench based on a thermal oxidation process; Performing a second etching back process on the substrate structure having the isolation oxide layer to remove the second oxide layer, a portion of the first oxide layer and a portion of the isolation oxide layer, and making the side edge of the hard mask layer flush with the side wall of the first trench; An interlayer dielectric layer is formed in the first trench to obtain a target semiconductor structure.

2. The forming method according to claim 1, characterized in that: The first etch-back process etches back the hard mask layer less than the second etch-back process etches back the hard mask layer.

3. The forming method according to claim 1, characterized in that: After the first back-etching process, the first side edge of the hard mask layer and the second side edge of the first oxide layer are recessed inward relative to the inner wall of the first trench to expose a local area of ​​the top of the epitaxial layer; the first side edge and the second side edge are respectively the side edges of the hard mask layer and the first oxide layer close to the inner wall of the first trench.

4. The forming method according to claim 1, characterized in that: Before performing a second etching back process on the substrate structure having the isolation oxide layer, the method further comprises: A third etching back process is performed on the substrate structure having the isolation oxide layer to expose an end portion of the hard mask layer.

5. The forming method according to claim 4, characterized in that: The thickness of the second oxide layer after the third back-etching process is less than the thickness of the second oxide layer after the first back-etching process.

6. The forming method according to claim 5, characterized in that: After the third etching back process, the thickness of the second oxide layer is greater than or equal to a first preset thickness, and the first preset thickness is 450 to 550 angstroms.

7. The forming method according to any one of claims 1 to 6, characterized in that: The step of forming an isolation oxide layer on the surface of the first trench based on a thermal oxidation process comprises: forming an isolation oxide layer on the surface of the first trench based on a thermal oxidation process, thereby obtaining a second trench formed by the isolation oxide layer surrounding the first trench; A source conductor is formed in the second trench; a top of the source conductor is lower than a top of the epitaxial layer.

8. The forming method according to claim 7, characterized in that: The step of forming an interlayer dielectric layer in the first trench to obtain a target semiconductor structure includes: forming an interlayer dielectric layer in the first trench and on the surface of the hard mask layer; performing a planarization process on the surface of the substrate structure formed with the interlayer dielectric layer to remove the interlayer dielectric layer and a portion of the hard mask layer located on the hard mask layer; The hard mask layer, the first oxide layer and a portion of the interlayer dielectric layer are removed so that a top of the interlayer dielectric layer is lower than a top of the epitaxial layer and the interlayer dielectric layer covers an end of the source conductor.

9. The forming method according to any one of claims 1 to 6, characterized in that: In the target semiconductor structure, an angle between a top of the isolation oxide layer and an inner wall of the first trench is an obtuse angle.

10. The forming method according to any one of claims 1 to 6, characterized in that: The thickness of the isolation oxide layer is 4000 to 9000 angstroms.

11. A semiconductor structure, characterized in that: It is prepared based on the formation method according to any one of claims 1 to 10.

12. A method for forming a semiconductor device, characterized in that: include: After forming the target semiconductor structure, a gate is formed; the target semiconductor structure is prepared based on the formation method according to any one of claims 1 to 10.

13. A semiconductor device, characterized in that: It is prepared based on the formation method as claimed in claim 12.

14. An electronic device, characterized in that: Comprising the semiconductor device as claimed in claim 13.

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