Semiconductor device

Abstract

A semiconductor device includes: a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; an internal gate electrode between a first semiconductor pattern and a second semiconductor pattern adjacent to each other among the plurality of semiconductor patterns; an internal gate insulating layer between the internal gate electrode and the first and second semiconductor patterns; an internal high-k dielectric layer between the internal gate electrode and the internal gate insulating layer; and an inner spacer between the inner gate insulating layer and the source / drain pattern. Since the internal gate insulating layer includes the internal gate spacer, the internal gate electrode may stably fill the internal gate space. As a result, electrical characteristics of the semiconductor device may be improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0105286 filed in the Korean Intellectual Property Office on August 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the semiconductor device. Background Art

[0004] A semiconductor device may include an integrated circuit having a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rules of semiconductor devices have been reduced, MOSFETs have been scaled down. The operating characteristics of semiconductor devices may be degraded by reducing the size of MOSFETs. Therefore, various methods for forming semiconductor devices having excellent performance while overcoming limitations caused by high integration have been studied. Summary of the invention

[0005] Embodiments of the inventive concept may provide a semiconductor device having improved reliability and electrical characteristics.

[0006] In some embodiments, a semiconductor device may include: a substrate including an active pattern; a channel pattern located on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; an internal gate electrode located between adjacent first and second semiconductor patterns among the plurality of semiconductor patterns; an internal gate insulating layer located between the internal gate electrode and the first and second semiconductor patterns; an internal high-k dielectric layer located between the internal gate electrode and the internal gate insulating layer; and an internal spacer located between the internal gate insulating layer and the source / drain pattern. The internal gate insulating layer may include: an upper insulating layer located between the internal gate electrode and the second semiconductor pattern; a lower insulating layer located between the internal gate electrode and the first semiconductor pattern; and an internal gate spacer located between the internal gate electrode and the source / drain pattern. A first thickness of the internal gate spacer located at a central portion of the internal gate spacer may be greater than a second thickness of the upper insulating layer or the lower insulating layer, and a third thickness of the internal spacer may be greater than the first thickness of the internal gate spacer.

[0007] In some embodiments, a semiconductor device may include: a substrate including a first active pattern and a second active pattern; a first channel pattern and a second channel pattern, the first channel pattern and the second channel pattern are respectively located on the first active pattern and the second active pattern, and the first channel pattern and the second channel pattern each include a plurality of semiconductor patterns spaced apart from each other; a first source / drain pattern electrically connected to the first channel pattern; a second source / drain pattern electrically connected to the second channel pattern; a first internal gate electrode located between adjacent semiconductor patterns among the plurality of semiconductor patterns of the first channel pattern; a second internal gate electrode located between adjacent semiconductor patterns among the plurality of semiconductor patterns of the second channel pattern; a first internal gate insulating layer located between the first internal gate electrode and an adjacent semiconductor pattern of the first channel pattern; a second internal gate insulating layer located between the second internal gate electrode and an adjacent semiconductor pattern of the second channel pattern; a first internal high-k dielectric layer located between the first internal gate electrode and the first internal gate insulating layer; and a second internal high-k dielectric layer located between the second internal gate electrode and the second internal gate insulating layer. The first internal gate insulating layer may include: a first upper insulating layer located on the top surface of the first internal gate electrode; a first lower insulating layer located on the bottom surface of the first internal gate electrode; and a first internal gate spacer located on both sidewalls of the first internal gate electrode. The second internal gate insulating layer may include: a second upper insulating layer located on the top surface of the second internal gate electrode; a second lower insulating layer located on the bottom surface of the second internal gate electrode; and a second internal gate spacer located on both sidewalls of the second internal gate electrode. The semiconductor device may also include an internal spacer located between the first internal gate spacer and the first source / drain pattern. The thickness of the second internal gate spacer may be less than the sum of the thickness of the first internal gate spacer and the thickness of the internal spacer.

[0008] In some embodiments, a semiconductor device may include: a substrate including an active pattern; a channel pattern located on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode located on the plurality of semiconductor patterns, the gate electrode including an internal gate electrode located between adjacent semiconductor patterns in the plurality of semiconductor patterns and an external gate electrode located on the uppermost semiconductor pattern in the plurality of semiconductor patterns; a gate insulating layer located between the gate electrode and the plurality of semiconductor patterns, the gate insulating layer including an internal gate insulating layer located between the internal gate electrode and the plurality of semiconductor patterns and an external gate insulating layer located on the uppermost semiconductor pattern; a high-k dielectric layer located between the gate electrode and the gate insulating layer; and an internal spacer located between the internal gate insulating layer and the source / drain pattern. The internal gate insulating layer may include: an upper insulating layer located on a top surface of the internal gate electrode; a lower insulating layer located on a bottom surface of the internal gate electrode; and an internal gate spacer located between the internal gate electrode and the internal spacer. Each of the upper insulating layer and the lower insulating layer may include: a main body portion parallel to the top surface or the bottom surface of the internal gate electrode; and a tail portion located on the side of the main body portion. The main body portion may have a first length in a vertical direction perpendicular to the substrate, and the tail portion may have a second length in the vertical direction. The second length may be greater than the first length according to the predetermined horizontal distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to some embodiments of the inventive concept.

[0010] Figure 4 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0011] Figure 5A , Figure 5B , Figure 5C and Figure 5D Along the Figure 4 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0012] Fig. 6A It is shown Figure 5A An enlarged view of an embodiment of region "M".

[0013] Figure 6B It is shown Figure 5B An enlarged view of an embodiment of region "N".

[0014] Figure 6C It is shown Fig. 6A An enlarged view of an embodiment of region "P".

[0015] Fig.6D It is shown Figure 5A An enlarged view of an embodiment of region "M".

[0016] Figure 7 It is shown Figure 5A An enlarged view of an embodiment of region "M".

[0017] Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C and Fig.13D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0018] Figures 14 to 16 It is shown that the formation Fig. 10A A magnified view of the area "M" approach.

[0019] Figures 17 to 19 It is shown that the formation Fig. 12A A magnified view of the area "M" approach. DETAILED DESCRIPTION

[0020] Figures 1 to 3 is a conceptual diagram illustrating a logic unit of a semiconductor device according to some embodiments of the inventive concept.

[0021] Reference Figure 1 , a single height cell SHC may be provided. More specifically, a first power interconnection line M1_R1 and a second power interconnection line M1_R2 may be disposed on the substrate 100. The first power interconnection line M1_R1 may be a path through which a source voltage (VSS, for example, a ground voltage) is provided. The second power interconnection line M1_R2 may be a path through which a drain voltage (VDD, for example, a power supply voltage) is provided.

[0022] The single height cell SHC may be defined between the first power interconnect line M1_R1 and the second power interconnect line M1_R2. The single height cell SHC may include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 may be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. In other words, the single height cell SHC may have a CMOS structure disposed between the first power interconnect line M1_R1 and the second power interconnect line M1_R2. For example, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0023] Each of the first active region AR1 and the second active region AR2 may have a single width W_SHC in the first direction D1. The length of the single height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to a distance (eg, a pitch) between the first power interconnection line M1_R1 and the second power interconnection line M1_R2.

[0024] The single height cell SHC may form a logic unit. In this specification, a logic unit may refer to a logic element (e.g., an AND gate element, an OR gate element, an XOR gate element, an XNOR gate element, an inverter, etc.) for performing a specific function. In other words, a logic unit may include transistors constituting the logic element and interconnects connecting the transistors to each other.

[0025] Reference Figure 2 , a double height cell DHC may be provided. More specifically, a first power interconnection line M1_R1, a second power interconnection line M1_R2, and a third power interconnection line M1_R3 may be disposed on the substrate 100. The first power interconnection line M1_R1 may be disposed between the second power interconnection line M1_R2 and the third power interconnection line M1_R3. The third power interconnection line M1_R3 may be a path through which a drain voltage (VDD) is provided.

[0026] The double height cell DHC may be defined between the second power interconnection line M1_R2 and the third power interconnection line M1_R3. The double height cell DHC may include two first active regions AR1 and two second active regions AR2.

[0027] One of the two second active regions AR2 may be adjacent to the second power interconnection line M1_R2. The other of the two second active regions AR2 may be adjacent to the third power interconnection line M1_R3. The two first active regions AR1 may be adjacent to the first power interconnection line M1_R1. When viewed in a plan view, the first power interconnection line M1_R1 may be disposed between the two first active regions AR1.

[0028] The length of the double height unit DHC in the first direction D1 may be defined as a second height HE2. The second height HE2 may be Figure 1 The two first active regions AR1 of the double-height cell DHC may be combined with each other to operate as a single active region.

[0029] In the present invention, Figure 2 The double height cell DHC shown in FIG. 1 may be defined as a multi-height cell. Although not shown in the drawings, the multi-height cell may include a triple-height cell whose cell height is approximately three times that of the single-height cell SHC.

[0030] Reference Figure 3 , the first single height cell SHC1, the second single height cell SHC2, and the double height cell DHC may be two-dimensionally arranged on the substrate 100. The first single height cell SHC1 may be arranged between the first power interconnection line M1_R1 and the second power interconnection line M1_R2. The second single height cell SHC2 may be arranged between the first power interconnection line M1_R1 and the third power interconnection line M1_R3. The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1.

[0031] The double height cell DHC may be disposed between the second power interconnection line M1_R2 and the third power interconnection line M1_R3 . The double height cell DHC may be adjacent to the first and second single height cells SHC1 and SHC2 in the second direction D2 .

[0032] The isolation structure DB may be disposed between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. The active region of the double height cell DHC may be electrically isolated from the active region of each of the first single height cell SHC1 and the second single height cell SHC2 by the isolation structure DB.

[0033] Figure 4 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. Figure 5A , Figure 5B , Figure 5C and Figure 5D Along the Figure 4 Cross-sectional views taken along lines AA', BB', CC' and DD'. Fig. 6A It is shown Figure 5A An enlarged view of an embodiment of region "M", and Figure 6B It is shown Figure 5B An enlarged view of an embodiment of region "N".

[0034] Figure 6C It is shown Fig. 6A An enlarged view of an embodiment of region "P". Figure 4 and FIG. 5A to FIG. 5D The semiconductor device shown in FIG. Figure 1 A more detailed embodiment of a single height unit SHC corresponds.

[0035] Reference Figure 4 and FIG. 5A to FIG. 5D The single height cell SHC may be disposed on the substrate 100. A logic transistor including a logic circuit may be disposed on the single height cell SHC. The substrate 100 may be a semiconductor substrate including silicon, germanium or silicon germanium, or a compound semiconductor substrate. For example, the substrate 100 may be a silicon substrate.

[0036] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in the second direction D2. In some embodiments, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0037] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed in an upper portion of the substrate 100. The first active pattern AP1 may be disposed on the first active region AR1, and the second active pattern AP2 may be disposed on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically protruding portions of the substrate 100.

[0038] The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover or may not overlap the first channel pattern CH1 and the second channel pattern CH2 to be described below.

[0039] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (i.e., a third direction D3).

[0040] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon. In some embodiments of the present inventive concept, the first to third semiconductor patterns SP1, SP2, and SP3 may be stacked nanosheets.

[0041] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first recesses RS1 may be formed on the first active pattern AP1. The first source / drain patterns SD1 may be disposed in the first recesses RS1, respectively. The first source / drain pattern SD1 may be a doped region having a first conductivity type (e.g., n-type). The first channel pattern CH1 may be disposed between a pair of first source / drain patterns SD1. In other words, the first to third semiconductor patterns SP1, SP2, and SP3 stacked sequentially may connect a pair of first source / drain patterns SD1 to each other.

[0042] A plurality of second source / drain patterns SD2 may be disposed on the second active pattern AP2. A plurality of second recesses RS2 may be formed on the second active pattern AP2. The second source / drain patterns SD2 may be disposed in the second recesses RS2, respectively. The second source / drain pattern SD2 may be a doped region having a second conductivity type (e.g., p-type). The second channel pattern CH2 may be disposed between a pair of second source / drain patterns SD2. In other words, the first to third semiconductor patterns SP1, SP2, and SP3 stacked sequentially may connect a pair of second source / drain patterns SD2 to each other.

[0043] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. In some embodiments, a top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than a top surface of the third semiconductor pattern SP3. In a specific embodiment, a top surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be located at substantially the same level as a top surface of the third semiconductor pattern SP3.

[0044] In some embodiments of the present inventive concept, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element (e.g., Si) of the substrate 100. Therefore, a pair of second source / drain patterns SD2 may provide compressive stress to the second channel pattern CH2 between the pair of second source / drain patterns SD2.

[0045] In some embodiments of the present inventive concept, the sidewall of the second source / drain pattern SD2 may have an uneven embossing shape. In other words, the sidewall of the second source / drain pattern SD2 may have a wavy profile. The sidewall of the second source / drain pattern SD2 may protrude toward the first to third internal gate electrodes PO1, PO2, and PO3 of the second gate electrode GE2 to be described below.

[0046] The first gate electrode GE1 and the second gate electrode GE2 may be disposed on the first channel pattern CH1 and the second channel pattern CH2, respectively. The first gate electrode GE1 and the second gate electrode GE2 may intersect the first channel pattern CH1 and the second channel pattern CH2, and may extend in the first direction D1. The first gate electrode GE1 and the second gate electrode GE2 may vertically overlap the first channel pattern CH1 and the second channel pattern CH2, respectively. The gate electrodes GE may be arranged in the second direction D2 at a first pitch, and each of the gate electrodes GE includes the first gate electrode GE1 and the second gate electrode GE2.

[0047] Each of the first gate electrode GE1 and the second gate electrode GE2 may include: a first internal gate electrode PO1, which is arranged between the active pattern AP1 or AP2 and the first semiconductor pattern SP1; a second internal gate electrode PO2, which is arranged between the first semiconductor pattern SP1 and the second semiconductor pattern SP2; a third internal gate electrode PO3, which is arranged between the second semiconductor pattern SP2 and the third semiconductor pattern SP3; and an external gate electrode PO4, which is located on the third semiconductor pattern SP3.

[0048] Reference Figure 5D , each of the first gate electrode GE1 and the second gate electrode GE2 may be disposed on the top surface TS, the bottom surface BS, and both sidewalls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. In other words, the transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., a multi-bridge channel metal oxide semiconductor field effect transistor (MBCFET) or a gate-all-around field effect transistor (GAAFET)) in which each of the first gate electrode GE1 and the second gate electrode GE2 three-dimensionally surrounds a channel.

[0049] The internal spacer ISP may be disposed between the first source / drain pattern SD1 and the first to third internal gate electrodes PO1, PO2, and PO3 of the first gate electrode GE1, respectively, on the first active region AR1. Each of the first to third internal gate electrodes PO1, PO2, and PO3 of the first gate electrode GE1 may be spaced apart from the first source / drain pattern SD1, and the internal spacer ISP is interposed between each of the first to third internal gate electrodes PO1, PO2, and PO3 of the first gate electrode GE1 and the first source / drain pattern SD1. The internal spacer ISP may prevent leakage current from the first gate electrode GE1. The following will refer to Fig. 6A and Figure 6C The internal spacer ISP according to the present inventive concept is described in more detail.

[0050] Refer again Figure 4 and Figure 5A , Figure 5B , Figure 5C and Figure 5D , a pair of gate spacers GS may be respectively disposed on both side walls of the outer gate electrode PO4 of each of the first gate electrode GE1 and the second gate electrode GE2. The gate spacer GS may extend in the first direction D1 along the first gate electrode GE1 and the second gate electrode GE2. The top surface of the gate spacer GS may be higher than the top surface of the first gate electrode GE1 and the second gate electrode GE2. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110 to be described below. For some examples, the gate spacer GS may include at least one of SiCN, SiCON, and SiN. For a specific example, each of the gate spacers GS may include a plurality of layers formed of at least two of SiCN, SiCON, and SiN.

[0051] Refer again Figure 4 and Figure 5A , Figure 5B , Figure 5C and Figure 5D , the gate capping pattern GP may be disposed on the first gate electrode GE1 and the second gate electrode GE2. The gate capping pattern GP may extend in the first direction D1 along the first gate electrode GE1 and the second gate electrode GE2. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to be described below. For example, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN.

[0052] The gate insulating layer GI may be disposed between the first gate electrode GE1 and the first channel pattern CH1 and between the second gate electrode GE2 and the second channel pattern CH2. The gate insulating layer GI may cover the top surface TS, the bottom surface BS, and the two side walls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3, be located on the top surface TS, the bottom surface BS, and the two side walls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3, or overlap with the top surface TS, the bottom surface BS, and the two side walls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover the top surface of the device isolation layer ST under the gate electrode GE, be located on the top surface of the device isolation layer ST under the gate electrode GE, or overlap with the top surface of the device isolation layer ST under the gate electrode GE. Reference will be made to Fig. 6A , Figure 6B and Figure 6C The gate insulating layer GI according to the inventive concept is described in more detail.

[0053] A high-k dielectric layer may be disposed between the gate insulating layer GI and each of the gate electrodes GE1 and GE2. In a specific embodiment, the gate insulating layer GI may have a structure in which a silicon oxide layer and a high-k dielectric layer are stacked. Fig. 6A and Figure 6B The high-k dielectric layer according to the inventive concept is described in more detail.

[0054] High-k dielectric layers (see Fig. 6A and Figure 6B The high-k dielectric material may include a high-k dielectric material having a dielectric constant higher than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0055] In certain embodiments, the semiconductor device according to the inventive concept may include a negative capacitance (NC) FET using a negative capacitor.For example, the gate insulating layer GI may include a ferroelectric material layer having a ferroelectric property and a paraelectric material layer having a paraelectric property.

[0056] The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series with each other and the capacitance of each of the capacitors has a positive value, the total capacitance may be reduced to be less than the capacitance of each of the capacitors. On the contrary, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance may have a positive value and may be greater than the absolute value of the capacitance of each of the capacitors.

[0057] When a ferroelectric material layer having negative capacitance is connected in series to a paraelectric material layer having positive capacitance, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series can be increased. A transistor including a ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature by using the increase in the total capacitance value.

[0058] The ferroelectric material layer may have ferroelectric properties. For example, the ferroelectric material layer may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, for example, hafnium zirconium oxide may be a material formed by doping hafnium oxide with zirconium (Zr). For another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0059] The ferroelectric material layer may further include a dopant doped therein. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the type of ferroelectric material included in the ferroelectric material layer.

[0060] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0061] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 at% (atomic %) to 8 at% of aluminum. Here, the ratio of the dopant may be a ratio of the amount of aluminum to the sum of the amounts of hafnium and aluminum.

[0062] When the dopant is silicon (Si), the ferroelectric material layer may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50at% to 80at% zirconium.

[0063] The paraelectric material layer may have paraelectric properties. For example, the paraelectric material layer may include at least one of silicon oxide and a metal oxide having a high-k dielectric constant. For example, the metal oxide included in the paraelectric material layer may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0064] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer may be different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0065] The ferroelectric material layer may have a thickness that exhibits ferroelectric properties. For example, the thickness of the ferroelectric material layer may be in the range of 0.5 nm to 10 nm, but the embodiments of the present invention are not limited thereto. The critical thickness that exhibits ferroelectric properties may vary depending on the type of ferroelectric material, and therefore, the thickness of the ferroelectric material layer may vary depending on the type of ferroelectric material included therein.

[0066] In some examples, the gate insulating layer GI may include a single ferroelectric material layer. For a specific example, the gate insulating layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer GI may have a stacked structure in which ferroelectric material layers and paraelectric material layers are alternately stacked.

[0067] Refer again Figure 4 and Figure 5A , Figure 5B , Figure 5C and Figure 5D , each of the first gate electrode GE1 and the second gate electrode GE2 may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that adjusts the threshold voltage of the transistor. The desired threshold voltage of the transistor may be obtained by adjusting the thickness and composition of the first metal pattern. For example, the first internal gate electrode to the third internal gate electrode PO1, PO2, and PO3 of the first gate electrode GE1 and the second gate electrode GE2 may be formed by a first metal pattern having a work function metal.

[0068] The first metal pattern of the first gate electrode GE1 and the second gate electrode GE2 may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W) and / or molybdenum (Mo). In addition, the first metal pattern may further include carbon (C). In some embodiments, the first metal pattern may include a plurality of stacked work function metal layers.

[0069] The second metal pattern of the first gate electrode GE1 and the second gate electrode GE2 may include a metal having a lower resistance than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti) and / or tantalum (Ta). For example, the outer gate electrode PO4 of the first gate electrode GE1 and the second gate electrode GE2 may include a first metal pattern and a second metal pattern on the first metal pattern.

[0070] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2, be located on the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2, or overlap the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate capping pattern GP and the top surface of the gate spacer GS. The second interlayer insulating layer 120 covering the gate capping pattern GP or overlapping the gate capping pattern GP may be disposed on the first interlayer insulating layer 110. The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. For example, each of the first interlayer insulating layer 110 to the fourth interlayer insulating layer 140 may include a silicon oxide layer.

[0071] The single height cell SHC may have a first boundary BD1 and a second boundary BD2 opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The single height cell SHC may have a third boundary BD3 and a fourth boundary BD4 opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0072] A pair of isolation structures DB opposite to each other in the second direction D2 may be respectively disposed on both sides of the single height cell SHC. For example, a pair of isolation structures DB may be respectively disposed on the first boundary BD1 and the second boundary BD2 of the single height cell SHC. The isolation structure DB may extend in the first direction D1 parallel to the first gate electrode GE1 and the second gate electrode GE2. The pitch between the isolation structure DB and the first gate electrode GE1 and the second gate electrode GE2 adjacent thereto may be equal to the first pitch.

[0073] The isolation structure DB may penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and may extend into the first active pattern AP1 and the second active pattern AP2. The isolation structure DB may penetrate an upper portion of each of the first active pattern AP1 and the second active pattern AP2. The isolation structure DB may electrically isolate the active region of the single height cell SHC from the active region of another cell adjacent thereto.

[0074] The active contact AC may penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A pair of active contacts AC may be disposed at both sides of the gate electrode GE, respectively. When viewed in a plan view, the active contact AC may have a bar shape extending in the first direction D1.

[0075] The active contact AC may be a self-aligned contact. In other words, the active contact AC may be formed to be self-aligned with the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the sidewall of the gate spacer GS or overlap at least a portion of the sidewall of the gate spacer GS. Although not shown in the drawings, the active contact AC may cover a portion of the top surface of the gate capping pattern GP or overlap a portion of the top surface of the gate capping pattern GP.

[0076] A metal semiconductor compound layer SC (e.g., a silicide layer) may be disposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC may be electrically connected to the source / drain pattern SD1 or SD2 through the metal semiconductor compound layer SC. For example, the metal semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0077] The gate contact GC may penetrate the second interlayer insulating layer 120 and the gate capping pattern GP to be electrically connected to the gate electrode GE. When viewed in a plan view, the gate contact GC may overlap the first active region AR1 and the second active region AR2, respectively. For example, the gate contact GC may be disposed on the second active pattern AP2 (see FIG. Figure 5B )superior.

[0078] In some embodiments of the present inventive concept, reference Figure 5B , the upper portion of the active contact AC adjacent to the gate contact GC may be filled with the upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP may be lower than the bottom surface of the gate contact GC. In other words, the top surface of the active contact AC adjacent to the gate contact GC may be lower than the bottom surface of the gate contact GC due to the upper insulating pattern UIP. Therefore, an electrical short circuit between the gate contact GC and the active contact AC adjacent thereto may be prevented.

[0079] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM, overlap the sidewalls and bottom surface of the conductive pattern FM, or be located on the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer and / or a metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

[0080] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. For example, the first metal layer M1 may include a first power interconnection line M1_R1, a second power interconnection line M1_R2, and a first interconnection line M1_I. The interconnections M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

[0081] More specifically, the first power interconnection line M1_R1 and the second power interconnection line M1_R2 may be disposed on the third boundary BD3 and the fourth boundary BD4 of the single height cell SHC, respectively. The first power interconnection line M1_R1 may extend in the second direction D2 along the third boundary BD3. The second power interconnection line M1_R2 may extend in the second direction D2 along the fourth boundary BD4.

[0082] The first interconnection lines M1_I of the first metal layer M1 may be disposed between the first power interconnection lines M1_R1 and the second power interconnection lines M1_R2. The first interconnection lines M1_I of the first metal layer M1 may be arranged in the first direction D1 at a second pitch. The second pitch may be smaller than the first pitch. The line width of each of the first interconnection lines M1_I may be smaller than the line width of each of the first power interconnection lines M1_R1 and the second power interconnection lines M1_R2.

[0083] The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed below the interconnection lines M1_R1, M1_R2, and M1_I of the first metal layer M1. The active contact AC may be electrically connected to a corresponding one of the interconnection lines of the first metal layer M1 through a corresponding one of the first vias VI1. The gate contact GC may be electrically connected to a corresponding one of the interconnection lines of the first metal layer M1 through a corresponding one of the first vias VI1.

[0084] Different processes may be used to form the interconnection line of the first metal layer M1 and the first via VI1 located below the interconnection line of the first metal layer M1. In other words, each of the interconnection line of the first metal layer M1 and the first via VI1 may be formed using a single damascene process. The semiconductor device according to the present embodiment may be formed using a process less than 20 nm.

[0085] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second interconnection lines M2_I. Each of the second interconnection lines M2_I of the second metal layer M2 may have a line shape or a bar shape extending in the first direction D1. In other words, the second interconnection lines M2_I may extend parallel to each other in the first direction D1.

[0086] The second metal layer M2 may further include a second via VI2 disposed below the second interconnect line M2_I. The interconnect line of the first metal layer M1 may be electrically connected to the interconnect line of the second metal layer M2 through the second via VI2. For example, the interconnect line of the second metal layer M2 and the second via VI2 below the interconnect line of the second metal layer M2 may be formed together through a dual damascene process.

[0087] The interconnection lines of the first metal layer M1 and the interconnection lines of the second metal layer M2 may include the same conductive material or different conductive materials. For example, the interconnection lines of the first metal layer M1 and the interconnection lines of the second metal layer M2 may include at least one metal material of aluminum, copper, tungsten, molybdenum, ruthenium and cobalt. Although not shown in the drawings, a metal layer (e.g., M3, M4, M5, ...) stacked on the fourth interlayer insulating layer 140 may be provided additionally. Each of the stacked metal layers may include an interconnection line for wiring between units.

[0088] Will refer to Fig. 6A , Figure 6B and Figure 6CThe first source / drain pattern SD1 and the second source / drain pattern SD2, the gate insulating layer GI, the high-k dielectric layer HK, and the internal spacer ISP are described in more detail. Due to the internal spacer ISP, the first source / drain pattern SD1 may not protrude between the semiconductor patterns SP1 to SP3 adjacent to each other. The second source / drain pattern SD2 may include protrusions PRP protruding from the first internal gate electrode PO1 to the third internal gate electrode PO3 toward the second gate electrode GE2, respectively.

[0089] The first source / drain pattern SD1 may have a first sidewall CSW1 shared with the inner spacer ISP. The protrusion PRP of the second source / drain pattern SD2 may have a fifth sidewall CSW5. The fifth sidewall CSW5 according to the present embodiment may protrude toward a corresponding one of the first to third internal gate electrodes PO1, PO2, and PO3 of the second gate electrode GE2.

[0090] In some embodiments of the present inventive concept, the first to third internal gate electrodes PO1, PO2, and PO3 may have different widths. For example, the maximum width of the first internal gate electrode PO1 in the second direction D2 may be greater than the maximum width of the second internal gate electrode PO2 in the second direction D2. The maximum width of the second internal gate electrode PO2 in the second direction D2 may be greater than the maximum width of the third internal gate electrode PO3 in the second direction D2.

[0091] The first source / drain pattern SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 on the first semiconductor layer SEL1. In some embodiments, when the first source / drain pattern SD1 has an n-type, the first semiconductor layer SEL1 may include the same semiconductor material (e.g., silicon (Si)) as the second semiconductor layer SEL2. However, the concentration of the n-type dopant (e.g., phosphorus or arsenic) of the second semiconductor layer SEL2 may be greater than the concentration of the n-type dopant of the first semiconductor layer SEL1.

[0092] The second source / drain pattern SD2 may include a third semiconductor layer SEL3 and a fourth semiconductor layer SEL4 on the third semiconductor layer SEL3. In some embodiments, in the case where the second source / drain pattern SD2 has a p-type, the third semiconductor layer SEL3 may include the same semiconductor material (e.g., silicon germanium (SiGe)) as the fourth semiconductor layer SEL4. However, the germanium concentration of the fourth semiconductor layer SEL4 may be greater than the germanium concentration of the third semiconductor layer SEL3. In addition, the concentration of the p-type dopant (e.g., boron) of the fourth semiconductor layer SEL4 may be greater than the concentration of the p-type dopant of the third semiconductor layer SEL3.

[0093] The third semiconductor layer SEL3 may be in direct contact with the first to third semiconductor patterns SP1, SP2, and SP3. The third semiconductor layer SEL3 may include the above-mentioned protrusion PRP. The second internal gate spacer IGP2 to be described below may directly cover the third semiconductor layer SEL3 or overlap the third semiconductor layer SEL3. The first to third internal gate electrodes PO1, PO2, and PO3 of the second gate electrode GE2 may be spaced apart from the third semiconductor layer SEL3, and the second internal gate spacer IGP2 is interposed between the first to third internal gate electrodes PO1, PO2, and PO3 of the second gate electrode GE2 and the third semiconductor layer SEL3.

[0094] The gate insulating layer GI may include an insulating material containing silicon (Si). For example, the gate insulating layer GI may include SiO x 、Si x N y 、Si x O y C z N v or any combination thereof.

[0095] The gate insulating layer GI may include a first internal gate insulating layer IIL1 between the first to third semiconductor patterns SP1, SP2, and SP3 of the first channel pattern CH1 and the first to third internal gate electrodes PO1, PO2, and PO3 of the first gate electrode GE1, and a first external gate insulating layer OIL1 between the third semiconductor pattern SP3 and the external gate electrode PO4 of the first gate electrode GE1.

[0096] In addition, the gate insulation layer GI may include a second internal gate insulation layer IIL2 located between the first to third semiconductor patterns SP1, SP2 and SP3 of the second channel pattern CH2 and the first to third internal gate electrodes PO1, PO2 and PO3 of the second gate electrode GE2, and a second external gate insulation layer OIL2 located between the third semiconductor pattern SP3 and the external gate electrode PO4 of the second gate electrode GE2.

[0097] Each of the first and second outer gate insulating layers OIL1 and OIL2 may be disposed on the bottom surface and the sidewall of the outer gate electrode PO4. Each of the first and second outer gate insulating layers OIL1 and OIL2 may extend to the gate capping pattern GP (see Figure 5A and Figure 5B ) on the top surface of the external gate electrode PO4, the gate capping pattern GP covers the top surface of the external gate electrode PO4, overlaps with the top surface of the external gate electrode PO4, or is located on the top surface of the external gate electrode PO4.

[0098] Each of the first internal gate insulating layer IIL1 and the second internal gate insulating layer IIL2 may be disposed between the first to third semiconductor patterns SP1 to SP3 and the first to third internal gate electrodes PO1 to PO3. In other words, each of the first internal gate insulating layer IIL1 and the second internal gate insulating layer IIL2 may surround each of the first to third internal gate electrodes PO1 to PO3.

[0099] More specifically, the first internal gate insulating layer IIL1 may include a first upper insulating layer IILT1 located on one of the first to third internal gate electrodes PO1 to PO3, a first lower insulating layer IILB1 disposed under one internal gate electrode, and a first internal gate spacer IGP1 located on both side walls of one internal gate electrode.

[0100] The second internal gate insulating layer IIL2 may include a second upper insulating layer IILT2 on one of the first to third internal gate electrodes PO1 to PO3, a second lower insulating layer IILB2 disposed under one internal gate electrode, and a second internal gate spacer IGP2 on both sidewalls of one internal gate electrode.

[0101] Reference Figure 6C , each of the first upper insulating layer IILT1 and the first lower insulating layer IILB1 may include a body portion BDP parallel to the top surface or the bottom surface of the second internal gate electrode PO2, and tail portions TLP1 or TLP2 disposed on both sides of the body portion BDP. More specifically, the first upper insulating layer IILT1 may include a first tail portion TLP1, and the first lower insulating layer IILB1 may include a second tail portion TLP2.

[0102] Each of the first and second tail portions TLP1 and TLP2 may be located between the body portion BDP and the first internal gate spacer IGP1. In other words, each of the first and second tail portions TLP1 and TLP2 may connect the body portion BDP and the first internal gate spacer IGP1.

[0103] The body portion BDP may have a first length L1 in a third direction D3 corresponding to a direction perpendicular to the bottom surface of the substrate 100, and each of the tail portions TLP1 and TLP2 may have a second length L2 in the third direction D3. Each of the first length L1 and the second length L2 may be defined as the shortest length from the top surface of the inner high-k dielectric layer IHK to the bottom surface of the closest semiconductor pattern among the first to third semiconductor patterns SP1 to SP3.

[0104] The top surface or bottom surface of the inner high-k dielectric layer IHK vertically overlapping the body portion BDP may be a flat surface, and thus the first length L1 may have a uniform value. The top surface of the inner high-k dielectric layer IHK vertically overlapping the first tail portion TLP1 may be a curved surface, and thus the second length L2 may gradually increase toward the second direction D2 intersecting the third direction D3.

[0105] The first length L1 may have a constant value, and the second length L2 may have a variable value. In other words, the second length L2 may vary more than the first length L1 according to the predetermined horizontal distance TLW. For example, the predetermined horizontal distance TLW may be in the range of 1 nm to 3 nm.

[0106] In certain embodiments of the present inventive concept, the second length L2 may have a value very close to the first length L1. For example, the ratio (L2 / L1) of the second length L2 to the first length L1 may be in the range of 1 to 2 (specifically, in the range of 1.1 to 1.5).

[0107] The first internal gate spacer IGP1 may include a vertical portion VPO, a first corner portion CPO1 disposed on the vertical portion VPO, and a second corner portion CPO2 disposed below the vertical portion VPO. The first tail portion TLP1 may be located between the body portion BDP and the first corner portion CPO1 of the first internal gate spacer IGP1. The second tail portion TLP2 may be located between the body portion BDP and the second corner portion CPO2 of the first internal gate spacer IGP1.

[0108] The vertical portion VPO may have a third length L3 in the second direction D2 corresponding to a direction parallel to the bottom surface of the substrate 100. The first corner portion CPO1 may have a fourth length L4 in the second direction D2, and the second corner portion CPO2 may have a fifth length L5 in the second direction D2. The third length L3 may be defined as the shortest length from the fourth side wall CSW4 of the inner high-k dielectric layer IHK to the second side wall CSW2 of the inner spacer ISP. Each of the fourth length L4 and the fifth length L5 may be defined as the shortest length from the baseline S1 to the second side wall CSW2 of the inner spacer ISP, the baseline S1 extending from the fourth side wall CSW4 in the third direction D3.

[0109] The fourth length L4 and the fifth length L5 may be greater than the third length L3. The fourth length L4 and the fifth length L5 may be equal to each other. For example, the third length L3 may be to Each of the fourth length L4 and the fifth length L5 can be within the range of to within the range of (specifically, to within the range of ).

[0110] Refer again Fig. 6A and Figure 6B , the first inner gate spacer IGP1 may be spaced apart from the first source / drain pattern SD1, and the inner spacer ISP is interposed between the first inner gate spacer IGP1 and the first source / drain pattern SD1. The second inner gate spacer IGP2 may directly contact the second source / drain pattern SD2.

[0111] The high-k dielectric layer HK may include an inner high-k dielectric layer IHK and an outer high-k dielectric layer OHK. The inner high-k dielectric layer IHK may be disposed between each of the inner gate insulating layers IIL1 and IIL2 and the first to third inner gate electrodes PO1, PO2, and PO3 of each of the first gate electrode GE1 and the second gate electrode GE2. The outer high-k dielectric layer OHK may be disposed between the outer gate electrode PO4 of each of the first gate electrode GE1 and the second gate electrode GE2 and each of the outer gate insulating layers OIL1 and OIL2.

[0112] The inner high-k dielectric layer IHK may surround each of the first to third inner gate electrodes PO1, PO2, and PO3 with a uniform thickness. In other words, the inner high-k dielectric layer IHK may be conformally formed in the inner gate space to be described below (see Fig.19 The external high-k dielectric layer OHK may extend from the bottom surface of the external gate electrode PO4 to the sidewall. For example, the gate insulating layer GI may be stacked on the high-k dielectric layer HK.

[0113] Refer again Figure 6C , the inner high-k dielectric layer IHK may include a third sidewall CSW3 in contact with the second inner gate electrode PO2 and a fourth sidewall CSW4 in contact with the first inner gate spacer IGP1. The third sidewall CSW3 and the fourth sidewall CSW4 may have a flat surface shape in a third direction D3 perpendicular to the bottom surface of the substrate 100. In some embodiments, the third sidewall CSW3 and the fourth sidewall CSW4 may have a curved surface shape.

[0114] IDR (see Fig.14 ) may be defined between the first source / drain pattern SD1 and each of the first to third internal gate electrodes PO1 to PO3 of the first gate electrode GE1. The recessed region IDR (see Fig.14) may be an empty space extending from the first source / drain pattern SD1 toward a corresponding internal gate electrode among the first to third internal gate electrodes PO1 to PO3. The sidewall of the first internal gate spacer IGP1 may be formed by a recessed region IDR (see Fig.14 ) is recessed.

[0115] The internal spacer ISP may be disposed in the recessed region IDR (see Fig.14 ) in each of the . According to the present embodiment, the inner spacer ISP may completely fill the concave region IDR (see Fig.14 ). The first sidewall CSW1 of the internal spacer ISP may be in direct contact with the first source / drain pattern SD1. The second sidewall CSW2 of the internal spacer ISP may be in direct contact with the gate insulating layer GI. More specifically, the second sidewall CSW2 may be in direct contact with the first internal gate spacer IGP1 of the first internal gate insulating layer IIL1.

[0116] The first side wall CSW1 may be opposite to the second side wall CSW2 in the second direction D2. The first side wall CSW1 and the second side wall CSW2 may be curved surfaces. The curvature of the first side wall CSW1 may be less than the curvature of the second side wall CSW2. In some embodiments, the curvature of the first side wall CSW1 may be substantially equal to the curvature of the second side wall CSW2.

[0117] The internal spacer ISP may include an insulating material containing silicon (Si). For example, the internal spacer ISP may include SiO x 、Si x N y 、Si x O y C z N v or any combination thereof. For example, the internal spacer ISP may include an insulating material different from insulating materials of the gate spacer GS and the first internal gate spacer IGP1.

[0118] The inner spacer ISP may vertically overlap the gate spacer GS. More specifically, the gate spacer GS may vertically overlap a portion of the inner spacer ISP and a portion of the first inner gate spacer IGP1.

[0119] Refer again Fig. 6A and Figure 6B , the first inner gate spacer IGP1 may have a first thickness TH1. The first thickness TH1 may be defined as the shortest distance between one sidewall of the inner high-k dielectric layer IHK and one sidewall of the inner spacer ISP. The first thickness TH1 may be a distance in the second direction D2.

[0120] The first upper insulating layer IILT1 or the first lower insulating layer IILB1 may have a second thickness TH2. The second thickness TH2 may be defined as the shortest distance between the top surface of the inner high-k dielectric layer IHK and the bottom surface of the upper semiconductor pattern (e.g., SP2) among the semiconductor patterns adjacent to each other. The second thickness TH2 may be a distance in the third direction D3.

[0121] The first outer gate insulating layer OIL1 may have a third thickness TH3 and a fourth thickness TH4. The third thickness TH3 may be defined as the shortest distance between one sidewall of the outer high-k dielectric layer OHK and one sidewall of the gate spacer GS. The third thickness TH3 may be a distance in the second direction D2. The fourth thickness TH4 may be defined as the shortest distance between the bottom surface of the outer high-k dielectric layer OHK and the top surface of the uppermost semiconductor pattern SP3. The fourth thickness TH4 may be a distance in the third direction D3.

[0122] The inner spacer ISP may have a fifth thickness TH5. The fifth thickness TH5 may be defined as the shortest distance between one sidewall of the first inner gate spacer IGP1 and one sidewall of the first source / drain pattern SD1. The fifth thickness TH5 may be a distance in the second direction D2.

[0123] The gate spacer GS may have a sixth thickness TH6. The sixth thickness TH6 may be defined as the shortest distance between one sidewall of the first outer gate insulating layer OIL1 and one sidewall of the first interlayer insulating layer 110. The sixth thickness TH6 may be a distance in the second direction D2.

[0124] The second inner gate spacer IGP2 may have a seventh thickness TH7. The seventh thickness TH7 may be defined as the shortest distance between one sidewall of the inner high-k dielectric layer IHK and one sidewall of the second source / drain pattern SD2. The seventh thickness TH7 may be a distance in the second direction D2.

[0125] The second upper insulating layer IILT2 or the second lower insulating layer IILB2 may have an eighth thickness TH8. The eighth thickness TH8 may be defined as the shortest distance between the top surface of the inner high-k dielectric layer IHK and the bottom surface of the upper semiconductor pattern (e.g., SP2) among the semiconductor patterns adjacent to each other. The eighth thickness TH8 may be a distance in the third direction D3.

[0126] The first thickness TH1 may be greater than the second thickness TH2. The fifth thickness TH5 may be greater than the first thickness TH1. The third thickness TH3 and the fourth thickness TH4 may be greater than the second thickness TH2 and may be less than the first thickness TH1. The third thickness TH3 and the fourth thickness TH4 may be equal to each other. The sixth thickness TH6 may be greater than the fifth thickness TH5. In other words, the width of the gate spacer GS may be greater than the maximum width of the internal spacer ISP. In a specific embodiment, the sum of the first thickness TH1 and the fifth thickness TH5 may be greater than the sixth thickness TH6.

[0127] The first thickness TH1 may be equal to (or defined as) an average value of the third length L3 of the vertical portion VPO, the fourth length L4 of the first corner portion CPO1, and the fifth length L5 of the second corner portion CPO2. For example, the average value may be a target value for forming the first internal gate spacer IGP1 between the internal spacer ISP and the internal gate electrodes PO1, PO2, and PO3.

[0128] The seventh thickness TH7 may be less than the sum of the first thickness TH1 and the fifth thickness TH5. The seventh thickness TH7 may be equal to the first thickness TH1 or may be less than the first thickness TH1. The seventh thickness TH7 may be greater than the eighth thickness TH8. The ratio of the seventh thickness TH7 to the eighth thickness TH8 may be in the range of 1.1 to 1.8 (specifically, may be 1.5).

[0129] For example, each of the first thickness TH1 and the seventh thickness TH7 may be to Each of the second thickness TH2 and the eighth thickness TH8 may be within the range of to Each of the third thickness TH3 and the fourth thickness TH4 may be to The fifth thickness TH5 may be within the range of to within the range.

[0130] According to an embodiment of the present invention, the sum of the thickness of the first internal gate spacer IGP1 and the thickness of the internal spacer ISP may be greater than the thickness of the second internal gate spacer IGP2, and therefore, the leakage current of the transistor may be effectively reduced. In other words, the three-dimensional field effect transistor according to the present invention may have a double spacer capable of preventing gate leakage current on the NMOSFET region, and may have a single spacer capable of preventing gate leakage current on the PMOSFET region. Therefore, the gate leakage current of the transistor may be selectively controlled.

[0131] In addition, the double spacer can increase the distance between the gate electrode and the first source / drain pattern, and therefore, the capacitance and gate leakage current can be effectively reduced. According to the inventive concept, the thickness of the double spacer can be selectively increased to improve the electrical characteristics of the semiconductor device. The single spacer can separate the gate electrode from the second source / drain pattern, and the second source / drain pattern can protrude between the semiconductor patterns. Therefore, the second source / drain pattern can be formed without defects. As a result, the reliability and electrical characteristics of the semiconductor device according to the inventive concept can be improved.

[0132] Fig.6D It is shown Figure 5A In this embodiment, for the purpose of ease and convenience of explanation, the above reference will be omitted. Figures 1 to 6A The description of the same technical features mentioned above is omitted, and the differences between this embodiment and the above embodiments will be mainly described.

[0133] Reference Fig.6D , the internal spacer ISP may be disposed in the recessed region IDR (see Fig.14 ) in each of the . According to the present embodiment, the inner spacer ISP may completely fill the concave region IDR (see Fig.14 ). The first sidewall CSW1 of the internal spacer ISP may be in direct contact with the first source / drain pattern SD1. The second sidewall CSW2 of the internal spacer ISP may be in direct contact with the gate insulating layer GI. More specifically, the second sidewall CSW2 may be in direct contact with the first internal gate spacer IGP1 of the first internal gate insulating layer IIL1.

[0134] The first side wall CSW1 may be opposite to the second side wall CSW2 in the second direction D2. The first side wall CSW1 and the second side wall CSW2 may have curved surfaces. The curvature of the first side wall CSW1 may be substantially equal to the curvature of the second side wall CSW2.

[0135] The internal spacer ISP may include a top surface TSF and a bottom surface BSF adjacent to the semiconductor patterns SP1 to SP3. The top surface TSF and the bottom surface BSF may be opposite to each other in the third direction D3. For example, the top surface TSF of the internal spacer ISP may contact a portion of the bottom surface of the second semiconductor pattern SP2, and the bottom surface BSF of the internal spacer ISP may contact a portion of the top surface of the first semiconductor pattern SP1.

[0136] The inner spacer ISP may vertically overlap the gate spacer GS. More specifically, the gate spacer GS may vertically overlap a portion of the inner spacer ISP and a portion of the first inner gate spacer IGP1.

[0137] Each of the internal spacers ISP may have a uniform width in the second direction D2. This may be to uniformly at least partially or completely fill the internal gate space to be described below with the body oxide layer. Therefore, the width of the first internal gate spacer IGP1 in the second direction D2 may be uniform. Since the internal gate space is ensured, the edge portion of the internal gate space may be rounded to stably form the internal gate electrodes PO1 to PO3. In other words, the work function of each of the internal gate electrodes PO1 to PO3 may be uniform. Therefore, the electrical characteristics of the semiconductor device according to the embodiment of the inventive concept may be improved.

[0138] Figure 7 It is shown Figure 5A In this embodiment, for the purpose of ease and convenience of explanation, the above reference will be omitted. Figures 1 to 6A and Fig.6D The description of the same technical features mentioned above is omitted, and the differences between this embodiment and the above embodiments will be mainly described.

[0139] Reference Figure 7 , an air gap VAG may be defined between the first internal gate insulating layer IIL1 and the internal spacer ISP. The air gap VAG may be surrounded by the internal spacer ISP, the first internal gate insulating layer IIL1, and one of the first to third semiconductor patterns SP1 to SP3.

[0140] The air gap VAG may be disposed on a first corner portion CPO1 and a second corner portion CPO2 of the first internal gate spacer IGP1. For example, the air gap VAG may be defined between the first corner portion CPO1 and the internal spacer ISP and between the second corner portion CPO2 and the internal spacer ISP, respectively. In some embodiments, four air gaps VAG may be disposed in the internal region IRG to be described below. The four air gaps VAG may be adjacent to four corners of the internal gate space IGE to be described below, respectively.

[0141] According to the manufacturing method to be described below, the sacrificial layer SAL exposed through the outer region ORG formed by selectively removing the sacrificial pattern PP may be removed. The sacrificial layer SAL may be selectively removed to form the first to third inner regions IRG1 to IRG3. The first inner gate insulating layer IIL1 may be formed in the first to third inner regions IRG1 to IRG3.

[0142] A space adjacent to the internal spacer ISP in each of the first to third inner regions IRG1 to IRG3 may be narrower than another space. In other words, a sidewall of the internal spacer ISP may be formed as a curved surface, and thus, a space adjacent to the internal spacer ISP may have a tapered shape.

[0143] Therefore, when the bulk oxide layer BOX is deposited in the first to third inner regions IRG1 to IRG3 , the space adjacent to the inner spacer ISP may not be filled. According to an embodiment of the inventive concept, the unfilled space may be defined as an air gap VAG.

[0144] Although not shown in the drawings, an optimized deposition process may be performed to form a bulk oxide layer BOX in the first to third inner regions IRG1 to IRG3. In other words, the bulk oxide layer BOX may be deposited without an empty space. In this case, the air gap VAG may not be formed between the inner spacer ISP and the first inner gate insulating layer IIL1. A semiconductor device in which the air gap VAG is not formed may be similar to Fig. 6A The embodiment corresponds to .

[0145] Refer again Figure 7 , the topmost surface of the internal spacer ISP may be located at the same level as the topmost surface of the first upper insulating layer IILT1 in the third direction D3. In other words, the topmost surface of the internal spacer ISP and the topmost surface of the first upper insulating layer IILT1 may be in contact with the bottom surface of the third semiconductor pattern SP3. The bottommost surface of the internal spacer ISP may be located at the same level as the bottommost surface of the first lower insulating layer IILB1 in the third direction D3. In other words, the bottommost surface of the internal spacer ISP and the bottommost surface of the first lower insulating layer IILB1 may be in contact with the top surface of the second semiconductor pattern SP2.

[0146] Although not shown in the drawings, in certain embodiments, the topmost surface of the internal spacer ISP may be located at a level lower than the topmost surface of the first upper insulating layer IILT1 in the third direction D3. The bottommost surface of the internal spacer ISP may be located at a level higher than the bottommost surface of the first lower insulating layer IILB1 in the third direction D3.

[0147] This may be because when the recessed region IDR is formed in the manufacturing method to be described below (see Fig.14 ) is performed fully when the selective etching process is performed. For example, the sacrificial layer SAL (see Fig.14 ). Therefore, the sacrificial layer SAL (see Fig.14 ) and the sidewalls of the first to third semiconductor patterns SP1 to SP3 (see Fig.14) adjacent portions may be vertically flat. The sacrificial layer SAL (see Fig.14 ) may be recessed. As a result, the topmost surface of the internal spacer ISP may be located at a level lower than the topmost surface of the first upper insulating layer IILT1 in the third direction D3, and the bottommost surface of the internal spacer ISP may be located at a level higher than the bottommost surface of the first lower insulating layer IILB1 in the third direction D3.

[0148] According to the present embodiment, the air gap VAG may be provided at a corner portion of the inner spacer ISP to reduce capacitance between the first source / drain pattern SD1 and each of the inner gate electrodes PO1, PO2, and PO3. As a result, electrical characteristics of the semiconductor device according to the inventive concept may be improved.

[0149] FIG. 8A to FIG. 13D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept. More specifically, Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A and Fig.13A is with Figure 4 The cross-sectional view corresponding to the line AA'. Fig. 10B , Fig. 11B , Fig. 12B and Fig. 13B is with Figure 4 The cross-sectional view corresponding to the line BB'. Fig. 10C , Fig. 11C , Fig. 12C and Fig. 13C is with Figure 4 The cross-sectional view corresponding to the line CC'. Figure 8B , Fig. 9B , Fig. 10D , Fig.12D and Fig.13D is with Figure 4 The cross-sectional view corresponding to the line D-D'.

[0150] Reference Fig. 8A and Figure 8B , a substrate 100 including a first active region AR1 and a second active region AR2 may be provided. Active layers ACL and sacrificial layers SAL may be formed to be alternately stacked on the substrate 100. The active layer ACL may include one of silicon (Si), germanium (Ge) and / or silicon germanium (SiGe), and the sacrificial layer SAL may include another of silicon (Si), germanium (Ge) and / or silicon germanium (SiGe).

[0151] The sacrificial layer SAL may include a material having an etching selectivity relative to the active layer ACL. For example, the active layer ACL may include silicon (Si), and the sacrificial layer SAL may include silicon germanium (SiGe). The concentration of germanium (Ge) in each of the sacrificial layers SAL may be in the range of 10 at % to 30 at %.

[0152] Mask patterns may be respectively formed on the first active area AR1 and the second active area AR2 of the substrate 100. Each of the mask patterns may have a line shape or a bar shape extending in the second direction D2.

[0153] A patterning process may be performed using the mask pattern as an etching mask to form trenches TR defining first and second active patterns AP1 and AP2. The first active pattern AP1 may be formed on the first active area AR1. The second active pattern AP2 may be formed on the second active area AR2.

[0154] A stack pattern STP may be formed on each of the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may include active layers ACL and sacrificial layers SAL that are alternately stacked. The stack pattern STP may be formed together with the first active pattern AP1 and the second active pattern AP2 in a patterning process.

[0155] A device isolation layer ST filling the trench TR may be formed. For example, an insulating layer covering the first and second active patterns AP1 and AP2 and the stacked pattern STP, being located on the first and second active patterns AP1 and AP2 and the stacked pattern STP, or overlapping the first and second active patterns AP1 and AP2 and the stacked pattern STP may be formed on the entire top surface of the substrate 100. The insulating layer may be recessed until the stacked pattern STP is exposed, thereby forming the device isolation layer ST.

[0156] The device isolation layer ST may include an insulating material (eg, silicon oxide). The stack pattern STP may be exposed above the device isolation layer ST. In other words, the stack pattern STP may protrude vertically above the device isolation layer ST.

[0157] Reference Fig.9A and Fig. 9B , sacrificial patterns PP intersecting the stacked patterns STP may be formed on the substrate 100. Each of the sacrificial patterns PP may be formed to have a line shape or a bar shape extending in the first direction D1. The sacrificial patterns PP may be arranged in the second direction D2 at a first pitch.

[0158] For example, the formation of the sacrificial pattern PP may include forming a sacrificial layer on the entire top surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask. The sacrificial layer may include polysilicon.

[0159] A pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns PP, respectively. The formation of the gate spacer GS may include conformally forming a gate spacer layer on the entire top surface of the substrate 100 and anisotropically etching the gate spacer layer. In some embodiments, the gate spacer GS may be formed of a multilayer including at least two layers.

[0160] Reference Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D , a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. It is also possible to form a first recess RS1 and a second recess RS2 (see Fig. 10C ) during the formation of the first active pattern AP1 and the second active pattern AP2, the device isolation layer ST located at both sides of each of the first active pattern AP1 and the second active pattern AP2 is recessed.

[0161] For example, the stacked pattern STP on the first active pattern AP1 may be etched using the hard mask pattern MP and the gate spacer GS as an etching mask to form the first recess RS1. The first recess RS1 may be formed between a pair of sacrificial patterns PP.

[0162] In some embodiments of the present inventive concept, a selective etching process may be additionally performed on the sacrificial layer SAL exposed by the second recess RS2. Each of the sacrificial layers SAL may be recessed by the selective etching process to form a recessed area IDE. The recessed area IDE may be formed on the second active pattern AP2. The second recess RS2 may have a wave-shaped inner sidewall by the recessed area IDE.

[0163] First to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent first recesses RS1 may be formed from the active layer ACL, respectively. The first to third semiconductor patterns SP1, SP2, and SP3 located between adjacent first recesses RS1 may constitute a first channel pattern CH1.

[0164] First to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between the second recesses RS2 adjacent to each other may be formed from the active layer ACL, respectively. The first to third semiconductor patterns SP1, SP2, and SP3 located between the second recesses RS2 adjacent to each other may constitute a second channel pattern CH2.

[0165] Figures 14 to 16 It is shown that the formation Fig. 10A An enlarged view of the area "M" of the method. Fig.14 As described above, the first recess RS1 may be formed between the sacrificial patterns PP adjacent to each other. The width of the first recess RS1 in the second direction D2 may become smaller toward the substrate 100 .

[0166] The sacrificial layer SAL may be exposed by the first recess RS1. An etching process may be performed on the exposed sacrificial layer SAL. The etching process may include a wet etching process that selectively removes silicon germanium. Each of the sacrificial layers SAL may be recessed by the etching process to form a recessed region IDR. The sidewall of the sacrificial layer SAL may be recessed by the recessed region IDR. The width of the sacrificial layer SAL in the second direction D2 may be smaller than the width of each of the first to third semiconductor patterns SP1 to SP3 in the second direction D2.

[0167] Reference Fig.15 , a body insulating layer PIL filling the recessed region IDR may be formed in the first recess RS1. More specifically, the body insulating layer PIL may extend from the inner surface of the first recess RS1 to the sidewall of the gate spacer GS. For example, the body insulating layer PIL may include SiO x 、Si x N y 、Si x O y C z N v Or any combination thereof. The body insulating layer PIL may be deposited by performing a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. The body insulating layer PIL formed on the sidewalls of the sacrificial layer SAL may be thicker than the body insulating layer PIL formed on the sidewalls of the first to third semiconductor patterns SP1 to SP3 and the sidewalls of the gate spacers GS.

[0168] Reference Fig.16, the internal spacer ISP may be formed to fill the recessed region IDR. For example, the formation of the internal spacer ISP may include wet-etching the body insulating layer PIL to expose the sidewalls of the first to third semiconductor patterns SP1, SP2, and SP3. Therefore, the body insulating layer PIL may remain only in the recessed region IDR to form the internal spacer ISP.

[0169] Reference Fig.11A , Fig. 11B and Fig. 11C , first source / drain patterns SD1 may be formed in the first recess RS1, respectively. For example, a SEG process using the inner surface of the first recess RS1 as a seed layer may be performed to form an epitaxial layer filling the first recess RS1. The epitaxial layer may be grown using the first to third semiconductor patterns SP1, SP2, and SP3 and the substrate 100 exposed by the first recess RS1 as seeds. For example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0170] In some embodiments of the present inventive concept, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. A dopant (e.g., phosphorus, arsenic, or antimony) that allows the first source / drain pattern SD1 to have an n-type may be in-situ implanted during the formation of the first source / drain pattern SD1. In some embodiments, after the first source / drain pattern SD1 is formed, the dopant may be implanted or implanted into the first source / drain pattern SD1.

[0171] Second source / drain patterns SD2 may be formed in the second recesses RS2, respectively. For example, the second source / drain patterns SD2 may be formed by performing a SEG process using inner surfaces of the second recesses RS2 as a seed layer.

[0172] In some embodiments of the present inventive concept, the second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. A dopant (e.g., boron, gallium, or indium) that allows the second source / drain pattern SD2 to have a p-type may be in-situ implanted during the formation of the second source / drain pattern SD2. In some embodiments, after the second source / drain pattern SD2 is formed, the dopant may be implanted or implanted into the second source / drain pattern SD2.

[0173] Reference Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D, the first interlayer insulating layer 110 may be formed to cover or overlap the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0174] The first interlayer insulating layer 110 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MP may be completely removed during the planarization process. As a result, the top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0175] The exposed sacrificial pattern PP may be selectively removed. An outer region ORG (see FIG. 1 ) exposing the first and second channel patterns CH1 and CH2 may be formed by removing the sacrificial pattern PP. Fig.12D ). The removal of the sacrificial pattern PP may include performing a wet etching process using an etching solution capable of selectively etching polysilicon.

[0176] The sacrificial layer SAL exposed through the outer region ORG may be selectively removed to form the inner region IRG (see Fig.12D ). For example, an etching process that selectively etches the sacrificial layer SAL may be performed to remove the sacrificial layer SAL while leaving the first to third semiconductor patterns SP1, SP2, and SP3. The etching process may have a high etching rate relative to silicon germanium having a relatively high germanium concentration. For example, the etching process may have a high etching rate relative to silicon germanium having a germanium concentration greater than 10 at%.

[0177] The sacrificial layer SAL on the first active region AR1 and the second active region AR2 may be removed during the etching process. The etching process may be a wet etching process. The etching material used in the etching process may quickly remove the sacrificial layer SAL having a relatively high germanium concentration.

[0178] Refer again Fig.12D, since the sacrificial layer SAL is selectively removed, the first to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked may remain on each of the first active pattern AP1 and the second active pattern AP2. The first to third inner regions IRG1, IRG2, and IRG3 may be formed by removing the sacrificial layer SAL. More specifically, the first inner region IRG1 may be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, the second inner region IRG2 may be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the third inner region IRG3 may be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0179] Refer again FIG. 12A to FIG. 12D , a gate insulating layer GI may be formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may be formed to surround each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may be formed in each of the first to third inner regions IRG1, IRG2, and IRG3. The gate insulating layer GI may be formed in the outer region ORG.

[0180] Figures 17 to 19 It is shown that the formation Fig. 12A An enlarged view of the area "M" of the method. Fig.17 As described above, the sacrificial pattern PP may be selectively removed to form the outer region ORG. The sacrificial layer SAL exposed by the outer region ORG may be selectively removed to form the first to third inner regions IRG1 to IRG3. Each of the first to third inner regions IRG1 to IRG3 may be located between a pair of first source / drain patterns SD1. More specifically, each of the first to third inner regions IRG1 to IRG3 may be located between a pair of inner spacers ISP.

[0181] Representatively, the second inner region IRG2 may expose the second side wall CSW2 of the inner spacer ISP. The second inner region IRG2 may expose the top surface of the first semiconductor pattern SP1 and the bottom surface of the second semiconductor pattern SP2.

[0182] In some embodiments of the present inventive concept, the second sidewall CSW2 of the inner spacer ISP may have a convex profile. As the height in the third direction D3 increases, the length (or width) of each of the inner regions IRG1 to IRG3 in the second direction D2 may decrease and then increase. Due to the second sidewall CSW2, the first side of the first inner region IRG1 may be recessed.

[0183] Reference Fig.18 , a first process may be performed on the first inner region IRG1 to the third inner region IRG3 and the outer region ORG. The first process may include conformally depositing a body oxide layer BOX. The body oxide layer BOX may be formed using a deposition process such as an ALD process or a CVD process. The body oxide layer BOX may not completely fill the inner regions IRG1 to IRG3, but may partially fill the inner regions IRG1 to IRG3. Therefore, an internal gate space IGE surrounded by the body oxide layer BOX may be defined in each of the inner regions IRG1 to IRG3. For example, the body oxide layer BOX may include a silicon oxide layer or a silicon oxynitride layer. For example, the body oxide layer BOX may include SiO x 、Si x O y C z N v or any combination thereof.

[0184] Reference Fig.19 , a second process may be performed on the first to third inner regions IRG1 to IRG3 and the outer region ORG. The second process may include partially and selectively etching the body oxide layer BOX. The second process may include a wet etching process using an etching solution capable of selectively etching the body oxide layer BOX. More specifically, an etching material may be provided through the internal gate space IGE to etch the body oxide layer BOX.

[0185] After the etching process, the body oxide layer BOX may remain on the second side wall CSW2 of the internal spacer ISP. Specifically, a relatively large amount of the body oxide layer BOX may remain on the second side wall CSW2 of the internal spacer ISP. In other words, the etched body oxide layer BOX may remain thicker on the side wall of the internal spacer ISP, and may remain thinner on the top and bottom surfaces of the semiconductor patterns SP1 to SP3 adjacent thereto. The etched body oxide layer BOX may be formed into a first internal gate insulating layer IIL1 and a first external gate insulating layer OIL1. The first internal gate insulating layer IIL1 may provide a first internal gate insulating layer IIL2 and a second external gate insulating layer OIL3. Fig.18 The internal gate space IGE is enlarged compared to the internal gate space IGE.

[0186] Thereafter, a high-k dielectric layer HK may be formed in the outer region ORG and the first to third inner regions IRG1 to IRG3 (see Fig. 6A ). can be formed in the internal gate space IGE Fig. 6A In some embodiments of the present invention, the high-k dielectric layer HK may be conformally formed. Fig. 6AIn other words, the thickness of the high-k dielectric layer HK in the horizontal direction may be substantially equal to the thickness of the high-k dielectric layer HK in the vertical direction.

[0187] Reference FIG. 13A to FIG. 13D , a gate electrode GE including a first gate electrode GE1 and a second gate electrode GE2 may be formed on the gate insulating layer GI. More specifically, a high-k dielectric layer HK (see Fig. 6A ) is formed on the gate electrode GE. In other words, a high-k dielectric layer HK may be formed on the gate insulating layer GI, and gate electrodes GE1 and GE2 may be formed on the high-k dielectric layer HK. Each of the gate electrodes GE1 and GE2 may include first to third internal gate electrodes PO1, PO2, and PO3 formed in the first to third internal regions IRG1, IRG2, and IRG3, respectively, and an external gate electrode PO4 formed in the external region ORG. The gate electrode GE may be recessed to reduce its height. A gate capping pattern GP may be formed on the recessed gate electrode GE.

[0188] Refer again Figure 5A , Figure 5B , Figure 5C and Figure 5D , a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. An active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110, and the active contact AC may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP, ​​and the gate contact GC may be electrically connected to the gate electrode GE.

[0189] The formation of each of the active contact AC and the gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include a metal layer / metal nitride layer. The conductive pattern FM may include a low resistance metal.

[0190] An isolation structure DB may be formed at the first and second boundaries BD1 and BD2 of the single height cell SHC, respectively. The isolation structure DB may penetrate the second interlayer insulating layer 120 and the gate electrode GE and may extend into the active pattern AP1 or AP2. The isolation structure DB may include an insulating material such as silicon oxide or silicon nitride.

[0191] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0192] In a three-dimensional field effect transistor according to the present invention, the internal gate insulating layer may include an internal gate spacer capable of preventing leakage current of the gate. The thickness of the side of the internal gate insulating layer may be selectively increased, and the thickness of the horizontal portion and the corner portion of the internal gate insulating layer may be minimized, thereby ensuring sufficient internal gate space. Therefore, the internal gate electrode may stably fill the internal gate space. In addition, the edge portion of the internal gate electrode may be rounded to stably fill the internal gate space with the internal gate electrode. Therefore, the work function of the internal gate electrode may be uniform. As a result, the electrical characteristics of the semiconductor device according to the present invention may be improved.

[0193] The three-dimensional field effect transistor according to the present invention can have a double spacer that can prevent gate leakage current on the NMOSFET region, and can have a single spacer that can prevent gate leakage current on the PMOSFET region. The double spacer can reduce the capacitance and gate leakage current between the gate electrode and the first source / drain pattern. The single spacer can form the second source / drain pattern without defects. As a result, the reliability and electrical characteristics of the semiconductor device according to the present invention can be improved.

[0194] While embodiments of the inventive concept have been particularly shown and described, one of ordinary skill in the art will understand that changes in form and details may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate including an active pattern; a channel pattern located on the active pattern, the channel pattern comprising a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; an internal gate electrode located between adjacent first and second semiconductor patterns among the plurality of semiconductor patterns; an internal gate insulating layer located between the internal gate electrode and the first semiconductor pattern and the second semiconductor pattern; an inner high-k dielectric layer between the inner gate electrode and the inner gate insulating layer; as well as an inner spacer located between the inner gate insulating layer and the source / drain pattern, Wherein, the internal gate insulating layer comprises: an upper insulating layer located between the internal gate electrode and the second semiconductor pattern; a lower insulating layer located between the internal gate electrode and the first semiconductor pattern; and an inner gate spacer located between the inner gate electrode and the source / drain pattern, wherein a first thickness of the inner gate spacer at a central portion of the inner gate spacer is greater than a second thickness of the upper insulating layer or the lower insulating layer, and Wherein, a third thickness of the inner spacer is greater than the first thickness of the inner gate spacer.

2. The semiconductor device according to claim 1, wherein The first thickness is to within the range.

3. The semiconductor device according to claim 1, wherein The second thickness is to within the range.

4. The semiconductor device according to claim 1, wherein The third thickness is to within the range.

5. The semiconductor device according to claim 1, wherein The inner gate spacer and each of the inner spacers include SiO x 、Si x N y 、Si x O y C z N v or a combination thereof, and Wherein, the inner gate spacer and the inner spacer include different insulating materials.

6. The semiconductor device according to claim 1, further comprising: An air gap is located between the inner gate spacer and the inner spacer.

7. The semiconductor device according to claim 1, wherein The internal spacer comprises: a first sidewall contacting the source / drain pattern; and a second sidewall, which is in contact with the inner gate spacer, Wherein, each of the first side wall and the second side wall has a curved surface.

8. The semiconductor device according to claim 7, wherein: The curvature of the first side wall is smaller than the curvature of the second side wall.

9. The semiconductor device according to claim 7, wherein: The inner high-k dielectric layer comprises: a third side wall contacting the internal gate electrode; and a fourth sidewall in contact with the inner gate spacer, and Wherein, each of the third side wall and the fourth side wall has a flat surface in a direction perpendicular to the surface of the substrate.

10. The semiconductor device according to claim 1, wherein The internal gate spacer comprises: a vertical portion having a first length in a first direction; a first angle portion located on the vertical portion and having a second length in the first direction; and a second angle portion located below the vertical portion and having a third length in the first direction, The first thickness is an average value of the first length, the second length and the third length.

11. The semiconductor device according to claim 1, further comprising: an external gate electrode located on an uppermost semiconductor pattern among the plurality of semiconductor patterns; an external gate insulating layer located between the uppermost semiconductor pattern and the external gate electrode, wherein the external gate insulating layer is located on opposite side walls of the external gate electrode; an outer high-k dielectric layer between the outer gate electrode and the outer gate insulating layer; and a first gate spacer and a second gate spacer, the first gate spacer and the second gate spacer being located on respective sidewalls of the outer gate insulating layer, The fourth thickness of the external gate insulating layer in the first direction is substantially equal to the fifth thickness of the external gate insulating layer in the second direction intersecting with the first direction.

12. The semiconductor device according to claim 11, wherein The first gate spacer has a sixth thickness in the first direction, and Wherein, the sixth thickness is greater than the third thickness.

13. The semiconductor device according to claim 11, wherein The first gate spacer overlaps the inner spacer or a portion of the inner spacer in a direction perpendicular to a surface of the substrate.

14. A semiconductor device comprising: a substrate comprising a first active pattern and a second active pattern; a first channel pattern and a second channel pattern, the first channel pattern and the second channel pattern being respectively located on the first active pattern and the second active pattern, wherein the first channel pattern and the second channel pattern each include a plurality of semiconductor patterns spaced apart from each other; a first source / drain pattern electrically connected to the first channel pattern; a second source / drain pattern electrically connected to the second channel pattern; a first internal gate electrode located between adjacent semiconductor patterns among the plurality of semiconductor patterns of the first channel pattern; a second internal gate electrode located between adjacent semiconductor patterns among the plurality of semiconductor patterns of the second channel pattern; a first internal gate insulating layer located between the first internal gate electrode and the adjacent semiconductor pattern of the first channel pattern; a second internal gate insulating layer located between the second internal gate electrode and the adjacent semiconductor pattern of the second channel pattern; a first inner high-k dielectric layer between the first inner gate electrode and the first inner gate insulating layer; and a second inner high-k dielectric layer between the second inner gate electrode and the second inner gate insulating layer, Wherein, the first internal gate insulating layer comprises: a first upper insulating layer located on a top surface of the first internal gate electrode; a first lower insulating layer located on a bottom surface of the first internal gate electrode; and a first internal gate spacer located on two sidewalls of the first internal gate electrode, Wherein, the second internal gate insulating layer comprises: a second upper insulating layer located on a top surface of the second internal gate electrode; a second lower insulating layer located on a bottom surface of the second internal gate electrode; and a second inner gate spacer located on two sidewalls of the second inner gate electrode, Wherein, the semiconductor device further comprises: an inner spacer located between the first inner gate spacer and the first source / drain pattern, The thickness of the second inner gate spacer is less than the sum of the thickness of the first inner gate spacer and the thickness of the inner spacer.

15. The semiconductor device according to claim 14, wherein: The first inner gate spacer is spaced apart from the first source / drain pattern, and Wherein, the second inner gate spacer contacts the second source / drain pattern.

16. The semiconductor device according to claim 14, further comprising: An air gap is located between the first inner gate spacer and the inner spacer.

17. The semiconductor device according to claim 14, wherein: The first inner gate spacer and the second inner gate spacer and each of the inner spacers include SiO x 、Si x N y 、Si x O y C z N v or a combination thereof, and Wherein, the first inner gate spacer and the inner spacer comprise different insulating materials.

18. A semiconductor device comprising: a substrate including an active pattern; a channel pattern located on the active pattern, the channel pattern comprising a plurality of semiconductor patterns spaced apart from each other; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode, which is located on the plurality of semiconductor patterns, wherein the gate electrode comprises: an internal gate electrode located between adjacent semiconductor patterns among the plurality of semiconductor patterns; and an external gate electrode located on an uppermost semiconductor pattern among the plurality of semiconductor patterns; a gate insulating layer, located between the gate electrode and the plurality of semiconductor patterns, wherein the gate insulating layer comprises: an internal gate insulating layer located between the internal gate electrode and the plurality of semiconductor patterns; and an external gate insulating layer located on the uppermost semiconductor pattern; a high-k dielectric layer located between the gate electrode and the gate insulating layer; and an inner spacer located between the inner gate insulating layer and the source / drain pattern, Wherein, the internal gate insulating layer comprises: an upper insulating layer located on a top surface of the internal gate electrode; a lower insulating layer located on a bottom surface of the internal gate electrode; and an inner gate spacer located between the inner gate electrode and the inner spacer, Wherein, each of the upper insulating layer and the lower insulating layer comprises: a body portion parallel to a top surface or a bottom surface of the internal gate electrode; and tail portions, which are located on both sides of the main body portion, wherein the main body portion has a first length in a vertical direction perpendicular to the substrate, wherein the tail has a second length in the vertical direction, and The second length varies with a predetermined horizontal distance, which is greater than the first length varies with the predetermined horizontal distance.

19. The semiconductor device according to claim 18, wherein: The first length has a substantially uniform value.

20. The semiconductor device according to claim 18, wherein The second length gradually increases toward a direction intersecting with the vertical direction.

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