A cascaded GaN power device

Abstract

The application discloses a cascade GaN power device, and relates to the technical field of semiconductors. The cascade GaN power device comprises a GaN device, a Si MOS tube and a resistor. The source of the GaN device is connected with the drain of the Si MOS tube. The gate of the GaN device is connected with one end of the resistor. The other end of the resistor is connected with the source of the Si MOS tube. The drain of the GaN device serves as the drain of the cascade GaN power device. The gate of the Si MOS tube serves as the gate of the cascade GaN power device. The source of the Si MOS tube serves as the source of the cascade GaN power device. The application has simple structure and can improve EMI characteristics.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a cascade GaN power device. BACKGROUND

[0002] GaN power device has great advantages in high temperature, high pressure and high frequency applications due to its excellent characteristics. The most important advantage of GaN power device is high switching frequency and small switching loss. The former can improve the power density of the module to reduce the volume, and the latter can improve the efficiency of the module.

[0003] GaN power device is divided into enhancement type and depletion type. In circuit application, enhancement type device is needed. There are two ways to realize enhancement type GaN power device, one is p-GaN structure GaN device, which is enhancement type itself, and the other is cascade power device. In the cascade power device, the Si MOS tube controls the turn-on and turn-off of the GaN device. When the Si MOS tube is turned on, the gate voltage of the GaN device rapidly drops below the threshold voltage, and the channel of the GaN device is turned on, and the whole cascade power device starts to conduct. When the Si MOS tube is turned off, the gate voltage of the GaN device exceeds the threshold voltage, and the channel of the GaN device is turned off, and the whole cascade power device starts to turn off. The switching of the GaN device is controlled by the turn-on of the Si MOS tube, and the turn-on and turn-off time is difficult to control, and the electromagnetic interference (EMI) characteristic is poor. Therefore, how to design a simple structure of cascade GaN power device and improve the EMI characteristic is very important. SUMMARY

[0004] The purpose of the present application is to provide a cascade GaN power device with simple structure and improved EMI characteristic.

[0005] To achieve the above purpose, the present application provides the following scheme:

[0006] The present application provides a cascade GaN power device, comprising: a GaN device, a Si MOS tube and a resistor.

[0007] The source of the GaN device is connected with the drain of the Si MOS tube; the gate of the GaN device is connected with one end of the resistor; the other end of the resistor is connected with the source of the Si MOS tube; the drain of the GaN device serves as the drain of the cascade GaN power device; the gate of the Si MOS tube serves as the gate of the cascade GaN power device; and the source of the Si MOS tube serves as the source of the cascade GaN power device.

[0008] Optionally, the GaN device comprises: a substrate, a source electrode, a gate electrode, a drain electrode, a passivation layer and an epitaxial structure; the epitaxial structure comprises: a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer, which are epitaxially grown on the substrate in turn from bottom to top.

[0009] One end of the passivation layer is provided with a source electrode recess; the source electrode recess extends downward from the top surface of the one end of the passivation layer to the GaN channel layer; the source electrode is arranged in the source electrode recess and is connected with a two-dimensional free electron gas formed in the GaN channel layer;

[0010] The other end of the passivation layer is provided with a drain electrode recess; the drain electrode recess extends downward from the top surface of the other end of the passivation layer to the GaN channel layer; the drain electrode is arranged in the drain electrode recess and is connected with a two-dimensional free electron gas formed in the GaN channel layer;

[0011] The gate electrode is arranged on the top surface of the passivation layer and is arranged in a spaced-apart manner with the source electrode.

[0012] Optionally, the GaN device is a depletion-mode GaN device.

[0013] Optionally, the passivation layer is obtained by depositing SiO2, SiN or Al2O3 by PECVD, LPCVD or ALD.

[0014] Optionally, the resistance is composed of a two-dimensional free electron gas formed in the GaN channel layer.

[0015] Optionally, the resistance has a resistance value of 8 ohms.

[0016] Optionally, the cascade GaN power device further comprises: a resistance electrode.

[0017] The resistance electrode is arranged on the GaN device; the resistance is connected with the resistance electrode; and the resistance electrode is connected with the source electrode of a Si MOS tube.

[0018] Optionally, the source electrode, the gate electrode and the drain electrode are all obtained by semiconductor process.

[0019] Optionally, the semiconductor process comprises: photolithography, sputtering and etching.

[0020] Optionally, the epitaxial structure is obtained by epitaxial growth in a MOCVD device.

[0021] According to the specific embodiments provided in the application, the application has the following technical effects:

[0022] The application provides a kind of cascade type GaN power device, the cascade type GaN power device includes: GaN device, SiMOS tube and resistance;The source of GaN device is connected with the drain of Si MOS tube;The gate of GaN device is connected with the one end of resistance;The other end of resistance is connected with the source of Si MOS tube;The drain of GaN device is as the drain of cascade type GaN power device;The gate of SiMOS tube is as the gate of cascade type GaN power device;The source of Si MOS tube is as the source of cascade type GaN power device.Because the cascade structure of GaN device and Si MOS tube is increased only one resistance in the application, so that the structure of GaN power device of the application is simple;Again, due to the existence of resistance, the turn-on time of GaN device can be slowed down, thereby the EMI characteristics can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the related art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, without creative labor, other drawings can also be obtained from these drawings.

[0024] Figure 1 For the circuit structure diagram corresponding to the common-source common-gate structure;

[0025] Figure 2 For the circuit structure diagram corresponding to the cascade type GaN power device;

[0026] Figure 3 For the top view of GaN device;

[0027] Figure 4 For the top view of GaN device along the cutting line a;

[0028] Figure 5 For the corresponding sectional view of GaN device after cutting along the cutting line a;

[0029] Figure 6 For the top view of GaN device along the cutting line b;

[0030] Figure 7 For the corresponding sectional view of GaN device after cutting along the cutting line b;

[0031] Figure 8 For the top view of GaN device along the cutting line c;

[0032] Figure 9 For the corresponding sectional view of GaN device after cutting along the cutting line c.

[0033] Figure reference numerals: GaN device-1, Si MOS transistor-2, gate of Si MOS transistor-G1, source of Si MOS transistor-S1, drain of Si MOS transistor-D1, gate of GaN device-G2, source of GaN device-S2, drain of GaN device-D2, resistor-R. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In practical applications, cascaded power devices utilize Si MOS transistors to control the switching of depletion-mode GaN devices, thereby achieving enhancement mode. In this cascaded structure, the source of the Si MOS transistor is connected to the gate of the depletion-mode GaN device, and the drain of the Si MOS transistor is connected to the source of the depletion-mode GaN device; therefore, it is also called a common-source, common-gate structure. Figure 1 As shown. Because the switching of GaN devices is limited by the turn-on of Si MOS transistors, their turn-on and turn-off times are difficult to control, resulting in poor EMI characteristics.

[0036] To improve EMI characteristics, it is necessary to slow down the turn-on of GaN devices. Based on this, this application proposes a novel cascaded GaN power device. During device fabrication, an AlGaN / GaN heterojunction is used, with a resistor connected in series with the gate of the depletion-mode GaN device. When cascaded with a Si MOSFET, the gate of the depletion-mode GaN device is cascaded with the source of the Si MOSFET through this series resistor. The presence of the resistor slows down the turn-on time of the GaN device, thus improving EMI characteristics. Compared to other EMI-improving cascaded devices, this application has a simpler structure, requiring only a single resistor and no additional components. Therefore, it offers higher area utilization for the subsequent GaN chip and is more suitable for mass production. The GaN chip is an integration of the GaN device, Si MOSFET, and resistor.

[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 2 As shown in the figure, this application provides a cascaded GaN power device, including: GaN device 1, SiMOS transistor 2 and resistor R.

[0039] The source S2 of the GaN device is connected with the drain D1 of the Si MOS tube; the gate G2 of the GaN device is connected with one end of the resistor R; the other end of the resistor R is connected with the source S1 of the Si MOS tube; the drain D2 of the GaN device is used as the drain of the cascade GaN power device; the gate G1 of the Si MOS tube is used as the gate of the cascade GaN power device; and the source S1 of the Si MOS tube is used as the source of the cascade GaN power device.

[0040] The GaN device comprises a substrate, a source, a gate, a drain, a passivation layer and an epitaxial structure; the epitaxial structure comprises a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer which are epitaxially grown on the substrate from bottom to top. The epitaxial structure is obtained by epitaxial growth in a MOCVD device.

[0041] One end of the passivation layer is provided with a source recess; the source recess extends downward from the top surface of the one end of the passivation layer into the GaN channel layer; the source is arranged in the source recess and is connected with the two-dimensional free electron gas formed in the GaN channel layer.

[0042] The other end of the passivation layer is provided with a drain recess; the drain recess extends downward from the top surface of the other end of the passivation layer into the GaN channel layer; the drain is arranged in the drain recess and is connected with the two-dimensional free electron gas formed in the GaN channel layer.

[0043] The gate is arranged on the top surface of the passivation layer and is arranged at a position close to the source and spaced apart from the source.

[0044] The source, the gate and the drain are all obtained by semiconductor process. The semiconductor process comprises photolithography, sputtering and etching.

[0045] In an embodiment, the GaN device 1 is a depletion-mode GaN device; the passivation layer is obtained by depositing SiO2, SiN or Al2O3 by PECVD, LPCVD or ALD; the resistance is composed of the two-dimensional free electron gas formed in the GaN channel layer; and the resistance R has a resistance value of 8 ohms.

[0046] In an embodiment, the cascade GaN power device further comprises a resistance electrode.

[0047] The resistance electrode is arranged on the GaN device 1; the resistance R is connected with the resistance electrode; and the resistance electrode is connected with the source S1 of the Si MOS tube.

[0048] Figure 3is a top view of the GaN device mentioned in the present application, the gate G2 of the GaN device is connected with the gate insertion finger on the GaN chip through the gate lead. The resistance R is formed by the two-dimensional electron gas under the AlGaN / GaN, i.e. the AlGaN barrier layer and the GaN channel layer, and the resistance electrode (R electrode) is also fabricated on the GaN device, which is directly connected with the source of the Si MOS tube when cascaded with the Si MOS tube later. Figure 3 The area circled by the dashed box is the area where the resistance is located. Because the resistance R is formed by the two-dimensional electron gas at the heterojunction of the AlGaN barrier layer and the GaN channel layer, therefore, the three areas of the resistance R, the R electrode, and the gate G2 of the GaN device are non-injection areas, and other areas within the dashed box are injection areas. The injection area refers to the use of ion implantation to destroy the two-dimensional electron gas below, so that the area becomes an insulating area.

[0049] To further illustrate the structure of the GaN device of the present application, the top view and the sectional view of each area of the GaN device are analyzed. Figure 4 is a top view along the dashed line a as the cutting line. When the dashed line a is the cutting line, the source insertion finger, the gate insertion finger, and the drain insertion finger corresponding to the GaN device in the GaN chip are cut. Figure 5 is the sectional view corresponding to the dashed line a, from bottom to top in turn is the substrate, the GaN buffer layer, the GaN channel layer, and the AlGaN barrier layer.

[0050] The formation steps of these structures are: placing the substrate into a metal-organic chemical vapor deposition (MOCVD) device, and epitaxially growing the GaN buffer layer, the GaN channel layer, and the AlGaN barrier layer on the substrate in turn, i.e. forming an epitaxial structure. A passivation layer (the deposition material can be SiO2, SiN, Al2O3, etc.) is deposited above the AlGaN barrier layer, and the deposition method can be plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc. The source, the gate, and the drain are then fabricated by using semiconductor processes such as photolithography, sputtering, and etching.

[0051] Figure 6 is a top view of the GaN device along the dashed line b as the cutting line. The dashed line b is the cutting line along the R electrode, the resistance R, and the gate G2 of the GaN device; Figure 7is a corresponding sectional view taken along the broken line b. The resistance R is connected to the gate G2 of the GaN device via the R electrode (indicated by a broken line in the figure) Figure 7 The resistance R is connected to the gate G2 of the GaN device via the R electrode (indicated by a broken line in the figure)

[0052] For the resistance R, the recommended resistance value is between 3 ohms and 20 ohms, and the typical resistance value is 8 ohms. If the resistance value is too small, the turn-on time is not greatly affected, and the turn-on is still fast, and the EMI performance is poor. If the resistance value is too large, a large stress is formed in the Si MOS tube due to RC delay at the turn-off, and the Si MOS tube avalanche is caused.

[0053] Figure 8 is a plan view of the GaN device taken along the broken line c as a cutting line. The broken line c is a cutting line taken along the gate G2 of the GaN device and the gate lead. Figure 9 is a corresponding sectional view taken along the broken line c. The gate G2 of the GaN device is connected to the gate plug via the gate lead.

[0054] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.

[0055] The principles and implementation manners of the present application are described by using specific examples in the present application. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed. In summary, the content of the present application should not be understood as a limitation.

Claims

1. A cascaded GaN power device, characterized by, The cascade GaN power device comprises a GaN device, a Si MOS tube and a resistance; The source of the GaN device is connected with the drain of the Si MOS tube; the gate of the GaN device is connected with one end of the resistance; the other end of the resistance is connected with the source of the Si MOS tube; the drain of the GaN device serves as the drain of the cascade GaN power device; the gate of the Si MOS tube serves as the gate of the cascade GaN power device; and the source of the Si MOS tube serves as the source of the cascade GaN power device; The resistance is composed of two-dimensional electron gas formed by heterojunction of an AlGaN barrier layer and a GaN channel layer, and the three regions of the resistance, a resistance electrode and the gate of the GaN device are non-injection regions; the injection region refers to a region where the two-dimensional electron gas below is destroyed by ion injection, so that the region becomes an insulating region; The resistance electrode and the gate of the GaN device are connected with the resistance; the other resistance electrode is connected with the source of the Si MOS tube; and the resistance is used to slow down the turn-on time of the GaN device. The resistance has a resistance value of 3-20 ohms.

2. The cascode GaN power device of claim 1, wherein, The GaN device comprises a substrate, a source, a gate, a drain, a passivation layer and an epitaxial structure; the epitaxial structure comprises a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer which are epitaxially grown on the substrate from bottom to top. One end of the passivation layer is provided with a source recess; the source recess extends downward from the top surface of the one end of the passivation layer to the GaN channel layer; the source is arranged in the source recess and connected with the two-dimensional free electron gas formed in the GaN channel layer; The other end of the passivation layer is provided with a drain recess; the drain recess extends downward from the top surface of the other end of the passivation layer to the GaN channel layer; the drain is arranged in the drain recess and connected with the two-dimensional free electron gas formed in the GaN channel layer; The gate is arranged on the top surface of the passivation layer and spaced apart from the source.

3. The cascode GaN power device of claim 1, wherein, The GaN device is a depletion-mode GaN device.

4. The cascode GaN power device of claim 2, wherein, The passivation layer is obtained by depositing SiO2, SiN or Al2O3 by PECVD, LPCVD or ALD.

5. The cascode GaN power device of claim 2, wherein, The resistance is composed of the two-dimensional free electron gas formed in the GaN channel layer.

6. The cascode GaN power device of claim 1, wherein, The resistance has a resistance value of 8 ohms.

7. The cascode GaN power device of claim 2, wherein, The source, the gate and the drain are all obtained by semiconductor process.

8. The cascode GaN power device of claim 7, wherein, The semiconductor process comprises photolithography, sputtering and etching.

9. The cascode GaN power device of claim 2, wherein, The epitaxial structure is obtained by epitaxial growth in a MOCVD device.

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