A method for controlling the surface shape of a cadmium zinc telluride wafer

Abstract

The application discloses a kind of tellurium zinc cadmium wafer surface shape control methods, first need to determine actual process condition under tellurium zinc cadmium wafer damage layer thickness and surface shape with the general change in polishing process process;Combination analysis result, before each tellurium zinc cadmium wafer surface treatment, remove the damage layer of the two sides of tellurium zinc cadmium wafer by chemical etching method;While measuring the surface shape of wafer before chemical polishing, different process parameters are used for chemical polishing in combination with surface shape situation.Chemical etching stress removal damage layer should be the etching solution of specific concentration of chemical etching liquid, and the chemical etching time is determined by the required removal thickness.Chemical polishing solution of chemical polishing process is the etching solution of specific concentration, and the chemical polishing time is determined by the surface shape value of wafer measured before chemical polishing, and the chemical polishing carrier is a specially designed carrier.The application process is simple, reproducible, process controllable, and can be used for surface shape control of tellurium zinc cadmium substrate, with batch capacity.

Description

Technical Field

[0001] This invention belongs to the field of photoelectric detection technology, specifically relating to a method for controlling the surface shape of cadmium zinc telluride wafers. Background Technology

[0002] Mercury cadmium telluride (HgCdTe) focal plane array infrared detectors are currently the most widely used and mature infrared detectors. By adjusting the Cd composition, detection across the entire infrared band can be achieved. The lattice constant of cadmium zinc telluride (CdZnTe) crystals can vary with different zinc contents, enabling high lattice matching with HgCdTe thin films of different detection cutoff wavelengths. CdZnTe has also become the most important epitaxial substrate material for fabricating high-performance HgCdTe infrared detectors.

[0003] To achieve the superior performance of HgCdTe infrared detectors, obtaining CdZnTe wafers with high flatness and low surface damage is fundamental and a prerequisite. The fabrication of CdZnTe wafers typically involves multiple processes, including crystal growth, cutting, grinding, polishing, cleaning, and chemical polishing. During the processing of CdZnTe wafers, surface layer damage is unavoidable, causing processing stress and residual stress, which can lead to deformation of the CdZnTe wafer. Simultaneously, improper chemical polishing can also cause surface edge collapse deformation, severely affecting subsequent processing of the HgCdTe detector.

[0004] In traditional chip manufacturing processes, double-sided grinding and polishing is usually used to avoid wafer deformation caused by residual stress. However, double-sided grinding and polishing has strict requirements on wafer size and shape, and is not suitable for most mainstream CdZnTe wafer manufacturing processes. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for controlling the surface shape of cadmium zinc telluride wafers, which addresses the above-mentioned shortcomings of the existing technology. This method controls the PV value (Peak to Valley), and the process is simple, repeatable, and controllable, making it more suitable for industrial production. Even if there are differences between different processes, it is still applicable. Therefore, the present invention is applicable to most mainstream cadmium zinc telluride wafer fabrication processes.

[0006] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0007] A method for controlling the surface shape of cadmium zinc telluride wafers, the method comprising:

[0008] (1) Determine the general variation of the thickness and surface shape of the damaged layer of cadmium zinc telluride wafers under actual process conditions during the grinding and polishing process;

[0009] (2) Before each grinding or polishing of the zinc zinc cadmium substrate, the stress of the damaged layer on both sides of the zinc zinc cadmium substrate is removed by chemical etching.

[0010] (3) Measure the PV value of the wafer before chemical polishing. Based on the substrate PV value of the wafer, select the appropriate type of chemical polishing solution, concentration of chemical polishing solution and chemical polishing time, and perform chemical polishing with a chemical polishing carrier.

[0011] According to the above scheme, the solutes of the chemical etching solution and the chemical polishing solution are selected from one or more of bromine, hydrobromic acid, hydrogen peroxide, potassium dichromate and nitric acid, and the concentrations are all 0.1% to 10.0%; the solvents include a base solvent and a corresponding solute combination, and the base solvent is selected from one or more of water, methanol, ethanol and ethylene glycol.

[0012] According to the above scheme, the thickness of the damaged layer of the zinc zinc cadmium wafer and the required corrosion time are determined according to the following method:

[0013] (1) Prepare a zinc zinc cadmium substrate (its thickness must be consistent with the thickness of a normal process substrate).

[0014] (2) The stress residual surface of the damaged layer of the zinc zinc cadmium substrate is denoted as surface I, and the other surface is denoted as surface II;

[0015] (3) After grinding and polishing the II surface, measure the PV value of the II surface of the substrate;

[0016] (4) Prepare a chemical etching solution of a specific concentration, immerse the substrate to be etched in the chemical etching solution for etching, take it out after each fixed etching time and measure the PV value of the II side and the substrate thickness until the PV value of the II side no longer changes. The difference between the substrate thickness at this time and the substrate thickness before etching is the thickness of the damaged layer; the time used at this time is the etching time.

[0017] According to the above scheme, the chemical polishing time is determined according to the following method:

[0018] (1) Measure the PV value of the zinc zinc cadmium substrate before chemical polishing, and record it as PV. B The target PV value is denoted as PV. G ;

[0019] (2) The basic chemical polishing time is the shortest chemical polishing time to meet the requirements of the epitaxial substrate, denoted as t. The requirements of the epitaxial substrate include scratches and roughness.

[0020] (3) When PV B ≤PV G The chemical polishing time is t; when PV B >PV G The chemical polishing time is t+a(PV) B -PV G), where a is an empirical constant related to the chemical polishing solution and its concentration, which needs to be confirmed by experiments based on the actual process conditions after selecting other chemical polishing process parameters.

[0021] According to the above scheme, the chemical polishing carrier must adhere to the following design principles:

[0022] (1) The bottom surface of the chemical polishing carrier consists of a wafer groove located at the center of the carrier and a flow channel located around the wafer;

[0023] (2) The flatness of the wafer groove surface should be less than 5μm;

[0024] (3) Let the area of ​​the wafer trench be A1, the area of ​​the flow channel be A2, and the remaining non-trenching area be A3. The area of ​​A2÷(A1+A3) >30% should be satisfied.

[0025] (4) The width of the guide groove should be increased or decreased proportionally as the wafer groove area increases or decreases.

[0026] According to the above scheme, the material of the chemical polishing carrier can resist the corrosion of the chemical polishing liquid; optional materials include polypropylene, polytetrafluoroethylene and polyvinylidene fluoride.

[0027] Compared with the prior art, the advantages of the present invention are as follows:

[0028] (1) The present invention can be improved based on existing practical processes;

[0029] (2) The present invention produces high flatness zinc cadmium telluride wafer material. The process is simple, repeatable, and controllable, making it more suitable for industrial production.

[0030] (3) Even if there are differences between different processes, it is still applicable. Therefore, the present invention is applicable to most mainstream cadmium zinc telluride wafer fabrication processes. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the processing technology for cadmium zinc telluride wafers.

[0032] Figure 2 Model of a specially designed chemical polishing carrier (left) and schematic diagram of the bottom groove (right).

[0033] Figure 3 The PV values ​​of Examples 1, 2, and 3 before chemical polishing are shown.

[0034] Figure 4 The PV values ​​after chemical polishing are for Examples 1, 2, and 3. Detailed Implementation

[0035] The present invention will be further described in detail below with reference to the embodiments, but the content of the present invention is not limited to the following examples.

[0036] Before proceeding with this embodiment, it is necessary to determine the general variation of the damaged layer thickness of the zinc zinc cadmium substrate under actual process conditions, and to determine the composition of the chemical etching solution or chemical polishing solution and the required processing time for each grinding and polishing process.

[0037] The thickness of the damaged layer is determined according to the following method:

[0038] (1) Prepare a zinc zinc cadmium substrate (its thickness must be consistent with the thickness of a normal process substrate).

[0039] (2) The stress residual surface of the damaged layer of the zinc zinc cadmium substrate is denoted as surface I, and the other surface is denoted as surface II;

[0040] (3) After grinding and polishing the II surface, measure the PV value of the II surface of the substrate;

[0041] (4) Prepare a chemical etching solution of a specific concentration, immerse the substrate to be etched in the chemical etching solution for etching, take it out after each fixed etching time and measure the PV value of the II side and the substrate thickness until the PV value of the II side no longer changes. The difference between the substrate thickness at this time and the substrate thickness before etching is the thickness of the damaged layer; the thickness of the damaged layer divided by the etching time is the etching rate.

[0042] like Figure 1 As shown, a method for controlling the surface shape of a cadmium zinc telluride wafer includes the following steps:

[0043] 1) The cadmium zinc telluride wafers cut from single crystal telluride zinc telluride were chemically etched using a 1.5% concentration of bromomethanol for 6 minutes.

[0044] 2) The etched cadmium zinc telluride wafer was fixed onto a silicon wafer with paraffin wax, and side A (the front and back sides of the cadmium zinc telluride wafer are represented by side B and side A, respectively) was polished. After polishing, the paraffin wax was removed, and the cadmium zinc telluride wafer was chemically etched again with a 0.8% concentration of bromomethanol for 6 minutes.

[0045] 3) The etched cadmium zinc telluride wafers are fixed onto silicon wafers with paraffin wax, and the B-side is polished. After processing, the wafers are cut into the required size and cleaned.

[0046] 4) After cleaning, measure the PV value of the B-side of the wafer, then place the wafer into a specially designed chemical polishing carrier (e.g., Figure 2 Chemical polishing was performed on the wafer (as shown in the image) using a 0.3% concentration of bromomethanol as the polishing solution. The chemical polishing time was determined using the following method: The PV value of the zinc-cadmium telluride wafer before chemical polishing was recorded as PV. B The target PV value is denoted as PV.G Let t be the basic chemical polishing time (the shortest time to satisfy the epitaxial index). When PV B <PV G The chemical polishing time is t; when PV B >PV G The chemical polishing time is t+a(PV) B -PV G ), where a is a constant related to the concentration of the chemical polishing solution, confirmed experimentally by actual process conditions. In this embodiment, t is 2 and a is 1.45.

[0047] The cadmium zinc telluride wafer material prepared according to steps 1) to 4) above is used as an example, and the cadmium zinc telluride wafer material without some of the processes is used as comparative example 1, comparative example 2, and comparative example 3. The comparisons are shown in Table 1:

[0048] Table 1. Process details of Examples and Comparisons 1, 2, and 3

[0049]

[0050] like Figure 3 As shown in Table 1, the PV value of the untreated zinc cadmium telluride wafer (Comparative Example 1) is significantly larger (5.6 μm) due to deformation caused by residual stress, resulting in poor flatness. In contrast, the PV values ​​of Examples 1, 2, and 3 after the chemical etching process are all less than 3.0 μm.

[0051] According to step 4) of the present invention, the PV value before chemical polishing in the embodiment is relatively small. B =2.849μm, set the target value PV G =2.5μm, then according to t+a(PV B -PV G The calculated chemical polishing time was 2.5 min.

[0052] like Figure 4 As shown, in the examples, the PV value after chemical polishing is close to the target value, and the PV value in the central part is consistent, indicating good overall flatness. In contrast, in Comparative Examples 1 and 2, even though the PV values ​​in the central part are mostly consistent, the lack of a specialized chemical polishing carrier and control over the chemical polishing time resulted in stronger chemical corrosion at the wafer edges, leading to significant edge collapse. Compared to before chemical polishing, the PV value increased significantly, resulting in poor overall flatness. Comparative Example 3, although using a specialized chemical polishing carrier to suppress edge collapse, did not control the chemical polishing time, resulting in slight edge collapse, a small increase in PV value, and poor overall flatness. In conclusion, the method for preparing a high-flatness cadmium zinc telluride wafer material provided by this invention is feasible.

[0053] The examples described above are merely a subset of examples of the present invention and are not intended to limit the scope of the invention. The scope of protection of the present invention should be defined as the technical solutions described in the claims, including equivalent alternatives to the technical features described in the claims. That is, equivalent substitutions and improvements within this scope are also within the scope of protection of the present invention.

Claims

1. A method for controlling the surface shape of cadmium zinc telluride wafers, characterized in that, Includes the following steps: (1) Determine the general variation of the thickness and surface shape of the damaged layer of cadmium zinc telluride wafers under actual process conditions during the grinding and polishing process; (2) Before each grinding or polishing of the zinc zinc cadmium substrate, the stress of the damaged layer on both sides of the zinc zinc cadmium substrate is removed by chemical etching. (3) Measure the PV value of the wafer before chemical polishing, and select the appropriate type of chemical polishing solution, concentration of chemical polishing solution and chemical polishing time according to the substrate PV value of the wafer, and perform chemical polishing with chemical polishing carrier; The parameters required for the chemical etching process to remove stress from the damaged layer of the zinc zinc cadmium telluride substrate, based on general variations, include the damaged layer thickness, the type and concentration of the chemical etching solution, and the etching time; the parameters required for the chemical polishing process, based on general variations, include the type and concentration of the chemical polishing solution and the chemical polishing time. The chemical polishing time was determined according to the following method: (1) Measure the PV value of the zinc zinc cadmium substrate before chemical polishing, and record it as PV. B The target PV value is denoted as PV. G ; (2) The basic chemical polishing time is the shortest chemical polishing time to meet the requirements of the epitaxial substrate, denoted as t. The requirements of the epitaxial substrate include scratches and roughness. (3) When PV B ≤PV G The chemical polishing time is t; when PV B >PV G The chemical polishing time is t+a(PV) B -PV G ), where a is an empirical constant related to the chemical polishing solution and its concentration, which needs to be confirmed by experiments based on the actual process conditions after selecting other chemical polishing process parameters.

2. The method for controlling the surface shape of a cadmium zinc telluride wafer according to claim 1, characterized in that, The solutes in the chemical etching solution and chemical polishing solution are selected from one or more of bromine, hydrobromic acid, hydrogen peroxide, potassium dichromate and nitric acid; the solvents include a base solvent and a corresponding solute, and the base solvent is selected from one or more of water, methanol, ethanol and ethylene glycol.

3. The method for controlling the surface shape of a cadmium zinc telluride wafer according to claim 1, characterized in that, The thickness of the damaged layer and the required etching time of the zinc-cadmium telluride wafer were determined according to the following method: (1) Prepare a zinc zinc cadmium substrate, the thickness of which is the same as that of a normal process substrate; (2) The stress residual surface of the damaged layer of the zinc zinc cadmium substrate is denoted as surface I, and the other surface is denoted as surface II; (3) After grinding and polishing the II surface, measure the PV value of the II surface of the substrate; (4) Prepare a chemical etching solution, immerse the substrate to be etched in the chemical etching solution for etching, take it out after each fixed etching time and measure the PV value of the II side and the substrate thickness until the PV value of the II side no longer changes. The difference between the substrate thickness at this time and the substrate thickness before etching is the thickness of the damaged layer; the time used at this time is the etching time.

4. The method for controlling the surface shape of a cadmium zinc telluride wafer according to claim 3, characterized in that, The concentrations of the chemical etching solution and the chemical polishing solution are both 0.1% to 10.0%.

5. A method for controlling the surface shape of a cadmium zinc telluride wafer according to any one of claims 1-4, characterized in that, The bottom surface of the chemical polishing carrier comprises a wafer groove at its center and flow channels around the wafer. The flatness of the wafer groove should be less than 5 μm. The area of ​​the wafer groove is denoted as A1, the area of ​​the flow channels is denoted as A2, and the remaining non-groove area is denoted as A3. The area of ​​A2 ÷ (A1 + A3) > 30%. The width of the flow channels should increase or decrease proportionally as the area of ​​the wafer groove increases or decreases.

6. The method for controlling the surface shape of a cadmium zinc telluride wafer according to claim 5, characterized in that, The material of the chemical polishing carrier is resistant to corrosion from the chemical polishing solution.

7. The method for controlling the surface shape of a cadmium zinc telluride wafer according to claim 6, characterized in that, The material of the chemical polishing carrier is selected from polypropylene, polytetrafluoroethylene, and polyvinylidene fluoride, which are resistant to corrosion by the chemical polishing solution.

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