Display device and method for manufacturing display device

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a first base layer; a circuit layer over the first base layer; a silicon substrate over the circuit layer; a light emitting element over the silicon substrate and electrically connected to the circuit layer through an opening defined by the silicon substrate; and a second base layer over the silicon substrate and the light emitting element.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0103973 filed in the Korean Intellectual Property Office on August 9, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device and to a method for manufacturing the display device. Background Art

[0003] In recent years, as interest in information display has increased, research and development of display devices have been ongoing. Summary of the invention

[0004] The present disclosure provides a display device and a method for manufacturing the display device which can reduce manufacturing costs and simplify processes.

[0005] Aspects of the present disclosure are not limited to the above, but other aspects not described herein will be clearly understood by those skilled in the art from the following description.

[0006] According to one or more embodiments, a display device includes: a first base layer; a circuit layer above the first base layer; a silicon substrate above the circuit layer; a light-emitting element above the silicon substrate and electrically connected to the circuit layer through an opening defined by the silicon substrate; and a second base layer above the silicon substrate and the light-emitting element.

[0007] The thickness of the first base layer may be greater than the thickness of the silicon substrate.

[0008] The thickness of the first base layer may be greater than the thickness of the second base layer.

[0009] The second base layer may include a transparent inorganic material.

[0010] The first base layer and the second base layer may include the same material.

[0011] The light emitting element may include: a first semiconductor layer over the silicon substrate; an active layer over the first semiconductor layer; and a second semiconductor layer over the active layer.

[0012] The display device may further include an electrode layer over the second semiconductor layer and covered by the second base layer.

[0013] The display device may further include an electrode layer over the second semiconductor layer and exposed by the second base layer.

[0014] The opening defined by the silicon substrate may expose the first semiconductor layer.

[0015] According to one or more embodiments, a method for manufacturing a display device includes: forming a light-emitting element on a first surface of a silicon substrate; forming a first inorganic layer on the first surface of the silicon substrate and above the light-emitting element; grinding a second surface of the silicon substrate; forming an opening by etching the silicon substrate; forming a circuit layer on the second surface of the silicon substrate and above the light-emitting element; and forming a second inorganic layer above the circuit layer.

[0016] The opening of the silicon substrate may expose the light emitting element.

[0017] The circuit layer can contact the light emitting element through the opening of the silicon substrate.

[0018] The thickness of the silicon substrate may be smaller than the thickness of the second inorganic layer.

[0019] The manufacturing method may further include grinding the first inorganic layer.

[0020] The thickness of the first inorganic layer may be smaller than the thickness of the second inorganic layer.

[0021] The first inorganic layer and the second inorganic layer may include the same material.

[0022] According to one or more embodiments, a method for manufacturing a display device includes: forming a light-emitting element layer above a first silicon substrate; forming a second silicon substrate above the light-emitting element layer; forming an opening by etching the second silicon substrate; forming a circuit layer above the second silicon substrate and the light-emitting element layer; forming an inorganic layer above the circuit layer; removing the first silicon substrate; and forming a light-emitting element by etching the light-emitting element layer.

[0023] The opening of the second silicon substrate may expose the light emitting element layer.

[0024] The circuit layer may contact the light emitting element layer through the opening of the second silicon substrate.

[0025] The thickness of the second silicon substrate may be smaller than the thickness of the inorganic layer.

[0026] Specific details of other embodiments are included in the description and drawings.

[0027] According to the above embodiment, the two surfaces of the silicon substrate can be used to form the light emitting element and the circuit layer, and the light emitting element and the circuit layer can be electrically connected through the opening of the silicon substrate. Therefore, the bonding process for combining the light emitting element and the circuit layer can be omitted, thereby reducing costs and simplifying the process.

[0028] Aspects according to the embodiments are not limited to the above-mentioned contents, and more various aspects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a plan view showing a display device according to one or more embodiments.

[0030] Figure 2 is a circuit diagram of a pixel according to one or more embodiments.

[0031] Figures 3 to 6 is a cross-sectional view of a display device according to one or more embodiments.

[0032] Figures 7 to 17 are cross-sectional views illustrating process steps of a method for manufacturing a display device according to one or more embodiments.

[0033] Figures 18 to 24 are cross-sectional views illustrating process steps of a method for manufacturing a display device according to one or more embodiments.

[0034] Figures 25 to 32 are cross-sectional views illustrating process steps of a method for manufacturing a display device according to one or more embodiments. DETAILED DESCRIPTION

[0035] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and their implementation methods. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0036] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown here. The use of "may (may)", "will" or "may not (will not)" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and alternatives within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are feasible. Each embodiment may be implemented independently of one another or may be implemented together in association.

[0037] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is often provided in the drawings to make the boundaries between adjacent elements clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0038] Here, various embodiments are described with reference to the cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. In this way, changes in the shapes of the diagrams caused by, for example, manufacturing techniques and / or tolerances will be expected. In addition, for the purpose of describing embodiments according to the concept of the present disclosure, the specific structural or functional descriptions disclosed herein are only illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers or regions, but will include deviations in shapes caused by, for example, manufacturing.

[0039] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0040] For ease of explanation, spatially relative terms such as "under", "below", "lower", "under", "below", "above", "upper", "upper", etc. may be used here to describe the relationship between one element or feature and another (some) elements or features as shown in the drawings. It will be understood that in addition to the orientation depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as "under", "under" or "below" other elements or features will subsequently be oriented to be "above" the other elements or features. Therefore, the example terms "under" and "under" can cover both upper and lower orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used here should be interpreted accordingly. Similarly, when a first portion (component) is described as being disposed “on” a second portion (component), this indicates that the first portion (component) is disposed at the upper or lower side of the second portion (component), and is not limited to the upper side of the second portion based on the gravity direction.

[0041] In addition, the phrase "in a plan view" means when viewing the object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing the schematic cross-section taken by vertically cutting the object portion from the side. The term "superimposed" or "overlapping" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "superimposed" may include stacking, facing or facing, extending on ..., covering or partially covering or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The expression "non-superimposed" may include meanings such as "separated from ... "or "offset from ... "or "offset from ... "and any other suitable equivalents as will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although the first object and the second object still face each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0042] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be formed directly on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or may be formed indirectly on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. Additionally, this may collectively refer to direct coupling (connection) or indirect coupling (or connection) and integral coupling (or connection) or non-integral coupling (or connection). For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, etc. When describing an embodiment, unless explicitly described as being directly connected, the expression of connection includes direct connection and indirect connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component, or is on another component, without intermediate components.

[0043] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions such as "between...", "directly between...", "adjacent to..." and "directly adjacent to..." that describe the relationship between components can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0044] For the purposes of this disclosure, expressions such as “at least one of” or “any of” or “one or more of” when preceding (preceding) a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases, when following (preceding) a list of elements, modify the entire list of elements, but do not modify the individual elements in the list.

[0045] It will be understood that, although the terms "first", "second", "third", etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or section described below can be referred to as the second element, component, region, layer or section. Describing an element as a "first" element may not require or imply the presence of a second element or other element. The terms "first", "second", etc. can also be used here to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0046] In the example, the X-axis, Y-axis and / or Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0047] The terms used herein are only for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (kind / person)" are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It will also be understood that when the terms "include" and its variations, "have" and its variations and "include" and its deformations are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0048] When one or more embodiments may be implemented differently, a specific process order may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in a reverse order to the described order.

[0049] As used herein, the terms "substantially", "approximately", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to explain the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. As used herein, "approximately" or "approximately" includes the stated value and means: taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system), within the acceptable deviation range of the specific value as determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0051] Figure 1 is a plan view showing a display device according to one or more embodiments.

[0052] Figure 1 A display device (for example, a display panel PNL provided in the display device) that can use a light emitting element as a light source is shown.

[0053] For ease of description, Figure 1 The structure of the display panel PNL is briefly shown with the display area DA in FIG. 1 as the center. However, according to the present disclosure, at least one driving circuit (for example, at least one of a scan driver and a data driver), a line and / or a pad (or referred to as a "pad") may be further located in the display panel PNL.

[0054] Reference Figure 1, the display panel PNL is defined within a plane defined by an X-axis and a Y-axis, and may include a base layer BSL (or a first base layer BSL1) and pixels PXU located on the base layer BSL. The pixel PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. Hereinafter, when at least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is arbitrarily mentioned, or when two or more types of pixels are collectively referred to, it will be referred to as a "pixel PXL" or "a plurality of pixels PXL".

[0055] The base layer BSL (or the first base layer BSL1) may constitute a base member of the display panel PNL and may be used as a substrate. For example, the base layer BSL may be formed of an inorganic layer. The base layer BSL may include a material selected from silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ), but is not necessarily limited thereto.

[0056] The display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. The pixels PXL may be located in the display area DA. Various lines, pads, and / or built-in circuits connected to the pixels PXL of the display area DA may be located in the non-display area NDA. The pixels PXL may be arranged according to stripes or PENTILE ® PENTILE ® is a registered trademark of Samsung Display Co., Ltd. of South Korea) are regularly arranged. However, the arrangement of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA in various structures and / or manners.

[0057] According to one or more embodiments, two or more types of pixels PXL for emitting light of different colors may be located in the display area DA. For example, a first pixel PXL1 for emitting light of a first color, a second pixel PXL2 for emitting light of a second color, and a third pixel PXL3 for emitting light of a third color may be arranged in the display area DA. At least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 positioned adjacent to each other may constitute one pixel PXU capable of emitting light of various colors. For example, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a sub-pixel for emitting light of a color (e.g., a predetermined color). According to an embodiment, the first pixel PXL1 may be a red pixel for emitting red light, the second pixel PXL2 may be a green pixel for emitting green light, and the third pixel PXL3 may be a blue pixel for emitting blue light, but is not limited thereto.

[0058] In one or more embodiments, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a light emitting element LD for emitting light of the same color as each other, and may include a color conversion layer and / or a color filter layer of different colors located on each of the light emitting elements LD, thereby emitting light of the first color, light of the second color, and light of the third color, respectively. In one or more other embodiments, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may use a light emitting element of the first color, a light emitting element of the second color, and a light emitting element of the third color as a light source, respectively, thereby emitting light of the first color, light of the second color, and light of the third color, respectively. However, the color, type, and / or number of the pixels PXL constituting each pixel PXU are not particularly limited. That is, the color of the light emitted from each pixel PXL may be changed differently.

[0059] The pixel PXL may include at least one light source driven by a control signal (e.g., a predetermined control signal such as a scan signal and / or a data signal) and / or a power source (e.g., a predetermined power source such as a first power source and a second power source). In one or more embodiments, the light source may include an ultra-small light-emitting element having a size of several nanometers to several microns. However, the present disclosure is not necessarily limited thereto, and various types of light-emitting elements may be used as the light source of the pixel PXL.

[0060] In one or more embodiments, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving method of the pixel PXL applicable to the display device are not particularly limited. For example, each pixel PXL may be made of a pixel of a passive or active light-emitting display device having various structures and / or driving methods.

[0061] Figure 2 is a circuit diagram of a pixel according to one or more embodiments.

[0062] Figure 2 The electrical connection relationship between the constituent elements included in the pixel PXL which can be applied to the active display device is shown. However, the types of constituent elements included in the pixel PXL are not necessarily limited thereto.

[0063] According to one or more embodiments, Figure 2 The pixel PXL shown in FIG. 1 may be arranged in Figure 1 Any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 in the display panel PNL of the display panel PNL. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have structures substantially the same as or similar to each other.

[0064] Reference Figure 2 Each pixel PXL may include a light emitting unit EMU that generates light having brightness corresponding to a data signal. In addition, the pixel PXL may further include a pixel circuit PXC for driving the light emitting unit EMU.

[0065] According to one or more embodiments, the light emitting unit EMU may include at least one light emitting element LD electrically connected between a first power line PL1 and a second power line PL2, the first power line PL1 is applied with a voltage of a first driving power source VDD, and the second power line PL2 is applied with a voltage of a second driving power source VSS. For example, the light emitting unit EMU may include a first electrode EL1 connected to the first driving power source VDD through a pixel circuit PXC and the first power line PL1, a second electrode EL2 connected to the second driving power source VSS through a second power line PL2, and a light emitting element LD connected between the first electrode EL1 and the second electrode EL2. In one or more embodiments, the first electrode EL1 may be an anode, and the second electrode EL2 may be a cathode.

[0066] The light emitting element LD may include one end connected to the first driving power source VDD and the other end connected to the second driving power source VSS. In an embodiment, one end of the light emitting element LD may be integrally provided with the first electrode EL1 to be connected to the first electrode EL1, and the other end of the light emitting element LD may be integrally provided with the second electrode EL2 to be connected to the second electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials from each other. In this case, during the light emitting period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to be greater than or equal to the threshold voltage of the light emitting element LD.

[0067] The light emitting element LD may constitute an effective light source of the light emitting unit EMU. The light emitting element LD may emit light having a brightness corresponding to the driving current supplied by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to the grayscale value of the corresponding frame data to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may flow through the light emitting element LD. Therefore, while the light emitting element LD emits light having a brightness corresponding to the driving current, the light emitting unit EMU may emit light.

[0068] The pixel circuit PXC may be connected to a scan line (e.g., an i-th scan line Si) and a data line (e.g., a j-th data line Dj) of the pixel PXL. For example, when the pixel PXL is located in the i-th row (i is a positive integer) and the j-th column (j is a positive integer) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. According to one or more embodiments, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to the same Figure 2 The corresponding embodiments.

[0069] A first terminal of the first transistor T1 (driving transistor) may be connected to a first driving power source VDD, and a second terminal thereof may be electrically connected to the light emitting element LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may control the amount of driving current supplied to the light emitting element LD in response to a voltage of the first node N1.

[0070] A first terminal of a second transistor T2 (e.g., a switch transistor) may be connected to the j-th data line Dj, and a second terminal thereof may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 may be different terminals. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode. A gate electrode of the second transistor T2 may be connected to the i-th scan line Si.

[0071] When a scan signal of a voltage that can turn on the second transistor T2 is supplied from the i-th scan line Si, the second transistor T2 can be turned on and can electrically connect the j-th data line Dj and the first node N1. The data signal of the corresponding frame can be supplied to the data line Dj, so the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be charged in the storage capacitor Cst.

[0072] The storage capacitor Cst may charge a voltage corresponding to the data signal supplied to the first node N1 and may maintain the charged voltage until a data signal of a next frame is supplied.

[0073] exist Figure 2 , it is shown that the pixel circuit PXC includes a second transistor T2 for transmitting a data signal to the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a driving current corresponding to the data signal to the light emitting element LD, but the present disclosure is not limited thereto, and the structure of the pixel circuit PXC may be changed differently. For example, the pixel circuit PXC may further include at least one transistor element (such as a transistor element for compensating for a threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the light emitting time of the light emitting element LD, etc.) or other circuit elements (such as a boost capacitor for increasing the voltage of the first node N1, etc.).

[0074] Figures 3 to 6 is a cross-sectional view of a display device according to one or more embodiments.

[0075] Reference Figure 3 and Figure 4 The circuit layer PCL may be located on the first base layer BSL1. The first base layer BSL1 may be formed of an inorganic layer. The first base layer BSL1 may include a silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ), but is not necessarily limited thereto. The first base layer BSL1 may be formed to have a thickness of several hundred micrometers, but is not necessarily limited thereto.

[0076] The circuit layer PCL may include a pixel circuit ( Figure 2 For example, the circuit layer PCL may be formed of CMOS which is a combination of NMOS and PMOS, but is not necessarily limited thereto.

[0077] The silicon substrate SW may be located on the circuit layer PCL. The silicon substrate SW may include a single crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. The thickness of the silicon substrate SW may be thinner than that of the first base layer BSL1. For example, the silicon substrate SW may be formed to have a thickness of several micrometers, but is not necessarily limited thereto.

[0078] The silicon substrate SW may include / define an opening OP. The opening OP of the silicon substrate SW may expose the light emitting element LD (or the first semiconductor layer 11). The circuit layer PCL may be electrically connected to the light emitting element LD (or the first semiconductor layer 11) through the opening OP of the silicon substrate SW. The circuit layer PCL may directly contact the light emitting element LD (or the first semiconductor layer 11) through the opening OP of the silicon substrate SW.

[0079] The light emitting element LD may be located on the silicon substrate SW. In one or more embodiments, the light emitting element LD may be a structure manufactured by stacking or growing on the silicon substrate SW, and may be directly located on the silicon substrate SW. The light emitting element LD may be arranged on the silicon substrate SW in a shape extending from the silicon substrate SW in a third direction (Z-axis direction). The light emitting element LD may be a light emitting diode (LED) manufactured in an ultra-small size having a diameter and / or length of several nanometers to several micrometers. However, the present disclosure is not necessarily limited thereto, and the size of the light emitting element LD may be changed differently to meet the requirements (or design conditions) of the lighting device or display device to which the light emitting element LD is applied.

[0080] Each of the light emitting elements LD may include a first semiconductor layer 11 , an active layer 12 , and / or a second semiconductor layer 13 .

[0081] The first semiconductor layer 11 may be a semiconductor layer of a first conductivity type. For example, the first semiconductor layer 11 may include a p-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, and AlN, and may include a p-type semiconductor layer doped with a first conductive dopant such as Mg. However, the material constituting the first semiconductor layer 11 is not limited thereto, and various other materials may constitute the first semiconductor layer 11.

[0082] The active layer 12 may be located between the first semiconductor layer 11 and the second semiconductor layer 13. The active layer 12 may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but is not limited thereto. The active layer 12 may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and various other materials may constitute the active layer 12.

[0083] When a threshold voltage or higher voltage is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light while electron-hole pairs are recombined in the active layer 12. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source for various light emitting elements including pixels of a display device.

[0084] The second semiconductor layer 13 may be located on the active layer 12, and may include a semiconductor layer of a different type from the first semiconductor layer 11. The second semiconductor layer 13 may include an n-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, and AlN, and may include an n-type semiconductor layer doped with a second conductive dopant such as Si, Ge, Sn, etc. However, the material constituting the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various materials.

[0085] The insulating film INF may be disposed on the surface of the light emitting element LD. The insulating film INF may at least partially surround the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13. For example, the insulating film INF may be partially located on the side surface of the light emitting element LD. The insulating film INF may expose one surface of the first semiconductor layer 11 and / or one surface of the second semiconductor layer 13 of the light emitting element LD. The insulating film INF may reduce or prevent the possibility of an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film INF may improve the lifespan and luminous efficiency of the light emitting element LD by reducing or minimizing surface defects of the light emitting element LD.

[0086] The insulating film INF may include a silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ) at least one of the following.

[0087] The electrode layer ELT may be located on the light emitting element LD and / or the insulating film INF. The electrode layer ELT may be located on the second semiconductor layer 13 of the light emitting element LD exposed by the insulating film INF. The electrode layer ELT may be electrically connected to the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may directly contact the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF.

[0088] The electrode layer ELT may include a transparent metal or a transparent metal oxide. For example, the electrode layer ELT may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but is not limited thereto. In this way, when the electrode layer ELT is made of a transparent metal or a transparent metal oxide, light generated in the active layer 12 of the light emitting element LD may pass through the electrode layer ELT and may be emitted to the outside of the light emitting element LD.

[0089] According to one or more embodiments, the reflective layer RF may also be located on the electrode layer ELT. The reflective layer RF may be located on the side surface of the light emitting element LD and / or the side surface of the electrode layer ELT, and may expose the upper surface of the light emitting element LD and / or the upper surface of the electrode layer ELT. The reflective layer RF may reflect the light emitted from the light emitting element LD and guide it in a third direction (e.g., the Z-axis direction) (i.e., in the front direction of the display panel PNL), thereby improving the light output efficiency. The material of the reflective layer RF is not particularly limited, and may include various reflective materials.

[0090] The second base layer BSL2 may be located on the light emitting element LD, the electrode layer ELT and / or the reflective layer RF. Figure 3 As shown in , the second base layer BSL2 can be arranged between the light emitting elements LD and on the light emitting elements LD. For example, the second base layer BSL2 can cover the electrode layer ELT and / or the reflective layer RF. The second base layer BSL2 can be located on the reflective layer RF positioned between the light emitting elements LD. The second base layer BSL2 can be directly located on the reflective layer RF positioned between the light emitting elements LD, but is not necessarily limited thereto. The second base layer BSL2 can be located on the upper surface of the electrode layer ELT exposed by the reflective layer RF. The second base layer BSL2 can be directly located on the upper surface of the electrode layer ELT exposed by the reflective layer RF, but is not necessarily limited thereto.

[0091] The thickness of the second base layer BSL2 may be thinner than that of the first base layer BSL1. For example, the second base layer BSL2 may be formed to have a thickness of about several micrometers, but is not necessarily limited thereto. Here, the thickness of the second base layer BSL2 may refer to a distance from the upper surface of the light emitting element LD (or the electrode layer ELT) to the upper surface of the second base layer BSL2.

[0092] like Figure 4 As shown in , the second base layer BSL2 may be disposed between the light emitting elements LD. For example, the second base layer BSL2 may cover the reflective layer RF located between the light emitting elements LD. The second base layer BSL2 may be directly located on the reflective layer RF located between the light emitting elements LD. The second base layer BSL2 may expose the electrode layer ELT exposed by the reflective layer RF.

[0093] The second base layer BSL2 may be formed of an inorganic layer. For example, the second base layer BSL2 may include a transparent inorganic material. Thus, when the second base layer BSL2 is made of a transparent inorganic material, light generated in the active layer 12 of the light emitting element LD may pass through the electrode layer ELT and may be emitted to the outside of the light emitting element LD. The second base layer BSL2 may include a material selected from silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ) at least one of the above, but not necessarily limited thereto. The second base layer BSL2 may include the same material as the above-mentioned first base layer BSL1, but not necessarily limited thereto.

[0094] According to the above, the light emitting element LD and the circuit layer PCL can be formed using the two surfaces of the silicon substrate SW. The light emitting element LD and the circuit layer PCL can be electrically connected through the opening OP of the silicon substrate SW. Therefore, the bonding process for combining the light emitting element LD and the circuit layer PCL can be omitted, thereby reducing costs and simplifying the process.

[0095] Reference Figure 5 The circuit layer PCL may be located on the base layer BSL. The base layer BSL may be formed of an inorganic layer. The base layer BSL may include a material selected from silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ) at least one of, but not necessarily limited thereto. The base layer BSL may be formed to have a thickness of several hundred micrometers, but not necessarily limited thereto.

[0096] The circuit layer PCL may include a pixel circuit ( Figure 2 For example, the circuit layer PCL may be formed of CMOS which is a combination of NMOS and PMOS, but is not necessarily limited thereto.

[0097] The silicon substrate SW may be located on the circuit layer PCL. The silicon substrate SW may include a single crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. The thickness of the silicon substrate SW may be thinner than the thickness of the base layer BSL. For example, the silicon substrate SW may be formed to have a thickness of several micrometers, but is not necessarily limited thereto.

[0098] The silicon substrate SW may include / define an opening OP. The opening OP of the silicon substrate SW may expose the circuit layer PCL. The light emitting element LD may be located on the silicon substrate SW. In one or more embodiments, the light emitting element LD may be a structure manufactured by stacking or growing on the silicon substrate SW, and may be directly located on the silicon substrate SW. The light emitting element LD may be provided on the silicon substrate SW in a shape extending from the silicon substrate SW in a third direction (Z-axis direction). Figure 3 and Figure 4 A detailed description of the light emitting element LD is described, and thus repeated contents will be omitted.

[0099] The insulating film INF may be disposed on the surface of the light emitting element LD. The insulating film INF may at least partially surround the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13. For example, the insulating film INF may be located on the side surface of the light emitting element LD. The insulating film INF may expose one surface of the first semiconductor layer 11 and / or one surface of the second semiconductor layer 13 of the light emitting element LD. The insulating film INF may reduce or prevent the possibility of an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film INF may improve the lifespan and light emitting efficiency of the light emitting element LD by reducing or minimizing surface defects of the light emitting element LD.

[0100] The insulating film INF may include a silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ) at least one of the following.

[0101] The electrode layer ELT may be located on the light emitting element LD and / or the insulating film INF. The electrode layer ELT may be located on the second semiconductor layer 13 of the light emitting element LD exposed by the insulating film INF. The electrode layer ELT may be electrically connected to the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may directly contact the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may be electrically connected to the circuit layer PCL through the opening OP of the silicon substrate SW. The electrode layer ELT may directly contact the circuit layer PCL through the opening OP of the silicon substrate SW.

[0102] The electrode layer ELT may include a transparent metal or a transparent metal oxide. For example, the electrode layer ELT may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but is not limited thereto. In this way, when the electrode layer ELT is made of a transparent metal or a transparent metal oxide, light generated in the active layer 12 of the light emitting element LD may pass through the electrode layer ELT and may be emitted to the outside of the light emitting element LD.

[0103] According to one or more embodiments, the reflective layer RF may also be located on the electrode layer ELT. The reflective layer RF may be located on the side surface of the light emitting element LD and / or the side surface of the electrode layer ELT, and may expose the upper surface of the light emitting element LD and / or the upper surface of the electrode layer ELT. The reflective layer RF may reflect the light emitted from the light emitting element LD and guide it in a third direction (e.g., the Z-axis direction) (i.e., in the front direction of the display panel PNL), thereby improving the light output efficiency. The material of the reflective layer RF is not particularly limited, and may include various reflective materials.

[0104] According to the above, the light emitting element LD and the circuit layer PCL can be formed using the two surfaces of the silicon substrate SW, and the light emitting element LD and the circuit layer PCL can be electrically connected through the opening OP of the silicon substrate SW. Therefore, as described above, the bonding process for combining the light emitting element LD and the circuit layer PCL can be omitted, thereby reducing costs and simplifying the process.

[0105] Reference Figure 6 The circuit layer PCL may be located on the base layer BSL. The base layer BSL may be formed of an inorganic layer. The base layer BSL may include a material selected from silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x) and titanium oxide (TiO x ) at least one of, but not necessarily limited thereto. The base layer BSL may be formed to have a thickness of several hundred micrometers, but not necessarily limited thereto.

[0106] The circuit layer PCL may include a pixel circuit ( Figure 2 For example, the circuit layer PCL may be formed of CMOS which is a combination of NMOS and PMOS, but is not necessarily limited thereto.

[0107] The silicon substrate SW may be located on the circuit layer PCL. The silicon substrate SW may include a single crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. The thickness of the silicon substrate SW may be thinner than the thickness of the base layer BSL. For example, the silicon substrate SW may be formed to have a thickness of several micrometers, but is not necessarily limited thereto.

[0108] The silicon substrate SW may include / define an opening OP. The opening OP of the silicon substrate SW may expose the light emitting element LD (or the first semiconductor layer 11). The circuit layer PCL may be electrically connected to the light emitting element LD (or the first semiconductor layer 11) through the opening OP of the silicon substrate SW. The circuit layer PCL may directly contact the light emitting element LD (or the first semiconductor layer 11) through the opening OP of the silicon substrate SW.

[0109] The light emitting element LD may be located on the silicon substrate SW. In one or more embodiments, the light emitting element LD may be a structure manufactured by stacking or growing on the silicon substrate SW, and may be directly located on the silicon substrate SW. The light emitting element LD may be provided on the silicon substrate SW in a shape extending from the silicon substrate SW in a third direction (Z-axis direction). Figure 3 and Figure 4 A detailed description of the light emitting element LD is described, and thus repeated contents will be omitted.

[0110] The insulating film INF may be disposed on the surface of the light emitting element LD. The insulating film INF may at least partially surround the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13. For example, the insulating film INF may be located on the side surface of the light emitting element LD. The insulating film INF may expose one surface of the first semiconductor layer 11 and / or one surface of the second semiconductor layer 13 of the light emitting element LD. The insulating film INF may reduce or prevent the possibility of an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film INF may improve the lifespan and light emitting efficiency of the light emitting element LD by reducing or minimizing surface defects of the light emitting element LD.

[0111] The insulating film INF may include a silicon oxide (SiO x )、Silicon Nitride(SiNx ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ) at least one of the following.

[0112] The electrode layer ELT may be located on the light emitting element LD and / or the insulating film INF. The electrode layer ELT may be located on the second semiconductor layer 13 of the light emitting element LD exposed by the insulating film INF. The electrode layer ELT may be electrically connected to the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may directly contact the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may include a transparent metal or a transparent metal oxide. For example, the electrode layer ELT may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but is not limited thereto. In this way, when the electrode layer ELT is made of a transparent metal or a transparent metal oxide, light generated in the active layer 12 of the light emitting element LD may pass through the electrode layer ELT and may be emitted to the outside of the light emitting element LD.

[0113] According to one or more embodiments, the reflective layer RF may also be located on the electrode layer ELT. The reflective layer RF may be located on the side surface of the light emitting element LD and / or the side surface of the electrode layer ELT, and may expose the upper surface of the light emitting element LD and / or the upper surface of the electrode layer ELT. The reflective layer RF may reflect the light emitted from the light emitting element LD and guide it in a third direction (e.g., the Z-axis direction) (i.e., in the front direction of the display panel PNL), thereby improving the light output efficiency. The material of the reflective layer RF is not particularly limited, and may include various reflective materials.

[0114] According to the above, the light emitting element LD and the circuit layer PCL can be formed using the two surfaces of the silicon substrate SW, and the light emitting element LD and the circuit layer PCL can be electrically connected through the opening OP of the silicon substrate SW. Therefore, as described above, the bonding process for combining the light emitting element LD and the circuit layer PCL can be omitted, thereby reducing costs and simplifying the process.

[0115] Subsequently, a method for manufacturing the display device according to the above-described embodiment will be described.

[0116] Figures 7 to 17 are cross-sectional views illustrating process steps of a method for manufacturing a display device according to one or more embodiments. Figures 7 to 17 It is used to show Figure 3and Figure 4 A cross-sectional view of a method for manufacturing a display device is briefly shown, and detailed symbols are omitted for ease of description.

[0117] Reference Figure 7 First, a light emitting element layer (a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13) is formed on a first surface S1 of a silicon substrate SW. The silicon substrate SW may include a single crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be sequentially formed along a third direction (Z-axis direction) on the first surface S1 of the silicon substrate SW. The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by growing a seed crystal by an epitaxial method. According to one or more embodiments, the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not necessarily limited thereto, and the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by various methods such as electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual thermal evaporation, sputtering, and the like. Since reference has been made to Figure 3 and Figure 4 The first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are described, and thus redundant description will be omitted.

[0118] Reference Figure 8 , and then the light emitting element layers (e.g., the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) are etched to form the light emitting element LD on the first surface S1 of the silicon substrate SW. The etching process of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 is performed by dry etching, wet etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc., but is not necessarily limited thereto.

[0119] Reference Fig. 9 , and then an insulating film INF, an electrode layer ELT, and / or a reflective layer RF are formed on the light emitting element LD. The insulating film INF may be partially formed on the side surface of the light emitting element LD. For example, the insulating film INF may be formed on the entire surface of the silicon substrate SW, and then the insulating film INF may be partially removed to expose the upper surface of the light emitting element LD.

[0120] The electrode layer ELT may be formed on the light emitting element LD and the insulating film INF. The electrode layer ELT may be formed on the second semiconductor layer 13 of the light emitting element LD exposed by the insulating film INF. The electrode layer ELT may directly contact the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may be formed of a transparent metal or a transparent metal oxide. For example, the electrode layer ELT may be formed using at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but is not necessarily limited thereto.

[0121] According to one or more embodiments, a reflective layer RF may also be formed on the electrode layer ELT. The reflective layer RF may be partially formed on the side surface of the light emitting element LD and / or the side surface of the electrode layer ELT. For example, the reflective layer RF may be formed on the entire surface of the silicon substrate SW, and then the reflective layer RF may be partially removed to expose the upper surface of the light emitting element LD and / or the upper surface of the electrode layer ELT. The material of the reflective layer RF is not particularly limited, and may be formed of various reflective materials.

[0122] Reference Fig.10 A first inorganic layer IL1 may be formed on the first surface S1 of the silicon substrate SW and on the light emitting element LD. The first inorganic layer IL1 may cover the first surface S1 of the silicon substrate SW and may cover the insulating film INF, the electrode layer ELT and / or the reflective layer RF on the light emitting element LD.

[0123] The first inorganic layer IL1 may include a silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ), but is not necessarily limited thereto. The first inorganic layer IL1 may be formed to have a thickness of several hundred micrometers, but is not necessarily limited thereto.

[0124] Reference Fig.11 and Fig.12 , and then the silicon substrate SW and the first inorganic layer IL1 are reversed, and the second surface S2 of the silicon substrate SW is ground. The thickness of the silicon substrate SW may be ground to be thinner than the thickness of the first inorganic layer IL1. The silicon substrate SW may be formed to have a thickness of several micrometers, but is not necessarily limited thereto.

[0125] Reference Fig.13Then, the silicon substrate SW is etched to form an opening OP. The opening OP of the silicon substrate SW may expose the light emitting element LD (or the first semiconductor layer 11).

[0126] Reference Fig.14 Then, a circuit layer PCL and a second inorganic layer IL2 are formed on the light emitting element LD and the second surface S2 of the silicon substrate SW.

[0127] The circuit layer PCL may include a pixel circuit ( Figure 2 The circuit layer PCL may be formed of a transistor of a PXC in the silicon substrate SW. For example, the circuit layer PCL may be formed of CMOS which is a combination of NMOS and PMOS, but is not necessarily limited thereto. The circuit layer PCL may be electrically connected to the light emitting element LD (or the first semiconductor layer 11) through the opening OP of the silicon substrate SW. The circuit layer PCL may directly contact the light emitting element LD (or the first semiconductor layer 11) through the opening OP of the silicon substrate SW.

[0128] The second inorganic layer IL2 may include a silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ), but not necessarily limited thereto. In one or more embodiments, the second inorganic layer IL2 may be formed of the same material as the first inorganic layer IL1 described above, but not necessarily limited thereto. The second inorganic layer IL2 may be formed to have a thickness of about several hundred micrometers, but not necessarily limited thereto. The thickness of the second inorganic layer IL2 may be formed to be thicker than the thickness of the silicon substrate SW.

[0129] Reference Fig.15 and Fig.16 , and then the first inorganic layer IL1 and the second inorganic layer IL2 are reversed, and the first inorganic layer IL1 is ground. The thickness of the first inorganic layer IL1 may be ground to be thinner than the thickness of the second inorganic layer IL2. The first inorganic layer IL1 may be formed to have a thickness of several micrometers, but is not necessarily limited thereto. Here, the thickness of the first inorganic layer IL1 may refer to a distance from the upper surface of the light emitting element LD (or the electrode layer ELT) to the upper surface of the first inorganic layer IL1.

[0130] The first inorganic layer IL1 may be formed between the light emitting elements LD and on the light emitting elements LD. For example, the first inorganic layer IL1 may cover the electrode layer ELT and / or the reflective layer RF. The first inorganic layer IL1 may be formed directly on the reflective layer RF located between the light emitting elements LD. The first inorganic layer IL1 may be formed directly on the upper surface of the electrode layer ELT exposed by the reflective layer RF. Fig.16 The first inorganic layer IL1 may be Figure 3 The second base layer BSL2 corresponds to, Fig.16 The second inorganic layer IL2 may be Figure 3 Corresponding to the first base layer BSL1.

[0131] Reference Fig.17 In the step of grinding the first inorganic layer IL1, the electrode layer ELT may be partially exposed. For example, the first inorganic layer IL1 may expose the electrode layer ELT exposed by the reflective layer RF. The first inorganic layer IL1 may be disposed between the light emitting elements LD. For example, the first inorganic layer IL1 may cover the reflective layer RF. The first inorganic layer IL1 may be formed directly on the reflective layer RF located between the light emitting elements LD. Fig.17 The first inorganic layer IL1 may be Figure 4 The second base layer BSL2 corresponds to, Fig.17 The second inorganic layer IL2 may be Figure 4 Corresponding to the first base layer BSL1.

[0132] According to the above, the light emitting element LD and the circuit layer PCL can be formed using both surfaces of the silicon substrate SW, and the light emitting element LD and the circuit layer PCL can be electrically connected through the opening OP of the silicon substrate SW. Therefore, as described above, the bonding process for combining the light emitting element LD and the circuit layer PCL can be omitted, thereby reducing costs and simplifying the process.

[0133] Hereinafter, one or more other embodiments will be described. In the following embodiments, the same components as those described above will be denoted by the same reference numerals, and redundant descriptions will be omitted or simplified.

[0134] Figures 18 to 24 are cross-sectional views illustrating process steps of a method for manufacturing a display device according to one or more embodiments. Figures 18 to 24 It is used to show Figure 5 A cross-sectional view of a method for manufacturing a display device is briefly shown, and detailed symbols are omitted for convenience of description.

[0135] Reference Fig.18First, a circuit layer PCL is formed on the second surface S2 of the silicon substrate SW. The silicon substrate SW may include a single crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. The circuit layer PCL may include a pixel circuit ( Figure 2 For example, the circuit layer PCL may be formed of CMOS which is a combination of NMOS and PMOS, but is not necessarily limited thereto.

[0136] Reference Fig.19 Then, an inorganic layer IL is formed on the second surface S2 of the silicon substrate SW and the circuit layer PCL. The inorganic layer IL may include a silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ), but is not necessarily limited thereto. The inorganic layer IL may be formed to have a thickness of several hundred micrometers, but is not necessarily limited thereto.

[0137] Reference Fig. 20 and Fig.21 , and then the silicon substrate SW and the inorganic layer IL are reversed, and the first surface S1 of the silicon substrate SW is ground. The thickness of the silicon substrate SW may be ground to be thinner than the thickness of the inorganic layer IL. The silicon substrate SW may be formed to have a thickness of several micrometers, but is not necessarily limited thereto.

[0138] Reference Fig. 22 , and then a light emitting element layer (a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13) is formed on the first surface S1 of the silicon substrate SW. The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be sequentially formed along a third direction (Z-axis direction) on the first surface S1 of the silicon substrate SW. The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by growing a seed crystal by an epitaxial method. According to one or more embodiments, the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not necessarily limited thereto, and the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by various methods such as electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual thermal evaporation, sputtering, and the like. Since reference has been made to Figure 5The first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are described, and thus redundant description will be omitted.

[0139] Reference Fig.23 , and then the light emitting element layer (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13) is etched to form the light emitting element LD. The etching process of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 is performed by dry etching, wet etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc., but is not necessarily limited thereto. While etching the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, an opening OP may be formed in the silicon substrate SW. The opening OP of the silicon substrate SW may expose the circuit layer PCL.

[0140] Reference Fig.24 , and then an insulating film INF, an electrode layer ELT, and / or a reflective layer RF are formed on the light emitting element LD. The insulating film INF may be partially formed on the side surface of the light emitting element LD. For example, after the insulating film INF is formed on the entire surface of the silicon substrate SW, the insulating film INF may be partially removed so that the circuit layer PCL exposed by the upper surface of the light emitting element LD and the opening OP of the silicon substrate SW may be exposed.

[0141] The electrode layer ELT may be formed on the light emitting element LD, the insulating film INF, and the circuit layer PCL. The electrode layer ELT may be formed on the second semiconductor layer 13 of the light emitting element LD exposed by the insulating film INF. The electrode layer ELT may directly contact the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may be formed on the circuit layer PCL exposed by the opening OP of the silicon substrate SW. The electrode layer ELT may directly contact the circuit layer PCL exposed through the opening OP of the silicon substrate SW.

[0142] The electrode layer ELT may be formed of a transparent metal or a transparent metal oxide. For example, the electrode layer ELT may be formed using at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but is not necessarily limited thereto.

[0143] According to one or more embodiments, a reflective layer RF may also be formed on the electrode layer ELT. The reflective layer RF may be partially formed on the side surface of the light emitting element LD and / or the side surface of the electrode layer ELT. For example, the reflective layer RF may be formed on the entire surface of the silicon substrate SW, and then the reflective layer RF may be partially removed to expose the upper surface of the light emitting element LD and / or the upper surface of the electrode layer ELT. The material of the reflective layer RF is not particularly limited, and may be formed of various reflective materials. Fig.24 The inorganic layer IL can be Figure 5Corresponding to the base layer BSL.

[0144] According to the above, the light emitting element LD and the circuit layer PCL can be formed using both surfaces of the silicon substrate SW, and the light emitting element LD and the circuit layer PCL can be electrically connected through the opening OP of the silicon substrate SW. Therefore, as described above, the bonding process for combining the light emitting element LD and the circuit layer PCL can be omitted, thereby reducing costs and simplifying the process.

[0145] Figures 25 to 32 are cross-sectional views illustrating process steps of a method for manufacturing a display device according to one or more embodiments. Figures 25 to 32 It is used to show Figure 6 A cross-sectional view of a method for manufacturing a display device is briefly shown, and detailed symbols are omitted for convenience of description.

[0146] Reference Fig.25 , a light emitting element layer (a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13) is formed on the first silicon substrate SW1. The first silicon substrate SW1 may include a single crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. The thickness of the first silicon substrate SW1 may be formed to have a thickness of several hundred micrometers, but is not necessarily limited thereto.

[0147] The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by growing a seed by an epitaxial method. According to one or more embodiments, the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not necessarily limited thereto, and the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be formed by various methods such as electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual thermal evaporation, sputtering, etc. Since reference has been made to Figure 6 The first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are described, and thus redundant description will be omitted.

[0148] Reference Fig.26 , and then a second silicon substrate SW2 is formed on the light emitting element layer (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13). The second silicon substrate SW2 may be directly formed on the first semiconductor layer 11. The second silicon substrate SW2 may include a single crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. The thickness of the second silicon substrate SW2 may be thinner than that of the first silicon substrate SW1. For example, the second silicon substrate SW2 may be formed to have a thickness of several micrometers, but is not necessarily limited thereto.

[0149] Reference Fig. 27Then, the second silicon substrate SW2 is etched to form an opening OP. The opening OP of the second silicon substrate SW2 may expose the first semiconductor layer 11 of the light emitting element layer.

[0150] Reference Fig.28 Then, a circuit layer PCL is formed on the second silicon substrate SW2 and the light emitting element layer (the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13). The circuit layer PCL may include a pixel circuit ( Figure 2 The circuit layer PCL may be formed of a transistor of a PXC in the second silicon substrate SW2. For example, the circuit layer PCL may be formed of CMOS which is a combination of NMOS and PMOS, but is not necessarily limited thereto. The circuit layer PCL may be electrically connected to the first semiconductor layer 11 of the light emitting element layer through the opening OP of the second silicon substrate SW2. The circuit layer PCL may directly contact the first semiconductor layer 11 of the light emitting element layer through the opening OP of the second silicon substrate SW2.

[0151] Reference Fig.29 Then, an inorganic layer IL is formed on the circuit layer PCL. The inorganic layer IL may include a silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x )、HfO x ) and titanium oxide (TiO x ) at least one of the above, but not necessarily limited thereto. The thickness of the inorganic layer IL may be formed to be thicker than the thickness of the second silicon substrate SW2. The inorganic layer IL may be formed to have a thickness of several hundred micrometers, but not necessarily limited thereto.

[0152] Reference Fig.30 and Fig.31 , and then the first silicon substrate SW1 and the inorganic layer IL are reversed. Next, the first silicon substrate SW1 is removed, and the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are etched to form the light emitting element LD. The etching process of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 includes dry etching, wet etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc., but is not necessarily limited thereto.

[0153] Reference Fig.32, and then an insulating film INF, an electrode layer ELT, and / or a reflective layer RF are formed on the light emitting element LD. The insulating film INF may be partially formed on the side surface of the light emitting element LD. For example, the insulating film INF may be formed on the entire surface of the silicon substrate SW, and then the insulating film INF may be partially removed to expose the upper surface of the light emitting element LD.

[0154] The electrode layer ELT may be formed on the light emitting element LD and the insulating film INF. The electrode layer ELT may be formed on the second semiconductor layer 13 of the light emitting element LD exposed by the insulating film INF. The electrode layer ELT may directly contact the light emitting element LD (or the second semiconductor layer 13) exposed by the insulating film INF. The electrode layer ELT may be formed of a transparent metal or a transparent metal oxide. For example, the electrode layer ELT may be formed using at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but is not necessarily limited thereto.

[0155] According to one or more embodiments, a reflective layer RF may also be formed on the electrode layer ELT. The reflective layer RF may be partially formed on the side surface of the light emitting element LD and / or the side surface of the electrode layer ELT. For example, the reflective layer RF may be formed on the entire surface of the silicon substrate SW, and then the reflective layer RF may be partially removed to expose the upper surface of the light emitting element LD and / or the upper surface of the electrode layer ELT. The material of the reflective layer RF is not particularly limited and may be formed of various reflective materials. Fig.32 The inorganic layer IL can be Figure 6 The base layer BSL corresponds to, Fig.32 The second silicon substrate SW2 can be Figure 6 Corresponding to the silicon substrate SW.

[0156] According to the above, the light emitting element LD and the circuit layer PCL can be formed using both surfaces of the second silicon substrate SW2, and the light emitting element LD and the circuit layer PCL can be electrically connected through the opening OP of the second silicon substrate SW2. Therefore, as described above, the bonding process for combining the light emitting element LD and the circuit layer PCL can be omitted, thereby reducing costs and simplifying the process.

[0157] It will be appreciated by those skilled in the art that the disclosure may be implemented in a modified form without departing from the essential features described above. Therefore, the disclosed method will be considered to be illustrative rather than restrictive. The scope of the disclosure is described by the claims rather than the preceding description, and all differences within the equivalent range are to be interpreted as included in the disclosure.

Claims

1. A display device, comprising: a first substrate layer; A circuit layer, above the first substrate layer; a silicon substrate, above the circuit layer; a light emitting element, which is above the silicon substrate and electrically connected to the circuit layer through an opening defined by the silicon substrate; as well as The second base layer is above the silicon substrate and the light emitting element.

2. The display device according to claim 1, wherein: The thickness of the first base layer is greater than the thickness of the silicon substrate.

3. The display device according to claim 2, wherein: The thickness of the first base layer is greater than the thickness of the second base layer.

4. The display device according to claim 3, wherein: The second base layer includes a transparent inorganic material.

5. The display device according to claim 4, wherein: The first base layer and the second base layer include the same material.

6. The display device according to claim 5, wherein: The light emitting element comprises: A first semiconductor layer, above the silicon substrate; an active layer above the first semiconductor layer; and A second semiconductor layer is above the active layer. 7 . The display device according to claim 6 , further comprising an electrode layer above the second semiconductor layer and covered by the second base layer. 8 . The display device according to claim 6 , further comprising an electrode layer over the second semiconductor layer and exposed by the second base layer.

9. The display device according to claim 8, wherein: An opening defined by the silicon substrate exposes the first semiconductor layer.

10. A method for manufacturing a display device, the method comprising the following steps: forming a light emitting element over the first surface of the silicon substrate; forming a first inorganic layer on the first surface of the silicon substrate and above the light emitting element; grinding the second surface of the silicon substrate; forming an opening by etching the silicon substrate; forming a circuit layer on the second surface of the silicon substrate and above the light emitting element; as well as A second inorganic layer is formed over the circuit layer.

11. The manufacturing method according to claim 10, wherein: The opening of the silicon substrate exposes the light emitting element.

12. The manufacturing method according to claim 11, wherein: The circuit layer contacts the light emitting element through the opening of the silicon substrate.

13. The manufacturing method according to claim 12, wherein: The thickness of the silicon substrate is smaller than the thickness of the second inorganic layer. The manufacturing method according to claim 13 , further comprising grinding the first inorganic layer.

15. The manufacturing method according to claim 14, wherein: The thickness of the first inorganic layer is smaller than the thickness of the second inorganic layer.

16. The manufacturing method according to claim 15, wherein: The first inorganic layer and the second inorganic layer include the same material.

17. A method for manufacturing a display device, the method comprising the following steps: forming a light emitting element layer on the first silicon substrate; forming a second silicon substrate above the light emitting element layer; forming an opening by etching the second silicon substrate; forming a circuit layer above the second silicon substrate and the light emitting element layer; forming an inorganic layer above the circuit layer; removing the first silicon substrate; as well as The light emitting element is formed by etching the light emitting element layer.

18. The manufacturing method according to claim 17, wherein: The opening of the second silicon substrate exposes the light emitting element layer.

19. The manufacturing method according to claim 18, wherein: The circuit layer contacts the light emitting element layer through the opening of the second silicon substrate.

20. The manufacturing method according to claim 19, wherein: The thickness of the second silicon substrate is smaller than the thickness of the inorganic layer.

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