Display device

Abstract

The invention relates to a display device. The display device includes: a substrate including a display area and a peripheral area disposed outside the display area; a light emitting element disposed on the display area of the substrate; and an encapsulation member disposed on the light emitting element and including at least one inorganic encapsulation layer and at least one organic encapsulation layer. One of the at least one organic encapsulation layer includes surface enhanced Raman scattering (SERS) active nanoparticles.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the priority benefit of Korean Patent Application No. 10-2023-0110134 filed in the Korean Intellectual Property Office on August 22, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the same. Background Art

[0004] The display device visually displays data. Recently, the display device has been used in more various ways. In addition, the display device has become thinner and lighter in weight, and therefore, the scope of its use has been widened.

[0005] For example, in the case of an organic light-emitting display device, in order to manufacture a thin and light display device, the emission area may be encapsulated by using a thin film encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer instead of an encapsulation substrate formed of a glass material.

[0006] The organic encapsulation layer may planarize an upper surface of a display region of the organic light-emitting display device by covering the display region, and may prevent cracks from occurring in the inorganic encapsulation layer by covering a portion of a peripheral region of the organic light-emitting display device.

[0007] In the case where the organic encapsulation layer is coated by the inkjet method, it may be necessary to check whether the material of the organic encapsulation layer discharged by the inkjet process has been disposed at a target position of the peripheral area. Summary of the invention

[0008] One or more embodiments allow monitoring of the placement position of the organic encapsulation layer via Raman detection by adding surface-enhanced Raman scattering (SERS) active nanoparticles to the organic encapsulation layer. However, this technical feature is an example, and one or more embodiments are not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0010] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area disposed outside the display area; a light emitting element disposed on the display area of ​​the substrate; and an encapsulation member disposed on the light emitting element and including at least one inorganic encapsulation layer and at least one organic encapsulation layer. One of the at least one organic encapsulation layers includes surface enhanced Raman scattering (SERS) active nanoparticles.

[0011] The SERS active nanoparticles may be metal nanoparticles having a Raman labeling compound adsorbed on the surface thereof, wherein a size of each of the metal nanoparticles may be at least about 1 nm but not greater than about 20 nm.

[0012] The metal nanoparticles may include gold (Au), silver (Ag), or copper (Cu).

[0013] The Raman marker compound may include an aromatic ring.

[0014] The Raman labeling compound may include at least one of thiophenol, 4-mercaptophenol, 4-nitrothiophenol, 4-aminothiophenol, 4-mercaptophenylboronic acid, 4-mercaptobenzoic acid, and pyridine-4-thiol.

[0015] The content of the SERS active nanoparticles may be greater than 0 wt % but not greater than 5 wt % based on the total weight of one organic encapsulation layer.

[0016] The viscosity of an organic encapsulation layer may be in the range of 1 cP to 50 cP.

[0017] The at least one inorganic encapsulating layer may include a first inorganic encapsulating layer and a second inorganic encapsulating layer. An organic encapsulating layer may be disposed on the first inorganic encapsulating layer, and the second inorganic encapsulating layer may be disposed on the organic encapsulating layer.

[0018] The display device may further include a dam portion disposed on the peripheral area, wherein the first inorganic encapsulating layer and the second inorganic encapsulating layer may contact each other on the dam portion.

[0019] The display device may further include a valley portion disposed on the peripheral area and between the dam portion and the display area, wherein one organic encapsulation layer may overlap the valley portion.

[0020] The light emitting element may include a pixel electrode, an emission layer on the pixel electrode, and an opposing electrode on the emission layer.

[0021] According to one or more embodiments, a display device includes: a substrate; a light-emitting element disposed on the substrate and including a pixel electrode, an emission layer on the pixel electrode, and a relative electrode on the emission layer; and an encapsulation member disposed on the light-emitting element. The encapsulation member includes a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer. The organic encapsulation layer includes surface enhanced Raman scattering (SERS) active nanoparticles, in which the metal nanoparticles are surface-treated with a Raman labeling compound, wherein the Raman labeling compound includes an aromatic ring.

[0022] The size of each of the metal nanoparticles may be 20 nm or less.

[0023] The metal nanoparticles may include gold (Au), silver (Ag), or copper (Cu).

[0024] The Raman labeling compound may include at least one of thiophenol, 4-mercaptophenol, 4-nitrothiophenol, 4-aminothiophenol, 4-mercaptophenylboronic acid, 4-mercaptobenzoic acid, and pyridine-4-thiol.

[0025] The content of the SERS active nanoparticles may be greater than 0 wt % but not greater than 5 wt % based on the total weight of the organic encapsulation layer.

[0026] According to one or more embodiments, a method for manufacturing a display device includes: forming a first inorganic encapsulation layer on a light emitting element; forming an organic encapsulation layer on the first inorganic encapsulation layer, the organic encapsulation layer including surface enhanced Raman scattering (SERS) active nanoparticles; testing a setting position of the organic encapsulation layer by using Raman spectroscopy; and forming a second inorganic encapsulation layer on the organic encapsulation layer.

[0027] The SERS active nanoparticles may be formed by surface-treating metal nanoparticles with a Raman labeling compound, wherein a size of each of the metal nanoparticles may be 20 nm or less.

[0028] The Raman marker compound may include an aromatic ring.

[0029] The Raman labeling compound may include at least one of thiophenol, 4-mercaptophenol, 4-nitrothiophenol, 4-aminothiophenol, 4-mercaptophenylboronic acid, 4-mercaptobenzoic acid, and pyridine-4-thiol. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of certain embodiments of the present disclosure will become more apparent from the following description made in conjunction with the accompanying drawings.

[0031] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0032] Figure 2A and Figure 2B is an example of an equivalent circuit diagram of a sub-pixel included in a display device according to an embodiment.

[0033] Figure 3 is a display device according to an embodiment Figure 1 A schematic cross-sectional view taken along line II'.

[0034] Figure 4 is a schematic enlarged view of the organic encapsulation layer of the display device.

[0035] Figure 5 is a flowchart of a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0036] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout the text. In this regard, the embodiments presented may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or a variation thereof.

[0037] Since the specification allows for various variations and multiple embodiments, specific embodiments will be shown in the drawings and described in the written description. The effects and features of one or more embodiments and methods for achieving the effects and features will become apparent from the following detailed description of one or more embodiments in conjunction with the drawings. However, the embodiments presented may have different forms and should not be construed as being limited to the descriptions set forth herein.

[0038] One or more embodiments will be described in more detail below with reference to the accompanying drawings. Regardless of the figure number, the same reference numerals are given to those elements that are the same or correspond to each other, and redundant descriptions thereof are omitted.

[0039] Although terms such as "first" and "second" may be used to describe various elements, these elements are not necessarily limited to the above terms. The above terms are only used to distinguish one element from another element.

[0040] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0041] It will be understood that the terms “comprising,” “including,” and “having” as used herein specify the presence of the stated features or elements, but do not preclude the addition of one or more other features or elements.

[0042] It will also be understood that when a layer, region or element is referred to as being on another layer, region or element, it can be directly on the other layer, region or element or indirectly on the other layer, region or element. For example, intervening layers, regions or elements may be present.

[0043] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0044] When the embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order.

[0045] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0046] Figure 1 is a schematic plan view of a display device 1 according to an embodiment.

[0047] refer to Figure 1 , the display device 1 may display an image. The display device 1 may include a display area DA and a peripheral area PA. In an embodiment, the display area DA and the peripheral area PA may be defined on the substrate 100. In other words, the substrate 100 may include the display area DA and the peripheral area PA.

[0048] The display device 1 can provide an image through a plurality of sub-pixels P disposed in the display area DA. Each of the sub-pixels P of the display device 1 is an area capable of emitting light of a specific color, and the display device 1 can display an image by using the light emitted by the plurality of sub-pixels P. For example, the sub-pixel P can emit red light, green light, or blue light. As another example, the sub-pixel P can emit red light, green light, blue light, or white light.

[0049] The peripheral area PA may be disposed outside the display area DA. For example, the peripheral area PA may at least partially surround the display area DA. In an embodiment, the peripheral area PA may completely surround the display area DA. The peripheral area PA, which is an area where the sub-pixels P are not disposed, may be an area where no image is provided.

[0050] The first dam portion DP1 and the second dam portion DP2 may be disposed in the peripheral area PA. The first dam portion DP1 and the second dam portion DP2 may surround the display area DA. The first dam portion DP1 and the second dam portion DP2 may be separated from each other. Although in the present embodiment, the number of dam portions surrounding the display area DA is shown as two, one or more embodiments are not limited thereto, and the number may be changed to one or more than two. The first dam portion DP1 and the second dam portion DP2 may be used as a packaging member 300 (see FIG. 1 ) when formed by an inkjet process. Figure 3 ) (eg, included in the encapsulation member 300) of the organic encapsulation layer 320 (see Figure 3 ) is a dam that blocks the organic material from flowing toward the edge of the substrate 100, and thus can prevent the edge tail from being formed by the organic encapsulation layer 320 at the edge of the substrate 100.

[0051] like Figure 1 As shown, the display area DA may have a polygonal shape including a quadrilateral shape. For example, the display area DA may have a rectangular shape with a horizontal length greater than a vertical length, a rectangular shape with a horizontal length less than a vertical length, or a square shape. Alternatively, the display area DA may have various shapes such as an elliptical shape or a circular shape.

[0052] The display device 1 may be included in a mobile phone, a television, a billboard, a monitor, a tablet personal computer, a notebook computer, or the like.

[0053] The display device 1 is a device for displaying images and may be a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a field emission display, a surface conduction electron emission display, a plasma display, a cathode ray display or the like.

[0054] Figure 2A and Figure 2B is an example of an equivalent circuit diagram of a sub-pixel P included in the display device 1 according to the embodiment.

[0055] Specific reference Figure 2A Each sub-pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL and a light emitting element LED connected to the pixel circuit PC. For example, the light emitting element LED may be an organic light emitting diode.

[0056] The pixel circuit PC may include a driving thin film transistor T1 , a switching thin film transistor T2 , and a storage capacitor Cst.

[0057] The switching thin film transistor T2 is configured to transfer the data signal Dm input through the data line DL to the driving thin film transistor T1 according to the scan signal Sn input through the scan line SL.

[0058] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a first power voltage ELVDD (or referred to as a driving voltage) supplied to the driving voltage line PL.

[0059] The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can be configured to control the driving current flowing from the driving voltage line PL through the light emitting element LED in response to the voltage value stored in the storage capacitor Cst. The light emitting element LED can emit light with a specific brightness according to the driving current.

[0060] Although Figure 2A A case where the pixel circuit PC includes two thin film transistors T1 , T2 and one storage capacitor Cst is illustrated, but one or more embodiments are not limited thereto.

[0061] refer to Figure 2B The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, a first emission control thin film transistor T5, a second emission control thin film transistor T6 and a second initialization thin film transistor T7.

[0062] Although Figure 2B It is shown that each sub-pixel P includes a signal line (e.g., a first scan line SLn, a second scan line SLn-1, an emission control line EL, and a data line DL), an initialization voltage line VL, and a drive voltage line PL, but one or more embodiments are not limited thereto. In an embodiment, at least one of the signal lines (e.g., a first scan line SLn, a second scan line SLn-1, an emission control line EL, and a data line DL) and / or the initialization voltage line VL may be shared with adjacent sub-pixels P.

[0063] The drain electrode of the driving thin film transistor T1 may be electrically connected to the light emitting element LED via the second emission control thin film transistor T6. The driving thin film transistor T1 is configured to receive the data signal Dm according to the switching operation of the switching thin film transistor T2 and to supply a driving current to the light emitting element LED.

[0064] The gate electrode of the switching thin film transistor T2 is connected to the first scan line SLn, and the source electrode thereof is connected to the data line DL. The drain electrode of the switching thin film transistor T2 may be connected to the source electrode of the driving thin film transistor T1, and may also be connected to the driving voltage line PL via the first emission control thin film transistor T5.

[0065] The switching thin film transistor T2 is turned on according to the first scan signal Sn received through the first scan line SLn, and is configured to perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode of the driving thin film transistor T1 .

[0066] The gate electrode of the compensation thin film transistor T3 may be connected to the first scan line SLn. The source electrode of the compensation thin film transistor T3 may be connected to the drain electrode of the driving thin film transistor T1, and may also be connected to the pixel electrode of the light emitting element LED via the second emission control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 may be connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on according to the first scan signal Sn received through the first scan line SLn, and is configured to make the driving thin film transistor T1 diode-connected by connecting the gate electrode and the drain electrode of the driving thin film transistor T1 to each other.

[0067] The gate electrode of the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 (previous scan line). The drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 may be connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1, and may be configured to perform an initialization operation to initialize the voltage of the gate electrode of the driving thin film transistor T1 by transmitting the initialization voltage VINT to the gate electrode of the driving thin film transistor T1.

[0068] The gate electrode of the first emission control thin film transistor T5 may be connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 may be connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 may be connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0069] The gate electrode of the second emission control thin film transistor T6 may be connected to the emission control line EL. The source electrode of the second emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second emission control thin film transistor T6 may be electrically connected to the pixel electrode of the light emitting element LED. The first emission control thin film transistor T5 and the second emission control thin film transistor T6 are simultaneously turned on according to the emission control signal En received through the emission control line EL, and thereby, the first power voltage ELVDD is transmitted to the light emitting element LED, and the driving current flows through the light emitting element LED.

[0070] The gate electrode of the second initialization thin film transistor T7 may be connected to the second scan line SLn-1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the light emitting element LED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1, and may be configured to initialize the pixel electrode of the light emitting element LED.

[0071] Although Figure 2B The case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the second scan line SLn-1 is shown, but one or more embodiments are not limited thereto. In an embodiment, the first initialization thin film transistor T4 may be connected to the second scan line SLn-1 (which is the previous scan line) to operate according to the second scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line) to operate according to the signal transmitted to the corresponding scan line.

[0072] The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. One electrode of the storage capacitor Cst may be connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0073] The opposite electrode (eg, cathode) of the light emitting element LED receives the second power voltage ELVSS (or referred to as a common power voltage). The light emitting element LED receives the driving current from the driving thin film transistor T1 and emits light.

[0074] The pixel circuit PC is not limited to the reference Figure 2A and Figure 2B The numbers of thin film transistors and storage capacitors and circuit designs are described, and the numbers of thin film transistors and storage capacitors and circuit designs may be variously changed.

[0075] Figure 3 is a display device 1 according to an embodiment. Figure 1 A schematic cross-sectional view taken along line II'. Figure 4 is a schematic enlarged view of the organic encapsulation layer 320 of the display device 1 .

[0076] See also Figure 3 and Figure 4The display device 1 may include a substrate 100, a pixel circuit layer PCL, a light emitting element LED, and a packaging member 300. The display device 1 may further include a valley portion VP, a first dam portion DP1, and a second dam portion DP2. The valley portion VP may include a first valley portion VP1 and a second valley portion VP2.

[0077] The substrate 100 may include glass. In an embodiment, the substrate 100 may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. In an embodiment, the substrate 100 may have a multilayer structure including a base layer and a barrier layer (not shown), the base layer including the above polymer resin. Hereinafter, a case where the substrate 100 includes glass will be mainly described in detail.

[0078] The pixel circuit layer PCL may be disposed on the substrate 100. The pixel circuit layer PCL may include a buffer layer 101, a first inorganic insulating layer 103, a second inorganic insulating layer 105, a third inorganic insulating layer 107, a pixel circuit PC including a first thin film transistor TFT1, a second thin film transistor TFT2, and a third thin film transistor TFT3.

[0079] The pixel circuit PC may include at least one first thin film transistor TFT1 and a storage capacitor Cst. The first thin film transistor TFT1 may be disposed in the display area DA. The first thin film transistor TFT1 may be, but is not limited to, reference Figure 2A The driving thin film transistor T1 of the pixel circuit PC described or the reference Figure 2B The second emission control thin film transistor T6 of the pixel circuit PC is described.

[0080] The second thin film transistor TFT2 and the third thin film transistor TFT3 may be disposed in the peripheral area PA. Each of the second thin film transistor TFT2 and the third thin film transistor TFT3 may be a thin film transistor of a drive circuit. For example, the second thin film transistor TFT2 may be a thin film transistor of a scan drive circuit, and the third thin film transistor TFT3 may be a thin film transistor of an emission control drive circuit.

[0081] Each of the first thin film transistor TFT1 , the second thin film transistor TFT2 , and the third thin film transistor TFT3 may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0082] The buffer layer 101 may be disposed on the substrate 100 to planarize the upper surface of the substrate 100 and block the inflow of impurities from the substrate 100. The buffer layer 101 may include an inorganic insulating material such as silicon oxide (SiO x), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). The buffer layer 101 may include a single layer or a multi-layer structure including the above inorganic insulating materials.

[0083] The semiconductor layer Act may be disposed on the buffer layer 101. The semiconductor layer Act may include an oxide semiconductor and / or a silicon semiconductor. When the semiconductor layer Act includes an oxide semiconductor, the semiconductor layer Act may include, for example, an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the semiconductor layer Act may be an InSnZnO (ITZO) semiconductor layer, an InGaZnO (IGZO) semiconductor layer, and the like. When the semiconductor layer Act includes a silicon semiconductor, the semiconductor layer Act may include, for example, amorphous silicon or low temperature polycrystalline silicon (LTPS).

[0084] The gate electrode GE may be disposed on the semiconductor layer Act, and the first inorganic insulating layer 103 is between the gate electrode GE and the semiconductor layer Act. The gate electrode GE may overlap with the channel region of the semiconductor layer Act. The gate electrode GE may include a low-resistance metal material. For example, the gate electrode GE may have a single-layer or multi-layer structure, which includes one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu). The gate electrode GE may be connected to a gate line configured to apply an electrical signal to the gate electrode GE.

[0085] The first inorganic insulating layer 103 may be disposed on the buffer layer 101. The first inorganic insulating layer 103 may be disposed between the semiconductor layer Act and the gate electrode GE. The first inorganic insulating layer 103 may include, for example, an inorganic insulating material such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may include ZnO and / or ZnO 2 ).

[0086] The second inorganic insulating layer 105 may be disposed on the first inorganic insulating layer 103. The second inorganic insulating layer 105 may cover the gate electrode GE. In a similar manner to the first inorganic insulating layer 103, the second inorganic insulating layer 105 may include an inorganic insulating material such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may include ZnO and / or ZnO 2 ).

[0087] The upper electrode CE2 of the storage capacitor Cst may be disposed on the second inorganic insulating layer 105. In an embodiment, the upper electrode CE2 may overlap the gate electrode GE. In this regard, the gate electrode GE and the upper electrode CE2 overlapping each other with the second inorganic insulating layer 105 therebetween may constitute the storage capacitor Cst. That is, the gate electrode GE may serve as the lower electrode CE1 of the storage capacitor Cst. As described above, the storage capacitor Cst and the first thin film transistor TFT1 may overlap each other. In an embodiment, the storage capacitor Cst and the first thin film transistor TFT1 may not overlap each other.

[0088] The third inorganic insulating layer 107 may be disposed on the second inorganic insulating layer 105. The third inorganic insulating layer 107 may cover the upper electrode CE2. The third inorganic insulating layer 107 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which may include ZnO and / or ZnO 2 ). The third inorganic insulating layer 107 may have a single-layer or multi-layer structure including the above inorganic insulating materials.

[0089] The source electrode SE and the drain electrode DE may each be disposed on the third inorganic insulating layer 107. The source electrode SE and the drain electrode DE may be electrically connected to the semiconductor layer Act through contact holes formed in the first inorganic insulating layer 103, the second inorganic insulating layer 105, and the third inorganic insulating layer 107. The source electrode SE and the drain electrode DE may include a highly conductive material. At least one of the source electrode SE and the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a multilayer or single-layer structure including the above materials. In an embodiment, at least one of the source electrode SE and the drain electrode DE may have a multilayer structure of Ti / Al / Ti.

[0090] In an embodiment, the display device 1 may further include a power voltage line 11 in the pixel circuit layer PCL. The power voltage line 11 may be disposed on the third inorganic insulating layer 107. The power voltage line 11 may be disposed in the peripheral area PA. The power voltage line 11 may be a wiring configured to transmit various signals and / or voltages to be provided to the pixel circuit PC. For example, the power voltage line 11 may be a wiring configured to provide a power supply to the sub-pixel P (see Figure 2A and Figure 2B ) each provides a second power voltage ELVSS (see Figure 2A and Figure 2B )'s public power voltage line.

[0091] The display device 1 may further include at least one planarization layer disposed on the pixel circuit layer PCL. In an embodiment, the display device 1 may include a first planarization layer 110 and a second planarization layer 120 disposed on the pixel circuit layer PCL.

[0092] The first planarization layer 110 may be disposed on the pixel circuit layer PCL. The first planarization layer 110 may cover the pixel circuit PC. The first planarization layer 110 may be disposed on the third inorganic insulating layer 107. The first planarization layer 110 may be disposed on the source electrode SE and the drain electrode DE. The first planarization layer 110 may be disposed on the first thin film transistor TFT1 in the display area DA, and may be disposed on the second thin film transistor TFT2 and the third thin film transistor TFT3 in the peripheral area PA. The second planarization layer 120 may be disposed on the first planarization layer 110 while covering the connection electrode CM described below.

[0093] Each of the first planarization layer 110 and the second planarization layer 120 may include an organic insulating layer. Each of the first planarization layer 110 and the second planarization layer 120 may include an organic material. Each of the first planarization layer 110 and the second planarization layer 120 may include an organic insulating material, such as a conventional commercial polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol-based group, an acrylic acid-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a mixture thereof. The first planarization layer 110 and the second planarization layer 120 may planarize the upper surface of the pixel circuit PC, thereby planarizing the surface on which the light-emitting element LED will be positioned.

[0094] In an embodiment, the display device 1 may further include a connection electrode CM disposed on the first planarization layer 110 in the display area DA. The connection electrode CM may be disposed between the first planarization layer 110 and the second planarization layer 120. The connection electrode CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer or single-layer structure including the above materials. In an embodiment, the connection electrode CM may have a multilayer structure of Ti / Al / Ti. The second planarization layer 120 may be disposed on the first planarization layer 110 while covering the connection electrode CM.

[0095] The light emitting element LED may be arranged above the pixel circuit layer PCL in the display area DA. The light emitting element LED may be electrically connected to the pixel circuit PC, and the pixel circuit PC is arranged between the substrate 100 and the light emitting element LED in a direction perpendicular to the substrate 100 (e.g., direction z). The light emitting element LED may be arranged on the second planarization layer 120. The light emitting element LED may emit red light, green light, or blue light, or may emit red light, green light, blue light, or white light. The stacked structure of the pixel electrode 210, the intermediate layer 220, and the relative electrode 230 may constitute a light emitting element LED.

[0096] The light emitting element LED may be an organic light emitting diode including an organic emission layer. Alternatively, the light emitting element LED may be an inorganic light emitting diode including an inorganic emission layer. The light emitting diode may have a micrometer-scale size or a nanometer-scale size. For example, the light emitting diode may be a micro light emitting diode. Alternatively, the light emitting diode may be a nanorod light emitting diode. The nanorod light emitting diode may include gallium nitride (GaN). In an embodiment, a color conversion layer may be provided on the nanorod light emitting diode. The color conversion layer may include quantum dots. Alternatively, the light emitting diode may be a quantum dot light emitting diode including a quantum dot emission layer.

[0097] The pixel electrode 210 may be disposed on the second planarization layer 120. The pixel electrode 210 may be electrically connected to the connection electrode CM through a contact hole in the second planarization layer 120. In an embodiment, the pixel electrode 210 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In an embodiment, the pixel electrode 210 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In an embodiment, the pixel electrode 210 may also include a reflective layer including ITO, IZO, ZnO or In on / below the above reflective layer. 2 O 3 For example, the pixel electrode 210 may have a multi-layer structure of ITO / Ag / ITO.

[0098] A pixel defining layer 130 may be provided on the pixel electrode 210, and includes an opening 130OP that exposes a central portion of the pixel electrode 210. The pixel defining layer 130 may include an organic insulating material and / or an inorganic insulating material. One opening 130OP in the pixel defining layer 130 may correspond to one light emitting element LED, and may define one emission region. The region exposed by the opening 130OP of the pixel defining layer 130 may be defined as an emission region.

[0099] The intermediate layer 220 may be disposed on the pixel defining layer 130. The intermediate layer 220 may include an emission layer disposed in the opening 130OP of the pixel defining layer 130. The emission layer may include a high molecular weight or low molecular weight organic material that emits light of a specific color.

[0100] although Figure 3 Not shown, the first functional layer and the second functional layer may be further disposed below the emission layer and on the emission layer, respectively. For example, the first functional layer may include a hole transport layer (HTL), or may include an HTL and a hole injection layer (HIL). The second functional layer is an element disposed on the emission layer and is optional. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). In an embodiment, similar to the relative electrode 230 described below, the first functional layer and / or the second functional layer may be a common layer that completely covers the substrate 100.

[0101] The opposing electrode 230 may include a conductive material having a low work function. For example, the opposing electrode 230 may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. Alternatively, the opposing electrode 230 may also include a conductive material such as ITO, IZO, ZnO or In on the (semi) transparent layer including the above materials. 2 O 3 layer.

[0102] In some embodiments, a capping layer (not shown) may also be disposed on the counter electrode 230. The capping layer may include lithium fluoride (LiF), other inorganic materials, and / or organic materials.

[0103] The encapsulation member 300 may cover the light emitting element LED. The encapsulation member 300 may be disposed on the opposite electrode 230. In an embodiment, the encapsulation member 300 may be disposed in the display area DA. In an embodiment, the encapsulation member 300 includes at least one inorganic encapsulation layer and at least one organic encapsulation layer, and in an embodiment, the encapsulation member 300 is shown as including a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 sequentially stacked on each other.

[0104] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be completely disposed in the display area DA and the peripheral area PA. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be separated from each other in the display area DA. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be separated from each other in some areas of the peripheral area PA, and may contact each other in other areas. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contact each other over the first dam portion DP1 and / or the second dam portion DP2.

[0105] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include an inorganic material. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include, for example, aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO x , which may include ZnO and / or ZnO 2 ), silicon oxide (SiO 2 ), silicon nitride (SiN x ) and silicon oxynitride (SiON) or more inorganic materials.

[0106] The organic encapsulation layer 320 may be disposed in the display area DA. The organic encapsulation layer 320 may extend from the display area DA to the peripheral area PA. The organic encapsulation layer 320 may fill the first valley VP1 and the second valley VP2. The organic encapsulation layer 320 may overlap the first valley VP1 and the second valley VP2. The organic encapsulation layer 320 may not overlap at least the first dam portion DP1. The organic encapsulation layer 320 may not overlap the second dam portion DP2. The organic encapsulation layer 320 may extend from the display area DA to the inner side of the second dam portion DP2. The organic encapsulation layer 320 may overlap the second thin film transistor TFT2 and / or the third thin film transistor TFT3.

[0107] In the case of forming the organic encapsulation layer 320 using an inkjet method, when the inkjet discharge position of the organic material is biased toward one end of the substrate 100, the material of the organic layer may overflow to the outside of the first dam portion DP1. When the inkjet discharge position of the organic material is biased toward the display area DA, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be cracked due to lack of organic material filled in the peripheral area PA. Accordingly, it is necessary to monitor whether the organic material is accurately discharged to the target position and safely set on the target position, and it is necessary to adjust the discharge position of the organic material.

[0108] like Figure 4 As shown, the organic encapsulation layer 320 may include an organic material 321 and surface enhanced Raman scattering (SERS) active nanoparticles 400. The organic encapsulation layer 320 may be formed by adding the SERS active nanoparticles 400 to the organic material 321. The viscosity of the organic encapsulation layer 320 may be in the range of about 1 cP to about 50 cP. Because the organic encapsulation layer 320 includes the SERS active nanoparticles 400, it is possible to test whether the organic encapsulation layer 320 is disposed at a target position by Raman spectroscopy or Raman detection after the organic encapsulation layer 320 is formed. Because the layer disposed below the organic encapsulation layer 320 (e.g., the pixel defining layer 130, the opposite electrode 230 of the light emitting element LED, and / or the capping layer on the opposite electrode 230) does not include the SERS active nanoparticles, the position where one end of the organic encapsulation layer 320 is formed can be identified by distinguishing between the organic encapsulation layer 320 and the layer disposed below the organic encapsulation layer 320.

[0109] The SERS active nanoparticles 400 may be nanoparticles in which a Raman labeling compound 420 is adsorbed or bound to the surface of a metal nanoparticle 410. The SERS active nanoparticles 400 may be a material obtained by surface treating a metal nanoparticle 410 with a Raman labeling compound 420. In the present specification, the Raman labeling compound 420 may refer to a small molecule compound among materials that cause a Raman signal in vibrational modes, rotational modes, and other low-frequency modes of the material. The Raman signal is identified as a structural fingerprint for a molecule and is used as a probe for detecting a target material in a sample.

[0110] The content of the SERS active nanoparticles 400 may be greater than 0 wt % but not greater than about 5 wt % based on the total weight of the organic encapsulation layer 320. When the content of the SERS active nanoparticles 400 is greater than 5 wt %, the transmittance of the organic encapsulation layer 320 may decrease.

[0111] The size of the metal nanoparticles 410 may be, for example, at least about 1 nm, but not greater than about 20 nm. The size of the metal nanoparticles 410 may be, for example, at least about 5 nm, but not greater than about 20 nm. When the size of the metal nanoparticles 410 is less than 1 nm, the Raman labeling compound 420 may not be well adsorbed onto the metal nanoparticles 410. When the size of the metal nanoparticles 410 is greater than 20 nm, the transmittance of the organic encapsulation layer 320 may be reduced. For example, the metal nanoparticles 410 may include metal particles such as gold (Au), silver (Ag), or copper (Cu).

[0112] When the content of the SERS active nanoparticles 400 is greater than 0 wt % but not greater than about 5 wt %, and the size of the SERS active nanoparticles 400 or the metal nanoparticles 410 included in the SERS active nanoparticles 400 is 20 nm or less, the transmittance of the organic encapsulation layer 320 may be about 97% or greater. Accordingly, even when the organic encapsulation layer 320 includes the SERS active nanoparticles 400, the display quality of the display device 1 may not be degraded.

[0113] In an embodiment, the Raman marker compound 420 may include an aromatic ring. When the SERS active nanoparticles 400 include the Raman marker compound 420 including the aromatic ring, it can be easily distinguished from a layer disposed under the organic encapsulation layer 320. For example, the Raman marker compound 420 may include at least one of thiophenol, 4-mercaptophenol, 4-nitrothiophenol, 4-aminothiophenol, 4-mercaptophenylboric acid, 4-mercaptobenzoic acid, and pyridine-4-thiol.

[0114] The organic material 321 may include a photocurable organic material or a thermosetting organic material. The organic material 321 may include a polymer-based material. The organic material 321 may include a photocurable monomer or a thermosetting monomer. The organic material 321 may include an acrylic-based resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), an epoxy-based resin, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, polyimide, polyethylene, or any combination thereof.

[0115] The display device 1 may include a first dam portion DP1 and a second dam portion DP2. The first dam portion DP1 and the second dam portion DP2 may be disposed in the peripheral area PA. The first dam portion DP1 and the second dam portion DP2 may at least partially overlap with the power voltage line 11. The first dam portion DP1 may be separated from the organic encapsulation layer 320 in a first direction (e.g., direction x or direction y). The first dam portion DP1 may not overlap with the organic encapsulation layer 320. In other words, the first dam portion DP1 may not be covered by the organic encapsulation layer 320. The second dam portion DP2 may be disposed between the first dam portion DP1 and the organic encapsulation layer 320. The second dam portion DP2 may be disposed between the first dam portion DP1 and the first valley VP1.

[0116] The first dam portion DP1 may include a first insulation pattern 110Pa, a second insulation pattern 120Pa, a third insulation pattern 130Pa, and a fourth insulation pattern 140Pa sequentially stacked on each other. The first insulation pattern 110Pa may be disposed on the third inorganic insulation layer 107. The second insulation pattern 120Pa may be disposed on the first insulation pattern 110Pa. The third insulation pattern 130Pa may be disposed on the second insulation pattern 120Pa. The fourth insulation pattern 140Pa may be disposed on the third insulation pattern 130Pa.

[0117] The first insulating pattern 110Pa may be formed during the same process operation as the first planarization layer 110, and may include the same material as the first planarization layer 110. The second insulating pattern 120Pa may be formed during the same process operation as the second planarization layer 120, and may include the same material as the second planarization layer 120. The third insulating pattern 130Pa may be formed during the same process operation as the pixel defining layer 130, and may include the same material as the pixel defining layer 130. The fourth insulating pattern 140Pa may be formed during the same process operation as a spacer (not shown, which is disposed on the pixel defining layer 130 in the display area DA), and may include the same material as the spacer.

[0118] The second dam portion DP2 may include a fifth insulation pattern 120Pb, a sixth insulation pattern 130Pb, and a seventh insulation pattern 140Pb sequentially stacked on each other. The fifth insulation pattern 120Pb may be disposed on the third inorganic insulation layer 107. The sixth insulation pattern 130Pb may be disposed on the fifth insulation pattern 120Pb. The seventh insulation pattern 140Pb may be disposed on the sixth insulation pattern 130Pb.

[0119] The fifth insulating pattern 120Pb may be formed during the same process operation as the second planarization layer 120 and / or the second insulating pattern 120Pa, and may include the same material as the second planarization layer 120 and / or the second insulating pattern 120Pa. The sixth insulating pattern 130Pb may be formed during the same process operation as the pixel defining layer 130 and / or the third insulating pattern 130Pa, and may include the same material as the pixel defining layer 130 and / or the third insulating pattern 130Pa. The seventh insulating pattern 140Pb may be formed during the same process operation as the spacer (not shown, which is disposed on the pixel defining layer 130 in the display area DA) and / or the fourth insulating pattern 140Pa, and may include the same material as the spacer (not shown) and / or the fourth insulating pattern 140Pa.

[0120] The number and height of the insulation patterns included in the first and second dam portions DP1 and DP2 are not limited to those shown and may vary according to embodiments.

[0121] In the peripheral area PA, the display device 1 may further include an eighth insulating pattern 130h disposed on the second planarization layer 120. In an embodiment, the eighth insulating pattern 130h may be formed during the same process operation as the pixel defining layer 130, and due to a subsequent process, the height of the eighth insulating pattern 130h may be relatively smaller than the height of the pixel defining layer 130. In an embodiment, the eighth insulating pattern 130h may be an insulating pattern disposed on the second planarization layer 120 by a process separate from the pixel defining layer 130 of the display area DA.

[0122] The display device 1 may include a first valley portion VP1, which includes an opening OP1 in the first planarization layer 110 and an opening OP2 in the second planarization layer 120. The first valley portion VP1 may be disposed in the peripheral area PA. The first valley portion VP1 may be disposed between the first dam portion DP1 and the display area DA. The first valley portion VP1 may be disposed between the second dam portion DP2 and the display area DA. Portions of the first planarization layer 110 and the second planarization layer 120 in the peripheral area PA may be separated by the first valley portion VP1 from portions of the first planarization layer 110 and the second planarization layer 120 in the display area DA. The first valley portion VP1 may prevent or reduce moisture or foreign matter generated in an area disposed outside from penetrating into the display area DA through the first planarization layer 110 and / or the second planarization layer 120.

[0123] The power voltage line 11 may be disposed between the first insulating pattern 110Pa of the first dam portion DP1 and the first planarization layer 110. In an embodiment, an edge of the power voltage line 11 may be covered by the first insulating pattern 110Pa of the first dam portion DP1 and the first planarization layer 110, and a central portion of the power voltage line 11 may not be covered by the first dam portion DP1 and the first planarization layer 110 to have an exposed upper surface.

[0124] A conductive layer CLa may be disposed on the power voltage line 11. In an embodiment, the conductive layer CLa may include a first conductive layer CL1 and a second conductive layer CL2 on the first conductive layer CL1.

[0125] The first conductive layer CL1 may be disposed on the upper surface of the power voltage line 11, and may be disposed on the side surfaces of the first insulating pattern 110Pa and the side surfaces of the first planarization layer 110. In other words, the first conductive layer CL1 may be disposed on the upper surface of the power voltage line 11, and may extend to the side surfaces of the first insulating pattern 110Pa and the side surfaces of the first planarization layer 110. A portion of the first conductive layer CL1 may be disposed on the upper surface of the first insulating pattern 110Pa and the upper surface of the first planarization layer 110.

[0126] The second conductive layer CL2 may be disposed on the second valley VP2 described below. The second conductive layer CL2 may be disposed on the upper surface of the first conductive layer CL1, and may be disposed on the side surface of the fifth insulating pattern 120Pb and the side surface of the second planarization layer 120. In other words, the second conductive layer CL2 may be disposed on the upper surface of the first conductive layer CL1, and may extend to the side surface of the fifth insulating pattern 120Pb and the side surface of the second planarization layer 120. A portion of the second conductive layer CL2 may be disposed on the upper surface of the fifth insulating pattern 120Pb and the upper surface of the second planarization layer 120. The first inorganic encapsulation layer 310 may be disposed on the second conductive layer CL2.

[0127] A conductive pattern layer CPL may be disposed on the first valley portion VP1. The conductive pattern layer CPL may contact the upper surface of the third inorganic insulating layer 107 and may extend to the sidewalls of the first planarization layer 110, the sidewalls of the second planarization layer 120, and the upper surface of the second planarization layer 120. The first inorganic encapsulation layer 310 may be disposed on the conductive pattern layer CPL.

[0128] The display device 1 may further include a second valley portion VP2 disposed between the second dam portion DP2 and the first valley portion VP1. The second valley portion VP2 may be disposed in the peripheral area PA. The second valley portion VP2 may be disposed between the first dam portion DP1 and the display area DA. The second valley portion VP2 may be disposed between the second dam portion DP2 and the display area DA. The second valley portion VP2 may be a region where the second dam portion DP2 and the first planarization layer 110 and the second planarization layer 120 are separated from each other, and thereby prevents the encapsulation member 300 from overflowing to the outside of the second dam portion DP2.

[0129] Figure 5 is a flowchart of a method for manufacturing a display device according to an embodiment. Figure 3 and Figure 4 The display device 1 described can be based on reference Figure 5 A method of manufacturing a display device is described.

[0130] refer to Figures 3 to 5 , the method for manufacturing the display device 1 may include: in operation S1, an operation of forming a first inorganic encapsulation layer 310 on a light emitting element LED; in operation S2, an operation of forming an organic encapsulation layer 320 including SERS active nanoparticles 400 on the first inorganic encapsulation layer 310; in operation S3, an operation of testing a setting position of the organic encapsulation layer 320; and in operation S4, an operation of forming a second inorganic encapsulation layer 330 on the organic encapsulation layer 320.

[0131] Before forming the first inorganic encapsulation layer 310, a pixel circuit layer PCL including a pixel circuit PC may be formed on the substrate 100, and a light emitting element LED may be formed on the pixel circuit layer PCL. In an embodiment, a first dam DP1 and / or a second dam DP2 disposed in the peripheral area PA may be formed on the pixel circuit layer PCL. The first dam DP1 and the second dam DP2 may be disposed on the periphery of the substrate 100.

[0132] The first inorganic encapsulation layer 310 may be completely formed over the substrate 100. That is, the first inorganic encapsulation layer 310 may be completely formed in the display area DA where the light emitting element LED is disposed and the peripheral area PA where the light emitting element LED is not disposed.

[0133] The first inorganic encapsulating layer 310 may be formed on the light emitting element LED by a deposition process. For example, the first inorganic encapsulating layer 310 may be formed by chemical vapor deposition (CVD).

[0134] The first inorganic encapsulation layer 310 may include an inorganic material. The first inorganic encapsulation layer 310 may include, for example, aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO x , which may include ZnO and / or ZnO 2 ), silicon oxide (SiO 2 ), silicon nitride (SiN x ) and silicon oxynitride (SiON) or more inorganic materials.

[0135] The organic encapsulation layer 320 may be formed on the first inorganic encapsulation layer 310. The organic encapsulation layer 320 may be formed to cover the entire display area DA. The organic encapsulation layer 320 may be formed to cover only a portion of the peripheral area PA. For example, the organic encapsulation layer 320 may be formed not to overlap with the first dam portion DP1. For example, the organic encapsulation layer 320 may be formed not to overlap with the second dam portion DP2. For example, the organic encapsulation layer 320 may be formed not to overflow outside the first dam portion DP1 and / or the second dam portion DP2.

[0136] The organic encapsulation layer 320 may include a material obtained by adding the SERS active nanoparticles 400 to the organic material 321. For example, the organic encapsulation layer 320 may include a material obtained by adding the SERS active nanoparticles 400 to a component including a thermosetting monomer or a photocurable monomer. The monomer used to form the organic encapsulation layer 320 may be, for example, an acrylic monomer or an epoxy monomer. The organic encapsulation layer 320 may be formed, for example, by performing an inkjet process. The content of the SERS active nanoparticles 400 may be greater than 0wt% but not greater than 5wt% based on the total weight of the organic encapsulation layer 320.

[0137] The SERS active nanoparticles 400 added to the organic material 321 may be formed by surface treatment to adsorb or bind the Raman marker compound 420 to the metal nanoparticle 410. The size of the metal nanoparticle 410 may be, for example, at least about 1 nm, but not more than about 20 nm. The size of the metal nanoparticle 410 may be, for example, at least about 5 nm, but not more than about 20 nm. The metal nanoparticle 410 may include metal particles such as gold (Au), silver (Ag), or copper (Cu). The Raman marker compound 420 adsorbed onto the metal nanoparticle 410 may be a compound including an aromatic ring. For example, the Raman marker compound 420 adsorbed onto the metal nanoparticle 410 may include, for example, at least one of thiophenol, 4-mercaptophenol, 4-nitrothiophenol, 4-aminothiophenol, 4-mercaptophenylboronic acid, 4-mercaptobenzoic acid, and pyridine-4-thiol.

[0138] The organic encapsulation layer 320 includes a component including a photocurable monomer or a thermosetting monomer, and therefore, the organic encapsulation layer 320 may include a polymer-based material formed by curing an organic material. The organic material 321 included in the organic encapsulation layer 320 may be a polymer-based material formed by curing a photocurable monomer or a thermosetting monomer. For example, the organic material 321 may include an acrylic-based resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), an epoxy-based resin, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, polyimide, polyethylene, or any combination thereof.

[0139] After the organic encapsulation layer 320 is formed, an operation of testing the setting position of the organic encapsulation layer 320 may be performed. Because the organic encapsulation layer 320 includes the SERS active nanoparticles 400, the setting position of the organic encapsulation layer 320 may be analyzed by Raman spectroscopy or Raman detection. Unlike the organic encapsulation layer 320, the layers disposed below the organic encapsulation layer 320 (e.g., the pixel defining layer 130, the opposing electrode 230, and the capping layer on the opposing electrode 230) do not include the SERS active nanoparticles 400, and therefore, the organic encapsulation layer 320 may be identified by distinguishing the organic encapsulation layer 320 from the layers below using Raman spectroscopy or Raman detection. For example, Raman spectroscopy or Raman detection may be used to test whether the organic encapsulation layer 320 covers the light emitting element LED in the display area DA and has not overflowed to the outside of the first dam portion DP1 and / or the second dam portion DP2.

[0140] In the present specification, Raman spectroscopy or Raman detection may be a method in which Raman scattering occurring when a material having a Raman labeled compound scatters with loss or gain of molecular vibrational energy can be detected by a Raman spectrometer when the material is irradiated with a light source. Raman spectroscopy may be a method of measuring and analyzing a SERS spectrum formed for a target material by Raman scattering. Raman spectroscopy may include an operation of irradiating a target material with a light source and an operation of detecting Raman scattering (or a Raman signal) from the target material.

[0141] The second inorganic encapsulation layer 330 may be completely formed over the substrate 100. That is, the second inorganic encapsulation layer 330 may be completely formed in the display area DA where the light emitting element LED is disposed and in the peripheral area PA where the light emitting element LED is not disposed.

[0142] The second inorganic encapsulating layer 330 may be formed on the organic encapsulating layer 320 and the first inorganic encapsulating layer 310 by using a deposition process. For example, the second inorganic encapsulating layer 330 may be formed by chemical vapor deposition (CVD).

[0143] The second inorganic encapsulation layer 330 may include an inorganic material. The second inorganic encapsulation layer 330 may include, for example, aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO x , which may include ZnO and / or ZnO 2 ), silicon oxide (SiO 2 ), silicon nitride (SiN x ) and silicon oxynitride (SiON) or more inorganic materials.

[0144] According to one or more of the above embodiments, the setting position of the material for forming the organic encapsulation layer can be monitored via Raman detection by adding SERS active nanoparticles to the organic encapsulation layer. It can be easily checked whether the organic encapsulation layer has been formed at the target position, and thus the reliability of the display device can be improved. However, this effect is an example, and one or more embodiments are not limited thereto.

[0145] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a peripheral area arranged outside the display area; A light emitting element is disposed on the display area of ​​the substrate; as well as a packaging member, disposed on the light emitting element and comprising at least one inorganic packaging layer and at least one organic packaging layer, Wherein, one of the at least one organic encapsulation layer comprises surface enhanced Raman scattering active nanoparticles.

2. The display device according to claim 1, wherein: The surface-enhanced Raman scattering active nanoparticles are metal nanoparticles on the surface of which Raman labeling compounds are adsorbed. Wherein, the size of each of the metal nanoparticles is at least 1 nm but not greater than 20 nm.

3. The display device according to claim 2, wherein: The metal nanoparticles include gold, silver or copper.

4. The display device according to claim 2, wherein: The Raman labeling compound includes an aromatic ring.

5. The display device according to claim 4, wherein: The Raman labeling compound includes at least one of thiophenol, 4-mercaptophenol, 4-nitrothiophenol, 4-aminothiophenol, 4-mercaptophenylboric acid, 4-mercaptobenzoic acid and pyridine-4-thiol.

6. The display device according to claim 1, wherein: Based on the total weight of the one organic encapsulation layer, the content of the surface-enhanced Raman scattering active nanoparticles is greater than 0 wt % but not greater than 5 wt %.

7. A display device, comprising: substrate; A light emitting element is disposed on the substrate and includes a pixel electrode, an emission layer on the pixel electrode, and an opposite electrode on the emission layer; as well as a packaging member disposed on the light emitting element and comprising a first inorganic packaging layer, an organic packaging layer on the first inorganic packaging layer, and a second inorganic packaging layer on the organic packaging layer, The organic encapsulation layer includes surface-enhanced Raman scattering active nanoparticles, in which the metal nanoparticles are surface-treated with a Raman labeling compound. Wherein, the Raman labeling compound includes an aromatic ring.

8. The display device according to claim 7, wherein: Each of the metal nanoparticles has a size of 20 nm or less.

9. The display device according to claim 7, wherein: The metal nanoparticles include gold, silver or copper.

10. The display device according to claim 7, wherein: The Raman labeling compound includes at least one of thiophenol, 4-mercaptophenol, 4-nitrothiophenol, 4-aminothiophenol, 4-mercaptophenylboric acid, 4-mercaptobenzoic acid and pyridine-4-thiol.

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