Signal interpolation preserving least significant bit (lsb) information with low bit resolution processor

Abstract

One embodiment provides a method that includes receiving content having a first resolution. The processor separates the content into most significant bits and least significant bits. The processor also processes the most significant bits of the content while retaining the least significant bits. The processor additionally performs linear combination on the output that processes the most significant bits with the retained least significant bits to improve the quality of the content.

Description

Technical Field

[0001] One or more embodiments relate generally to integration of various image / video processing blocks, and in particular, to preserving the least significant bits (LSBs) in reconstruction of information after passing through a given processing block. Background Art

[0002] Typically, video image processing intellectual property (IP, i.e., such as one or more logic units, cells, chip layout designs, circuits, hardware components, etc.) is given in the form of hidden blocks (such as one or more libraries). In some cases, the provided IP (e.g., one or more blocks, libraries, etc.) cannot be modified, and the IP should be used as is. During the integration of these IPs into existing systems, it is critical to retain data accuracy with the available IPs, especially with regard to video image quality enhancement, and many image processing blocks also have bit conversion operations to generate different bit resolutions. Summary of the invention

[0003] One embodiment provides a method that includes receiving content having a first resolution. A processor separates the content into a most significant bit and a least significant bit. The processor also processes the most significant bit of the content while retaining the least significant bit. The processor additionally performs a linear combination of the output of the processing of the most significant bit and the retained least significant bit to improve the quality of the content.

[0004] One embodiment provides a device, the device including at least one memory configured to store instructions. The device includes at least one processor that executes instructions including processing, the processing configured to: receive content having a first resolution. The device includes at least one processor that executes instructions including processing, the processing configured to: separate the content into most significant bits and least significant bits. The device includes at least one processor that executes instructions including processing, the processing configured to: process the most significant bits of the content while retaining the least significant bits. The device includes at least one processor that executes instructions including processing, the processing configured to: perform a linear combination of the output of the processing of the most significant bits and the retained least significant bits to improve the quality of the content. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a fuller understanding of the nature and advantages of the embodiments, as well as the preferred mode of use, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 An example of a 12-bit system utilizing and integrating 8-bit intellectual property (IP) components resulting in reduced quality is shown; Figure 2 shows an example architecture of the disclosed technology according to an embodiment; Figure 3A comparison diagram showing system results at different resolutions according to an embodiment and system results of the disclosed technology is shown; Figure 4 shows an example architecture of the disclosed technology utilizing parallelization and multi-instantiation of low-level intellectual property (IP) according to an embodiment; Figure 5 An example diagram for comparing a linear domain processing result, a gamma correction processing result, and a processing result of the disclosed technology according to an embodiment of the present invention is shown; Figure 6 shows an example architecture 60 utilizing weighted averaging of neighboring outputs of lower order processing blocks with estimated weights from various algorithms, according to an embodiment; Figure 7 shows an example comparison graph of multiple adjacent function outputs according to an embodiment; Figure 8 shows an example architecture utilizing a bilinear approach according to an embodiment; Fig. 9 shows an example comparison graph of bilinear function outputs according to an embodiment; and Fig.10 A process for preserving least significant bit (LSB) information while using a low bit resolution processor is shown according to an embodiment. DETAILED DESCRIPTION

[0006] The following description is intended to illustrate the general principles of one or more embodiments and is not meant to limit the inventive concepts claimed herein. In addition, the specific features described herein may be used in combination with other described features in every possible combination and arrangement. Unless otherwise expressly defined herein, all terms will be given their broadest possible interpretation, including the meaning implied from the specification and the meaning understood by those skilled in the art and / or the meaning defined in dictionaries, papers, etc.

[0007] A description of the example embodiments is provided on the following pages. The text and drawings are provided as examples only to help the reader understand the disclosed technology. They are not intended to and should not be interpreted as limiting the scope of the disclosed technology in any way. Although specific embodiments and examples have been provided, it will be apparent to those skilled in the art based on the disclosure herein that the illustrated embodiments and examples may be changed without departing from the scope of the disclosed technology.

[0008] One or more embodiments generally relate to the integration of various image / video processing blocks, and in particular, to retaining the least significant bit (LSB) in information reconstruction after passing through a given processing block. One embodiment provides a method including receiving content having a first resolution. A processor separates the content into a most significant bit and a least significant bit. The processor also processes the most significant bit of the content while retaining the least significant bit. The processor additionally performs a linear combination of the output of the processing most significant bit and the retained least significant bit to improve the quality of the content.

[0009] As an example, the first resolution may include a resolution of the content.

[0010] Figure 1 An example 10 of a 12-bit system that utilizes and integrates 8-bit intellectual property (IP, e.g., such as one or more logic units, cells, chip layout designs, circuits, hardware components, etc.) components and results in degraded quality is shown. Combining and / or integrating various image / video processing blocks is one of the most frequent tasks that occur during system integration such as High Dynamic Range (HDR) 10+ (HDR video technology that adds dynamic metadata to HDR10 source files). However, not all processing blocks may fully meet system requirements, and a common variation in the different capabilities of each block is the bit resolution processing capability. To make matters worse, these blocks are often given in the form of hidden blocks or fixed blocks, such as in the form of libraries. Due to this limitation, in this case, some information is lost through the blocks because the LSBs may be deleted. Example 10 of a 12-bit system that utilizes and integrates 8-bit IP components results in degraded quality due to the bit depth conversion selection made using the 8-bit IP.

[0011] Figure 2 An example architecture 20 of the disclosed technology according to an embodiment is shown. In order to retain the lost LSB information when utilizing a single IP, one or more embodiments provide for preserving the LSB information by utilizing multiple IP instances, and the LSB information is also used to reconstruct the information after passing through a given processing block. Considering a system architecture 20 with a bit resolution of 12 bits as an example, there is an image processing block (hidden 8-bit image / video processing block 22) that has a bit resolution of 8 bits and is hidden to be integrated into the system architecture 20. Because the system architecture 20 utilizes a low-bit resolution processing block (hidden 8-bit image / video processing block 22), and the processing block can only process 8-bit resolution, the LSB may be deleted. The final result is matched with the 12-bit signal 33 ( Figure 3 ) may lose LSB information and may show jagged step lines ( Figure 38-bit signal 32). This jagged output from the IP may produce visual banding artifacts. Such problems can be systematically overcome by establishing a parallel LSB preservation and utilization mechanism using multiple instances of the same IP and specially designed pre-processing and post-processing algorithms to simulate the results that would ideally be produced based on processing using a 12-bit IP.

[0012] In one or more embodiments, the system architecture 20 may include a separator 21, an up-converter 23, a hidden 8-bit image / video processing block 22, an add-1 processing block 24, and a weighted average processing block 27. According to an embodiment, the separator 21 may separate the input of the separator 21 into an LSB portion and a most significant bit (MSB). After the hidden 8-bit image / video processing block 22 may process the MSB, in this example, the result may be converted from 8 bits to 12 bits by the up-converter 23, and the result may be processed by the weighted average processing block 27. The LSB separated from the input signal by the separator 21 may also be input to the weighted average processing block 27 and may be processed by the weighted average processing block 27. The add-1 processing block 24 may add one bit to the MSB portion, wherein the result may be processed by the hidden 8-bit image / video processing block 25. The result from the hidden 8-bit image / video processing block 25 may be up-converted from 8 bits to 12 bits by the up-converter 26, and the result may also be input to the weighted average processing block 27.

[0013] As an example, F(X8) represents the result of the 8-bit image / video processing block 22 hidden when the MSB is X8. As an example, F up (X8) represents the result of the up-converter (8-bit to 12-bit) 23 when the MSB is X8.

[0014] In an embodiment, the hidden 8-bit image / video processing block 22 may process the MSB and MSB+n. In an embodiment, the hidden 8-bit image / video processing block 22 may process the MSB and MSB-n. n represents an integer. As an example, the index may include the integer n.

[0015] Figure 3 A comparison diagram 30 of system results of different resolutions according to an embodiment and system results of the disclosed technology is shown. As shown in the figure, the curve graph 30 compares an 8-bit signal 32, a 12-bit signal 33, and an output result 31 proposed by the present technology. As shown in the figure, the curves of the 12-bit signal 33 and the output result 31 proposed by the present technology are very close, while the 8-bit signal 32 shows a jagged staircase (or sawtooth) line.

[0016] Figure 4An example architecture 40 of the disclosed technology utilizing parallelization and multi-instantiation of low-level IPs according to an embodiment is shown. The example architecture 40 uses bilinear interpolation. In one or more embodiments, the example architecture 40 may include a separator 41, two hidden 4-bit image / video processing blocks 42, an add-1 processing block 44, and a weighted average processing block 47. According to an embodiment, the output from the weighted average processing block 47 may be shown as (F(X4+1)×L4+F(X4)×(16-L4)) / 16, where 16 is the upper limit of the LSB (4 bits).

[0017] Figure 5 An example diagram for comparing the linear domain processing results, gamma correction processing results and processing results of the disclosed technology of a conventional system according to an embodiment is shown. For ease of comparison, an 8-bit synthetic bitmap image is used. Image 50 shows the results of conventional linear input / processing for an 8-bit system. Image 51 shows the results of conventional linear domain processing for a 4-bit system. Image 52 shows the results of one or more embodiments using 4-bit processing+LSB processing. Image 53 shows the results of conventional gamma encoding input / processing for an 8-bit system. Image 54 shows the results of conventional gamma correction processing for a 4-bit system. Image 55 shows the results of one or more embodiments using 4-bit processing+LSB processing. The results show that the proposed techniques seen in images 52 and 55 each have smooth outputs compared to the direct results of a single low-bit resolution processing block such as images 50, 51, 53 and 54. Therefore, the parallelization and multi-instantiation of low-level IPs and the addition of system extra logic can be used to improve picture quality, and the disclosed technology can be used to build new high-quality systems without changing IP components.

[0018] Compared to the direct results of a single low-bit resolution processing block (see, for example, images 50, 51, 53, and 54), the example results (see, for example, images 52 and 55) show that the disclosed technology provides a smooth output. Therefore, one or more embodiments of the disclosed technology utilize parallelization and multiple instantiation of low-level IPs and additional system extra logic to improve picture quality; the disclosed technology can be used to build a high-quality system without changing IP components.

[0019] Figure 6An example architecture 60 is shown that utilizes a weighted average of adjacent outputs of low-bit processing blocks and estimated weights from various algorithms according to an embodiment. In one or more embodiments, the architecture 60 may include: a separator 61, a plurality of subtraction processing blocks that subtract one or more bits (e.g., a subtraction 1 processing block 64, a subtraction 2 processing block 65, etc.), a plurality of addition processing blocks that add one or more bits (e.g., an addition 1 processing block 62, an addition 2 processing block 63, etc.), a plurality of hidden N-bit image / video processing blocks 66 (where N is a positive integer), a plurality of N-bit to M-bit up-converters 67 (where N and M are positive integers and M>N), and a weighted average 68 using various algorithms. The embodiment uses estimated weights from various algorithms (such as bilinear, bicubic, spline, histogram equalization, etc.) to provide a weighted average of adjacent outputs of low-bit processing blocks according to the weighted average 68 using various algorithms.

[0020] According to an embodiment, Calculate the weighted average using various algorithms 68. k represents the index of the adjacent index. N represents the reference input range used for interpolation. W k Represents the appropriate weights for interpolation determined by logic (such as bilinear, bicubic, spline, histogram equalization, synchronous function, etc.). X MSB represents the input value truncated due to the bit limit of the given hidden function. F(x) represents the function output of the hidden function.

[0021] According to an embodiment, the separator 61 may separate an input of the separator 61 (eg, M bits) into an LSB portion (eg, MN bits) and a most significant bit (MSB) (eg, N bits).

[0022] According to an embodiment, after the hidden N-bit image / video processing block 66 may process the MSB, in this example, the result may be converted from N bits to M bits by an up-converter 67 , where the result may be processed by a weighted average processing block 68 .

[0023] According to an embodiment, the LSB separated from the input signal by the separator 61 may also be input to the weighted average processing block 68 and may be processed by the weighted average processing block 68 .

[0024] According to an embodiment, an addition processing block (e.g., addition processing block 62, addition processing block 63) or a subtraction processing block (e.g., subtraction processing block 64, subtraction processing block 65) may add or subtract one or more bits to the MSB portion, wherein the result may be processed by the hidden N-bit image / video processing block 66. The result from the hidden N-bit image / video processing block 66 may be up-converted from N bits to M bits by an up-converter 67, and the result may also be input to the weighted average processing block 68.

[0025] As an example, the number of addition processing blocks (eg, addition processing block 62 , addition processing block 63 ) and subtraction processing blocks (eg, subtraction processing block 64 , subtraction processing block 65 ) may be one or more.

[0026] As an example, the number of hidden N-bit image / video processing blocks 66 may be one or more.

[0027] As an example, adjacent may include adding one or more bits to the MSB portion or subtracting one or more bits from the MSB portion.

[0028] As an example, a low-resolution black box block may include an image / video processing block without LSB bits.

[0029] As an example, a high resolution suboptimal processing block may include a block that reconstructs the final output.

[0030] As an example, the first processing block for the most significant bits may be one of the concealed N-bit image / video processing blocks 66 .

[0031] As an example, the second processing block for the most significant bits may be one of the concealed N-bit image / video processing blocks 66 .

[0032] As an example, the additional bits may be bits added to or subtracted from the MSB portion.

[0033] Figure 7 An example comparison graph 70 of multiple adjacent function outputs according to an embodiment is shown. The graph 70 includes a high-resolution function output 71, a low-resolution function output 72, and an interpolated function output 73 based on one or more embodiments. Four adjacent function outputs 74 are also shown. In this example comparison graph 70, four adjacent function outputs 74 are used to reconstruct the high-resolution function output. An embodiment may provide for interpolating the target function output using a given pixel through various algorithms. After interpolation, the high-resolution output is obtained by combining the bypassed LSB and the estimated final output.

[0034] Figure 8 An example architecture 80 utilizing a bilinear approach according to an embodiment is shown. In one or more embodiments, the example architecture 80 includes: a separator 61, two hidden N-bit image / video processing blocks 66, two N-bit to M-bit up-converters 67, an add-one processing block 62, and a weighted average processing block 68. According to an embodiment, the proposed simple and efficient algorithm implementation is bilinear.

[0035] Fig. 9An example comparison graph 90 of bilinear function outputs according to an embodiment is shown. In one or more embodiments, the example architecture 90 may have similar results to the example architecture 70. The graph 90 includes a high-resolution function output 91, a low-resolution function output 92, and an interpolation function output 93 based on one or more embodiments. Two adjacent function outputs 94 are also shown. In this example comparison graph 90, two adjacent function outputs 94 are used to reconstruct the high-resolution function output. An embodiment may provide for interpolating the target function output using a given pixel through various algorithms. After interpolation, a high-resolution output is obtained by combining the bypassed LSB and the estimated final output.

[0036] Fig.10 A process 1000 is shown for retaining LSB information while using a low bit resolution processor according to an embodiment. In block 1010, the process 1000 receives content (e.g., video, one or more images, etc.) having a first resolution (e.g., 4 bits, 8 bits, etc.). In block 1020, the process 1000 separates (using a processor (e.g., a computing processor / multiprocessor, etc.) the content into Figure 2 Separator 21, Figure 4 Separator 41, Figure 6 Separator 61, Figure 8 In block 1030, process 1000 processes the MSB of the content by the processor while retaining the LSB. In block 1040, process 1000 performs a linear combination (e.g., Figure 2 The weighted average of 27 Figure 4 The weighted average of 47 Figure 6 The weighted average of 68 Figure 8 weighted average 68) to improve the quality of the content.

[0037] According to an embodiment, process 1000 also provides for processing the output of the MSB to produce estimated weights.

[0038] In one or more embodiments, process 1000 also provides that the linear combination includes a weighted average (e.g., Figure 2 The weighted average is 27; Figure 4 The weighted average is 47; Figure 6 The weighted average of 68 Figure 8 The weighted average of the

[0039] In one or more embodiments, process 1000 also provides for processing the output of the MSB to produce estimated weights.

[0040] According to an embodiment, process 1000 additionally provides weighted averaging based on exploiting parallelization and multi-instancing of low-level content processing and additional system logic to improve the picture quality of the display.

[0041] In one or more embodiments, process 1000 also provides that additional system logic is configured to convert a low resolution black box block into a high resolution sub-optimal processing block by combining the low resolution logic with the LSBs of the content.

[0042] According to an embodiment, process 1000 further includes: weighted averaging includes interpolating a final output using the output of processing the most significant bits and the retained least significant bits.

[0043] In one or more embodiments, process 1000 additionally includes the following feature: the final output includes the same number of bits as the number of bits of the content.

[0044] According to an embodiment, the process 1000 also includes the following features: the content includes n bit contents, the most significant bit includes m The least significant bit includes l Bit, n Greater than m and l ,and m Greater than l .

[0045] In one or more embodiments, process 1000 further includes the following feature: processing the MSB of the content includes parallel processing including a first processing block for the MSB and a second processing block for the MSB and the additional bits.

[0046] The present technique provides a better way to process high bit resolution signals with given processing blocks being hidden. In one example embodiment, for an 8-bit image / video processing library, source code is not available, and a 12-bit image / video needs to be processed, where the output typically loses 4 bits in detail. Using the present technique in this example embodiment, the system processes the 12-bit signal by utilizing the 4-bit LSB (e.g., from a system on a chip (SoC), one or more algorithms / processes, etc.) without losing 4 bits from the signal.

[0047] Embodiments have been described with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products. Each block or combination of such diagrams / graphs may be implemented by computer program instructions. The computer program instructions, when provided to a processor, produce a machine such that instructions executed by the processor create methods for implementing the functions / operations specified in the flowchart and / or block diagram. Each block in the flowchart / block diagram may represent a hardware and / or software module or logic. In alternative embodiments, the functions shown in the blocks may not occur in the order shown in the figure, may occur simultaneously, etc.

[0048] The terms "computer program medium", "computer usable medium", "computer readable medium" and "computer program product" are generally used to refer to media such as main memory, secondary memory, removable storage drives, hard disks installed in hard drives, and signals. These computer program products are devices for providing software to computer systems. Computer readable media allow computer systems to read data, instructions, messages or message packets, and other computer-readable information from computer readable media. Computer readable media may include, for example, non-volatile memory such as floppy disks, ROMs, flash memory, disk drive memory, CD-ROMs, and other permanent storage. For example, it is useful for transferring information (such as data and computer instructions) between computer systems. Computer program instructions may be stored in a computer readable medium, which may instruct a computer, other programmable data processing device, or other device to operate in a specific manner so that the instructions stored in the computer readable medium generate an article of manufacture including instructions for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0049] As will be appreciated by those skilled in the art, aspects of the embodiments may be implemented as systems, methods, or computer program products. Thus, aspects of the embodiments may take the form of full hardware embodiments, full software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software aspects and hardware aspects, which may generally be referred to herein as "circuits," "modules," or "systems." In addition, aspects of the embodiments may take the form of a computer program product implemented in one or more computer-readable media (having computer-readable program codes implemented thereon).

[0050] Any combination of one or more computer-readable media may be utilized. A computer-readable medium may be a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer-readable storage media may include the following: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this article, a computer-readable storage medium may be any tangible medium that may include or store a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0051] Computer program code for performing the operations of various aspects of one or more embodiments may be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as "C" programming language or similar programming languages). The program code may be run entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., connected via the Internet using an Internet service provider).

[0052] The above-mentioned flowchart illustrations and / or block diagrams with reference to methods, devices (systems) and computer program products describe various aspects of one or more embodiments. It will be understood that each block of the flowchart illustrations and / or block diagrams and the combination of blocks in the flowchart illustrations and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a special-purpose computer or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a method for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0053] These computer program instructions may also be stored in a computer-readable medium, which may instruct a computer, other programmable data processing device, or other apparatus to operate in a specific manner so that the instructions stored in the computer-readable medium generate an article of manufacture including instructions for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0054] The computer program instructions may also be loaded onto a computer, other programmable data processing device or other apparatus so that a series of operational steps are performed on the computer, other programmable device or other apparatus to produce a computer-implemented process, so that the instructions running on the computer or other programmable device provide a process for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0055] The flow chart and block diagram in the accompanying drawings show the architecture, function and operation of the system, method and computer program product that may be realized according to various embodiments.In this regard, each frame in the flow chart or block diagram may represent a module, segment or part of an instruction, including one or more executable instructions for realizing the specified logical function.In some alternative embodiments, the function shown in the frame may not occur in the order shown in the figure.For example, the two frames shown in succession can actually be performed substantially at the same time, or these frames can sometimes be performed in reverse order, depending on the function involved.It will also be noted that each frame of the block diagram and / or flow chart diagram and the combination of frames in the block diagram and / or flow chart diagram can be realized by a system based on special hardware that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0056] Unless explicitly stated otherwise, a reference to an element in the singular in a claim is not intended to mean "one and only one," but rather "one or more." All structural and functional equivalents to the elements of the above-described exemplary embodiments that are currently known or later come to be known to those of ordinary skill in the art are intended to be encompassed by the present claims.

[0057] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form. It will also be understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0058] The corresponding structures, materials, acts, and equivalents of all method or step-plus-function elements in the following claims are intended to include any structure, material, or act for performing a function in conjunction with other claimed elements specifically claimed. The description of the embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments in the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention.

[0059] Although the embodiments have been described with reference to specific versions thereof; however, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.

[0060] According to an embodiment of the present disclosure, a method may include receiving content having a first resolution.

[0061] According to an embodiment of the present disclosure, the method may include: separating the content into most significant bits and least significant bits.

[0062] According to an embodiment of the present disclosure, the method may include: processing the most significant bits of the content while retaining the least significant bits.

[0063] According to an embodiment of the present disclosure, the method may include: performing a linear combination of an output of processing the most significant bit and a retained least significant bit to improve the quality of the content.

[0064] According to an embodiment of the present disclosure, the linear combination includes a weighted average.

[0065] According to an embodiment of the present disclosure, the output of the most significant bits is processed to generate estimated weights.

[0066] According to an embodiment of the present disclosure, weighted averaging is based on exploiting parallelization and multi-instancing of low-level content processing and additional system logic to improve the picture quality of the display.

[0067] According to an embodiment of the present disclosure, additional system logic is configured to convert low-resolution black box blocks into high-resolution sub-optimally processed blocks by combining the low-resolution logic with the least significant bits of the content.

[0068] According to an embodiment of the present disclosure, weighted averaging includes interpolating a final output using the output of processing the most significant bits and retaining the least significant bits.

[0069] According to an embodiment of the present disclosure, the final output includes the same number of bits as that of the content.

[0070] According to an embodiment of the present disclosure, processing the most significant bit of the content includes parallel processing including a first processing block for the most significant bit and a second processing block for the most significant bit and additional bits.

[0071] According to an embodiment of the present disclosure, a computer-readable storage medium stores at least one instruction, which, when executed, causes at least one processor to perform a method corresponding to the method.

[0072] According to an embodiment of the present disclosure, at least one processor is configured to receive content having a first resolution.

[0073] According to an embodiment of the present disclosure, at least one processor is configured to separate content into most significant bits and least significant bits.

[0074] According to an embodiment of the present disclosure, at least one processor is configured to process the most significant bits of the content while retaining the least significant bits.

[0075] According to an embodiment of the present disclosure, at least one processor is configured to perform a linear combination of an output of processing the most significant bits and a retained least significant bit to improve the quality of the content.

Claims

1. A method comprising: receiving content having a first resolution; separating the content into most significant bits and least significant bits; Processing the most significant bits of the content while retaining the least significant bits; as well as A linear combination is performed on the output of processing the most significant bits and the retained least significant bits to improve the quality of the content.

2. The method of claim 1, wherein: The linear combination comprises a weighted average.

3. The method according to any one of claims 1 and 2, wherein: Processing the most significant bit output produces an estimated weight.

4. The method of claim 2, wherein: The weighted average is based on exploiting parallelization and multi-instancing of low-level content processing and additional system logic to improve the picture quality of the display.

5. The method of claim 4, wherein: The additional system logic is configured to convert a low resolution black box block into a high resolution sub-optimal processing block by combining the low resolution logic with the least significant bits of the content.

6. The method according to any one of claims 2, 4 and 5, wherein: The weighted averaging includes interpolating a final output using the output of processing the most significant bits and retaining the least significant bits.

7. The method of claim 6, wherein: The final output includes the same number of bits as the content.

8. The method according to any one of claims 1 to 7, wherein: Processing the most significant bits of the content includes parallel processing including a first processing block for the most significant bits and a second processing block for the most significant bits and additional bits.

9. A computer-readable storage medium storing instructions, wherein: When the instructions are executed by at least one processor, the at least one processor performs the method of any one of claims 1 to 8.

10. A device comprising: Memory, which stores instructions; as well as at least one processor, executing the instructions including processing, the processing being configured to: receiving content having a first resolution; separating the content into most significant bits and least significant bits; Processing the most significant bits of the content while retaining the least significant bits; as well as A linear combination is performed on the output of processing the most significant bits and the retained least significant bits to improve the quality of the content.

11. The apparatus of claim 10, wherein: processing the output of the most significant bit to produce an estimated weight; and The linear combination comprises a weighted average.

12. The apparatus of claim 11, wherein: The weighted average is based on exploiting parallelization and multi-instancing of low-level content processing and additional system logic to improve the picture quality of the display.

13. The apparatus of claim 12, wherein: The additional system logic is configured to convert a low resolution black box block into a high resolution sub-optimal processing block by combining the low resolution logic with the least significant bits of the content; and The weighted averaging includes interpolating a final output using the output of processing the most significant bits and retaining the least significant bits.

14. The apparatus of claim 13, wherein: The final output includes the same number of bits as the content.

15. The apparatus of any one of claims 10 to 14, wherein: Processing the most significant bits of the content includes parallel processing including a first processing block for the most significant bits and a second processing block for the most significant bits and additional bits.

Images