Pre-sputter plasma cleaning

Abstract

The invention relates to pre-sputter plasma cleaning. A method of forming an integrated circuit includes forming a first copper feature (602, 604) in a first metal layer over a semiconductor substrate; and forming a dielectric layer (606) over the first copper feature. The method also includes forming an opening (608, 610) in the dielectric layer that exposes the copper feature; and exposing the first copper feature to a hydrogen plasma to chemically reduce a copper compound resulting from forming the opening (612). The hydrogen plasma is generated with an RF bias power (Wb) and an RF source power (Wa), where Wblt; and-0.938 Wa + 210.57, and the total weight of the The method further includes forming a second copper feature within the opening that is electrically connected to the first copper feature (614).

Description

Technical Field

[0001] The present disclosure relates to semiconductor manufacturing, and in particular, to pre-sputtering plasma cleaning. Background Art

[0002] Plasma is a high-energy state of matter containing charged particles. Plasma cleaning uses a plasma of a gas (such as argon, oxygen, or hydrogen) to clean the surface of an integrated circuit. During plasma cleaning, the charged particles interact with the surface of the integrated circuit to remove contaminants that may interfere with the manufacture or operation of the integrated circuit. Summary of the invention

[0003] In one example, a method of forming an integrated circuit includes: forming a first copper feature in a first metal layer above a semiconductor substrate; and forming a dielectric layer above the first copper feature. The method also includes: forming an opening in the dielectric layer to expose the copper feature; and exposing the first copper feature to a hydrogen plasma to chemically reduce copper compounds generated by forming the opening. The hydrogen plasma is generated with an RF bias power (W b ) and RF source power (W a ) is generated, where W b <-0.938W a +210.57. The method further includes forming a second copper feature within the opening that is electrically connected to the first copper feature.

[0004] In another example, a method of forming an integrated circuit includes: forming a dielectric layer having a top surface over a semiconductor substrate; and forming an opening in the dielectric layer, thereby exposing a metal surface. The method also includes cleaning a surface in the opening with a plasma process, the plasma process including generating a RF bias power (W) near the top surface. b ) and RF source power (W a ) of an inductively coupled hydrogen plasma, where W b <-0.938W a +210.57. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a flow chart of an example method for plasma cleaning that may be employed in the manufacture of integrated circuits.

[0006] Figure 2 For application Figure 1 An example graph of RF bias power versus RF source power for a method of

[0007] Figure 3 For application Figure 1 An example of a method of processing time versus RF source power is shown.

[0008] Figure 4 An example plasma cleaning system configured to perform remote plasma cleaning of integrated circuits is shown.

[0009] Figure 5 The display is configured to implement Figure 1 An example plasma cleaning method of the invention is a plasma cleaning system.

[0010] Figure 6 is a flowchart of an exemplary method for manufacturing an integrated circuit, the method comprising Figure 1 Plasma cleaning method.

[0011] Fig. 7A , 7B , 7C, 7D, 7E1, 7E2, 7F1, 7F2, 7G1, 7G2 and 7H are for display Figure 6 Cross-sectional views of examples of various manufacturing stages of the method. DETAILED DESCRIPTION

[0012] Dielectric materials are used in integrated circuits to electrically isolate one layer from another. As integrated circuit feature sizes decrease to enable the implementation of more complex circuits, materials with lower dielectric constants than silicon dioxide (low-k dielectric materials) are used to reduce capacitance between circuit components. For example, silicon dioxide has a dielectric constant of 3.9, and low-k dielectric materials can have a dielectric constant less than 3.9 (e.g., silicon oxycarbide dielectric materials can have a dielectric constant as low as 2.5). Ultra-low-k dielectric materials such as organic polymers can have a dielectric constant as low as 2.

[0013] For higher k dielectrics such as silicon dioxide, the surface of the integrated circuit can be cleaned between processing steps to remove residues and other contaminants using plasma sputter etching. Higher k dielectrics are relatively hard and are not adversely affected by sputter etching. Low k dielectrics are softer and can be degraded or damaged by sputter etching. Damage to the dielectric can lead to a wide variety of problems, including increased metal interconnect volume, reduced metal-to-metal spacing, and degradation of dielectric structural integrity. Increased metal interconnect volume can reduce interconnect resistance and increase interconnect capacitance. Reduced metal-to-metal spacing can increase interconnect capacitance. Degradation of dielectric structural integrity can lead to probe / package failures, short circuits, lifetime failures, electrically induced voiding, and / or migration failures.

[0014] The plasma cleaning method described herein applies a low temperature inductively coupled plasma (ICP) pre-clean chamber to remove contaminants from the surface of an integrated circuit. The operating parameters of the chamber are set as described herein to remove contaminants from the surface of the integrated circuit without damaging the exposed dielectric, which in some examples may be a low-k dielectric. Thus, the method provides effective cleaning of integrated circuits containing low-k dielectrics without damaging the dielectric and without the expense associated with a remote plasma cleaning system.

[0015] Figure 1 1 is a flow chart of an exemplary method 100 for plasma cleaning that can be applied in the manufacture of integrated circuits. Although depicted sequentially for convenience, at least some of the actions shown can be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown.

[0016] In block 102, an integrated circuit (IC) at an intermediate stage of fabrication is placed in a plasma cleaning chamber. The IC may be one of several nominally identical ICs on a semiconductor wafer. The plasma cleaning chamber is an ICP pre-clean chamber. The ICP pre-clean chamber may be produced by a ULVAC incorporated in some examples.

[0017] In block 104, parameters of the plasma cleaning chamber are set. The parameters may include radio frequency (RF) source power and RF bias power. RF bias power is the power applied to an integrated circuit substrate placed in the plasma cleaning chamber. Ion energy increases with RF bias power. RF source power is the power applied to a plasma generator of the plasma cleaning chamber. Plasma density increases with RF source power.

[0018] Figure 2 is a graph of example RF bias power versus RF source power suitable for use in method 100. In method 100, the RF source power may be set in a range of about 200 watts (W) to about 1900 W. The RF bias power applied in method 100 decreases as the RF source power increases. The RF bias power may be set in a range of about 0 W to about 195 W. In some examples, the RF bias power may be set according to the following formula:

[0019] W b <-0.938·W a +210.57

[0020] in:

[0021] W b is the RF bias power; and

[0022] W a is the RF source power.

[0023] In block 106, a cleaning time is set. For example, the cleaning time may be the time that the plasma cleaning chamber is set to generate the plasma. In some examples, the cleaning time may be set in the range of 10 seconds to 60 seconds. The cleaning time may decrease with higher RF source power.

[0024] Figure 3 For example, the minimum cleaning time (shown as Figure 3 For RF source powers of 900 W and higher, the minimum cleaning time may be about 10 seconds. When the RF source power is reduced from about 900 W to about 200 W, the cleaning time may increase from at least about 10 seconds to at least about 30 seconds. In some examples, the cleaning time at RF source power < 900 W may be set according to the following formula:

[0025] t<-0.0165·W a +31.192

[0026] where t is the cleaning time.

[0027] Table 1 below shows examples of RF source power, RF bias power, and cleaning times suitable for use with method 100 .

[0028] Table 1

[0029] RF source power (W) RF bias power (W) Cleaning time(s) 1900 0 to 35 1 to 60 1500 0 to 70 1 to 60 1200 0 to 90 1 to 60 900 0 to 125 10 to 60 700 0 to 145 20 to 60 500 0 to 160 22 to 60 400 0 to 175 25 to 60 200 0 to 195 28 to 60

[0030] In block 108, a plasma cleaning chamber generates plasma using the RF source power, RF bias power, and cleaning time settings provided in blocks 104 and 106. The ions of the plasma clean the surface of the integrated circuit. In an example of method 100, the RF source power, RF bias power, and cleaning time are selected so that the cleaning of the integrated circuit produces a relative reflectivity greater than 110% in the surface of the integrated circuit and a damage depth less than 3.5 nanometers in a low-k dielectric material with a dielectric constant <= 3.9. The relative reflectivity can be measured as the ratio of the reflectivity after cleaning to the reflectivity before cleaning. For example, a pilot wafer with blanket Cu can be oxidized, and the reflectivity can be measured to determine the reflectivity before cleaning. After applying method 100 to the pilot wafer, the reflectivity can be measured to determine the reflectivity after cleaning.

[0031] Figure 4An example conventional plasma cleaning system 400 configured to implement remote plasma cleaning of integrated circuits is shown. Plasma cleaning system 400 includes remote plasma cleaning chamber 402. Remote plasma cleaning chamber 402 includes remote plasma source generator 404, vacuum chamber 406, and pedestal 410. A wafer 412 to be cleaned is placed on pedestal 410. Remote plasma source generator 404 excites a gas (e.g., hydrogen) into a plasma. Free radicals of the excited gas flow into vacuum chamber 406 through channel 408. Free radicals of the excited gas react with contaminants on the surface of wafer 412 to clean wafer 412 without physical sputtering. Although plasma cleaning system 400 is capable of cleaning wafer 412 with reduced damage, this system requires the use of remote plasma cleaning chamber 402. This requirement includes new tool hardware or modification of existing tool hardware, which increases the overall cost of integrated circuit manufacturing.

[0032] Figure 5 An example plasma cleaning system 500 (low temperature inductively coupled plasma system) configured to implement the plasma cleaning method 100 according to various examples of the present disclosure is shown. The plasma cleaning system 500 includes an ICP pre-cleaning chamber 502 having a vacuum chamber 506, a cathode 504, and an anode 510. A wafer 512 (which may include any number of integrated circuits) is positioned above the anode 510. The RF source power and RF bias power selected in the method 100 are applied to the cathode 504 and the anode 510, respectively. The cathode 504 emits RF energy into a gas (e.g., hydrogen) contained within or flowing through the vacuum chamber 506 to form a plasma 514. By controlling the RF source power and the RF bias power according to the method 100, the intensity of the plasma 514 and the energy of the ions flowing from the plasma 514 to the wafer 512 are controlled. The positioning of the plasma 514 within the vacuum chamber 506 and the proximity of the plasma 514 to the wafer 512 can also be controlled. By controlling the voltage potential across the dark space sheath 516, the acceleration of the particles toward the surface of the wafer 512 can be controlled to reduce damage to the wafer 512 while providing a desired cleaning level. Thus, the plasma cleaning system 500 can process wafers 512, which may include low-k dielectrics or ultra-low-k dielectrics, thereby limiting damage to acceptable levels and without the expense associated with a remote plasma cleaning system as exemplified by the system 400.

[0033] Figure 6 6 is a flow chart of an example method 600 for manufacturing an integrated circuit according to the plasma cleaning method 100. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown. Figures 7A to 7His a cross-sectional view showing an example of various fabrication stages of IC 700 according to method 600 . Figure 6 and 7A to 7H are mentioned simultaneously in the following discussion.

[0034] The method 600 begins at block 602 where the IC 700 is at an intermediate manufacturing stage and the various electronic components have been formed and interconnected. Fig. 7A An integrated circuit 700 is shown that includes a semiconductor substrate 705 (e.g., bulk silicon or silicon on insulator). A transistor 710 (e.g., an n-type or p-type field effect transistor, a bipolar transistor, or other type of transistor) is disposed on / in the semiconductor substrate 705. A first insulating layer 715 (pre-metal dielectric) has been deposited on the semiconductor substrate 705. A barrier layer 720 (e.g., SiN) is located above the insulating layer 715. A second insulating layer 725 is located on the barrier layer 720 and is etched to provide access to terminals of electronic components of the integrated circuit (e.g., transistor 710). A conductive layer 730 (metal 1) is located above the insulating layer 725 and in a channel formed in the insulating layer 725. The conductive layer 730 may be formed by electroplating copper onto the surface of the insulating layer 725. A trench barrier (e.g., a barrier film based on tantalum and / or cobalt) and a seed layer (e.g., a copper-based film) may be deposited on the insulating layer 725 before forming the conductive layer 730.

[0035] In block 604 , conductive layer 730 is removed over insulating layer 725 , leaving metal 1 lines deposited in insulating layer 725 . Figure 7B Metal 1 lines 730a and 730b are shown after removal of conductive layer 730. In some examples, conductive layer 730 may be removed using chemical mechanical polishing.

[0036] In block 606, a barrier layer and a second insulating layer are deposited over the insulating layer 725. The material applied as the second insulating layer may be a low-k or ultra-low-k dielectric material, such as silicon oxycarbide or an organic polymer. Figure 7C A barrier layer 735 and a third insulating layer 740 are shown deposited on the insulating layer 725 .

[0037] In block 608, insulating layer 740 (and barrier layer 735) is etched to form a via to the metal 1 line. Fig.7D Shown in FIG. 7 are through-hole openings 750a and 750b.

[0038] In block 610, the insulating layer 740 is further etched to form metal 2 openings 755a and 755b in preparation for depositing a second metal layer (metal 2), such as Fig.7E1 and 7E2. Openings 755a and 755b may be wider than openings 750a and 750b. In the case of forming openings 750a, 750b, 755a, and 755b, metal 1 lines 730a and 730b are exposed, and an oxide (e.g., CuO or Cu2O) may be formed on the exposed metal. Such an oxide may be formed, for example, by exposing copper to ambient conditions after forming openings 750a, 750b, 755a, and 755b. Fig.7E1 and 7E2 An exposed metal 1 line is shown with metal oxide 756 formed thereon. Metal oxide 756 may inhibit or prevent the formation of a low resistance connection between the metal 1 line and the later formed metal 2 layer. In order to provide acceptable resistance, the oxide should be removed from the metal 1 line. Plasma cleaning may be applied to remove the oxide, for example by chemically reducing copper oxide to metallic copper. As provided by method 100, this chemical reduction is achieved with low sputtering to reduce damage to the underlying dielectric layer.

[0039] 7F shows the cleaning results using a baseline plasma cleaning process, such as may be produced by a conventional hydrogen sputter etch. The baseline plasma cleaning process employs a relatively high energy plasma that may damage the low-k dielectric of insulating layer 740. FIG7F shows damage 758 to insulating layer 740 that may be caused by sputtering of the baseline plasma cleaning process.

[0040] In order to remove the metal oxide without damaging the insulating layer 740 , in contrast to some conventional methods, the integrated circuit is cleaned in block 612 using the method 100 to remove the metal oxide. Figure 7G1 and 7G2 An integrated circuit having an opening 755a with smooth walls 760 (eg, surface roughness less than 3.5 nm extending into the horizontal surface of the insulating layer 740 ) is illustrated after cleaning using the method 100 .

[0041] In block 614, a second layer of conductive material (eg, Metal 2) is deposited on insulating layer 740 to fill openings 750a, 750b, 755a, and 755b. After depositing Metal 2, a portion thereof may be removed using chemical mechanical polishing, leaving metal-filled openings 750a, 750b, 755a, and 755b. Figure 7H Vias 760a and 760b are shown, as well as metal lines 765a, 765b formed by depositing a Metal 2 layer and polishing away the metal over barrier layer 745.

[0042] Method 600 describes using method 100 to clean an integrated circuit having specific components and features. However, method 100 may be used to clean integrated circuits having any number and / or type of components and features while reducing damage to underlying dielectric materials and reducing the overall cost of integrated circuit manufacturing.

[0043] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally).

[0044] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0045] Although certain elements of the described examples are included in an integrated circuit, in other example embodiments, additional or fewer features may be incorporated into an integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0046] Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. A method of forming an integrated circuit, comprising: forming a first copper feature in a first metal layer over a semiconductor substrate; forming a dielectric layer over the first copper feature; forming an opening in the dielectric layer exposing the first copper feature; as well as The first copper feature is exposed to a hydrogen plasma to chemically reduce copper compounds generated by forming the opening, wherein the hydrogen plasma is supplied with an RF bias power (W). b ) and RF source power (W a ) is generated, where W b <-0.938W a +210.57; and A second copper feature is formed within the opening that is electrically connected to the first copper feature.

2. The method according to claim 1, wherein W a At least 200 watts and no more than 1900 watts.

3. The method according to claim 2, wherein W b At least 0 watts and no more than -0.938W a +210.

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4. The method of claim 1 wherein the first copper feature is exposed to the hydrogen plasma for at least 10 seconds.

5. The method of claim 1 , wherein the first copper feature is exposed to the hydrogen plasma for a cleaning time (t), wherein t>-0.0165·W a +31.192, and W a At least 200 watts and no more than 900 watts.

6. The method of claim 1 wherein the first copper feature is exposed to the hydrogen plasma for 10 seconds and a At least 900 watts and no more than 1900 watts.

7. The method of claim 1, wherein the hydrogen plasma is generated by a low temperature inductively coupled plasma system.

8. The method of claim 1, further comprising generating the hydrogen plasma for no longer than 60 seconds.

9. The method of claim 1, wherein the opening is a first opening, and the method further comprises forming a second opening at a top of the first opening, thereby forming a horizontal surface of the dielectric layer connecting the first opening to the second opening, wherein damage extends less than 3.5 nanometers into the horizontal surface.

10. The method according to claim 1, further comprising limiting W a , W b and a plasma generation time such that a relative reflectivity of a surface of the first copper feature is greater than 110%.

11. A method of forming an integrated circuit, comprising: forming a dielectric layer having a top surface over the semiconductor substrate; forming an opening in the dielectric layer, thereby exposing a metal surface; as well as The surface within the opening is cleaned by a plasma process, the plasma process comprising generating a plasma near the top surface and having an RF bias power (W b ) and RF source power (W a ) of an inductively coupled hydrogen plasma, wherein IN b <-0.938W a +210.57。 12. The method according to claim 11, wherein: The opening is a first opening having a first width, and the method further includes forming a second opening wider than the first opening at a top of the first opening, wherein the cleaning is performed after forming the second opening.

13. The method according to claim 11, wherein W a At least 200 watts and no more than 1900 watts.

14. The method according to claim 13, wherein W b At least 0 watts and no more than -0.938W a +210.

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15. The method of claim 11, further comprising generating the inductively coupled hydrogen plasma for at least 10 seconds.

16. The method of claim 11, further comprising generating the inductively coupled hydrogen plasma for a cleaning time (t), wherein t>-0.0165·W a +31.192, and W a At least 200 watts and no more than 900 watts.

17. The method of claim 11, further comprising generating the inductively coupled hydrogen plasma for 10 seconds, wherein W a At least 900 watts and no more than 1900 watts.

18. The method of claim 11, further comprising generating the inductively coupled hydrogen plasma for no longer than 60 seconds.

19. The method of claim 11, wherein the inductively coupled hydrogen plasma is generated by a low temperature inductively coupled plasma system.

20. The method according to claim 11, further comprising: a The inductively coupled hydrogen plasma is generated at a value of W for a first cleaning time, and at a second W a The inductively coupled hydrogen plasma is generated at a value of a Value greater than the second W a value, and the first cleaning time is less than the second cleaning time.

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