Method for manufacturing a deposition mask

Abstract

A method for manufacturing a deposition mask includes depositing a seed metal layer on a front surface of a silicon substrate; forming a first photoresist pattern on the seed metal layer, the first photoresist pattern defining a plurality of first openings; growing a plating layer in the plurality of first openings of the first photoresist pattern; forming a mask diaphragm by removing the first photoresist pattern and retaining the plating layer; depositing a protective layer on the front surface of the seed metal layer to cover the front surface of the mask diaphragm; forming a second photoresist pattern on the back surface of the silicon substrate, the second photoresist pattern defining a plurality of cell openings respectively corresponding to the plurality of cell masks; exposing the seed metal layer by etching the back surface of the silicon substrate using the second photoresist pattern as a first mask; exposing a back surface of the mask diaphragm by etching the seed metal layer using the second photoresist pattern as a second mask; and removing the protective layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0114409, filed on August 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a method for manufacturing a deposition mask. Background Art

[0004] Wearable devices that form a focus at a short distance from the user's eyes are being developed in the form of glasses or helmets. For example, the wearable device may be a head mounted display (HMD) device or augmented reality (AR) glasses. Such a wearable device provides an AR screen or a virtual reality (VR) screen to the user.

[0005] Wearable devices such as HMD devices or AR glasses may be expected to have a display specification of at least 2000 pixels per inch (PPI) to allow users to use the wearable device for a long time without dizziness. In order to realize wearable devices, organic light emitting diode on silicon (OLEDoS) technology is being proposed as a small high-resolution organic light emitting display device. OLEDoS is a technology for placing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the invention

[0006] Embodiments of the present disclosure provide a method for manufacturing a deposition mask having improved reliability by improving pixel position accuracy (PPA).

[0007] An embodiment of the present disclosure also provides a method for manufacturing a deposition mask, which can improve the alignment accuracy of the mask and prevent spot defects caused by the concave portion of the mask by applying a mask grid (or mask strip), wherein a magnetic metal is applied to the mask grid (or mask strip) to prevent the mask from concave portion.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a deposition mask includes: depositing a seed metal layer on the front surface of a silicon substrate; forming a first photoresist pattern on the seed metal layer, the first photoresist pattern defining a plurality of first openings; growing a plating layer in the plurality of first openings of the first photoresist pattern; forming a mask diaphragm by removing the first photoresist pattern and retaining the plating layer; depositing a protective layer on the front surface of the seed metal layer to cover the front surface of the mask diaphragm; forming a second photoresist pattern on the back surface of the silicon substrate, the second photoresist pattern defining a plurality of unit openings corresponding to a plurality of unit masks respectively; exposing the seed metal layer by etching the back surface of the silicon substrate using the second photoresist pattern as a first mask; exposing the back surface of the mask diaphragm by etching the seed metal layer using the second photoresist pattern as a second mask; and removing the protective layer.

[0009] In an embodiment, the seed metal layer may include a first metal layer including titanium (Ti) and a second metal layer disposed on the first metal layer and including titanium nitride (TiN).

[0010] In an embodiment, the seed metal layer may include a single metal layer including titanium (Ti).

[0011] In an embodiment, the seed metal layer may include a single metal layer including titanium nitride (TiN).

[0012] In an embodiment, the mask diaphragm may include a plurality of mask grids formed by the plating layer, wherein a plurality of mask openings may be respectively defined between adjacently disposed mask grids among the plurality of mask grids to correspond to regions where the first photoresist pattern is removed.

[0013] In an embodiment, a cross-section of each of the plurality of mask grids may have a reverse tapered shape having a width that increases as it moves away from the back surface of the mask spacer toward the front surface of the mask spacer.

[0014] In an embodiment, each of the plurality of mask openings may have a width that decreases as it moves away from the back surface of the mask membrane toward the front surface of the mask membrane.

[0015] In an embodiment, each of the plurality of mask openings may have a first width at the back surface of the mask membrane, and a second width smaller than the first width at the front surface of the mask membrane.

[0016] In an embodiment, the plating layer may include tungsten (W).

[0017] In an embodiment, the plating layer may include copper (Cu).

[0018] According to an embodiment of the present disclosure, a method for manufacturing a deposition mask includes: forming an inorganic layer pattern on the front surface of a silicon substrate, the inorganic layer pattern defining a plurality of first openings; depositing a seed metal layer on the front surface of the silicon substrate to cover the inorganic layer pattern and the plurality of first openings; growing the coating layer on the seed metal layer in such a manner that the height of the coating layer becomes higher than the height of the inorganic layer pattern; polishing a portion of the seed metal layer disposed on the inorganic layer pattern and a portion of the coating layer disposed on the inorganic layer pattern by performing a chemical mechanical polishing (CMP) process; depositing a protective layer on the inorganic layer pattern; forming a photoresist pattern on the back surface of the silicon substrate, the photoresist pattern defining a plurality of unit openings corresponding to a plurality of unit masks respectively; exposing the seed metal layer and the inorganic layer pattern by etching the back surface of the silicon substrate using the photoresist pattern as a first mask; and forming a mask diaphragm by removing the inorganic layer pattern and the protective layer. The mask membrane may include a plurality of mask grids, each of the plurality of mask grids including the plating layer and the seed metal layer covering the plating layer.

[0019] In an embodiment, the seed metal layer may include a first metal layer including titanium (Ti) and a second metal layer disposed on the first metal layer and including titanium nitride (TiN).

[0020] In an embodiment, the seed metal layer may include a single metal layer including titanium (Ti).

[0021] In an embodiment, the seed metal layer may include a single metal layer including titanium nitride (TiN).

[0022] In an embodiment, a plurality of mask openings may be respectively defined between adjacently disposed mask grids among the plurality of mask grids to correspond to regions where the inorganic layer pattern is removed.

[0023] In an embodiment, a cross-section of each of the plurality of mask grids may have a reverse tapered shape having a width that increases as it moves away from a back surface of the mask diaphragm toward a front surface of the mask diaphragm.

[0024] In an embodiment, each of the plurality of mask openings may have a width that decreases as it moves away from the back surface of the mask membrane toward the front surface of the mask membrane.

[0025] In an embodiment, each of the plurality of mask openings may have a first width at the back surface of the mask membrane, and a second width smaller than the first width at the front surface of the mask membrane.

[0026] In an embodiment, the plating layer may include tungsten (W).

[0027] In an embodiment, the plating layer may include copper (Cu).

[0028] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0029] The method for manufacturing a deposition mask according to an embodiment may improve reliability by improving pixel position accuracy (PPA).

[0030] In addition, the method for manufacturing a deposition mask according to an embodiment prevents mask concavity by applying a mask grid (or mask strip) to which a magnetic metal is applied. Therefore, the alignment accuracy of the mask can be improved, and the spot defect caused by the concavity of the mask can be effectively prevented.

[0031] Furthermore, the method for manufacturing a deposition mask according to an embodiment has improved rigidity or durability of the mask, thereby increasing the number of times the mask can be used.

[0032] However, the effects of the embodiments of the present disclosure are not limited to the effects set forth herein. The above and other effects of the embodiments of the present disclosure will become more apparent to those skilled in the art by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features of the embodiments of the present disclosure will become more apparent by describing specific embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] Figure 1 is a perspective view of a head mounted display device according to an embodiment;

[0035] Figure 2 yes Figure 1 An exploded perspective view of an example of a head mounted display device;

[0036] Figure 3 is a perspective view of a head mounted display device according to an embodiment;

[0037] Figure 4 is an exploded perspective view of a display device according to an embodiment;

[0038] Figure 5is a cross-sectional view of an example of a portion of a display panel according to an embodiment;

[0039] Figure 6 is a perspective view of a mask according to an embodiment;

[0040] Figure 7 is a schematic cross-sectional view of a mask according to an embodiment;

[0041] Figures 8 to 16 It is used to illustrate the use of manufacturing Figure 7 A cross-sectional view of a method of forming a mask according to an embodiment shown in FIG.

[0042] Fig.17 is a schematic cross-sectional view of a mask according to an embodiment; and

[0043] Figures 18 to 25 It is used to illustrate the use of manufacturing Fig.17 0047 is a cross-sectional view of a method of forming a mask according to an embodiment shown in FIG. DETAILED DESCRIPTION

[0044] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0045] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0046] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0047] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limited. As used herein, unless the context clearly indicates otherwise, "one", "one (kind / person)", "described (the)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, the reference to "one" element followed by the reference to "described" element in the claim includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" will not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that the terms “comprises and / or comprising” or “includes and / or including” when used in this specification specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, relative terms are also intended to include different orientations of the device. For example, if the device in a figure is turned over, the element described as being on the "lower" side of the other element will then be oriented on the "upper" side of the other element. Therefore, the term "lower" may include both "lower" and "upper" orientations according to the specific orientation of the accompanying drawings. Similarly, if the device in a figure is turned over, the element described as "below" or "under" the other element will then be oriented as "above" the other element. Therefore, the term "below..." or "under..." may include both "above..." and "below..." orientations.

[0049] As used herein, "approximately" or "approximately" is inclusive of the stated value and means within an acceptable deviation range of the particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0051] Embodiments are described herein with reference to cross-sectional views which are schematic diagrams of idealized embodiments. Therefore, variations in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but rather include shape deviations caused by, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the current claims.

[0052] The features of each of the various embodiments of the present disclosure may be combined with each other in part or in whole, and may technically interact with each other in various ways, and the various embodiments may be implemented independently of each other, or may be implemented together in relation to each other.

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of a head mounted display device according to an embodiment. Figure 2 yes Figure 1 An exploded perspective view of an example of a head mounted display device.

[0055] Reference Figure 1 and Figure 2 The head mounted display device 1 according to the embodiment includes a first display device 10_1, a second display device 10_2, a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a headband 140, a middle frame 160, a first optical member 151, a second optical member 152, a control circuit board 170, and a connector. The display device housing 110 may have a rectangular shape having a long side extending in the fourth direction X and a short side extending in the fifth direction Y, and may have a thickness in the sixth direction Z, and the sixth direction Z may be substantially perpendicular to a plane defined by the fourth direction X and the fifth direction Y. The embodiments of the present disclosure are not limited thereto.

[0056] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is similar to the one to be referred to. Figure 4 and Figure 5 The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to as Figure 4 and Figure 5 The description given is used instead.

[0057] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0058] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 supports and fixes the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0059] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source received from the outside into digital video data, and transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0060] In an embodiment, the control circuit board 170 may transmit digital video data corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1, and transmit digital video data corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0061] The display device housing 110 receives or houses the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is positioned to cover the open surface of the display device housing 110. The housing cover 120 may include a first eyepiece 131 on which the user's left eye is positioned and a second eyepiece 132 on which the user's right eye is positioned. In an embodiment, as shown in FIG. Figure 1 and Figure 2As shown in , the first eyepiece 131 and the second eyepiece 132 are provided or arranged separately, but the embodiments of the present disclosure are not limited thereto. Optionally, the first eyepiece 131 and the second eyepiece 132 can also be combined into one.

[0062] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 151 through the first eyepiece 131, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 152 through the second eyepiece 132.

[0063] The headband 140 fixes the display device housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 remain positioned on the user's left eye and right eye, respectively. In an embodiment where it is desired that the display device housing 110 be lightweight and small, the head mounted display device 1 may include a Figure 3 , the eyeglass frames are shown in FIG. 1 rather than the headband 140 .

[0064] In an embodiment, the head mounted display device 1 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a wireless fidelity (Wi-Fi) module, or a Bluetooth module.

[0065] Figure 3 is a perspective view of a head mounted display device according to an embodiment.

[0066] Reference Figure 3 The head mounted display device 1_1 according to the embodiment may be a display device in which the display device housing 120_1 is implemented as a light-weight and small display device in the form of glasses. The head mounted display device 1_1 according to the embodiment may include a display device 10_3, a left-eye lens 311, a right-eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 120_1.

[0067] Figure 3 The display device 10_3 shown in FIG. Figure 4 and Figure 5 Therefore, the description of the display device 10_3 will be referred to as Figure 4 and Figure 5The description given is used instead.

[0068] The display device housing 120_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. An image displayed in the display device 10_3 may be magnified by the optical member 320, its optical path may be converted by the optical path conversion member 330, and then provided to the right eye of the user through the right eye lens 312. Therefore, the user may view an augmented reality image composed of a virtual image displayed in the display device 10_3 and a real image viewed through the right eye lens 312 through the right eye.

[0069] In an embodiment, Figure 3 As shown in , the display device housing 120_1 can be disposed at the right end of the support frame 350, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the display device housing 120_1 can also be disposed at the left end of the support frame 350. In such an embodiment, the image of the display device 10_3 can be provided to the left eye of the user. Optionally, the display device housing 120_1 can be disposed at both the left and right ends of the support frame 350. In such an embodiment, the user can view the image displayed in the display device 10_3 through both the left eye and the right eye.

[0070] Figure 4 is an exploded perspective view of a display device according to an embodiment.

[0071] Reference Figure 4 The display device 10 according to the embodiment is a device for displaying a moving image or a still image. The display device 10 according to the embodiment can be applied to a portable electronic device (such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, a laptop computer, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC)). In an embodiment, for example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. Optionally, the display device 10 can be applied to a smart watch, a watch phone, and a head-mounted display for realizing virtual reality and augmented reality.

[0072] The display device 10 according to the embodiment includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0073] The display panel 410 may have a planar shape similar to a quadrilateral. In an embodiment, for example, the display panel 410 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and having long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 410, each corner where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be rounded with a predetermined curvature, or may be at a right angle. The planar shape of the display panel 410 is not limited to a quadrilateral shape, but may also be similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may correspond to the planar shape of the display panel 410, but the embodiments of the present disclosure are not limited thereto.

[0074] The display panel 410 includes a display area where an image is displayed and a non-display area where no image is displayed.

[0075] The display area includes a plurality of pixels, and each of the pixels includes a plurality of sub-pixels SP1 to SP3 (see Figure 5 ). The sub-pixels SP1 to SP3 include a plurality of pixel transistors. The pixel transistors may be formed by a semiconductor process and may be disposed on a semiconductor substrate SSUB (see Figure 5 In an embodiment, for example, the pixel transistor may be formed as a complementary metal oxide semiconductor (CMOS).

[0076] The heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3 which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be provided on a surface (e.g., a back surface) of the display panel 410. The heat dissipation layer 420 dissipates heat generated in the display panel 410. The heat dissipation layer 420 may include graphite and a metal layer having high thermal conductivity (such as silver (Ag), copper (Cu), or aluminum (Al)).

[0077] The circuit board 430 may be electrically connected to a plurality of pads in the pad region of the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board including or made of a flexible material, or may be a flexible film. Figure 4 4 shows the circuit board 430 in an unfolded state, but the circuit board 430 may be bent. In the bent state, one end of the circuit board 430 may be positioned on the back surface of the display panel 410. The one end of the circuit board 430 may be an end opposite to the other end of the circuit board 430 connected to the pad in the pad area of ​​the display panel 410 by using a conductive adhesive member.

[0078] The driving circuit 440 may receive digital video data and a timing signal from the outside, and may generate a scanning timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 according to the timing signal.

[0079] The power supply circuit 450 may generate a plurality of panel driving voltages according to a power supply voltage received from the outside. In an embodiment, for example, the power supply circuit 450 may generate a first driving voltage (e.g., a low driving voltage), a second driving voltage (e.g., a high driving voltage), and a third driving voltage (e.g., an initialization voltage), and supply the first to third driving voltages to the display panel 410.

[0080] Each of the driving circuit 440 and the power supply circuit 450 may be formed as an integrated circuit and attached to a surface of the circuit board 430 .

[0081] Figure 5 is a cross-sectional view of an example of a portion of a display panel according to an embodiment. Specifically, Figure 5 A partial cross-sectional structure of a display area including a plurality of sub-pixels SP1 to SP3 is shown.

[0082] Reference Figure 5 , also refer to Figure 4 , an embodiment of the display panel 410 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizer (not shown).

[0083] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the pixel transistors PTR.

[0084] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be defined or provided on the upper surface of the semiconductor substrate SSUB. The well region WA may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. In an embodiment, for example, in the case where the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, in the case where the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0085] Each of the well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0086] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of each pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the opposite side of the gate electrode GE.

[0087] Each of the well regions WA also includes a first lightly doped impurity region disposed between the channel region CH and the source region SA and a second lightly doped impurity region disposed between the channel region CH and the drain region DA. The first lightly doped impurity region may be a region having a lower impurity concentration than the source region SA. The second lightly doped impurity region may be a region having a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first lightly doped impurity region and the second lightly doped impurity region. Therefore, the length of the channel region CH of each pixel transistor PTR may be increased, thereby effectively preventing a breakdown phenomenon and a hot carrier phenomenon caused by a short channel.

[0088] The first semiconductor insulating layer SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be based on silicon carbonitride (SiCN) or silicon oxide (SiO x ) of the inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0089] The second semiconductor insulating layer SINS2 may be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be based on silicon oxide (SiO x ) of the inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0090] The contact terminal CTE may be disposed on the second semiconductor insulating layer SINS2. Each of the contact terminals CTE may be connected to at least one selected from the gate electrode GE, the source region SA, and the drain region DA of the pixel transistor PTR by forming or defining a hole through the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The contact terminal CTE may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0091] The third semiconductor insulating layer SINS3 may be disposed on a side surface of each of the contact terminals CTE. The upper surface of each of the contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be based on silicon oxide (SiO x ) of the inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0092] In an embodiment, the semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as a polyimide substrate). In such an embodiment, the thin film transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that cannot be bent, and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0093] The light emitting element back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating layers INS1 to INS10 disposed between the first to eighth metal layers ML1 to ML8.

[0094] The first metal layer ML1 to the eighth metal layer ML8 are used to realize the circuit of the first sub-pixel SP1 by connecting the contact terminal CTE exposed in the semiconductor backplane SBP. That is, only the first transistor to the sixth transistor are formed in the semiconductor backplane SBP, and the connection of the first transistor to the sixth transistor and the first capacitor and the second capacitor is realized through the first metal layer ML1 to the eighth metal layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor and the source region corresponding to the source electrode of the fifth transistor and the first electrode of the light-emitting element is also realized through the first metal layer ML1 to the eighth metal layer ML8.

[0095] The first interlayer insulating layer INS1 may be disposed on the semiconductor backplane SBP. The first vias VA1 may penetrate or be disposed through the first interlayer insulating layer INS1 and may be respectively connected to the contact terminals CTE exposed in the semiconductor backplane SBP. The first metal layer ML1 may be disposed on the first interlayer insulating layer INS1 and may be respectively connected to the first vias VA1.

[0096] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. The second via holes VA2 may penetrate or be disposed through the second interlayer insulating layer INS2 and may be respectively connected to the exposed first metal layers ML1. The second metal layer ML2 may be disposed on the second interlayer insulating layer INS2 and may be respectively connected to the second via holes VA2.

[0097] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the second metal layer ML2. The third vias VA3 may penetrate or be disposed through the third interlayer insulating layer INS3 and may be respectively connected to the exposed second metal layers ML2. The third metal layer ML3 may be disposed on the third interlayer insulating layer INS3 and may be respectively connected to the third vias VA3.

[0098] The fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. The fourth vias VA4 may penetrate or be disposed through the fourth interlayer insulating layer INS4 and may be respectively connected to the exposed third metal layers ML3. The fourth metal layers ML4 may be disposed on the fourth interlayer insulating layer INS4 and may be respectively connected to the fourth vias VA4.

[0099] The fifth interlayer insulating layer INS5 may be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. The fifth vias VA5 may penetrate or be disposed through the fifth interlayer insulating layer INS5 and may be respectively connected to the exposed fourth metal layers ML4. The fifth metal layers ML5 may be disposed on the fifth interlayer insulating layer INS5 and may be respectively connected to the fifth vias VA5.

[0100] The sixth interlayer insulating layer INS6 may be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. The sixth vias VA6 may penetrate or be disposed through the sixth interlayer insulating layer INS6 and may be respectively connected to the exposed fifth metal layers ML5. The sixth metal layers ML6 may be disposed on the sixth interlayer insulating layer INS6 and may be respectively connected to the sixth vias VA6.

[0101] The seventh interlayer insulating layer INS7 may be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. The seventh vias VA7 may penetrate or be disposed through the seventh interlayer insulating layer INS7 and may be respectively connected to the exposed sixth metal layer ML6. The seventh metal layer ML7 may be disposed on the seventh interlayer insulating layer INS7 and may be respectively connected to the seventh vias VA7.

[0102] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. The eighth vias VA8 may penetrate or be disposed to pass through the eighth interlayer insulating layer INS8 and may be respectively connected to the exposed seventh metal layer ML7. The eighth metal layer ML8 may be disposed on the eighth interlayer insulating layer INS8 and may be respectively connected to the eighth vias VA8.

[0103] The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may include or be made of substantially the same material as each other. The first metal layer ML1 to the eighth metal layer ML8 and the first via hole VA1 to the eighth via hole VA8 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or may be made of an alloy including any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd). The first via hole VA1 to the eighth via hole VA8 may include or be made of substantially the same material as each other. In an embodiment, each of the first to eighth interlayer insulating layers INS1 to INS8 may be based on silicon oxide (SiO x ) of the inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0104] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same as each other. In an embodiment, for example, the thickness of the first metal layer ML1 may be about The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be about 100 Å. And the thickness of the first via hole VA1, the thickness of the second via hole VA2, the thickness of the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6 may each be about 1000 Å.

[0105] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 may each be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same as each other. In an embodiment, for example, the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be approximately The thickness of the seventh via hole VA7 and the thickness of the eighth via hole VA8 may each be about

[0106] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. In an embodiment, the ninth interlayer insulating layer INS9 may be based on silicon oxide (SiO x ) of the inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0107] The ninth via hole VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth metal layer ML8, respectively. In an embodiment, the ninth via hole VA9 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. In an embodiment, for example, the thickness of the ninth via hole VA9 may be about

[0108] The first reflective electrode RL1 may be disposed on the ninth interlayer insulating layer INS9 and may be connected to the ninth via holes VA9, respectively. The first reflective electrode RL1 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0109] The second reflective electrodes RL2 may be disposed on the first reflective electrodes RL1, respectively. The second reflective electrodes RL2 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. In an embodiment, for example, the second reflective electrode RL2 may be titanium nitride (TiN).

[0110] In the first sub-pixel SP1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light-emitting element layer to the fourth reflective electrode RL4, so as to facilitate the reflection of the light of the first color emitted from the first light-emitting element layer of the first sub-pixel SP1. In an embodiment, the step layer STPL may be based on silicon carbon nitride (SiCN) or silicon oxide (SiO x ) of the inorganic layer, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the thickness of the step layer STPL may be about

[0111] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In each of the second subpixel SP2 and the third subpixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0112] In an embodiment, at least one selected from the first to third reflective electrodes RL1 to RL3 may be omitted.

[0113] The fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may be a layer that reflects light from the first light emitting element layer to the third light emitting element layer. The fourth reflective electrode RL4 may include a metal having a high reflectivity to facilitate reflection of light. The fourth reflective electrode RL4 may include aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy as an alloy of silver (Ag), palladium (Pd) and copper (Cu), or an APC alloy and an indium tin oxide stacked structure (ITO / APC / ITO), or made of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy as an alloy of silver (Ag), palladium (Pd) and copper (Cu), or an APC alloy and an indium tin oxide stacked structure (ITO / APC / ITO), but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the thickness of each of the fourth reflective electrodes RL4 may be about 500 Å.

[0114] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9 and the fourth reflective electrode RL4. In an embodiment, the tenth interlayer insulating layer INS10 may be based on silicon oxide (SiO x ) of the inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0115] The tenth via hole VA10 may penetrate or be disposed to pass through the tenth interlayer insulating layer INS10, and may be connected to the exposed fourth reflective electrode RL4, respectively. The tenth via hole VA10 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. Due to the step layer STPL, the thickness of the tenth via hole VA10 in the first subpixel SP1 may be less than the thickness of the tenth via hole VA10 in each of the second subpixel SP2 and the third subpixel SP3. For example, the thickness of the tenth via hole VA10 in the first subpixel SP1 may be about 1000 Å. And the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 may be about 1000 Å.

[0116] The light emitting element layer EML may be disposed on the light emitting element back panel EBP. The light emitting element layer EML may include a light emitting element and a pixel defining layer PDL each including a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0117] The first electrode AND of each of the light emitting elements may be disposed on the tenth interlayer insulating layer INS10 and may be connected to the tenth via VA10. The first electrode AND of each of the light emitting elements may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. In an embodiment, for example, the first electrode AND of each of the light emitting elements may be titanium nitride (TiN).

[0118] The pixel defining layer PDL may be disposed on a portion of the first electrode AND of each of the light emitting elements. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the light emitting elements. The pixel defining layer PDL defines first to third emission areas EA1 to EA3.

[0119] The first emission area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT in the first sub-pixel SP1 are sequentially stacked to emit light. The second emission area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT in the second sub-pixel SP2 are sequentially stacked to emit light. The third emission area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT in the third sub-pixel SP3 are sequentially stacked to emit light.

[0120] The pixel defining layer PDL may include first to third pixel defining layers PDL1 to PDL3. The first pixel defining layer PDL1 may be disposed on the edge of the first electrode AND of each of the light emitting elements or disposed to cover the edge of the first electrode AND of each of the light emitting elements, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. In an embodiment, each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be based on silicon oxide (SiO x ), but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the thickness of the first pixel defining layer PDL1, the thickness of the second pixel defining layer PDL2, and the thickness of the third pixel defining layer PDL3 may each be about 1000 Å.

[0121] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0122] The intermediate layer IL may have a cascade structure including a plurality of intermediate layers IL1 to IL3 that respectively emit light of different colors or emit light in different wavelength ranges. In an embodiment, for example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0123] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer, and a first electron transport layer are sequentially stacked, and the first organic light emitting layer emits light of a first color. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer, and a second electron transport layer are sequentially stacked, and the second organic light emitting layer emits light of a third color. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer, and a third electron transport layer are sequentially stacked, and the third organic light emitting layer emits light of a second color.

[0124] The intermediate layer IL may cover the first electrode AND in each opening of the pixel defining layer PDL and cover the pixel defining layer PDL between adjacent sub-pixels SP1 to SP3 , but may be partially disconnected.

[0125] In an embodiment where the intermediate layer IL is disconnected between adjacent sub-pixels SP1 to SP3, leakage current between adjacent sub-pixels SP1 to SP3 can be effectively prevented, and a color interference phenomenon can be effectively prevented. The color interference phenomenon refers to, for example, a phenomenon in which a red sub-pixel adjacent to a blue sub-pixel is unexpectedly lit while a blue sub-pixel emits light. The color interference phenomenon occurs due to leakage current, and may occur when a blue sub-pixel and a red sub-pixel having a large pixel drive voltage difference are adjacent to each other. For example, leakage current refers to a phenomenon in which, while a drive current is supplied to a light-emitting element of a blue sub-pixel to light up the blue sub-pixel, a portion of the drive current is transmitted to a red sub-pixel through at least some conductive layers of the intermediate layer IL. If leakage current occurs, the red sub-pixel may be unexpectedly lit while the blue sub-pixel is lit.

[0126] The number of the intermediate layers IL1 to IL3 emitting light of different colors is not limited to Figure 5 In an embodiment, for example, the intermediate layer IL may include two intermediate layers. In such an embodiment, at least one intermediate layer selected from the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other intermediate layer may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In such an embodiment, a charge generation layer may be disposed between the two intermediate layers to supply electrons to at least one intermediate layer selected from the two intermediate layers and to supply holes to the other intermediate layer.

[0127] In an embodiment, the first to third intermediate layers IL1 to IL3 may all be disposed on Figure 5 In the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the first intermediate layer IL1 may be disposed in the first emission area EA1, and may not be disposed in the second emission area EA2 and the third emission area EA3. In such an embodiment, the second intermediate layer IL2 may be disposed in the second emission area EA2, and may not be disposed in the first emission area EA1 and the third emission area EA3. In such an embodiment, the third intermediate layer IL3 may be disposed in the third emission area EA3, and may not be disposed in the first emission area EA1 and the second emission area EA2. In this case, the first to third color filters CF1 to CF3 of the optical layer OPL may be omitted.

[0128] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of grooves. The second electrode CAT may include a transparent conductive material (TCO) that can transmit light (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag) or an alloy of Mg and Ag), or be made of a transparent conductive material (TCO) that can transmit light (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag) or an alloy of Mg and Ag). In an embodiment in which the second electrode CAT is made of a semi-transmissive conductive material, the light output efficiency of each of the first to third sub-pixels SP1 to SP3 may be improved by a microcavity effect.

[0129] The encapsulation layer TFE may be disposed on the light emitting element layer EML. The encapsulation layer TFE may include one or more inorganic layers to prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign matter (such as dust). In an embodiment, for example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0130] The first encapsulation inorganic layer TFE1 may be disposed on the second electrode CAT, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. Each of the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be a layer in which silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (Al x O y ) layers are alternately stacked. The encapsulation organic layer TFE2 may be a single layer. Alternatively, the encapsulation organic layer TFE2 may be an organic layer made of or including an organic material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin).

[0131] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL together. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent resin.

[0132] The optical layer OPL includes a plurality of color filters CF1 to CF3, a plurality of lenses LNS, and a filling layer FIL. The color filters CF1 to CF3 may include first to third color filters CF1 to CF3. The first to third color filters CF1 to CF3 may be disposed on the adhesive layer ADL.

[0133] The first color filter CF1 may overlap with the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of the first color, that is, light of a blue wavelength band. The blue wavelength band may be about 370 nanometers (nm) to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0134] The second color filter CF2 may overlap with the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of the second color, that is, light of a green wavelength band. The green wavelength band may be about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0135] The third color filter CF3 may overlap with the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color, that is, light of a red wavelength band. The red wavelength band may be about 600nm to about 750nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0136] Lenses LNS may be disposed on the first, second, and third color filters CF1, CF2, and CF3, respectively. Each of the lenses LNS may be a structure for increasing a ratio of light directed toward the front of the display device 10. Each of the lenses LNS may have an upwardly convex cross-sectional shape.

[0137] The filling layer FIL may be disposed on the lens LNS. The filling layer FIL may have a predetermined refractive index so that light may travel in the third direction DR3 at an interface between the lens LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer made of or including an organic material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin).

[0138] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer substrate (such as a resin substrate). In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In such an embodiment, the filling layer FIL may be used to bond the cover layer CVL. In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. In an embodiment where the cover layer CVL is a polymer substrate (such as a resin substrate), the cover layer CVL may be directly applied to the filling layer FIL.

[0139] A polarizer (not shown) may be disposed on the surface of the cover layer CVL. The polarizer may be a structure for preventing visibility reduction caused by reflection of external light. The polarizer may include a linear polarizer and a phase delay film. In an embodiment, for example, the phase delay film may be a quarter wave plate (λ / 4 plate), but the embodiments of the present disclosure are not limited thereto. If the visibility reduction caused by reflection of external light is sufficiently improved by the first color filter CF1 to the third color filter CF3, the polarizer may be omitted.

[0140] Figure 6 is a perspective view of a mask according to an embodiment. Figure 6 1 is a perspective view showing a state in which one unit mask UM is separated from a plurality of unit masks UM. Figure 6 The mask of the embodiment shown in FIG. 1 can be used to deposit reference Figure 5 In the process of at least a portion of the intermediate layer IL of the display panel 410 described above, for example, the intermediate layer IL may be configured to emit light of a different color in each of the sub-pixels SP1 to SP3.

[0141] Reference Figure 6 , also refer to Figure 4 , the mask MK (also referred to as a deposition mask MK) may include a mask frame MF and a plurality of unit masks UM. A plurality of unit openings COP formed to pass through the mask frame MF along a thickness direction (e.g., a third direction DR3) of the mask MK may be defined in the mask frame MF. The unit masks UM may be arranged to correspond to the unit openings COP, respectively. Each of the unit openings COP may correspond to one display panel 410. That is, one unit mask UM may be used in a process of depositing one display panel 410. In the present disclosure, the term "unit mask UM" may be replaced with a term such as "mask unit UM".

[0142] Each of the unit masks UM may include a mask body MP and a plurality of holes OP. The holes OP may be formed in the mask body MP and arranged in a matrix form. The holes OP may be defined as passing through the unit mask UM along the thickness direction (e.g., the third direction DR3) of the mask MK. The mask body MP of each of the unit masks UM may include a plurality of first mask grids extending along a first direction DR1 and spaced apart from each other. In addition, each of the unit masks UM may include a plurality of second mask grids extending along a second direction DR2 perpendicular to the first direction DR1 and spaced apart from each other. The first mask grid and the second mask grid may intersect with each other to define the holes OP. In the present disclosure, the term "mask body MP" may be replaced with terms such as "mask frame" or "mask support". In the present disclosure, the term "mask grid" may be replaced with terms such as "mask rib". In the present disclosure, a combination of mask grids may be referred to as terms such as "mask diaphragm" or "diaphragm". For example, a membrane may be a term indicating a portion serving as a blocking portion in one unit mask.

[0143] The unit mask UM may be disposed on the mask frame MF. The unit mask UM and the cell opening COP may be disposed to correspond to each other one by one.

[0144] In embodiments, an area of ​​the mask main body MP of each unit mask UM may be substantially the same as an area of ​​each unit opening COP on a plane (eg, a plane defined by the first direction DR1 and the second direction DR2 ).

[0145] Figure 7 is a schematic cross-sectional view of a mask according to an embodiment. Figure 7 The unit mask UM (see Figure 6 )one of the.

[0146] Reference Figure 7 , also refer to Figure 4 and Figure 6 , the mask MK according to the embodiment can be a silicon mask in which a mask diaphragm 730 (i.e., a mask grid 731) is provided or formed on a silicon substrate 710 (i.e., a silicon wafer substrate). Fine metal masks (FMMs) using invar sheets have been widely used as conventional deposition masks. However, FMMs have a problem in which the pixel position accuracy (PPA) performance of FMMs is insufficient to manufacture high-resolution pixels. The mask MK according to the embodiment can improve the alignment accuracy by forming a mask diaphragm 730 on a silicon substrate 710, and can be used to manufacture an organic light emitting diode on silicon (OLEDoS) panel having a high-resolution pixel of about 2000 pixels per inch (PPI) or more.

[0147] The mask MK (i.e., the unit mask UM) according to the embodiment may include a silicon substrate 710 serving as a mask body MP, a seed metal layer 720 disposed on the silicon substrate 710, and a mask membrane 730 disposed on the seed metal layer 720, the mask membrane 730 defining a plurality of holes OP (i.e., mask openings) passing through the mask membrane 730. The silicon substrate 710 may be provided with a unit opening COP defined in the silicon substrate 710 to overlap with the plurality of holes OP.

[0148] The seed metal layer 720 may include a first metal layer 721 and a second metal layer 722, the first metal layer 721 including or containing titanium (Ti), and the second metal layer 722 is disposed on the first metal layer 721 and includes or contains titanium nitride (TiN). According to another embodiment, the seed metal layer 720 may be a single metal layer including or containing titanium (Ti). According to another embodiment, the seed metal layer 720 may be a single metal layer including titanium nitride (TiN). The metal material forming the seed metal layer 720 is not limited to titanium (Ti) and titanium nitride (TiN), but may be any metal material as long as the seed metal layer 720 can be used for an electroplating method or an electroforming method. In an embodiment, for example, the seed metal layer 720 may include copper (Cu).

[0149] Each of the mask grids 731 may include a plating layer formed by a damascene process using, for example, an electroplating method or an electroforming method.

[0150] Each of the mask grids 731 may have a reverse tapered shape having a width that increases from the back surface 7311 to the upper surface 7312. Here, the back surface 7311 of each of the mask grids 731 may be a surface facing the deposition source DS, and the upper surface 7312 of each of the mask grids 731 may be a surface facing the deposition target substrate (e.g., the display panel 410 (i.e., the backplane substrate)). The mask grid 731 according to the embodiment may reduce shadow defects due to its reverse tapered shape. In an embodiment, for example, the tapered angle (taperangle) (e.g., the tapered angle A1) of each mask grid 731 may be less than or equal to the deposition incident angle, which is an angle from the deposition source DS to the hole OP. In an embodiment, for example, the tapered angle of each mask grid 731 may be designed or provided to be in the range of about 60 degrees to about 90 degrees, the width L1 of the cross section of each mask grid 731 may be less than or equal to about 10 micrometers (μm), and the thickness L2 of the cross section of each mask grid 731 may be less than or equal to about 15 μm. The mask MK according to an embodiment may reduce shadow defects by reducing the thickness L2 of each mask grid 731 and providing each mask grid 731 to have a reverse tapered shape. The hole OP (i.e., the mask opening) has a width that decreases as it moves away from the back surface of the mask diaphragm 730 toward the front surface of the mask diaphragm 730. The hole OP (i.e., the mask opening) has a first width at the back surface of the mask diaphragm 730, and has a second width smaller than the first width at the front surface of the mask diaphragm 730.

[0151] The mask grid 731 according to the embodiment may have a sag problem because its thickness is reduced to less than or equal to about 15 μm. In an embodiment, the mask grid 731 according to the embodiment includes a magnetic metal or is made of a magnetic metal. Therefore, a magnetic member (not shown) can be used inside a depositor (not shown) to effectively prevent the sag of the mask grid 731, and the alignment accuracy can be improved.

[0152] Figures 8 to 16 It is used to illustrate the use of manufacturing Figure 7 0047 is a cross-sectional view of a method of forming a mask according to an embodiment shown in FIG.

[0153] In reference Figures 8 to 16 The mask MK described (see Figure 6 ) before or after each manufacturing process, other processes in the method for manufacturing the mask MK involved in the present disclosure may be added. Figures 8 to 16 Before or after each manufacturing process of the mask MK described, other processes in the manufacturing process of the mask MK known in the art may be added.

[0154] Figure 8FIG. 2 shows a process of depositing a seed metal layer 720 on a silicon substrate 710 (hereinafter referred to as a first-first process). Figure 8 , the seed metal layer 720 may be used as a seed and barrier metal to prevent the plated layer from penetrating into the silicon substrate 710 when electroplating is performed. The seed metal layer 720 may be a single layer or a multilayer including at least one metal material selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), gold (Au), and molybdenum (Mo) or made of at least one metal material selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), gold (Au), and molybdenum (Mo).

[0155] The seed metal layer 720 may include a first metal layer 721 and a second metal layer 722, the first metal layer 721 including or containing titanium (Ti), and the second metal layer 722 is disposed on the first metal layer 721 and includes or contains titanium nitride (TiN). According to another embodiment, the seed metal layer 720 may be a single metal layer including titanium (Ti) (e.g., a single layer of titanium (Ti)). According to another embodiment, the seed metal layer 720 may be a single metal layer including titanium nitride (TiN) (e.g., a single layer of titanium nitride (TiN)). The metal material forming the seed metal layer 720 is not limited to titanium (Ti) and titanium nitride (TiN), but may be any metal material as long as it is used for an electroplating method or an electroforming method. In another embodiment, for example, the seed metal layer 720 may include copper (Cu).

[0156] The seed metal layer 720 may be formed by a physical vapor deposition process such as sputtering or a chemical vapor deposition process such as chemical vapor deposition (CVD) or plasma chemical vapor deposition (PECVD).

[0157] In the present disclosure, the seed metal layer 720 may be referred to as the same term as a “preliminary conductive layer”.

[0158] Fig. 9 A process of forming a first photoresist pattern 910 on the seed metal layer 720 as a process performed after the first-first process (hereinafter referred to as a first-second process) is shown. Fig. 9, a first photoresist pattern 910 may be formed by applying a photoresist composition on the seed metal layer 720 and then patterning the photoresist composition. The cross section of the first photoresist pattern 910 may have a regular tapered shape having a width that decreases as it moves away from the seed metal layer 720. In an embodiment, for example, the first photoresist pattern 910 may have a regular tapered shape by patterning a positive photoresist composition. The cross section of the first photoresist pattern 910 has a regular tapered shape so that the mask diaphragm 730 (see Figure 7 ) has a cross-section of a coating having a reverse tapered shape.

[0159] According to an embodiment, the first photoresist pattern 910 may be patterned to define a plurality of first openings 911. The plurality of first openings 911 may expose the seed metal layer 720 and form a substrate for growing the plating layer 1010 (see Fig.10 ) space.

[0160] Fig.10 A process of growing the plating layer 1010 is shown as a process performed after the first-second process (hereinafter referred to as the first-third process). Fig.10 The plating layer 1010 may include tungsten (W) or copper (Cu). The plating layer 1010 may be grown inside the plurality of first openings 911 of the first photoresist pattern 910. The height of the plating layer 1010 may be substantially the same as the height of the first photoresist pattern 910.

[0161] Fig.11 FIG. 1 shows the removal of the first photoresist pattern 910 as a process performed after the first to third processes (see FIG. 1 ). Fig.10 ) processes (hereinafter referred to as the first to fourth processes). Fig.11 , also refer to Figure 6 and Figure 7 After forming the plating layer 1010, the first photoresist pattern 910 may be removed. The plating layer 1010 remaining after removing the first photoresist pattern 910 may be used as the mask diaphragm 730. That is, the plating layer 1010 remaining after removing the first photoresist pattern 910 may be the mask grid 731 of the mask diaphragm 730.

[0162] According to an embodiment, since the first photoresist pattern 910 used as a mold in which the plating layer 1010 is grown has a regular tapered shape, the cross section of each of the mask grids 731 of the mask diaphragm 730 may have a reverse tapered shape. In an embodiment, for example, the tapered angle of the mask grid 731 may be designed or provided to be in the range of about 60 degrees to about 90 degrees, the width of the cross section of the mask grid 731 may be less than or equal to about 10 μm, and the thickness of the cross section of the mask grid 731 may be less than or equal to about 15 μm. The mask MK according to an embodiment may reduce shadow defects by reducing the thickness of the mask grid 731 and forming the mask grid 731 to have a reverse tapered shape.

[0163] Fig.12 The process of forming the mask spacer 730 (see FIG. Figure 7 ) on the front surface of the protective layer 1210 (hereinafter referred to as the first to fifth processes). Fig.12 The protection layer 1210 can be used to prevent damage to the mask membrane 730 in subsequent processes.

[0164] The protective layer 1210 may include an inorganic layer including silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ) and aluminum oxide (Al x O y )

[0165] The protective layer 1210 may include an organic layer including at least one selected from acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0166] The protective layer 1210 may be a multi-layer including the above-mentioned inorganic layer and the above-mentioned organic layer.

[0167] Fig.13 A process of forming a second photoresist pattern 1310 on the back surface of the silicon substrate 710 (hereinafter referred to as a first to sixth process) is shown as a process performed after the first to fifth processes. Fig.13 The second photoresist pattern 1310 may define a second opening, and the second opening is used to define a plurality of unit masks UM (see Figure 6 ) corresponds to each of the unit openings COP. In an embodiment, for example, each of the second openings may correspond to a corresponding one of the unit openings COP.

[0168] Fig.14 A process of etching the back surface of the silicon substrate 710 (hereinafter referred to as the first to seventh process) is shown as a process performed after the first to sixth processes. Fig.14 , the silicon substrate 710 may be etched from a rear direction using the second photoresist pattern 1310. Here, the rear direction refers to a direction in which the deposition source DS is positioned. The seed metal layer 720 may be exposed from the etched back surface of the silicon substrate 710. When the silicon substrate 710 is etched, the seed metal layer 720 may serve as an etching stopper.

[0169] Fig.15 A process of etching the seed metal layer 720 is shown as a process performed after the first to seventh processes (hereinafter referred to as the first to eighth processes). Fig.15 , also refer to Figure 6 and Figure 7 , the portion of the seed metal layer 720 corresponding to the cell opening COP (or exposed through the cell opening COP) can be etched using the second photoresist pattern 1310 as a mask. Therefore, the portion of the seed metal layer 720 overlapping the mask grid 731 configuring the mask diaphragm 730 is removed, and the mask diaphragm 730 formed by the plating layer 1010 and the protective layer 1210 covering the mask diaphragm 730 are retained.

[0170] Fig.16 FIG. 1 shows the removal of the second photoresist pattern 1310 (see FIG. 10 ) as a process performed after the first to eighth processes. Fig.15 ) and protective layer 1210 (see Fig.15 ) processes (hereinafter referred to as the first to ninth processes). Fig.16 , also refer to Figure 6 , the manufacturing process of the mask MK according to the embodiment may be completed by removing the second photoresist pattern 1310 and the protective layer 1210. Therefore, the mask diaphragm 730 formed by the plating layer 1010 may be disposed in the mask MK, and the seed metal layer 720 and a portion of the plating layer 1010 disposed on the seed metal layer 720 may be disposed in the mask body MP except for the cell opening COP.

[0171] The method for manufacturing the deposition mask MK according to the embodiment may improve reliability by improving pixel position accuracy (PPA).

[0172] In addition, the method for manufacturing a deposition mask according to an embodiment effectively prevents the mask MK from being dented by applying a mask grid 731 (or a mask strip) to which a magnetic metal is applied. Therefore, the alignment accuracy of the mask MK can be improved, and a mura defect caused by the denting of the mask MK can be prevented.

[0173] Furthermore, the method for manufacturing the deposition mask MK according to the embodiment has improved mask rigidity or durability, thereby increasing the number of usages of the mask MK.

[0174] Fig.17 is a schematic cross-sectional view of a mask according to an embodiment.

[0175] In addition to forming the mask grid 731 by using an inorganic material and a magnetic metal material, Fig.17 Examples and Fig.16 The embodiments are basically the same. In the following, Fig.17 Any repeated detailed description of elements and features that are the same or similar to those described above will only be described Fig.17 Embodiments of the invention Figures 7 to 16 Elements or features that are different from those of the embodiments.

[0176] Reference Fig.17 , also refer to Figures 4 to 7 The mask MK (i.e., unit mask UM) according to the embodiment may include a silicon substrate 710 serving as a mask body MP and a mask membrane 730 disposed on the silicon substrate 710 and providing a plurality of holes OP (i.e., mask openings). The silicon substrate 710 may be provided with a unit opening COP defined in the silicon substrate 710 to overlap with the plurality of holes OP.

[0177] The mask membrane 730 may include a plurality of mask grids 731, and each of the plurality of mask grids 731 may include a plating layer 2010 and a capping layer 1910 covering the plating layer 2010. The capping layer 1910 may be formed of a seed metal layer for electroplating. Here, the capping layer 1910 may be referred to as a "seed metal layer 1910".

[0178] Each of the mask grids 731 may have a reverse tapered shape with a width that increases as it moves away from the back surface 7311 toward the upper surface 7312. Here, the back surface 7311 of each of the mask grids 731 may be a surface facing the deposition source DS, and the upper surface 7312 of each of the mask grids 731 may be a surface facing the deposition target substrate (e.g., the display panel 410 (i.e., the backplane substrate)). The mask grid 731 according to the embodiment may reduce shadow defects due to its reverse tapered shape. In an embodiment, for example, the tapered angle of each mask grid 731 may be less than or equal to the deposition incident angle, which is the angle from the deposition source DS to the hole OP. In an embodiment, for example, the tapered angle of the mask grid 731 may be designed to be in the range of about 60 degrees to about 90 degrees, the width of the cross section of the mask grid 731 may be less than or equal to about 10 μm, and the thickness of the cross section of the mask grid 731 may be less than or equal to about 15 μm. The mask MK according to the embodiment can reduce the shadow defect by reducing the thickness of the mask grid 731 and providing the mask grid 731 to have a reverse tapered shape. The hole OP (i.e., the mask opening) has a width that decreases as it moves away from the back surface of the mask diaphragm 730 toward the front surface of the mask diaphragm 730. The hole OP (i.e., the mask opening) has a first width at the back surface of the mask diaphragm 730, and has a second width smaller than the first width at the front surface of the mask diaphragm 730.

[0179] The mask grid 731 according to the embodiment may have a concave problem because its thickness is reduced to less than or equal to about 15 μm. In an embodiment, the mask grid 731 according to the embodiment includes a magnetic metal including a plating layer 2010 and a cover layer 1910, or is made of a magnetic metal including a plating layer 2010 and a cover layer 1910. Therefore, a magnetic member (not shown) may be used inside a depositor (not shown) to effectively prevent the concave of the mask grid 731, and the alignment accuracy may be improved.

[0180] Figures 18 to 25 It is used to illustrate the use of manufacturing Fig.17 0047 is a cross-sectional view of a method of forming a mask according to an embodiment shown in FIG.

[0181] In reference Figures 18 to 25 Before or after each manufacturing process of the mask MK described in the present disclosure, other processes of the manufacturing method of the mask MK involved in the present disclosure may be added. Figures 18 to 25 Before or after each manufacturing process of the mask MK described, other processes of the manufacturing process of the mask MK known in the art may be added.

[0182] Fig.18 1 shows a process (hereinafter referred to as a second-first process) of forming an inorganic layer pattern 1810 on a silicon substrate 710. Fig.18 , also refer to Fig.17 , the inorganic layer pattern 1810 may include a silicon-based material. In an embodiment, for example, the inorganic layer pattern 1810 may include a silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (Al x O y The inorganic layer pattern 1810 may be formed by depositing an inorganic layer including or containing the above-mentioned materials and then patterning the deposited inorganic layer.

[0183] The inorganic layer pattern 1810 defines a plurality of first openings 1811. The plurality of first openings 1811 may expose the silicon substrate 710 and form a space for growing the plating layer 2010.

[0184] The cross-section of the inorganic layer pattern 1810 disposed between adjacent first openings 1811 may be patterned to have a regular tapered shape to allow the cross-section of the plating layer 2010 as the mask membrane 730 to have a reverse tapered shape.

[0185] Fig.19 A process of depositing a seed metal layer 1910 to cover the inorganic layer pattern 1810 and the plurality of first openings 1811 (hereinafter referred to as a second-second process) is shown as a process performed after the second-first process. Fig.19 , also refer to Fig.17 The seed metal layer 1910 may be used as a barrier metal for preventing the plated layer 2010 from penetrating the inorganic layer pattern 1810 when electroplating is performed, and may be used as a seed. The seed metal layer 1910 may be a single layer or a multilayer in which each layer includes at least one selected from metal materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), gold (Au), and molybdenum (Mo).

[0186] According to an embodiment, the seed metal layer 1910 may include a first metal layer and a second metal layer, the first metal layer including or containing titanium (Ti), and the second metal layer is disposed on the first metal layer and including or containing titanium nitride (TiN). According to another embodiment, the seed metal layer 1910 may be a single metal layer including or containing titanium (Ti). According to yet another embodiment, the seed metal layer 1910 may be a single metal layer including or containing titanium nitride (TiN). The metal material forming the seed metal layer 1910 is not limited to titanium (Ti) and titanium nitride (TiN), but may be any metal material as long as it is used for electroplating or electroforming. In an embodiment, for example, the seed metal layer 1910 may include copper (Cu). In Fig.19 , the seed metal layer 1910 is shown as a single layer, but the seed metal layer 1910 may be a multilayer including a first metal layer and a second metal layer, the first metal layer including or containing titanium (Ti), and the second metal layer including or containing titanium nitride (TiN).

[0187] The seed metal layer 1910 may be formed by a physical vapor deposition process such as sputtering or a chemical vapor deposition process such as chemical vapor deposition (CVD) and plasma chemical vapor deposition (PECVD). Such a seed metal layer 1910 may be used as a capping layer covering the plating layer 2010.

[0188] In the present disclosure, the seed metal layer 1910 may be referred to by a term such as “preliminary conductive layer”.

[0189] Fig. 20 A process of growing the plating layer 2010 is shown as a process performed after the second-second process (hereinafter referred to as the second-third process). Fig. 20 , the plating layer 2010 may include tungsten (W) or copper (Cu).

[0190] The plating layer 2010 may be grown to have a height higher than the inorganic layer pattern 1810. In an embodiment, for example, the second to third processes as the plating processes may be processes of growing the plating layer 2010 such that the height of the plating layer 2010 is higher than that of the inorganic layer pattern 1810.

[0191] Fig.21 A process of performing a chemical mechanical polishing (CMP) process as a process performed after the second-third process (hereinafter referred to as the second-fourth process) is shown. Fig.21 , also refer to Figure 6 and Fig.17, a portion of the seed metal layer 1910 disposed on the inorganic layer pattern 1810 and a portion of the plating layer 2010 disposed on the inorganic layer pattern 1810 may be polished by a CMP process. Therefore, a surface of the inorganic layer pattern 1810 and a surface of the plating layer 2010 may be generally uniform.

[0192] The portion of the plating layer 2010 that remains after the CMP process may become the mask grid 731 of the mask diaphragm 730. Since the inorganic layer pattern 1810 used as a mold in which the plating layer 2010 is grown has a regular tapered shape, the portion of the plating layer 2010 that remains after the CMP process has a uniform thickness and may have a cross-sectional structure in a reverse tapered shape. In an embodiment, for example, the tapered angle of the mask grid 731 may be designed to be in the range of about 60 degrees to about 90 degrees, the width of the cross section of the mask grid 731 may be less than or equal to about 10 μm, and the thickness of the cross section of the mask grid 731 may be less than or equal to about 15 μm. The mask MK according to an embodiment may reduce shadow defects by reducing the thickness of the mask grid 731 and making the mask grid 731 in a reverse tapered shape.

[0193] Fig. 22 A process of depositing a protective layer 2210 on the inorganic layer pattern 1810 (hereinafter referred to as a second to fifth process) is shown as a process performed after the second to fourth processes. Fig. 22 , also refer to Fig.17 The protection layer 2210 can be used to prevent damage to the mask membrane 730 in subsequent processes.

[0194] The protective layer 2210 may include an inorganic layer including silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ) and aluminum oxide (Al x O y )

[0195] The protective layer 2210 may include an organic layer including at least one selected from acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0196] The protective layer 2210 may be a multi-layer including the above-mentioned inorganic layer and the above-mentioned organic layer.

[0197] Fig.23 A process of forming a photoresist pattern 1310 on the rear surface of the silicon substrate 710 (hereinafter referred to as a second-sixth process) is shown as a process performed after the second-fifth process. Fig.23 , also refer to Figure 6 The photoresist pattern 1310 may be provided with a second opening for defining a cell opening COP corresponding to each of the plurality of unit masks UM. In an embodiment, for example, each of the second openings may correspond to a corresponding one of the cell openings COP.

[0198] Fig.24 A process of etching the back surface of the silicon substrate 710 (hereinafter referred to as the second-seventh process) is shown as a process performed after the second-sixth process. Fig.24 , also refer to Figure 6 and Fig.17 , the silicon substrate 710 may be etched from a rear direction using the photoresist pattern 1310 as a mask. Here, the rear direction refers to a direction in which the deposition source DS is positioned (eg, Fig.24 The seed metal layer 1910 may be exposed from the etched back surface of the silicon substrate 710. When the silicon substrate 710 is etched, the seed metal layer 1910 may serve as an etching stopper.

[0199] Fig.25 The removal of the inorganic layer pattern 1810 (see FIG. Fig.24 ) and protective layer 2210 (see Fig.24 ) process (hereinafter referred to as the second to eighth process). Fig.25 , also refer to Figure 6 , the manufacturing process of the mask MK according to the embodiment may be completed by removing the inorganic layer pattern 1810 and the protective layer 2210. Therefore, the mask membrane 730 including the plating layer 2010 and the capping layer 1910 may be disposed in the cell opening COP in the mask MK.

[0200] The method for manufacturing the deposition mask MK according to the embodiment may improve reliability by improving pixel position accuracy (PPA).

[0201] In addition, the method for manufacturing the deposition mask MK according to the embodiment effectively prevents the mask from being dented by applying the mask grid 731 (or mask strip) to which the magnetic metal (i.e., the plating layer 2010) is applied. Therefore, the alignment accuracy of the mask MK can be improved, and the spot defect caused by the dent of the mask MK can be effectively prevented.

[0202] Furthermore, the method for manufacturing the deposition mask MK according to the embodiment has improved mask rigidity or durability, thereby increasing the number of usages of the mask MK.

[0203] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0204] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A method for manufacturing a deposition mask, wherein: The method comprises: depositing a seed metal layer on the front surface of the silicon substrate; forming a first photoresist pattern on the seed metal layer, the first photoresist pattern defining a plurality of first openings; growing a plating layer in the plurality of first openings of the first photoresist pattern; forming a mask diaphragm by removing the first photoresist pattern and retaining the plating layer; depositing a protective layer on the front surface of the seed metal layer to cover the front surface of the mask diaphragm; forming a second photoresist pattern on a back surface of the silicon substrate, the second photoresist pattern defining a plurality of unit openings corresponding to the plurality of unit masks, respectively; exposing the seed metal layer by etching the back surface of the silicon substrate using the second photoresist pattern as a first mask; exposing a back surface of the mask diaphragm by etching the seed metal layer using the second photoresist pattern as a second mask; and The protective layer is removed.

2. The method according to claim 1, in, The seed metal layer includes a first metal layer including titanium and a second metal layer, the first metal layer including titanium nitride and disposed on the first metal layer.

3. The method according to claim 1, in, The seed metal layer includes a single metal layer including titanium.

4. The method according to claim 1, in, The seed metal layer includes a single metal layer including titanium nitride.

5. The method according to claim 1, in, The mask membrane includes a plurality of mask grids formed by the plating layer, A plurality of mask openings are respectively defined between adjacently arranged mask grids among the plurality of mask grids to correspond to regions where the first photoresist pattern is removed.

6. The method according to claim 5, in, A cross-section of each of the plurality of mask grids has a reverse tapered shape having a width that increases as it moves away from the back surface of the mask diaphragm toward the front surface of the mask diaphragm.

7. The method according to claim 6, in, Each of the plurality of mask openings has a width that decreases from the back surface of the mask membrane to the front surface of the mask membrane.

8. The method according to claim 7, in, Each of the plurality of mask openings has a first width at the back surface of the mask membrane and has a second width smaller than the first width at the front surface of the mask membrane.

9. The method according to claim 1, in, The coating includes tungsten.

10. The method according to claim 1, in, The plating layer includes copper.

11. A method for manufacturing a deposition mask, wherein: The method comprises: forming an inorganic layer pattern on the front surface of the silicon substrate, the inorganic layer pattern defining a plurality of first openings; depositing a seed metal layer on the front surface of the silicon substrate to cover the inorganic layer pattern and the plurality of first openings; growing the plating layer on the seed metal layer in such a manner that a height of the plating layer becomes higher than a height of the inorganic layer pattern; polishing a portion of the seed metal layer disposed on the inorganic layer pattern and a portion of the plating layer disposed on the inorganic layer pattern by performing a chemical mechanical polishing process; depositing a protective layer on the inorganic layer pattern; forming a photoresist pattern on a back surface of the silicon substrate, the photoresist pattern defining a plurality of unit openings corresponding to the plurality of unit masks, respectively; exposing the seed metal layer and the inorganic layer pattern by etching the back surface of the silicon substrate using the photoresist pattern as a first mask; and forming a mask membrane by removing the inorganic layer pattern and the protective layer, The mask membrane includes a plurality of mask grids, and each of the plurality of mask grids includes the plating layer and the seed metal layer covering the plating layer.

12. The method according to claim 11, in, The seed metal layer includes a first metal layer including titanium and a second metal layer, the first metal layer including titanium nitride and disposed on the first metal layer.

13. The method according to claim 11, in, The seed metal layer includes a single metal layer including titanium.

14. The method according to claim 11, in, The seed metal layer includes a single metal layer including titanium nitride.

15. The method according to claim 11, in, A plurality of mask openings are respectively defined between adjacently disposed mask grids among the plurality of mask grids to correspond to regions where the inorganic layer pattern is removed.

16. The method according to claim 15, in, A cross-section of each of the plurality of mask grids has a reverse tapered shape having a width that increases as it moves away from a back surface of the mask diaphragm toward a front surface of the mask diaphragm.

17. The method according to claim 16, in, Each of the plurality of mask openings has a width that decreases as it moves away from the back surface of the mask membrane toward the front surface of the mask membrane.

18. The method according to claim 17, in, Each of the plurality of mask openings has a first width at the back surface of the mask membrane and has a second width smaller than the first width at the front surface of the mask membrane.

19. The method according to claim 11, in, The coating includes tungsten.

20. The method according to claim 11, in, The plating layer includes copper.

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