Method of forming semiconductor structure including two-dimensional metal dichalcogenide layer

Abstract

Methods for forming a semiconductor structure including a 2D-transition metal dichalcogenide layer, methods for forming a gate stack including a metallic 2D-transition metal dichalcogenide layer, and methods for forming a ternary phase 2D-transition metal dichalcogenide layer by an atomic layer deposition process (ALD) are disclosed.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor processing methods and related semiconductor structures, and the field of device and integrated circuit manufacturing. More specifically, the present disclosure relates to methods for forming semiconductor structures including 2D-transition metal dichalcogenide layers and gate stacks including metallic 2D-transition metal dichalcogenide layers. The present disclosure also relates to methods for forming ternary phase 2D-transition metal dichalcogenide layers and their use in semiconductor device structures. Background Art

[0002] The reduction in size of semiconductor devices such as field effect transistors (FETs) and complementary metal oxide semiconductor (CMOS) devices has led to significant increases in the speed and density of integrated circuits. However, conventional device scaling techniques face significant challenges in future technology nodes. For example, the formation of gate stacks, i.e., the material layer between the device channel and the device control terminal, faces increasing design constraints due to the spatial constraints imposed as device structures move to next generation architectures such as full gate structures. Such design constraints impose restrictions on the thickness of the layers that make up the gate stack. However, certain gate stacks, such as the layers that make up the gate electrode layer, are negatively impacted by the reduction in layer thickness. Therefore, methods are needed that can form ultra-thin gate stacks without associated effects on device performance.

[0003] Any discussion set forth in this section, including discussion of problems and solutions, has been included in the present disclosure merely to provide context for the present disclosure. Such discussion should not be considered as an admission that any or all of the present inventions are previously known or constitute prior art. Summary of the invention

[0004] This Summary may introduce some concepts in a simplified form that are further described below. This Summary is not intended to necessarily identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0005] Various embodiments of the present disclosure relate to methods for forming semiconductor structures, and in particular, methods for forming semiconductor structures including 2D-transition metal dichalcogenide layers. As described in more detail below, the 2D-transition metal dichalcogenide layers of the present disclosure can be used as metal work function metal layers within gate stacks of semiconductor devices. The 2D-transition metal dichalcogenide layers of the present disclosure allow for ultra-thin gate stacks that are compatible with next generation device architectures. In addition, the 2D-transition metal dichalcogenide layers of the present disclosure can include ternary phase 2D-transition metal dichalcogenide layers (in alloy form or doped form), which allows for further adjustment of the properties of the 2D-transition metal dichalcogenide layer to optimize specific device structures.

[0006] According to an example of the present disclosure, a method for forming a semiconductor structure is provided. In such an example, the method may include placing a substrate in a reaction chamber, the substrate including a dielectric layer, and depositing a 2D-transition metal dichalcogenide layer directly on the dielectric layer by performing one or more deposition cycles of a cyclic deposition process. In such an example, each deposition cycle of the cyclic deposition process includes providing a transition metal precursor to the reaction chamber, and providing a chalcogen precursor to the reaction chamber. In such an example, a further step of the method may include depositing a metallic capping layer directly on the 2D-transition metal dichalcogenide layer. In some embodiments, the dielectric layer is a high-k dielectric layer. In some embodiments, the cyclic deposition process is an atomic layer deposition process. In some embodiments, the substrate temperature during the atomic layer deposition process is less than 500°C. According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer is a metallic work function layer. In such an example, the 2D-transition metal dichalcogenide layer is selected from MoS2, VS2, TaS2, MoTe2, TaSe2, NbSe2 and TiSe2. According to an example of the present disclosure, the chalcogen precursor includes a chalcogen selected from sulfur, selenium and tellurium. According to an example of the present disclosure, one or more deposition cycles further include providing a metal precursor to the reaction chamber. In such an example, the metal precursor is an additional metal element, and the transition metal precursor is a transition metal element different from the additional metal element. In such an example, the additional metal element is selected from aluminum, tungsten and tellurium. In such an example, the additional metal element may be a doping metal element, and the 2D-transition metal dichalcogenide layer is a metal-doped 2D-transition metal dichalcogenide layer. In such an example, the additional metal element may be a metal alloy element, and the 2D-transition metal dichalcogenide layer is a ternary phase 2D-transition metal dichalcogenide alloy layer. According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer is deposited to a thickness between 1 nm and 5 nm. According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer is deposited to a thickness between 1 monolayer and 5 monolayers.

[0007] Various other embodiments of the present disclosure relate to methods of forming at least a portion of a gate stack for a semiconductor device structure. As described in more detail below, the methods described herein can be used to form ultra-thin gate stacks suitable for next generation device architectures, such as gate-all-around (GAA) transistor device structures, nanosheet device structures, and complementary FET (CFET) device structures.

[0008] According to an example of the present disclosure, a method for forming at least a portion of a gate stack for a semiconductor device structure is provided. In such an example, the method may include placing a substrate in a reaction chamber, the substrate including a plurality of partially manufactured device structures, wherein one or more partially manufactured device structures include a surface layer comprising a high-k dielectric layer. In such an example, the method may also include performing one or more deposition cycles of a first atomic layer deposition process to deposit a metallic 2D-transition metal dichalcogenide work function layer directly on the surface of the high-k dielectric layer, and performing one or more deposition cycles of a second atomic layer deposition process to deposit a metallic capping layer directly on the metallic 2D-transition metal dichalcogenide work function layer. According to an example of the present disclosure, the high-k dielectric layer, the metallic 2D-transition metal dichalcogenide work function layer, and the metallic capping layer together constitute a gate stack of a semiconductor device structure. According to an example of the present disclosure, the semiconductor device structure may include an NMOS device structure, and the effective work function of the gate stack is between 4.2eV and 4.4eV, and the total gate stack thickness is less than 20 nanometers. According to an example of the present disclosure, the semiconductor device structure may include a PMOS device structure, and the effective work function of the gate stack is between 5.2 eV and 5.6 eV, and the total gate stack thickness is less than 20 nanometers.

[0009] Various further embodiments of the present disclosure relate to methods of forming a ternary phase 2D-transition metal dichalcogenide layer by an atomic layer deposition process, the ternary phase 2D-transition metal dichalcogenide layer having a chemical formula comprising a transition metal element, a chalcogen element, and a ternary element comprising a metal element different from the transition metal element. In such examples, a transition metal precursor is used as a source of the transition metal element, a chalcogen precursor is used as a source of the chalcogen element, and a metal precursor is used as a source of the ternary metal element.

[0010] These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the accompanying figures.The present invention is not limited to any particular embodiment disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0012] A more complete understanding of embodiments of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the following illustrative drawings.

[0013] Figure 1 A method according to an exemplary embodiment of the present disclosure is shown.

[0014] Figure 2 A semiconductor structure according to an example of the present disclosure is shown.

[0015] Figure 3 Another semiconductor structure according to an example of the present disclosure is shown.

[0016] Figure 4 Additional semiconductor structures according to examples of the present disclosure are shown.

[0017] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the size of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] The description of exemplary embodiments of the method provided below is merely exemplary and is for illustration purposes only. The following description is not intended to limit the scope of the present disclosure or the claims. In addition, the recitation of multiple embodiments having the indicated features or steps is not intended to exclude other embodiments having additional features or steps, or other embodiments incorporating different combinations of the described features or steps.

[0019] As described in more detail below, various embodiments of the present disclosure relate to methods of forming a semiconductor structure including a 2D-transition metal dichalcogenide layer. As described in more detail, the 2D-transition metal dichalcogenide layer described herein can be used in the manufacturing process of an electronic device. Such a 2D-transition metal dichalcogenide layer can reduce the complexity and / or cost of manufacturing a device / integrated circuit and increase the functionality of such a 2D-transition metal dichalcogenide layer.

[0020] In more detail, the continued scaling down of device structures and related integrated circuits (e.g., FETs, CMOS, etc.) increases the material deposition challenges to both improve / maintain material properties while reducing material layer thicknesses. For example, in the case of layers that make up the gate stack of future transistor architectures (e.g., in gate-around structures, etc.), there may be less than 10 nanometers of available space, which may translate into material layer thicknesses of less than 5 nanometers for certain layers within the gate stack (e.g., work function metal layers).

[0021] To address these issues, the present disclosure provides two-dimensional (2D) materials and specific 2D-transition metal dichalcogenide layers as work function metals within the gate stack of a semiconductor device structure. 2D materials, particularly 2D transition metal dichalcogenide layers, have previously been proposed for use within semiconductor device structures, but such layers have been used as channel regions and / or phase change materials, and in such cases, the 2D materials have non-metallic and unstable material properties. In contrast, the present disclosure provides a 2D-transition metal dichalcogenide layer with stable metallic properties, which can be used as a conductive work function metal layer within a gate stack, as well as other functions and uses. Due to the inherent atomically thin thickness of such 2D materials, the use of 2D-transition metal dichalcogenide layers can alleviate the current strict spatial constraints in gate stack integration. Therefore, the 2D-transition metal dichalcogenide layer can alleviate the requirements for dipole engineering within the gate stack and provide flexibility in selecting the integration scheme adopted (e.g., dipole first, dipole last, dipole patterning, etc.). In addition to the ultrathin thickness of the 2D-transition metal dichalcogenide layer, the absence of dangling bonds in the 2D material can further contribute to the conductivity of the gate stack.

[0022] The present disclosure also provides a ternary phase 2D-transition metal dichalcogenide layer in alloy form or doped form to further increase the functionality of the 2D material as a stable metallic layer within a gate stack of a semiconductor device structure. As a non-limiting example, the doped / alloyed 2D-transition metal dichalcogenide layer can be used as a work function metal with tunable electronic properties (e.g., work function and band gap), which are at least partially controlled by selecting the materials, precursors, deposition process, and alloying / doping elements within the ternary phase metallic 2D-transition metal dichalcogenide layer.

[0023] As used herein, the terms "precursor" and "reactant" may refer to molecules (compounds or molecules containing a single element) that participate in a chemical reaction that produces another compound. A precursor typically contains a moiety that is at least partially incorporated into the compound or element produced by the chemical reaction. The compound or element so obtained may be deposited on a substrate. A reactant may be an element or compound that is not incorporated to a large extent into the resulting compound or element. In some cases, the term reactant may be used interchangeably with the term precursor.

[0024] As used herein, the term “transition metal precursor” may refer to a precursor that may be represented by a chemical formula including a transition metal element.

[0025] As used herein, the term "chalcogen precursor" may refer to a precursor that may be represented by a chemical formula including a chalcogen, wherein a chalcogen is an element from Group VI of the periodic table including sulfur, selenium, and tellurium.

[0026] As used herein, the terms "metallic" and "metallic layer" may refer to materials and material layers having metallic properties and / or semi-metallic properties.

[0027] As used herein, the terms "stable" and "stable layer" may refer to materials and material layers whose properties remain substantially unchanged under bias conditions and operations.

[0028] As used herein, the terms "layer" and "film" may refer to any continuous or discontinuous structure and material, such as a material formed and / or deposited by the methods disclosed herein. For example, a layer (or film) may include a two-dimensional material, a three-dimensional material, nanoparticles, or even a partial or complete molecular layer or a partial or complete atomic layer or atom and / or molecular clusters. A layer may include a material or layer having pinholes. A layer may be at least partially continuous. A layer may be patterned, such as subdivided, and may include multiple semiconductor devices.

[0029] As used herein, the term "substrate" may refer to any one or more underlying materials that can be used to form or can be formed on a device, circuit or film by a method according to an embodiment of the present invention. The substrate may include a bulk material, such as silicon (e.g., single crystal silicon), other IV group materials, such as germanium, or other semiconductor materials, such as II-VI or III-V semiconductor materials, and may include one or more layers covering or located below the bulk material. In addition, the substrate may include various features, such as depressions, protrusions, etc. formed in or on at least a portion of the substrate layer. For example, the substrate may include a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material. In addition, the term "substrate" may refer to any one or more underlying materials that can be used or on which a device, circuit or film can be formed. "Substrate" may be continuous or non-continuous; rigid or flexible; solid or porous. "Substrate" may be in any form, such as a powder, a plate or a workpiece. Plate-shaped substrates may include wafers of various shapes and sizes. The substrate may be made of materials such as silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride and silicon carbide. The continuous substrate can extend beyond the boundary of the processing chamber where the deposition process occurs, and can be moved through the processing chamber so that the process continues until the end of the substrate is reached. The continuous substrate can be provided by a continuous substrate feeding system, which allows the continuous substrate to be manufactured and output in any suitable form. Non-limiting examples of continuous substrates may include sheets, nonwoven films, rolls, foils, nets, flexible materials, a bundle of continuous filaments or fibers (i.e., ceramic fibers or polymer fibers). The continuous substrate may also include a carrier or thin sheet on which a non-continuous substrate is mounted. For example, the substrate may include a semiconductor material. The semiconductor material may include or be used to form one or more of the source, drain or channel regions of the device. The substrate may also include an interlayer dielectric (e.g., silicon oxide) and / or a high dielectric constant material layer covering the semiconductor material. In this article, a high dielectric constant material (or high-k dielectric material) is a material whose dielectric constant is greater than the dielectric constant of silicon dioxide.

[0030] As used herein, the terms "structure" and "semiconductor structure" may be or include a substrate as described herein. A structure may include a substrate and one or more layers overlying the substrate, such as one or more layers formed by a method according to the present disclosure. The structure may include or be used to form, for example, vias or lines in BEOL processing, or contacts or local interconnects in MEOL processing. The structure may also be used to form gate stacks, gate electrodes, layers in buried power rails in logic applications, and to form word lines or bit lines in advanced memory applications. A "structure" may also include fabricated and / or partially fabricated device structures, such as transistors, memory and / or logic elements.

[0031] As used herein, the term "cyclic deposition" may refer to the sequential introduction of precursors (also referred to as reactants) into a reaction chamber to deposit a layer (or film) on a substrate, and includes deposition techniques such as atomic layer deposition, cyclic chemical vapor deposition, plasma enhanced atomic layer deposition, and plasma enhanced cyclic chemical vapor deposition.

[0032] As used herein, the term "atomic layer deposition" (ALD) may refer to a vapor deposition process in which a deposition cycle, preferably a plurality of consecutive deposition cycles, is performed in a processing chamber. Typically, during each cycle, a precursor is chemically adsorbed to a deposition surface (e.g., a substrate surface or a previously deposited underlying surface, such as material from a previous ALD cycle) to form a monolayer or sub-monolayer that is not easily reacted with additional precursors (i.e., a self-limiting reaction). Thereafter, if desired, a reactant (e.g., another precursor or a reactive gas) may subsequently be introduced into the processing chamber for converting the chemically adsorbed precursor into the desired material on the deposition surface. Typically, the reactant is capable of further reacting with the precursor. In addition, a purge step may also be used during each cycle to remove excess precursor from the processing chamber and / or remove excess reactants and / or reaction byproducts from the processing chamber after the chemically adsorbed precursor is converted. In addition, the term "atomic layer deposition" as used herein is also meant to include processes designated by related terms, such as "chemical vapor atomic layer deposition", "atomic layer epitaxy" (ALE), molecular beam epitaxy (MBE), gas source MBE or organometallic MBE, and chemical beam epitaxy when performed with alternating pulses of a precursor composition, a reactive gas, and a purge gas (e.g., an inert carrier gas).

[0033] As used herein, the term "cyclic chemical vapor deposition" may refer to any process in which a substrate is sequentially exposed to two or more volatile precursors that react and / or decompose on the substrate to produce the desired deposition.

[0034] As used herein, the term "purge" may refer to the process of providing an inert or substantially inert gas to a reaction chamber between two gas pulses, which gases may otherwise react with each other. For example, a purge may be provided between a precursor pulse and a reactant pulse, for example using an inert gas, such as a rare gas, to reduce gas phase interactions that may occur between the precursor and the reactant. It should be understood that the purge may be performed in time or space, or both. For example, in the case of a time purge, a purge step may be used, for example, in a time sequence of providing a precursor to the reaction chamber, providing a purge gas to the reaction chamber, and providing a reactant or another precursor to the reaction chamber, wherein the substrate on which the layer is deposited does not move. In the case of a space purge, the purge step may take the form of moving the substrate from a first position where a precursor is (e.g., continuously) supplied to a second position where a reactant or other precursor is (e.g., continuously) supplied through a purge gas curtain.

[0035] In addition, in the present disclosure, any two numbers of a variable may constitute a feasible range of the variable, and any range indicated may include or exclude endpoints. In addition, any values ​​of the variables indicated (regardless of whether they are expressed as "about") may refer to exact values ​​or approximate values, and include equivalents, and may refer to average values, median values, representative values, majority values, etc. In addition, in the present disclosure, the terms "including", "consisting of" and "having" independently refer to "usually or broadly including", "comprising", "essentially consisting of" or "consisting of" in some embodiments. In the present disclosure, the meaning of any definition does not necessarily exclude the common and customary meanings in some embodiments.

[0036] Turning now to the accompanying drawings, Figure 1 An exemplary method 100 is shown. The method 100 includes the steps of placing a substrate in a reaction chamber (step 102), depositing a 2D-transition metal dichalcogenide layer on the substrate (step 104), and optionally depositing a metallic capping layer on the 2D-transition metal dichalcogenide layer (step 116).

[0037] During step 102, the substrate is positioned within a reaction chamber. The reaction chamber used during step 102 may be or include a reaction chamber of a chemical vapor deposition reactor system configured to perform a chemical vapor deposition process or a cyclic deposition process. In some embodiments, the reaction chamber used during step 102 may be or include a reaction chamber of an atomic layer deposition reactor system configured to perform a cyclic deposition process. In some embodiments, the reaction chamber used during step 102 may be or include a reaction chamber of a plasma enhanced atomic layer deposition reactor system configured to perform a cyclic deposition process using a suitable plasma species. In some embodiments, the reaction chamber used during step 102 may be or include a reaction chamber of a plasma enhanced chemical vapor deposition reactor system configured to perform a cyclic deposition process using a suitable plasma species.

[0038] The reaction chamber may be a stand-alone reaction chamber or part of a combination tool. The reaction chamber may include a substrate heater to heat the substrate to the substrate temperatures mentioned herein.

[0039] According to an example of the present disclosure, the substrate located within the reaction chamber during step 102 may include a dielectric layer. In such an example, the dielectric layer is a surface dielectric layer. In some embodiments, the dielectric layer includes a high dielectric constant layer (i.e., a high-k dielectric layer), wherein the high-k dielectric layer exhibits a dielectric constant greater than about 7. Exemplary high-k dielectric layers include, but are not limited to, hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), hafnium silicate (HfSiO x), aluminum oxide (Al2O3), lanthanum oxide (La2O3), and mixtures / stacks comprising one or more of these layers.

[0040] According to examples of the present disclosure, the dielectric layer may include a portion of a partially fabricated device structure and / or an integrated circuit structure. In such examples, one or more partially fabricated device structures may include a surface layer including a high-k dielectric layer. In such examples, the high-k dielectric layer may be selected from the following materials: HfO2, Ta2O5, ZrO2, TiO2, HfSiO x , Al2O3, La2O3 and mixtures / stacks including one or more of such layers. According to an example of the present disclosure, the high-k dielectric layer may include a portion of a gate stack of a partially fabricated semiconductor device structure.

[0041] Figure 2 A portion of a substrate suitable for use as a substrate during step 102 is shown. The substrate 200 includes a semiconductor body 202 and a dielectric layer 204 disposed on the semiconductor body. The dielectric layer 204 may also include an interface layer (not shown) disposed between the semiconductor body 202 and the dielectric layer 204. According to examples of the present disclosure, the substrate 200 may form a portion of a partially fabricated semiconductor device structure, such as a wrap-around gate transistor, a nanosheet transistor, a fork-sheet transistor, a complementary FET (CFET) device, a CMOS device structure, and / or a memory device (e.g., a DRAM). In such examples, the dielectric layer 204 may include a high-k dielectric layer and may form a portion of a gate stack. In such examples, a lower region of the semiconductor body 202 adjacent to the dielectric layer 204 may include a channel region of the semiconductor device structure.

[0042] Once the substrate is positioned in the reaction chamber (step 102), the method 100 may continue with the step of depositing a 2D-transition metal dichalcogenide layer on the surface of the substrate (step 104). According to an example of the present disclosure, step 104 includes depositing the 2D-transition metal dichalcogenide layer directly on the dielectric layer disposed on the surface of the substrate, i.e., directly depositing the 2D-transition metal dichalcogenide layer on the dielectric layer disposed on the surface of the substrate. Figure 2 on the dielectric layer 204.

[0043] The step of depositing the 2D-transition metal dichalcogenide layer (step 104) may be performed at a substrate temperature between 100° C. and 500° C., or between 150° C. and 400° C., or between 250° C. and 350° C., or between 275° C. and 325° C., or between 280° C. and 320° C. In some embodiments, the step of depositing the 2D-transition metal dichalcogenide layer (step 104) may be performed at a substrate temperature below 500° C., or below 400° C., or below 300° C., or below 200° C., or below 100° C. In alternative embodiments of the present disclosure, the 2D-transition metal dichalcogenide layer may be deposited on a substrate surface that does not include a sensitive dielectric layer, and in such embodiments, the thermal budget of the deposition step 104 may be increased. In such an example, the step of depositing the 2D-transition metal dichalcogenide layer (step 104) can be performed at a substrate temperature between 100° C. and 800° C., or between 200° C. and 700° C., or between 300° C. and 400° C. In such an example, the step of depositing the 2D-transition metal dichalcogenide layer (step 104) can be performed at a substrate temperature below 800° C., or below 600° C., or below 500° C., or below 450° C., or below 400° C.

[0044] In addition to controlling the temperature of the substrate, the pressure in the reaction chamber may also be adjusted. For example, in some embodiments of the present disclosure, the pressure in the reaction chamber during step 102 may be less than 760 Torr, or between 0.2 Torr and 760 Torr, or between about 1 Torr and 100 Torr, or between about 1 Torr and 10 Torr.

[0045] According to an example of the present disclosure, the step of depositing a 2D-transition metal dichalcogenide layer (step 104 ) may include a cyclic chemical vapor deposition process.

[0046] According to a further example of the present disclosure, the step of depositing the 2D-transition metal dichalcogenide layer on the surface of the dielectric layer (step 104) may include a thermal deposition process, such as a thermal cycle deposition process. In a thermal deposition process, the elevated temperature relative to the ambient temperature promotes a chemical reaction. In an alternative embodiment, the step of depositing the 2D-transition metal dichalcogenide layer on the surface of the dielectric layer (step 104) may include a plasma-assisted deposition process, such as plasma-enhanced atomic layer deposition or plasma-enhanced cyclic chemical vapor deposition. In such a plasma-assisted deposition process, the chemical reaction is promoted by a suitable plasma precursor / reactant.

[0047] According to further examples of the present disclosure, and with reference to Figure 1, the step of depositing the 2D-transition metal dichalcogenide layer (step 104) may include a thermal cyclic deposition process. In such an example, the step of depositing the 2D-transition metal dichalcogenide layer directly on the dielectric layer (step 104) may include a cyclic deposition process 106, such as an atomic layer deposition process. According to an example of the present disclosure, the cyclic deposition process 106 may include providing a transition metal precursor to a reaction chamber to form an absorbed transition metal species on the surface of the dielectric layer (step 108), and providing a chalcogen precursor to the reaction chamber (step 110) to react with the transition metal species to form the 2D-transition metal dichalcogenide layer directly on the surface of the dielectric layer. In some examples of the present disclosure, an optional step of the cyclic deposition process 106 includes providing a metal precursor to the reaction chamber (step 112) to form a ternary phase 2D-transition metal dichalcogenide layer, which option will be described in more detail below.

[0048] According to an example of the present disclosure, steps 108 and 110 (and optional step 112) can be repeated as shown in loop 114, each loop including a separate deposition cycle of the cyclic deposition process 106 (e.g., an atomic layer deposition process). In addition, steps 108 and 110 (and optional step 112) can be started and / or terminated in any order. In addition, the cyclic deposition process 106 can include one or more (e.g., 1-3 times, 1-5 times, or 1-10 times) repetitions of steps 108 and / or 110 (and / or optional step 112) before proceeding to the next process step of the cyclic deposition process 106.

[0049] According to an example of the present disclosure, a transition metal precursor is provided to the reaction chamber during step 108. The temperature and pressure within the reaction chamber may be as described above in connection with step 104.

[0050] In some embodiments, the transition metal precursor is provided as a single compound or a mixture of two or more compounds. In the mixture, other compounds besides the transition metal compound may be one or more inert compounds or elements, i.e., inert gases. In some embodiments, the transition metal precursor is provided as a composition. Compositions suitable for use may include a transition metal compound and an effective amount of one or more stabilizers and / or inert gases or carrier gases, such as argon, nitrogen, and / or hydrogen. The composition may be a solution or a gas at NTP.

[0051] According to an example of the present disclosure, the transition metal precursor includes a transition metal element. In such an example, the transition metal precursor includes a chemical formula including at least one transition metal element. In such an example, the transition metal element can be selected from molybdenum, vanadium, tantalum, niobium and titanium. In addition, in such an example, the transition metal precursor can include a gas phase transition metal halide.

[0052] According to examples of the present disclosure, the transition metal precursor may include a molybdenum precursor. In such examples, the molybdenum precursor may include a molybdenum halide precursor. In further examples, the molybdenum halide precursor may include a molybdenum sulfide, and in some embodiments, the molybdenum halide precursor may include a molybdenum sulfide halide. For example, the molybdenum sulfide halide precursor may include an oxyhalide molybdenum selected from molybdenum oxychloride, molybdenum oxyiodide, and molybdenum oxybromide. In example embodiments, the molybdenum halide precursor may include molybdenum oxychloride, including but not limited to molybdenum trichloride (V) (MoOCl3), molybdenum tetrachloride (VI) (MoOCl4), and molybdenum dichloride (IV) (MoO2Cl2). In some embodiments, the molybdenum precursor includes a cyclopentadienyl (Cp) ligand. For example, the molybdenum precursor may include MoCp2Cl2 or MoCp2H2, Mo(iPrCp)2Cl2, Mo(iPrCp)2H2, Mo(EtCp)2H2, or consist of or substantially consist of it. As non-limiting examples, the molybdenum precursor may also include at least one of: molybdenum pentachloride (MoCl5), molybdenum hexachloride (MoCl6), molybdenum hexafluoride (MoF6), molybdenum triiodide (MoI3), or molybdenum dibromide (MoBr2).

[0053] According to further examples of the present disclosure, the transition metal precursor may include a vanadium precursor. In such examples, the vanadium precursor may be selected from vanadium halides, vanadium oxyhalides, and organometallic vanadium compounds. In some embodiments, the vanadium precursor may include a vanadium halide. In some embodiments, the vanadium halide includes vanadium chloride. In some embodiments, the vanadium chloride includes vanadium (IV) chloride. In some embodiments, the vanadium precursor includes vanadium beta-diketonate.

[0054] According to further examples of the present disclosure, the transition metal precursor may include a tantalum precursor. In such examples, the tantalum precursor may include one or more alkylamine ligands. A suitable tantalum precursor may include five (dimethylamino) tantalum (V). In some embodiments, the tantalum precursor may be selected from five (dimethylamino) tantalum, ethoxide tantalum (V), tris (diethylamido) (tert-butylimide) tantalum, tris (ethylmethylamido) (tert-butylimide) tantalum, tetraethoxydimethylamino tantalum ethoxide and tert-butylimide tris (diethylamido) tantalum.

[0055] According to further examples of the present disclosure, the transition metal precursor may include a niobium precursor. In such an example, the niobium precursor may be selected from (tert-butylimino)-tris-(diethylamino)-niobium (Nb(N t Bu)(NEt2)3), Nb(OEt)5, NbF5, NbCl5 and NbF5.

[0056] According to further examples of the present disclosure, the transition metal precursor may include a titanium precursor. In such examples, the titanium precursor may be selected from titanium tetrachloride (TiCl4), titanium tetraiodide (TiI4), titanium tetrabromide (TiBr4), Ti(NEt2)4, Ti(NEtMe)3(guan-NEtMe), Ti(NMe2)4, Ti(NMeEt)4, Ti(OEt)4, Ti(OEt)4, Ti(O i Pr)2(dmae)2,Ti(O i Pr)2(thd)2 and Ti(OiPr).

[0057] During each deposition cycle of the cyclic deposition process 106, step 108 ( Figure 1 ) can have a duration between 0.1 seconds and 60 seconds, between 0.1 seconds and 10 seconds, or between 0.5 seconds and 5.0 seconds. The flow rate of the transition metal precursor to the reaction chamber can be less than 1000 sccm, or less than 500 sccm, or less than 100 sccm, or less than 10 sccm, or less than 1 sccm, or range from 1 sccm to 2000 sccm, from 5 sccm to 1000 sccm, or from 10 sccm to 500 sccm.

[0058] During step 110, a chalcogen precursor is provided to the reaction chamber. In such an example, the chalcogen precursor may include at least one chalcogen selected from Group VI of the periodic table. According to an example of the present disclosure, the chalcogen precursor includes at least one chalcogen selected from sulfur, selenium, and tellurium.

[0059] According to an example of the present disclosure, the chalcogen precursor may be selected from hydrogen sulfide (H2S), hydrogen selenide (H2Se), dimethyl sulfide ((CH3)2S) and dimethyl tellurium (CH3)2Te. In some embodiments, the chalcogen precursor is selected from the following list: H2S, H2Se, H2Te, (CH3)2S, (NH4)2S, dimethyl sulfoxide ((CH3)2SO), (CH3)2Se, (CH3)2Te, element or atom S, Se, Te, other precursors containing chalcogen hydrogen bonds, such as H2S2, H2Se2, H2Te2, or chalcogen alcohols having the formula RYH, wherein R may be a substituted or unsubstituted hydrocarbon, preferably a C1-C8 alkyl or substituted alkyl, such as an alkylsilyl, more preferably a linear or branched C1-C5 alkyl, and Y may be S, Se or Te. In some embodiments, the chalcogen precursor is a thiol having the formula RSH, wherein R can be a substituted or unsubstituted hydrocarbon group, preferably a C1-C8 alkyl group, more preferably a C1-C5 alkyl group that is linear or branched. In some embodiments, the chalcogen precursor has the formula (R3Si)2Y, wherein R3Si is an alkylsilyl group and Y can be Se or Te. In some embodiments, the chalcogen precursor comprises S or Se. In some embodiments, the chalcogen precursor comprises S. In some embodiments, the chalcogen precursor may comprise an elemental chalcogen, such as elemental sulfur. In some embodiments, the chalcogen precursor does not comprise Te. In some embodiments, the chalcogen precursor does comprise Se. In some embodiments, the chalcogen precursor is selected from a precursor comprising S, Se, or Te.

[0060] In some embodiments, the chalcogen precursor may include chalcogen plasma, chalcogen atoms or chalcogen free radicals. In some embodiments of chalcogen precursors that require excitation, plasma may be generated in the reaction chamber or upstream of the reaction chamber. In some embodiments, the chalcogen precursor does not include an excited chalcogen precursor, such as a plasma, an atom or a free radical. In some embodiments, the chalcogen precursor may include a chalcogen plasma, a chalcogen atom or a chalcogen group formed by a chalcogen precursor including a chalcogen hydrogen bond (e.g., H2S). In some embodiments, the chalcogen precursor may include a chalcogen plasma, a chalcogen atom or a chalcogen group, such as a plasma including sulfur, selenium or tellurium, preferably a plasma including sulfur. In some embodiments, the plasma, the atom or the free radical includes tellurium. In some embodiments, the plasma, the atom or the free radical includes selenium. In some embodiments, the chalcogen precursor does not include a tellurium precursor.

[0061] During step 110 of method 100 ( Figure 1), the flow rate of the chalcogen precursor to the reaction chamber may be greater than zero and less than 250 sccm, or less than 200 sccm, or less than 150 sccm, or less than 100 sccm, or less than 50 sccm, or less than 25 sccm, or less than 15 sccm, or less than 10 sccm. In such examples, the flow rate of the chalcogen precursor to the reaction chamber may be between 10 sccm and 250 sccm, or between 15 sccm and 200 sccm, or between 25 sccm and 150 sccm. In some embodiments, the chalcogen precursor is provided to the reaction chamber for a period of between 0.1 seconds and 2.0 seconds, or between 0.01 seconds and 10 seconds, or less than 20 seconds, or less than 10 seconds, or less than 5 seconds.

[0062] The cyclic deposition process 106 may be repeated until an end criterion is met. For example, the end criterion may be based on the number of deposition cycles performed, or by the desired thickness of the deposited 2D-transition metal dichalcogenide layer. According to examples of the present disclosure, the 2D-transition metal dichalcogenide layer may be deposited to an average layer thickness between 1 nanometer and 10 nanometers, or between 2 nanometers and 6 nanometers, or between 3 nanometers and 5 nanometers. In some embodiments, the 2D-transition metal dichalcogenide layer is deposited to an average layer thickness greater than 0 nanometer and less than 10 nanometers, or less than 8 nanometers, or less than 6 nanometers, or less than 5 nanometers, or less than 4 nanometers, or less than 3 nanometers, or less than 2 nanometers, or less than 1 nanometer, or between 1 nanometer and 5 nanometers. According to examples of the present disclosure, the 2D-transition metal dichalcogenide layer may be deposited to have a thickness between 1 monolayer and 6 monolayers, or between 2 monolayers and 5 monolayers, or between 3 monolayers and 4 monolayers. In such examples, the 2D-transition metal dichalcogenide layer can be deposited to have a thickness of less than 6 monolayers, or less than 5 monolayers, or less than 4 monolayers, or less than 3 monolayers, or less than 2 monolayers, or equal to 1 monolayer.

[0063] According to an example of the present disclosure, each deposition cycle of the cyclic deposition process 106 may include providing a transition metal precursor to the reaction chamber (step 108), and providing a chalcogen precursor to the reaction chamber (step 110), omitting the optional step 112. In such an example, the cyclic deposition process 106 deposits a binary phase 2D-transition metal dichalcogenide layer directly on the dielectric layer. In such an example, the deposited 2D-transition metal dichalcogenide layer may be selected from MoS2, VS2, TaS2, MoTe2, TaSe2, NbSe2, TiSe2. In some embodiments, the binary phase 2D-transition metal dichalcogenide layer deposited by the method of the present disclosure has a general formula A x C y , where A is a transition metal element, C is a chalcogen element, and X and Y represent the composition of the binary phase 2D-transition metal dichalcogenide layer.

[0064] According to further examples of the present disclosure, each deposition cycle of the cyclic deposition process 106 may include providing a transition metal precursor to the reaction chamber (step 108), providing a chalcogenide precursor to the reaction chamber (step 110), wherein one or more deposition cycles further include providing a metal precursor to the reaction chamber (step 112). In some embodiments, each deposition cycle includes providing a metal precursor to the reaction chamber (step 112), such that each deposition cycle of the cyclic deposition process 106 includes providing a transition metal precursor to the reaction chamber (step 108), providing a chalcogenide precursor to the reaction chamber (step 110), and providing a metal precursor to the reaction chamber (step 112).

[0065] In other embodiments, the optional step of providing a metal precursor may be performed once every 2 deposition cycles, or once every 3 deposition cycles, or once every 4 deposition cycles, or once every 5 deposition cycles, or once every 6 deposition cycles, or once every 7 deposition cycles, or once every 8 deposition cycles, or once every 9 deposition cycles, or once every 10 deposition cycles.

[0066] In other embodiments of the present disclosure, the metal precursor may be provided to the reaction chamber (step 112) together with the transition metal precursor (step 108) or together with the chalcogen precursor (step 110). In this case, step 112 may overlap at least some time with step 108 and / or step 110.

[0067] According to an example of the present disclosure, the addition of an optional step 112 comprising providing a metal precursor to the cyclic deposition process 106 can be used to deposit a ternary phase 2D-transition metal dichalcogenide layer. In such an example, the ternary phase 2D-transition metal dichalcogenide layer can be an alloyed 2D-transition metal dichalcogenide layer or a doped 2D-transition metal dichalcogenide layer. In such an example, the metal precursor provides an additional metal element to deposit an alloyed 2D-transition metal dichalcogenide layer, or provides an additional metal element to deposit a doped 2D-transition metal dichalcogenide layer. In such an example, the metal precursor includes an additional metal element, which is selected to be different from the transition metal element provided by the transition metal precursor in step 108. In such an example, the metal precursor includes an additional metal element, and the transition metal precursor includes a transition metal element different from the additional metal element. In some embodiments, the metal precursor includes a doping metal element, and the deposited layer includes a ternary phase doped 2D-transition metal dichalcogenide layer. Alternatively, in some embodiments, the metal precursor includes an alloying metal element and the deposited layer includes a ternary phase alloyed 2D-transition metal dichalcogenide layer.

[0068] According to an example of the present disclosure, the additional metal element provided by the metal precursor during optional step 112 is selected from Group 6 metals, Group 13 metals, and Group 16 metals. In some embodiments, the additional metal element provided by the metal precursor during optional step 112 is selected from aluminum, tungsten, and tellurium. In some embodiments, the additional metal element provided by the metal precursor during optional step 112 is selected from Group 6 metals. In some embodiments, the additional metal element provided by the metal precursor during optional step 112 is aluminum. In such an example, the cyclic deposition process 106 deposits a ternary phase 2D-transition metal dichalcogenide layer directly on the dielectric layer.

[0069] According to an example of the present disclosure, the deposited ternary 2D-transition metal dichalcogenide layer is a ternary alloy selected from the group of 2D-transition metal dichalcogenide alloy layers consisting of: MoAl x S y ,MoW x S y ,MoTe x S y ,VA1 x S y ,VW x S y ,VTe x S y ,TaAl x S y ,TaW x S y ,TaTe x S y ,MoAl x Te y ,MoW x Te y ,TaAl x Se y ,TaW x Se y ,TaTe x Se y ,NbAl x Se y ,NbW x Se y ,NbTe x Se y ,TiAl x Se y ,TiW x Se y and TiTe x Se y In some embodiments, the deposited ternary 2D-transition metal dichalcogenide layer comprises a ternary 2D-transition metal dichalcogenide having the general formula A x B y Cz An alloy of the type described above, wherein A is a transition metal element, B is a metal element different from the transition metal element A, C is a chalcogen element, and X, Y and Z represent the composition of the alloy layer.

[0070] According to a further example of the present disclosure, the deposited ternary 2D-transition metal dichalcogenide layer is a doped 2D-transition metal dichalcogenide layer selected from the group of doped 2D-transition metal dichalcogenide layers consisting of: Al:Mo x S y ,W:Mo x S y ,Te:Mo x S y ,Al:V x S y ,W:V x S y ,Te:V x S y ,Al:Ta x S y ,W:Ta x S y ,Te:Ta x S y ,Al:Mo x Te y ,W:Mo x Te y ,Al:Ta x Se y ,W:Ta x Se y ,Te:Ta x Se y ,Al:Nb x Se y ,W:Nb x Se y ,Te:Nb x Se y ,Al:Ti x Se y ,W:Ti x Se y and Te:Ti x Se y In some embodiments, the deposited doped 2D-transition metal dichalcogenide layer comprises a layer having the general formula B:A x C y A doped 2D-transition metal dichalcogenide layer, wherein B is a doping metal element, A is a transition metal element different from the doping metal element B, C is a chalcogen element, and X and Y represent the composition of the doping layer.

[0071] Figure 3The structure 300 is shown after the 2D-transition metal dichalcogenide layer deposition is completed (step 104). As shown, the 2D-transition metal dichalcogenide layer 302 is deposited directly on the dielectric layer 204. In such an example, the 2D-transition metal dichalcogenide layer 302 is deposited directly on the dielectric layer 204 (e.g., a high-k dielectric layer) without any intermediate layers between the 2D-transition metal dichalcogenide layer 302 and the dielectric layer 204.

[0072] According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer 302 is a work function metal layer. In some embodiments of the present disclosure, the 2D-transition metal dichalcogenide layer 302 is a metallic layer with stable metallic properties, so that the 2D-transition metal dichalcogenide layer 302 maintains its metallic properties under bias conditions when used in a functional semiconductor device structure. According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer of the present disclosure has stable work function properties. According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer of the present disclosure has stable conductivity / resistivity. According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer of the present disclosure has a stable band gap energy. In some embodiments of the present disclosure, the 2D-transition metal dichalcogenide layer 302 is not a phase change material. In addition, in some embodiments of the present disclosure, the 2D-transition metal dichalcogenide layer 302 is not a channel material.

[0073] Method 100( Figure 1 ) may proceed to the optional step of depositing a metallic capping layer on the 2D-transition metal dichalcogenide layer. In some embodiments, the metallic capping layer is deposited directly on the 2D-transition metal dichalcogenide layer. According to examples of the present disclosure, the 2D-transition metal dichalcogenide layer may be used as a metallic work function layer, and the optional metallic capping layer may be used as a conductive electrode to complete the gate stack. In such an example, a dielectric layer (e.g., a high-k dielectric layer) on the surface of the substrate is used as a gate dielectric layer (with or without an intermediate interface layer between the channel region and the gate dielectric layer), the 2D-transition metal dichalcogenide layer is used as a work function metal layer, and the metallic capping layer is used as a gate electrode layer.

[0074] According to an example of the present disclosure, optional step 116 includes depositing a metallic capping layer on the 2D-transition metal dichalcogenide layer. In such an example, the metallic capping layer can be deposited by a further cyclic deposition process 118. In such an example, the 2D-transition metal dichalcogenide layer can be deposited by performing one or more deposition cycles of the first cyclic deposition process 106, as described above, and the metallic capping layer can be deposited by performing one or more deposition cycles of the second cyclic deposition process 118. According to an example of the present disclosure, the 2D-transition metal dichalcogenide layer can be deposited by performing one or more deposition cycles of the first atomic layer deposition process to deposit the metallic 2D-transition metal dichalcogenide work function layer directly on the surface of the high-k dielectric layer, as described above with reference to the cyclic deposition process 106. In such an example, the metallic capping layer can be deposited by performing one or more deposition cycles of the second atomic layer deposition process to deposit the metallic capping layer directly on the metallic 2D-transition metal dichalcogenide layer (cyclic deposition process 118). In some embodiments, an optional metallic capping layer is deposited directly on the 2D-transition metal dichalcogenide layer in the same reaction chamber without any intermediate layer disposed between the 2D-transition metal dichalcogenide layer and the metallic capping layer, and without breaking vacuum between the deposition processes.

[0075] According to an example of the present disclosure, each deposition cycle of the second cyclic deposition process 118 (e.g., the second atomic deposition process) may include providing an additional metal precursor to the reaction chamber (step 120), and providing a reactant to the reaction chamber (step 122). According to an example of the present disclosure, the optional metallic capping layer may be or include one or more of the following: titanium nitride; vanadium nitride; a metal stack including titanium nitride and a metal (e.g., W, Co, Ru, Mo) or titanium nitride, titanium aluminum carbon, and titanium nitride; tungsten; tungsten nitride carbon; cobalt; copper; molybdenum; ruthenium, etc. In such an example, the additional metal precursor provided to the reaction chamber during step 120 may include a metal element selected from Ti, Va, W, Co, Ru, Mo, Cu, and Mo. In addition, in such an example, the reactant provided to the reaction chamber during step 122 may be selected from a reducing agent, a nitriding agent, a carbonizing agent, and / or mixtures and combinations thereof.

[0076] According to an example of the present disclosure, as in loop 124 ( Figure 1 ), steps 120 and 122 may be repeated, with each cycle comprising a separate deposition cycle of the cyclic deposition process 118, such as a second atomic layer deposition process. Furthermore, steps 120 and 122 may be initiated and / or terminated in any order. Furthermore, the cyclic deposition process 118 may include one or more (e.g., 1-3, or 1-5, or 1-10) repetitions of steps 120 and / or 122 before proceeding to the next process step of the cyclic deposition process 118.

[0077] The cyclic deposition process 118, such as the second atomic layer deposition process, can be repeated until the end criterion is met. For example, the end criterion can be based on the number of deposition cycles performed, or by the desired thickness of the deposited metallic capping layer. The metallic covering should be closed, and according to examples of the present disclosure, the metallic covering can be deposited to an average layer thickness of at least about 0.5 nanometers, such as 1 nanometer, or 1.5 nanometers or 3 nanometers. According to other examples of the present disclosure, the metallic covering can be deposited to the following average layer thickness: less than 20 nanometers, or less than 15 nanometers, or less than 10 nanometers, or less than 5 nanometers, or less than 3 nanometers.

[0078] Figure 4 The structure 400 is shown after the deposition of the optional metallic capping layer (step 116) is completed. As shown, the metallic capping layer 402 is deposited on the 2D-transition metal dichalcogenide layer 302. In such an example, the metallic capping layer 402 can be directly deposited on the 2D-transition metal dichalcogenide layer 302. In such an example, the 2D-transition metal dichalcogenide layer 302 can be directly disposed between the metallic capping layer 402 and the dielectric layer 204 (e.g., a high-k dielectric layer). In some embodiments, the metallic capping layer 402 can be directly deposited on the 2D-transition metal dichalcogenide layer 302 without any intermediate layers between the metallic capping layer 402 and the 2D-transition metal dichalcogenide layer 302.

[0079] According to an example of the present disclosure, ( Figure 4 The structure 400 includes a gate stack 404 (or at least a portion of a gate stack). In such an example, the dielectric layer 204 (e.g., a high-k dielectric layer) is a gate dielectric, the 2D-transition metal dichalcogenide layer 302 is a work function metal layer, and the metallic cap layer 402 is a gate electrode layer. In some embodiments, the total gate stack thickness is about 20 nanometers or less, such as less than 10 nanometers or less than 7 nm. For example, the thickness of the gate stack can be about 20 nm, about 15 nm, about 10 nm, about 8 nm, or about 5 nm. Similar gate stack thicknesses are applicable to NMOS and PMOS devices.

[0080] According to an example of the present disclosure, the structure 400 ( Figure 4) may include at least a portion of a partially fabricated semiconductor device structure. In this case, structure 400 may include a portion of a CMOS device. In such an example, structure 400 may include a portion of an NMOS device structure, and 2D-transition metal dichalcogenide layer 302 is used as a stable metallic n-type work function metal selected from MoS2, MoTe2, VS2, wherein gate stack 404 has an effective work function between 4.2eV and 4.4eV. In an alternative example, structure 400 may include a portion of a PMOS device structure, and 2D-transition metal dichalcogenide layer 302 is used as a stable metallic p-type work function metal selected from TaS2, TaSe2, NbSe2, TiSe2 and VSe2, wherein gate stack 404 has an effective work function between 5.2eV and 5.6eV.

[0081] The exemplary embodiments disclosed above do not limit the scope of the present invention, as these embodiments are merely examples of embodiments of the present invention, and the scope of the present invention is defined by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the present invention. In fact, various modifications of the present disclosure, such as alternative useful combinations of the described elements, in addition to those shown and described herein, will become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

[0082] Although certain embodiments and examples have been discussed, it will be understood by those skilled in the art that the scope of the claims extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses and obvious modifications and equivalents thereof. Indeed, various modifications of the present disclosure, such as alternative useful combinations of the described elements, in addition to those shown and described herein, will become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

[0083] In the present disclosure, where conditions and / or structures are not specified, those skilled in the art can readily provide such conditions and / or structures as routine experimentation in view of the present disclosure.

Claims

1. A method for forming a semiconductor structure, the method comprising: placing a substrate in a reaction chamber, the substrate comprising a dielectric layer; Depositing the 2D-transition metal dichalcogenide layer directly on the dielectric layer by performing one or more cycles of a cyclic deposition process, each deposition cycle of the cyclic deposition process comprising: providing a transition metal precursor to a reaction chamber; providing a chalcogen precursor to the reaction chamber; and A metallic capping layer is deposited directly on the 2D-transition metal dichalcogenide layer.

2. The method according to claim 1, wherein: The dielectric layer includes a high-k dielectric layer.

3. The method according to claim 2, wherein: The cyclic deposition process includes an atomic layer deposition process.

4. The method according to claim 3, wherein: During the atomic layer deposition process, the substrate temperature is lower than 500°C.

5. The method according to claim 1, wherein: The 2D-transition metal dichalcogenide layer includes a metallic work function layer.

6. The method according to claim 5, wherein: The 2D-transition metal dichalcogenide layer is selected from MoS2, VS2, TaS2, MoTe2, TaSe2, NbSe2 and TiSe2.

7. The method according to claim 1, wherein: The transition metal precursor includes a transition metal element selected from the group consisting of molybdenum, vanadium, tantalum, niobium and titanium.

8. The method according to claim 1, wherein: The chalcogen precursor includes a chalcogen selected from the group consisting of sulfur, selenium, and tellurium.

9. The method according to claim 1, wherein: One or more deposition cycles further include providing a metal precursor to the reaction chamber.

10. The method according to claim 9, wherein: The metal precursor includes an additional metal element, and the transition metal precursor includes a transition metal element different from the additional metal element.

11. The method according to claim 10, wherein: The additional metal element is selected from aluminum, tungsten and tellurium.

12. The method according to claim 11, wherein: The additional metal element includes a doping metal element, and the 2D-transition metal dichalcogenide layer includes a metal-doped 2D-transition metal dichalcogenide layer.

13. The method according to claim 11, wherein: The additional metal element includes a metal alloy element, and the 2D-transition metal dichalcogenide layer includes a ternary phase 2D-transition metal dichalcogenide alloy layer.

14. The method according to claim 1, wherein: The 2D-transition metal dichalcogenide layer is deposited to a thickness between 1 nm and 5 nm.

15. The method according to claim 1, wherein: The 2D-transition metal dichalcogenide layer is deposited to a thickness between 1 monolayer and 5 monolayers.

16. A method of forming at least a portion of a gate stack for a semiconductor device structure, the method comprising: placing a substrate within a reaction chamber, the substrate comprising a plurality of partially fabricated device structures, wherein one or more of the partially fabricated device structures comprises a surface layer comprising a high-k dielectric layer; performing one or more deposition cycles of a first atomic layer deposition process to deposit a metallic 2D-transition metal dichalcogenide work function layer directly on a surface of the high-k dielectric layer; as well as One or more deposition cycles of the second atomic layer deposition process are performed to deposit a metallic capping layer directly on the metallic 2D-transition metal dichalcogenide layer.

17. The method according to claim 16, wherein: The high-k dielectric layer, the metallic 2D-transition metal dichalcogenide work function layer and the metallic capping layer together constitute a gate stack of the semiconductor device structure.

18. The method according to claim 17, wherein: The semiconductor device structure comprises an NMOS device structure, and the effective work function of the gate stack is between 4.2 eV and 4.4 eV, and the total gate stack thickness is less than 20 nanometers.

19. The method according to claim 17, wherein: The semiconductor device structure comprises a PMOS device structure, and the effective work function of the gate stack is between 5.2 eV and 5.6 eV, and the total gate stack thickness is less than 20 nanometers.

20. A method for forming a ternary phase 2D-transition metal dichalcogenide layer by an atomic layer deposition process (ALD), wherein the ternary phase 2D-transition metal dichalcogenide layer has a chemical formula comprising a transition metal element, a chalcogen element, and a ternary element composed of a metal element different from the transition metal element, wherein a transition metal-containing precursor is used as a source of the transition metal element, a chalcogen element-containing precursor is used as a source of the chalcogen element, and a metal-containing precursor is used as a source of the ternary metal element.

Images