Fan control method and device and server

Abstract

The embodiment of the invention provides a fan control method and device and a server. The method is applied to a server, the server comprises a board-level management control unit BMC, a programmable logic device CPLD and a fan, and the method comprises the steps that a first activation signal of the BMC and a feedback signal of the CPLD are obtained; fault information is determined according to the first activation signal and the feedback signal, and the fault information is used for indicating whether the BMC and the CPLD have faults or not; and according to the fault information, the fan is controlled through the BMC and / or the CPLD. And the flexibility of fan control is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a fan control method, device and server. Background Art

[0002] The server can be cooled by fans to avoid malfunctions caused by excessive temperature and ensure normal operation of the server.

[0003] In actual application, the fan can be controlled by the Baseboard Management Controller (BMC) and the Complex Programmable Logic Device (CPLD). When the server's BMC has not completed startup or the BMC fails, the fan is mainly controlled by the CPLD. The CPLD determines the fan speed and controls the fan to rotate at the speed. When the BMC is started, the CPLD recognizes the BMC startup signal and the BMC mainly controls the fan. In the above process, when the CPLD and / or BMC fails, the fan will work at the highest speed or the fan speed will be adjusted by manual intervention, resulting in low flexibility in fan control. Summary of the invention

[0004] The embodiments of the present application provide a fan control method, device and server to solve the problem of low flexibility of fan control.

[0005] In a first aspect, an embodiment of the present application provides a fan control method, which is applied to a server, wherein the server includes a board management control unit BMC, a programmable logic device CPLD and a fan, and the method includes:

[0006] Acquire a first activation signal of the BMC and a feedback signal of the CPLD;

[0007] Determine fault information according to the first activation signal and the feedback signal, where the fault information is used to indicate whether the BMC and the CPLD are faulty;

[0008] The fan is controlled by the BMC and / or the CPLD according to the fault information.

[0009] The server can determine fault information based on the signals output by the BMC and CPLD, and automatically control the fan through the BMC and / or CPLD based on the fault information, thus improving the flexibility of fan control.

[0010] In a possible implementation manner, the feedback signal includes a second activation signal and an error signal; and determining fault information according to the first activation signal and the feedback signal includes:

[0011] Performing an OR operation on the first activation signal and the second activation signal to obtain an intermediate signal;

[0012] Get the preset signal;

[0013] If the preset signal matches the intermediate signal, determining that the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states;

[0014] If the preset signal and the intermediate signal do not match, the fault information is determined according to the feedback signal.

[0015] Fault information can be determined through the intermediate signal or the feedback signal, and it can be accurately determined that the fault is in the BMC and / or CPLD, so that the fan can be accurately controlled through the BMC and / or CPLD according to the fault information, thereby improving the accuracy of fan control.

[0016] In a possible implementation manner, the error signal includes at least one register signal; and determining the fault information according to the feedback signal includes:

[0017] If the error signal is abnormal, the current state of each register is determined according to the register signal, and the fault information is determined according to the current state of each register, wherein the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state;

[0018] If the second activation signal is abnormal, it is determined that the fault information is used to indicate that the current state of the CPLD is a fault state.

[0019] According to the feedback signal, it is determined that the CPLD is partially or entirely faulty, and the fan can be controlled more accurately based on the fault information subsequently, thereby improving the accuracy of fan control.

[0020] In a possible implementation manner, controlling the fan by using the BMC and / or the CPLD according to the fault information includes:

[0021] If the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states, the BMC and the CPLD are reset, and the fan is controlled by the BMC or the CPLD according to a first processing duration corresponding to the BMC and a second processing duration corresponding to the CPLD;

[0022] If the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state, determining at least one target register whose current state is the fault state, and controlling the fan through the BMC and the CPLD according to the at least one target register;

[0023] If the fault information is used to indicate that the current state of the CPLD is a fault state, the fan is controlled by the BMC.

[0024] Since the fault information indicates that there are faulty components in the BMC and CPLD, corresponding processing is performed according to the fault information and the component that controls the fan is determined. This avoids the situation where the fan needs to be manually adjusted to run at the maximum speed when the BMC and / or CPLD fails. This reduces the loss of the fan and improves the flexibility of controlling the fan.

[0025] In a possible implementation, controlling the fan by the BMC or the CPLD according to the first processing duration corresponding to the BMC and the second processing duration corresponding to the CPLD includes:

[0026] If the first processing duration is less than or equal to the second processing duration, controlling the fan through the BMC;

[0027] If the first processing time is longer than the second processing time, the fan is controlled by the CPLD when the CPLD is reset, and the fan is controlled by the BMC and the CPLD when the BMC is reset.

[0028] When performing the reset process, the device that completes the reset first can be determined according to the processing time. The fan can be controlled by the device that completes the reset first, so as to reduce the time the fan runs at the preset speed, reduce the fan loss, and extend the service life of the fan.

[0029] In a possible implementation, controlling the fan through the BMC and the CPLD according to the at least one target register includes:

[0030] Performing a closing process on the at least one target register to obtain a target CPLD, wherein the state of at least one target register in the target CPLD is a closed state;

[0031] The fan is controlled by the BMC and the target CPLD.

[0032] The BMC can detect the fault condition of the CPLD part of the fan control system through the fault signal sent by the CPLD. Without adding additional chips, the BMC can adjust the fan module PWM control strategy according to the fault information, reducing the design complexity and cost.

[0033] In a second aspect, an embodiment of the present application provides a fan control device, the device comprising:

[0034] An acquisition module, used for acquiring a first activation signal of the BMC and a feedback signal of the CPLD;

[0035] A determination module, configured to determine fault information according to the first activation signal and the feedback signal, wherein the fault information is used to indicate whether the BMC and the CPLD are faulty;

[0036] A control module is used to control the fan through the BMC and / or the CPLD according to the fault information.

[0037] In a possible implementation manner, the determining module is specifically configured to:

[0038] Performing an OR operation on the first activation signal and the second activation signal to obtain an intermediate signal;

[0039] Get the preset signal;

[0040] If the preset signal matches the intermediate signal, determining that the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states;

[0041] If the preset signal and the intermediate signal do not match, the fault information is determined according to the feedback signal.

[0042] In a possible implementation manner, the determining module is specifically configured to:

[0043] If the error signal is abnormal, the current state of each register is determined according to the register signal, and the fault information is determined according to the current state of each register, wherein the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state;

[0044] If the second activation signal is abnormal, it is determined that the fault information is used to indicate that the current state of the CPLD is a fault state.

[0045] In a possible implementation manner, the control module is specifically used to:

[0046] If the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states, the BMC and the CPLD are reset, and the fan is controlled by the BMC or the CPLD according to a first processing duration corresponding to the BMC and a second processing duration corresponding to the CPLD;

[0047] If the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state, determining at least one target register whose current state is the fault state, and controlling the fan through the BMC and the CPLD according to the at least one target register;

[0048] If the fault information is used to indicate that the current state of the CPLD is a fault state, the fan is controlled by the BMC.

[0049] In a possible implementation manner, the control module is specifically used to:

[0050] If the first processing duration is less than or equal to the second processing duration, controlling the fan through the BMC;

[0051] If the first processing time is longer than the second processing time, the fan is controlled by the CPLD when the CPLD is reset, and the fan is controlled by the BMC and the CPLD when the BMC is reset.

[0052] In a possible implementation manner, the control module is specifically used to:

[0053] Performing a closing process on the at least one target register to obtain a target CPLD, wherein the state of at least one target register in the target CPLD is a closed state;

[0054] The fan is controlled by the BMC and the target CPLD.

[0055] In a third aspect, an embodiment of the present application provides a server, including:

[0056] at least one processor; and

[0057] a memory communicatively connected to the at least one processor; wherein,

[0058] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform any method described in the first aspect.

[0059] In a fourth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute any one of the methods described in the first aspect.

[0060] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements any method in the first aspect when executed by a processor.

[0061] The fan control method, device and server provided in the embodiment of the present application can determine fault information according to the signals output by the BMC and CPLD. And according to the fault information, the fan is automatically controlled through the BMC and / or CPLD. This avoids the situation where the fan will work at the highest speed or the fan speed will be adjusted by manual intervention when the CPLD and BMC fail, or the CPLD fails, thereby improving the flexibility of fan control. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0063] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present application;

[0064] Figure 2 A schematic diagram of a flow chart of a fan control method provided in an embodiment of the present application;

[0065] Figure 3 A schematic diagram of the structure of a server provided in an embodiment of the present application;

[0066] Figure 4 A flow chart of another fan control method provided in an embodiment of the present application;

[0067] Figure 5 A schematic diagram of a process for controlling at least one target register provided in an embodiment of the present application;

[0068] Figure 6 A schematic diagram of a fan control process provided by an embodiment of the present application;

[0069] Figure 7 A schematic diagram of the structure of a fan control device provided in an embodiment of the present application;

[0070] Figure 8 A schematic diagram of the structure of a server provided in an embodiment of the present application.

[0071] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0072] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0073] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0074] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0075] For ease of understanding, below, combined Figure 1 , the application scenarios to which the embodiments of the present application are applicable are described.

[0076] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of the present application. Figure 1 , including a server 101. The server 101 is provided with a BMC, a CPLD and a fan. Among them, the BMC and the CPLD can be a chip or a chip module. When the BMC of the server 101 has not completed the startup or the BMC fails, the fan is mainly controlled by the CPLD. The CPLD determines the speed of the fan and controls the fan to rotate at the speed. When the BMC is started, the CPLD recognizes the BMC startup signal, the BMC of the server 101 sends a control signal to the CPLD, and the CPLD controls the fan through the control signal.

[0077] In the above process, when the CPLD and BMC fail, or the CPLD fails, the fan will work at the highest speed or the fan speed will be adjusted manually, resulting in low flexibility of fan control.

[0078] In the embodiment of the present application, the server can determine the fault information according to the signals output by the BMC and the CPLD. And according to the fault information, the fan is automatically controlled through the BMC and / or the CPLD. This avoids the situation where the fan operates at the highest speed or the fan speed is adjusted manually when the CPLD and the BMC fail, or the CPLD fails, thereby improving the flexibility of fan control.

[0079] The method shown in the present application is described below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.

[0080] Figure 2 A schematic diagram of a fan control method provided in an embodiment of the present application. Figure 2 , the method may include:

[0081] S201, obtaining a first activation signal of a BMC and a feedback signal of a CPLD.

[0082] The execution subject of the embodiment of the present application can be a server, or a fan control device arranged in the server. The fan control device can be implemented by software, or by a combination of software and hardware. The server includes a BMC, a CPLD and a fan.

[0083] The feedback signal includes a second activation signal and an error signal. The activation signal may be an active signal. The error signal includes at least one register signal, and the error signal and the register signal may be pulse width modulation (PWM) signals. For example, the error signal may be a PWM Error signal, and the register signal may be a PWM_OK signal.

[0084] The server is provided with a chip, and the chip is provided with a logic gate module. The logic gate module of the server can obtain the first activation signal and the second activation signal of the BMC. The BMC in the server can obtain the feedback signal of the CPLD.

[0085] For example, the logic gate module of the server obtains the first activation signal of the BMC as signal A1, and obtains the second activation signal of the CPLD as signal A2. The feedback signal obtained by the BMC of the server from the CPLD includes signal A2 and error signal A3.

[0086] S202: Determine fault information according to the first activation signal and the feedback signal.

[0087] The fault information is used to indicate that the current status of the BMC and CPLD are respectively in a fault status.

[0088] The fault information can be determined according to the first activation signal and the feedback signal in the following manner: performing an OR operation on the first activation signal and the second activation signal to obtain an intermediate signal; obtaining a preset signal; if the preset signal and the intermediate signal match, determining that the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states; if the preset signal and the intermediate signal do not match, determining the fault information according to the feedback signal.

[0089] The preset signal may be a low level signal. The preset signal may be set in advance and stored in a preset storage space of the server.

[0090] If the current state of the BMC is a non-fault state, the first activation signal output by the BMC is a high level signal. If the current state of the BMC is a fault state, the first activation signal output by the BMC is a low level signal. If the current state of the CPLD is a non-fault state, the first activation signal output by the CPLD is a high level signal. If the current state of the CPLD is a fault state, the first activation signal output by the CPLD is a low level signal.

[0091] Fault information can be determined through the intermediate signal or the feedback signal, and it can be accurately determined that the fault is in the BMC and / or CPLD, so that the fan can be accurately controlled through the BMC and / or CPLD according to the fault information, thereby improving the accuracy of fan control.

[0092] For example, according to the above example, it is determined that the first activation signal of the BMC is signal A1, and the second activation signal of the CPLD is signal A2. Signal A1 and signal A2 are low-level signals respectively. The logic gate module of the server performs an OR operation on the first activation signal and the second activation signal, and the obtained intermediate signal is a low-level signal. The logic gate module of the server obtains the preset signal as a low-level signal. Therefore, the logic gate module of the server determines that the intermediate signal matches the preset signal. At this time, the logic gate module of the server determines that the fault information is used to indicate that the current states of the BMC and CPLD are respectively fault states.

[0093] S203: Control the fan through the BMC and / or CPLD according to the fault information.

[0094] If the fault information indicates that the BMC and CPLD are faulty, you can reset the BMC and CPLD. After the reset, the fans can be controlled through the BMC and CPLD. If the fault information indicates that the CPLD is faulty, the fans can be controlled through the BMC.

[0095] Next, combine Figure 3 , describing the structure of each component in the server. Figure 3 This is a schematic diagram of the structure of the server provided in the embodiment of the present application. Figure 3 , including a server 301. The server 301 includes a BMC, a CPLD, a fan module, a logic gate module and a watchdog module. The fan module includes a fan in the server and an integrated circuit connected to the fan. The logic gate module and the watchdog module are respectively arranged in the chip. The fan module is respectively connected to the BMC and the CPLD, the CPLD is connected to the BMC, the logic gate module is respectively connected to the watchdog module, the BMC and the CPLD, and the watchdog module is respectively connected to the logic gate module, the BMC and the CPLD.

[0096] The logic gate module obtains the first activation signal of the BMC and the second activation signal of the CPLD, and performs an OR operation on the first activation signal and the second activation signal to obtain an intermediate signal. When both the BMC and the CPLD are normal, the intermediate signal is a high-level signal. When the BMC and the CPLD are faulty respectively, the intermediate signal is a low-level signal. The logic gate module outputs the intermediate signal to the watchdog module. When the input signal of the watchdog module is a low-level signal, the watchdog module resets the BMC and the CPLD. During the reset process, the speed of the fan is the preset speed. After the BMC and the CPLD complete the reset, the speed of the fan is determined by the BMC and the fan is controlled to rotate. The preset speed can be the maximum speed corresponding to the fan.

[0097] When it is determined that the CPLD is faulty, the BMC obtains the fault signal of the CPLD. And according to the fault signal, the fault level of the CPLD is determined. When the fault level is 1, the PWM signal output by the CPLD is partially abnormal. According to the abnormal PWM signal, the BMC turns on the pass-through function of the PWM signal output by the BMC to the CPLD. At this time, the PWM signal output by the BMC to the CPLD does not pass through the module with the passthrough function, but is directly output by the BMC to the fan module. When the fault level is 2, the CPLD is abnormal as a whole. The BMC turns on the pass-through function of all PWM signals output to the CPLD, and the fan module is directly controlled by the BMC.

[0098] Since the fault information indicates that there are faulty components in the BMC and CPLD, corresponding processing is performed according to the fault information and the component that controls the fan is determined. This avoids the situation where the fan needs to be manually adjusted to run at the maximum speed when the BMC and / or CPLD fails. This reduces the loss of the fan and improves the flexibility of controlling the fan.

[0099] The fan control method provided in the embodiment of the present application obtains the first activation signal of the BMC and the feedback signal of the CPLD. According to the first activation signal and the feedback signal, the fault information is determined. According to the fault information, the fan is controlled by the BMC and / or the CPLD. In the above process, the server can determine the fault information according to the signals output by the BMC and the CPLD. And according to the fault information, the fan is automatically controlled by the BMC and / or the CPLD. When the CPLD and the BMC fail, or the CPLD fails, the fan is prevented from operating at the highest speed or adjusting the fan speed by manual intervention, thereby improving the flexibility of fan control.

[0100] Based on any of the above embodiments, Figure 4 , the detailed process of fan control is explained.

[0101] Figure 4 This is a flow chart of another fan control method provided in an embodiment of the present application. Figure 4 , the method comprising:

[0102] S401: Acquire a first activation signal of a BMC and a feedback signal of a CPLD.

[0103] It should be noted that the execution process of S401 can refer to S201 and will not be repeated here.

[0104] S402 , performing an OR operation on the first activation signal and the second activation signal to obtain an intermediate signal.

[0105] For example, the server's logic gate module obtains the first activation signal of the BMC as signal B1, and obtains the second activation signal of the CPLD as signal B2. The server's BMC obtains the feedback signal of the CPLD including signal B2 and error signal B3. Signal A1 and signal A2 are high-level signals respectively. The server's logic gate module performs an OR operation on the first activation signal and the second activation signal, and the obtained intermediate signal is a high-level signal.

[0106] S403: Obtain a preset signal.

[0107] The preset signal may be a low level signal.

[0108] S404: If the preset signal and the intermediate signal match, it is determined that the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states.

[0109] S405: If the preset signal and the intermediate signal do not match, determine the fault information according to the feedback signal.

[0110] The feedback signal includes a second activation signal and an error signal. The error signal includes at least one register signal.

[0111] If the preset signal and the intermediate signal do not match, the fault information can be determined according to the feedback signal in the following manner: if there is an abnormality in the error signal, the current state of each register is determined according to the register signal, and the fault information is determined according to the current state of each register, and the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state; if there is an abnormality in the second activation signal, the fault information is determined to indicate that the current state of the CPLD is a fault state.

[0112] According to the feedback signal, it is determined that the CPLD is partially or entirely faulty, and the fan can be controlled more accurately based on the fault information subsequently, thereby improving the accuracy of fan control.

[0113] If the second activation signal is a low level signal, it can be determined that the second activation signal is abnormal. If the second activation signal is a high level signal, it can be determined that the second activation signal is not abnormal.

[0114] Whether the error signal is abnormal can be determined in the following manner: determine the signal value corresponding to each register signal; if at least one signal value has a signal value that is a preset value, determine that the error signal is abnormal; if at least one signal value has no signal value that is the preset value, determine that the error signal is not abnormal.

[0115] The preset value may be 0. The preset value may be set in advance and stored in a preset storage space of the server.

[0116] For any register, if the signal value corresponding to the register signal is a preset value, the current state of the register can be determined to be a fault state. If the signal value corresponding to the register signal is not a preset value, the current state of the register can be determined to be a non-fault state.

[0117] For example, according to the above example, it is determined that signal A1 and signal A2 are high-level signals respectively, and the intermediate signal is a high-level signal. Therefore, it can be determined that the preset signal and the intermediate signal do not match. At this time, the BMC of the server obtains the feedback signal sent by the CPLD. The BMC of the server determines that the error signal B3 can be specifically shown in Table 1:

[0118] Table 1

[0119]

[0120] According to Table 1, it can be determined that the signal value corresponding to the register signal B31 is the preset value 0. Therefore, the BMC of the server can determine that the error signal B3 is abnormal. According to the signal value corresponding to the register signal B31 being the preset value 0, it can be determined that the current state of the register B1 is a fault state. The BMC of the server can determine that the fault information is used to indicate that the current state of the register B1 of the CPLD is a fault state.

[0121] S406: If the fault information indicates that the current states of the BMC and the CPLD are respectively fault states, the BMC and the CPLD are reset.

[0122] The fan control system of the server has a certain self-repair capability. When an abnormality occurs in the BMC or CPLD, the abnormal module can be reset. After a successful reset, the fan control system can be restored. Avoid manual adjustment or running the fan at the maximum speed for a long period of time.

[0123] For example, assuming that signal A1 and signal A2 are low-level signals respectively, it can be determined that the intermediate signal is a low-level signal. At this time, if the intermediate signal matches the preset signal, it can be determined that the fault information is used to indicate that the current states of the BMC and CPLD are respectively fault states. The watchdog module of the server sends a low-level signal to the BMC and CPLD to reset the BMC and CPLD.

[0124] S407 . Control the fan through the BMC or the CPLD according to the first processing duration corresponding to the BMC and the second processing duration corresponding to the CPLD.

[0125] The fan may be controlled by the BMC or the CPLD according to the first processing time corresponding to the BMC and the second processing time corresponding to the CPLD in the following manner: if the first processing time is less than or equal to the second processing time, the fan is controlled by the BMC; if the first processing time is greater than the second processing time, the fan is controlled by the CPLD when the CPLD is reset, and the fan is controlled by the BMC and the CPLD when the BMC is reset.

[0126] When performing the reset process, the device that completes the reset first can be determined according to the processing time. The fan can be controlled by the device that completes the reset first, so as to reduce the time the fan runs at the preset speed, reduce the fan loss, and extend the service life of the fan.

[0127] The fan can be controlled by the BMC and the CPLD in the following manner: the BMC determines a first speed of the fan according to the temperature and operating parameters of the server; the BMC generates a control signal according to the first speed, where the control signal is a PWM signal; the control signal is sent to the CPLD; and the CPLD controls the fan to run at the first speed according to the control signal.

[0128] The fan can be controlled by CPLD in the following manner: the CPLD determines a first speed of the fan according to the temperature and operating parameters of the server; the CPLD generates a control signal according to the first speed, where the control signal is a PWM signal; and the CPLD controls the fan to run at the first speed according to the control signal.

[0129] For example, according to the above example, the watchdog module of the server sends a low-level signal to the BMC and CPLD to reset the BMC and CPLD. The server obtains the first processing time corresponding to the BMC as 15s, and obtains the second processing time corresponding to the CPLD as 12s. Since the first processing time is longer than the second processing time, when the CPLD is reset, the CPLD determines that the first speed of the fan is 3500RPM based on the temperature, operating parameters, etc. of the server. The CPLD generates a control signal based on the first speed, and controls the fan to run at 3500RPM through the control signal. When it is determined that the BMC reset is completed, the BMC determines the first speed of the fan based on the temperature, operating parameters, etc. of the server, and generates a control signal based on the first speed. The BMC sends a control signal to the CPLD so that the CPLD controls the fan through the control signal.

[0130] S408: If the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state, determine at least one target register whose current state is a fault state.

[0131] For example, according to the above example, it is determined that the fault information is used to indicate that the current state of the register B1 of the CPLD is a fault state, and then the target register can be determined to be the register B1.

[0132] S409: Control the fan through the BMC and the CPLD according to at least one target register.

[0133] The fan can be controlled by the BMC and the CPLD according to at least one target register in the following manner: at least one target register is closed to obtain a target CPLD, wherein the state of at least one target register in the target CPLD is a closed state; and the fan is controlled by the BMC and the target CPLD.

[0134] The BMC may enable the pass through function of the target register to close at least one target register. The at least one target register is closed so that when the BMC inputs a control signal to the CPLD, the at least one target register is not passed through. The control signal is directly output to the fan module through the CPLD to control the operation of the fan.

[0135] The BMC can detect the fault condition of the CPLD part of the fan control system through the fault signal sent by the CPLD. Without adding additional chips, the BMC can adjust the fan module PWM control strategy according to the fault information, reducing the design complexity and cost.

[0136] For example, according to the above example, the target register is determined to be register B1. The BMC of the server turns on the pass through function of register B1 to close at least one target register to obtain a target CPLD. In this way, when the BMC inputs a control signal to the CPLD, it does not pass through register B1. The control signal is directly output to the fan module through the target CPLD to control the operation of the fan.

[0137] When the fan is controlled by the BMC and the target CPLD, the CPLD may be reset. When the reset is completed, the pass-through function of at least one target register may be turned off, and the fan may be controlled by the CPLD and the BMC.

[0138] Next, combine Figure 5 , describing a process of controlling at least one target register. Figure 5 A schematic diagram of a process for controlling at least one target register provided in an embodiment of the present application. Figure 5 , including server 501. Server 501 is provided with CPLD, BMC and fan module. The BMC of server 501 obtains a feedback signal. When it is determined that the first activation signal is normal and the error signal is abnormal. The BMC of server 501 obtains at least one register signal through the IIC signal, and determines the current state of each register according to the at least one register signal. And the register whose current state is a fault state is determined as the target register. The BMC of server 501 turns on the pass through function of register B1 to close at least one target register. In this way, the control signal can be output to the fan module through the CPLD without passing through the target register of the CPLD, thereby controlling the fan.

[0139] When the second activation signal is abnormal, it can be determined that the CPLD as a whole is abnormal. The BMC of the server 501 turns on the pass through function of the CPLD and directly outputs the control signal to the fan module.

[0140] When the CPLD as a whole fails, the fan is directly controlled by the BMC. At this time, the BMC of the server 501 outputs a reset signal to the CPLD. When the BMC of the server 501 determines that the second activation signal and the error signal are normal, the BMC turns off the passthrough function of the CPLD, and the fan is controlled by the BMC outputting a control signal (PWM) to the CPLD, which then outputs it to the fan module.

[0141] After the CPLD is reset, the fan control system can self-restore to a normal state, avoiding manual adjustments and improving the efficiency of fan control.

[0142] S410: If the fault information indicates that the current state of the CPLD is a fault state, control the fan through the BMC.

[0143] The fan control method provided in the embodiment of the present application obtains the first activation signal of the BMC and the feedback signal of the CPLD. The first activation signal and the second activation signal are processed by an OR operation to obtain an intermediate signal. A preset signal is obtained. Fault information is determined according to the intermediate signal and the feedback signal. If the fault information is used to indicate that the current states of the BMC and the CPLD are respectively in a fault state, the BMC and the CPLD are reset. The fan is controlled by the BMC or the CPLD according to the first processing duration corresponding to the BMC and the second processing duration corresponding to the CPLD. If the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state, at least one target register whose current state is a fault state is determined. According to at least one target register, the fan is controlled by the BMC and the CPLD. If the fault information is used to indicate that the current state of the CPLD is a fault state, the fan is controlled by the BMC. In the above process, the server can determine the fault information according to the signals output by the BMC and the CPLD. And according to the fault information, the fan is automatically controlled by the BMC and / or the CPLD. This prevents the fan from operating at the highest speed or requiring manual intervention to adjust the fan speed when the CPLD and BMC fail, or when the CPLD fails. This reduces fan loss and improves fan control flexibility.

[0144] Based on any of the above embodiments, Figure 6 , the fan control process is illustrated with an example.

[0145] Figure 6 This is a schematic diagram of the fan control process provided by the embodiment of the present application. Figure 6, including server 601. A fan control system and a fan module are provided in server 601. Among them, the fan control system includes BMC, CPLD, logic gate module and watchdog module. The logic gate module of server 601 obtains the first activation signal of BMC as signal C1, obtains the second activation signal of CPLD as signal C2, and performs OR operation on the first activation signal and the second activation signal to obtain the intermediate signal C11. The intermediate signal C11 is a high-level signal. If the server 601 obtains the preset signal as a low-level signal, it can be determined that the intermediate signal matches the preset signal. Therefore, the logic gate module outputs the intermediate signal to the watchdog module. The input signal of the watchdog module is a high-level signal. Therefore, the BMC and CPLD are not reset, so that the BMC and CPLD operate normally.

[0146] The BMC of server 601 obtains the feedback signal of CPLD, and determines that there is an abnormality in the second activation signal in the feedback signal. At this time, the BMC of server 601 determines that the CPLD is abnormal as a whole. The BMC of server 601 turns on the pass through function of CPLD and outputs the control signal directly to the fan module. That is, the BMC of server 601 directly controls the fan. The BMC of server 601 sends a reset signal to CPLD. After receiving the reset signal, the CPLD of server 601 resets the CPLD. When the BMC of server 601 determines that the second activation signal and the error signal are normal, the BMC of server 601 turns off the passthrough function of CPLD, and the fan control is output by the BMC to the CPLD, and the CPLD outputs it to the fan module.

[0147] The fan control process provided in the embodiment of the present application obtains the first activation signal of the BMC and the feedback signal of the CPLD. The first activation signal and the second activation signal are processed by OR operation to obtain an intermediate signal. The preset signal is obtained. The fault information is determined according to the intermediate signal and the feedback signal. If the fault information is used to indicate that the current states of the BMC and the CPLD are respectively in a fault state, the BMC and the CPLD are reset. According to the first processing duration corresponding to the BMC and the second processing duration corresponding to the CPLD, the fan is controlled by the BMC or the CPLD. If the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state, at least one target register whose current state is a fault state is determined. According to at least one target register, the fan is controlled by the BMC and the CPLD. If the fault information is used to indicate that the current state of the CPLD is a fault state, the fan is controlled by the BMC. In the above process, the fault conditions of the fan control system BMC and the CPLD can be detected by the logic gate module and the watchdog module. Without human intervention, the fan control system can work at full speed for a short period of time, and the fan system is controlled by the PWM signal of the BMC after the BMC and the CPLD are reset. This prevents the fan from operating at the highest speed or requiring manual intervention to adjust the fan speed when the CPLD and BMC fail, or when the CPLD fails. This reduces fan loss and improves fan control flexibility.

[0148] Figure 7 This is a schematic diagram of the structure of the fan control device provided in the embodiment of the present application. Figure 7 , the fan control device 10 may include:

[0149] An acquisition module 11 is used to acquire a first activation signal of the BMC and a feedback signal of the CPLD;

[0150] A determination module 12, configured to determine fault information according to the first activation signal and the feedback signal, wherein the fault information is used to indicate whether the BMC and the CPLD are faulty;

[0151] The control module 13 is used to control the fan through the BMC and / or the CPLD according to the fault information.

[0152] In a possible implementation manner, the determining module 12 is specifically configured to:

[0153] Performing an OR operation on the first activation signal and the second activation signal to obtain an intermediate signal;

[0154] Get the preset signal;

[0155] If the preset signal matches the intermediate signal, determining that the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states;

[0156] If the preset signal and the intermediate signal do not match, the fault information is determined according to the feedback signal.

[0157] In a possible implementation manner, the determining module 12 is specifically configured to:

[0158] If the error signal is abnormal, the current state of each register is determined according to the register signal, and the fault information is determined according to the current state of each register, wherein the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state;

[0159] If the second activation signal is abnormal, it is determined that the fault information is used to indicate that the current state of the CPLD is a fault state.

[0160] In a possible implementation manner, the control module 13 is specifically configured to:

[0161] If the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states, the BMC and the CPLD are reset, and the fan is controlled by the BMC or the CPLD according to a first processing duration corresponding to the BMC and a second processing duration corresponding to the CPLD;

[0162] If the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state, determining at least one target register whose current state is the fault state, and controlling the fan through the BMC and the CPLD according to the at least one target register;

[0163] If the fault information is used to indicate that the current state of the CPLD is a fault state, the fan is controlled by the BMC.

[0164] In a possible implementation manner, the control module 13 is specifically configured to:

[0165] If the first processing duration is less than or equal to the second processing duration, controlling the fan through the BMC;

[0166] If the first processing time is longer than the second processing time, the fan is controlled by the CPLD when the CPLD is reset, and the fan is controlled by the BMC and the CPLD when the BMC is reset.

[0167] In a possible implementation manner, the control module 13 is specifically configured to:

[0168] Performing a closing process on the at least one target register to obtain a target CPLD, wherein the state of at least one target register in the target CPLD is a closed state;

[0169] The fan is controlled by the BMC and the target CPLD.

[0170] The fan control device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0171] Figure 8 This is a schematic diagram of the structure of the server provided in the embodiment of the present application. Figure 8 The server 20 may include: a memory 21 and a processor 22. Exemplarily, the memory 21 and the processor 22 are interconnected via a bus 23.

[0172] The memory 21 is used to store program instructions;

[0173] The processor 22 is used to execute the program instructions stored in the memory, so as to enable the server 20 to execute the method shown in the above method embodiment.

[0174] The server provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0175] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the above method.

[0176] The embodiment of the present application may also provide a computer program product, including a computer program, which can implement the above method when executed by a processor.

[0177] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The above-mentioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the above-mentioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), flash memory, hard disk, solid state drive, magnetic tape, floppy disk, optical disc and any combination thereof.

[0178] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0179] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0180] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0181] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

[0182] In the present application, the term "include" and its variations may refer to non-restrictive inclusion; the term "or" and its variations may refer to "and / or". The terms "first", "second", etc. in the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In the present application, "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previously associated objects are in an "or" relationship.

Claims

1. A fan control method, characterized in that: Applied to a server, the server includes a board management control unit BMC, a programmable logic device CPLD and a fan, and the method includes: Acquire a first activation signal of the BMC and a feedback signal of the CPLD; Determine fault information according to the first activation signal and the feedback signal, where the fault information is used to indicate whether the BMC and the CPLD are faulty; The fan is controlled by the BMC and / or the CPLD according to the fault information.

2. The method according to claim 1, characterized in that The feedback signal includes a second activation signal and an error signal; and determining fault information according to the first activation signal and the feedback signal includes: Performing an OR operation on the first activation signal and the second activation signal to obtain an intermediate signal; Get the preset signal; If the preset signal matches the intermediate signal, determining that the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states; If the preset signal and the intermediate signal do not match, the fault information is determined according to the feedback signal.

3. The method according to claim 2, characterized in that The error signal includes at least one register signal; determining the fault information according to the feedback signal includes: If the error signal is abnormal, the current state of each register is determined according to the register signal, and the fault information is determined according to the current state of each register, wherein the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state; If the second activation signal is abnormal, it is determined that the fault information is used to indicate that the current state of the CPLD is a fault state.

4. The method according to any one of claims 1 to 3, characterized in that: According to the fault information, controlling the fan by the BMC and / or the CPLD includes: If the fault information is used to indicate that the current states of the BMC and the CPLD are respectively fault states, the BMC and the CPLD are reset, and the fan is controlled by the BMC or the CPLD according to a first processing duration corresponding to the BMC and a second processing duration corresponding to the CPLD; If the fault information is used to indicate that the current state of at least one register of the CPLD is a fault state, determining at least one target register whose current state is the fault state, and controlling the fan through the BMC and the CPLD according to the at least one target register; If the fault information is used to indicate that the current state of the CPLD is a fault state, the fan is controlled by the BMC.

5. The method according to claim 4, characterized in that According to the first processing duration corresponding to the BMC and the second processing duration corresponding to the CPLD, controlling the fan by the BMC or the CPLD includes: If the first processing duration is less than or equal to the second processing duration, controlling the fan through the BMC; If the first processing time is longer than the second processing time, the fan is controlled by the CPLD when the CPLD is reset, and the fan is controlled by the BMC and the CPLD when the BMC is reset.

6. The method according to claim 5, characterized in that According to the at least one target register, controlling the fan through the BMC and the CPLD includes: Performing a closing process on the at least one target register to obtain a target CPLD, wherein the state of at least one target register in the target CPLD is a closed state; The fan is controlled by the BMC and the target CPLD.

7. A fan control device, characterized in that: The device comprises: An acquisition module, used for acquiring a first activation signal of the BMC and a feedback signal of the CPLD; A determination module, configured to determine fault information according to the first activation signal and the feedback signal, wherein the fault information is used to indicate whether the BMC and the CPLD are faulty; A control module is used to control the fan through the BMC and / or the CPLD according to the fault information.

8. A server, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: in, The computer instructions are used to make a computer execute the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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