Server, data transmission method for server, and storage medium

Abstract

Embodiments of the present application provide a server, a data transmission method for the server, and a storage medium. The server comprises an extended chip, a front-end I3C bus, and a first programmable logic device; the extended chip comprises a first master I3C interface; the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces; the front-end I3C bus is an I3C bus that connects the first master I3C interface to the first slave I3C interface; the front-end I3C bus is used for performing data transmission between the extended chip and the first programmable logic device; and the extended chip is used for performing data exchange with the first programmable logic device by means of the front-end I3C bus, so as to realize GPIO extension of the extended chip by means of the plurality of GPIO interfaces. The present application solves the problem in the related art of poor adaptability of input / output extension of a server, and achieves the effect of improving the adaptability of input / output extension of a server.

Description

Server, data transmission method of server, and storage medium

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202410752496.1, filed on June 12, 2024, and entitled "Server, data transmission method of server, and storage medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of computers, and in particular, to a server, a data transmission method of the server, and a storage medium. BACKGROUND

[0004] The number of GPIOs (General Purpose Input / Output) of most chips in a server is usually fixed. With the development of server architecture, the number of GPIOs has gradually failed to meet the needs as the number of devices required to be connected by the chips and the communication protocols become more and more complex.

[0005] In the related art, the I / O (Input / Output) of the server can be extended using a communication bus in combination with hardware, for example, using a bridge chip to connect external devices. SUMMARY

[0006] Embodiments of the present application provide a server, a data transmission method of the server, and a storage medium to at least solve the problem of poor adaptability of input / output extension of the server in the related art.

[0007] According to an aspect of embodiments of the present application, a server is provided, which includes an extended chip, a front-end I3C bus, and a first programmable logic device, the extended chip includes a first master I3C interface, the first programmable logic device includes a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus is an I3C bus connecting the first master I3C interface and the first slave I3C interface, and the front-end I3C bus is configured to perform data transmission between the extended chip and the first programmable logic device, wherein the extended chip is configured to exchange data with the first programmable logic device through the front-end I3C bus, so as to realize GPIO extension of the extended chip through the plurality of GPIO interfaces.

[0008] According to another aspect of the embodiments of the present application, a data transmission method of a server is provided, the server comprising an extended chip, a front-end I3C bus and a first programmable logic device, the extended chip comprising a first master I3C interface, the first programmable logic device comprising a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus being an I3C bus connecting the first master I3C interface and the first slave I3C interface, the front-end I3C bus being configured to perform data transmission between the extended chip and the first programmable logic device, wherein the method comprises: receiving, by the first slave I3C interface, first control data transmitted by the extended chip via the front-end I3C bus, wherein the first control data is configured to control a first designated operation performed on a GPIO interface of the first programmable logic device, and the GPIO interface of the first programmable logic device is configured to extend a GPIO of the extended chip; and performing, in response to the received first control data, the first designated operation on a GPIO interface of the plurality of GPIO interfaces corresponding to the first control data.

[0009] According to another aspect of the embodiments of the present application, a computer readable storage medium is also provided, the computer readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the method embodiments described above when executed.

[0010] According to another aspect of the embodiments of the present application, an electronic device is also provided, comprising a memory and a processor, the memory storing a computer program, and the processor being configured to execute the computer program to perform the steps in any of the method embodiments described above.

[0011] According to another aspect of the embodiments of the present application, a computer program product is also provided, comprising a computer program, the computer program being executed by a processor to implement the steps in any of the method embodiments described above.

[0012] Through the present application, the extended chip exchanges data with the programmable logic device through the I3C bus to realize GPIO extension of the extended chip through the GPIO interface of the programmable logic device, and the GPIO extension is realized using the programmable logic device, the number of the extension can be changed according to the model of the programmable logic device, the number of the programmable logic devices and the internal code setting, the extension is diversified, and the problem of poor adaptability of the input and output extension of the server in the related art can be solved, the number of the input and output ports of the server and the flexibility of the server are increased, and thus the performance and the function of the server are improved, and the effect of improving the adaptability of the input and output extension of the server is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a schematic diagram of a server according to an embodiment of the present application.

[0014] FIG. 2 is a schematic diagram of a CPLD extension internal topology according to an embodiment of the present application.

[0015] FIG. 3 is a CPLD extended IO system topology diagram according to an embodiment of the present application.

[0016] FIG. 4 is a flow diagram of a data transmission method of a server according to an embodiment of the present application.

[0017] FIG. 5 is a schematic diagram of a typical HDR-BT mode frame according to an embodiment of the present application.

[0018] FIG. 6 is a flow diagram of another data transmission method of a server according to an embodiment of the present application.

[0019] FIG. 7 is an optional CPLD extended CPU IO example topology diagram according to an embodiment of the present application.

[0020] FIG. 8 is a schematic diagram of an I3C entering high-speed transmission diagram according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0022] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0023] In the present embodiment, a server is provided, and FIG. 1 is a schematic diagram of a server according to an embodiment of the present application, as shown in FIG. 1, the server comprises:

[0024] an extended chip, a front-end I3C (Improved Inter-Integrated Circuit) bus and a first programmable logic device, the extended chip comprising a first master I3C interface, the first programmable logic device comprising a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus being an I3C bus connecting the first master I3C interface and the first slave I3C interface, the front-end I3C bus being configured to perform data transmission between the extended chip and the first programmable logic device, wherein

[0025] the extended chip is configured to exchange data with the first programmable logic device through the front-end I3C bus, so as to realize GPIO extension of the extended chip through the plurality of GPIO interfaces.

[0026] With the emergence of artificial intelligence (AI) and machine learning workloads, servers tend to high-performance computing power and high storage capacity, requiring faster and more flexible I / O options. For chips such as CPU (Central Processing Unit), GPU (Graphic Processing Unit), BMC (Baseboard Management Controller, a controller on the server motherboard for server management), the number of GPIOs is fixed, but as the server architecture develops, the number of chips connected and communication protocols become more complex, and the number of GPIOs has gradually failed to meet the basic needs. Selecting a chip with more I / O is certainly one approach, but from a cost perspective, sometimes using bus expansion will have higher cost performance. Currently, traditional communication buses such as I2C (Inter-Integrated Circut, a serial communication bus) for expansion have limitations in speed, flexibility, layout, and wiring.

[0027] Currently, server I / O expansion includes various hardware and software bus solutions. In terms of hardware, 74HC595 shift register chips provide specific advantages for simple I / O expansion. Bridge chips provide another method for connecting external devices, enhancing the functionality of the server. In terms of buses, there are currently systems that use CPLD (Complex Programmable Logic Device) to implement I2C bus expansion. This system uses the BMC to communicate and configure the CPLD through the front-end I2C bus to establish a mapping between the front-end I2C and the back-end I2C bus to control the slave devices connected to the back-end I2C bus. In addition, there are system solutions that use SPI (Serial Peripheral Interface) and other buses to expand IO.

[0028] However, while the 74HC595 chip can be used for basic tasks, it lacks the programmability and complexity required for advanced I / O operations. Bridge chips, as fixed-function devices, lack the flexibility and adaptability of programmable logic devices such as CPLD. In addition, in terms of buses, I2C is generally slower than I3C, and requires additional IO interfaces to add in-band interrupt functionality. SPI consumes more power even when there is no data transmission due to the continuous clock signal. And SPI usually requires more pins than I3C, which increases the complexity of system design.

[0029] Overall, scalability, flexibility and speed are still major challenges in the field of I / O expansion, and the adaptability of hardware for server I / O expansion is poor. Therefore, the server in the related art has the problem of poor adaptability of input / output expansion.

[0030] To at least partially solve the above problems, in the present embodiment, a programmable logic device with an I3C bus is used to expand the input / output in the server. The expanded programmable logic device is linked with the expanded chip by using the I3C bus, and the expanded programmable logic device is programmed and configured with pins, finally realizing the functions of GPIO expansion and I3C expansion of the chip, and having the advantages of high transmission rate, in-band interruption, hot joining, etc. Each pin on the programmable logic device can be set as input or output, and the expanded chip can read or write these pins, achieving the effect of approximate physical connection.

[0031] Through the present embodiment, the peripheral signals and the redundant I3C bus can be monitored and controlled, and additional I / O can be added in the design, thereby freeing the GPIO of the expanded chip for other more important functions.

[0032] In one example embodiment, the first programmable logic device can include a plurality of GPIO interfaces. Here, the plurality of GPIO interfaces provides users with greater design flexibility, scalability, parallel processing capability, cost-effectiveness, integration, error tolerance, customization options, and ease of debugging and maintenance.

[0033] In one example embodiment, the first programmable logic device further includes a register and a GPIO controller, wherein,

[0034] The register is configured to temporarily store data received by the first slave I3C interface and transmitted by the expanded chip to the GPIO controller for reading by the GPIO controller, and to temporarily store data transmitted by the GPIO controller to the expanded chip for reading by the first slave I3C interface and then transmitted to the expanded chip through the front-end I3C bus;

[0035] The GPIO controller is configured to control the plurality of GPIO interfaces and temporarily store data to be transmitted to the expanded chip in the register.

[0036] The register in the programmable logic device is configured to store and process data, and the GPIO controller is responsible for communication with external devices. The register and the GPIO controller together provide flexibility and customizability for the design and implementation of digital systems.

[0037] In the embodiment, the extended chip communicates with the programmable logic device through the front-end I3C bus, and the internal registers of the programmable logic device are configured and read through the addressing operation of the programmable logic device. In the programmable logic device, the configuration logic module parses the configuration data of the front-end I3C, and stores and reads the data according to the preset frame format.

[0038] In one example embodiment, the server further includes at least one memory bank, and the plurality of GPIO interfaces are divided into at least one GPIO interface group, wherein the GPIO interfaces in the at least one GPIO interface group are used to connect the memory banks in the at least one memory bank.

[0039] For example, in the embodiment, the GPIO controller controls the IO pins of the programmable logic device itself, wherein the output signal is uniformly set to tri-state (can output high, low, and high impedance); and the input signal is connected to the register module after internal metastable state processing, so as to be read by the I3C module. Taking that the I3C can deliver 32 bytes of data at a time in the embodiment as an example, 32 IOs can be controlled at the same time. The byte width can be defined by the user. In the embodiment, 8 IOs can be taken as a group to control one DIMM (Dual In-line Memory Module, double in-line memory module, referred to as "memory bank", DIMM is a kind of computer hardware). The IO setting is as shown in FIG. 2.

[0040] Among them, the 8 IOs are: CPU_SA_PAR (CPU System Agent Parallel), CPU_SB_PAR (CPU System Bus Parallel), CPU_SA_RSP (CPU SA Response), CPU_SB_RSP (CPU System Bus Response), CPU_DIMM1_RESET (CPU related first memory reset), CPU_DIMM1_ALERT (CPU related first memory alert), PWRGD_DIMM1 (CPU related first memory power normal), reserved (reserved), in particular, the CPU_SA_PAR signal can be used to transmit the parallel communication signal between the CPU and the DIMM1; the CPU_SB_PAR signal can be used to transmit the parallel communication signal between the CPU and the front-end I3C bus; the CPU_SA_RSP signal can be used to transmit the response signal of the DIMM1 to the CPU; the CPU_SB_RSP signal can be used to transmit the response signal of the front-end I3C bus to the CPU; the CPU_DIMM1_RESET signal can be used to reset the first dual in-line memory module (DIMM1) of the CPU; the CPU_DIMM1_ALERT signal can be used to indicate that the first DIMM of the CPU has an error or needs attention; the PWRGD_DIMM1 signal can be used to indicate that the power supply state of the first DIMM of the CPU is good; and the reserved signal can be reserved for future expansion or specific application scenarios.

[0041] SCL represents Serial Clock Line, which is a clock line, and SDA represents Serial Data Line, which is a data line.

[0042] In an example embodiment, the server further comprises a back-end communication bus, and the first programmable logic device further comprises a second master I3C interface, wherein the back-end communication bus is one of: an I3C bus, an I2C bus, and the back-end communication bus is used to connect the second master I3C interface and a second slave I3C interface of a slave module of the first programmable logic device.

[0043] The back-end communication bus refers to a communication interface used to connect the programmable logic device chip and other external devices or modules after the field programmable gate array design is completed. The back-end communication bus is responsible for transmitting data between the programmable logic device and other devices, which can be input data, output data or control signals, etc. Through the back-end communication bus, the programmable logic device can send control instructions to control the connected external devices or modules, and realize the operation and control of these devices. The back-end communication bus allows the programmable logic device to be connected with other devices to form a larger system to realize the expansion and upgrade of functions and improve the performance and flexibility of the entire system.

[0044] Both I2C bus and I3C bus are serial communication protocols used to connect various electronic devices. I2C bus is widely used with lower transmission speed and simple implementation, while I3C bus provides higher transmission speed, full-duplex communication and other improved features, suitable for higher performance systems.

[0045] In one example embodiment, the server further includes at least one memory stick, the plurality of GPIO interfaces are divided into at least one GPIO interface group, the GPIO interface group in the at least one GPIO interface group is used to connect the memory stick in the at least one memory stick, and the slave module of the first programmable logic device includes at least one of the following: a second programmable logic device, a microcontroller, a serial presence detect hub on the memory stick in the at least one memory stick, a temperature sensor on the memory stick in the at least one memory stick, and a fan on the memory stick in the at least one memory stick.

[0046] For example, in the present embodiment, DDR5 (Double Data Rate Fifth-generation Synchronous Dynamic Random-Access Memory) introduces a sideband bus to access non-DRAM (Dynamic Random-Access Memory) modules. The sideband bus is based on MIPI I3C or I3C protocol. In addition to the sideband bus, as the number of components on DDR5 increases, there is also an SPD (Serial Presence Detect), i.e. a serial presence detect hub. Serial Presence Detect (SPD) is a standardized method of automatically accessing DDR3 / 4 / 5 memory module information. When an electronic system is powered on, it starts to automatically configure the system by identifying different hardware components. Through the extension of CPLD, the CPU can read the SPD on multiple DDR5 through a single I3C, and can control the pins of DDR5, etc.

[0047] Here, DIMM is a type of memory stick.

[0048] In one example embodiment, the first programmable logic device is a complex programmable logic device, the number of first programmable logic devices is multiple, and the multiple first programmable logic devices are connected in a daisy chain manner.

[0049] CPLD is a highly integrated programmable logic device, widely used in digital circuit design. CPLD can be regarded as a combination of multiple PLA (Programmable Logic Array) or PAL (Programmable Array Logic), with high integration and flexibility.

[0050] Daisy chain connection is a bus connection method, mainly used for the connection of multiple devices. In daisy chain connection, each device is connected to other devices through an input and an output terminal, forming a chain structure. The output terminal of the last device can be connected back to the input terminal of the first device, forming a closed loop structure.

[0051] Daisy chain connection can reduce the number of wiring required and reduce costs. Daisy chain connection can simplify circuit design, making it easier for designers to implement the connection of multiple devices. Due to the reduction in the number of wiring, daisy chain connection can reduce the failure rate of the circuit and improve system stability. Daisy chain connection makes it easy to add or remove devices, facilitating system expansion. Daisy chain connection can easily adjust the connection order as needed, improving the flexibility of the system.

[0052] For example, in this embodiment, CPLD is used to access the extended chip, and the topology of I3C extended IO is as shown in FIG. 3. Modify the extension CPLD code to communicate with chips such as BMC upward through I3C, obtain read commands and transfer related information through the fixed frame format. Read and control the pin information downward through GPIO, and communicate with other modules (such as temperature sensors sensor on DDR5 memory) through I3C.

[0053] In terms of the number of expansions, the expansion GPIO pins of each CPLD expansion chip are determined by the chip model and can be changed according to the needs and cost factors, and the CPLD can simulate I3C and I2C buses and other buses through built-in logic, can expand multiple downstream buses according to the needs, and can also cascade MCU (Microcontroller Unit) chips and other chips on the downstream buses. In addition, multiple CPLDs can be selected for expansion, and they can be connected in a daisy chain manner, and the number of links is only limited by potential signal attenuation / distortion when too many pins are cascaded. According to the MIPI (Mobile Industry Processor Interface) Association, the number of expansion CPLDs in the link can be no more than 11.

[0054] A data transmission method of a server is provided in the embodiment, and FIG. 4 is a schematic diagram of the data transmission method of the server according to the embodiment of the application. As shown in FIG. 4, the first programmable logic device is applied to the server, the server includes an expansion chip, a front-end I3C bus and the first programmable logic device, the expansion chip includes a first master I3C interface, the first programmable logic device includes a first slave I3C interface and a plurality of GPIO interfaces, and the front-end I3C bus is an I3C bus connecting the first master I3C interface and the first slave I3C interface. The front-end I3C bus is used for data transmission between the expansion chip and the first programmable logic device, and the method includes the following steps:

[0055] In step S402, the first control data transmitted by the expansion chip via the front-end I3C bus is received through the first slave I3C interface, wherein the first control data is used to control the first programmable logic device to perform a first specified operation on the GPIO interface, and the GPIO interface of the first programmable logic device is used to expand the GPIO of the expansion chip.

[0056] In step S404, in response to the received first control data, the first specified operation is performed on the GPIO interface corresponding to the first control data in the plurality of GPIO interfaces.

[0057] Through the above steps, the first control data transmitted by the expansion chip via the front-end I3C bus is received through the first slave I3C interface, wherein the first control data is used to control the first programmable logic device to perform a first specified operation on the GPIO interface, and the GPIO interface of the first programmable logic device is used to expand the GPIO of the expansion chip. In response to the received first control data, the first specified operation is performed on the GPIO interface corresponding to the first control data in the plurality of GPIO interfaces, which solves the problem of poor adaptability of input and output expansion of the server in the related art, and achieves the effect of improving the adaptability of input and output expansion of the server.

[0058] In the technical solution provided in step S402, the first programmable logic device receives first control data transmitted by the expansion chip via the front-end I3C bus through the first slave I3C interface, wherein the first control data is used to control the first programmable logic device to perform a first specified operation on the GPIO interface, and the GPIO interface of the first programmable logic device is used to expand the GPIO of the expansion chip.

[0059] In some embodiments, the expansion chip in the server can include but is not limited to: BMC (Baseboard Management Controller) chip: BMC chip is usually used for server management, providing remote monitoring and control functions, BMC chip may have a GPIO interface, allowing administrators to control and monitor server hardware; CPU chip, CPU model may have a GPIO interface for communication with external devices or to implement specific system functions; I / O expansion card: I / O expansion cards used in servers, such as SAS / SATA HBA (Host Bus Adapter) cards, network cards or PCIe expansion cards, may integrate GPIO interfaces; hardware monitoring module (HM): hardware monitoring module is usually used to monitor and control the environment within the server, such as temperature, voltage, fan speed, etc., and the hardware monitoring module may have a GPIO interface to communicate with other system components; power management chip: some power management chips may have a GPIO interface for monitoring power status, voltage and current parameters, and communicating with other parts of the server.

[0060] In some embodiments, I3C is a serial communication protocol used to connect and communicate with integrated circuits such as microcontrollers and sensors. I3C replaces the existing I2C (Inter-Integrated Circuit) protocol. I3C provides higher data transfer rates, lower power consumption and more flexible topology.

[0061] In an I3C system, there are two types of interfaces:

[0062] Master I3C Interface:

[0063] The master I3C interface is responsible for controlling the I3C bus, just like the master device in I2C. The master device can start, stop and control data transmission. Data can be sent to the slave device, and data can also be received from the slave device.

[0064] Slave I3C Interface:

[0065] The slave I3C interface is a passive device connected to the I3C bus. The slave device responds to the requests of the master device, sending or receiving data. The slave device can respond to the instructions of the master device. In an I3C system, there can be multiple slave devices, each with a unique address.

[0066] That is, in the present embodiment, the master I3C interface is responsible for controlling the bus and data transmission, and the slave I3C interface responds to the requests of the master device, sending or receiving data.

[0067] In some embodiments, the GPIO interface allows the device to exchange data with external devices. The GPIO interface can receive and send digital signals for controlling and monitoring various electronic devices and sensors. Expanding the GPIO of the extended chip provides a flexible, scalable, easy-to-program, low-cost and compatible way to connect and control various external devices, thereby enhancing the functionality and application range of electronic devices.

[0068] In some embodiments, the first control data refers to data received from the I3C interface for controlling or configuring the programmable logic device. These data can be transmitted through the front-end I3C bus. I3C is a serial communication protocol used for communication between integrated circuits.

[0069] The first control data can include but is not limited to the following types of information:

[0070] 1. Configuration Data: used to initialize and configure various parameters inside the programmable logic device, such as clock settings, pin function assignments, etc.

[0071] 2. Register Settings: used to set the values of internal registers of the programmable logic device, which may control the behavior, performance or interface with external devices of the device.

[0072] 3. Status Information: used to indicate the current status of the programmable logic device, such as power status, temperature status, error status, etc.

[0073] 4. Control Commands: used to perform specific operations, such as start, stop, reset, etc.

[0074] 5. Data Transfer: used to transfer data between the programmable logic device and other devices, such as reading or writing internal memory, processing external data, etc.

[0075] 6. Debugging and Testing: used for debugging and testing programmable logic devices to find and solve problems during development and maintenance.

[0076] Here, the first control data is data used to control and configure various parameters and behaviors of the programmable logic device. These data can be transmitted through the I3C interface and the front-end I3C bus to achieve effective control and management of the programmable logic device.

[0077] In the embodiment provided in the above step S404, the first programmable logic device, in response to the received first control data, performs a first specified operation on the GPIO interface corresponding to the first control data in the plurality of GPIO interfaces.

[0078] In some embodiments, the addresses of the plurality of GPIO interfaces can be unique, and the addresses of the plurality of GPIO interfaces are different from each other. The first specified operation on the GPIO interface corresponding to the first control data in the plurality of GPIO interfaces can be based on the implementation of the plurality of GPIO interfaces.

[0079] In some embodiments, the addresses of the plurality of GPIO interfaces can be static addresses or dynamic addresses, which are not limited in this embodiment.

[0080] Here, the dynamic address means that the address is variable during the programming of the programmable logic device, which can be specified by the user during programming. This type of address is usually used for communication with external devices (such as memories, other programmable logic devices, or other microprocessors), because the address space of these devices is usually configurable.

[0081] The user can customize the address according to the actual needs to adapt to different system designs; the dynamic address can be extended when needed to meet the demand for larger address space.

[0082] It should be noted that since the address is variable, it is necessary to ensure that there is no address conflict in the system.

[0083] The static address means that the address is fixed during the programming of the programmable logic device. This type of address is usually used for internal communication, such as communication between programmable logic device internal registers or on-chip peripherals and GPIO.

[0084] The static address does not need to be specified by the user during programming, which simplifies the programming process, and since the address is fixed, it is not easy to cause address conflict or error.

[0085] That is, dynamic addresses are suitable for communication with external devices, with higher flexibility and scalability, but higher programming complexity; static addresses are suitable for internal communication, simple and stable, but less flexible and scalable. In actual design, choose the appropriate address type according to the needs.

[0086] As an optional embodiment, the first control data is used to configure the interface mode of the first GPIO interface in the plurality of GPIO interfaces to be an input mode or an output mode.

[0087] S11, in response to the received first control data, performing a first specified operation on the GPIO interface corresponding to the first control data in the plurality of GPIO interfaces, including:

[0088] S12, in response to the received first control data, performing a configuration operation on the interface mode of the first GPIO interface.

[0089] Similar to the foregoing embodiments, the first control data can be configuration data for configuring the interface mode of the first GPIO interface in the plurality of GPIO interfaces to be an input mode or an output mode.

[0090] GPIO interfaces can be configured as input mode or output mode, both of which allow GPIO interfaces to implement different functions in different application scenarios.

[0091] When the GPIO interface is configured as an input mode, its role is to receive digital signals (0 or 1) from external devices. In this mode, the GPIO interface acts as a digital signal receiver, reading the state of the external device and converting it into data that the microcontroller can understand. Input mode is usually used to read sensor data, button status, etc.

[0092] When the GPIO interface is configured as an output mode, its role is to send digital signals (0 or 1) to external devices. In this mode, the GPIO interface acts as a digital signal transmitter, sending signals to external devices according to the instructions of the microcontroller. Output mode is usually used to control LED lights, relays, motors, etc.

[0093] Input mode and output mode are two basic working modes of GPIO interfaces. Input mode is used to receive external device signals, while output mode is used to send signals to external devices. By configuring the working mode of the GPIO interface, signal transmission and control functions in various electronic systems can be achieved.

[0094] As an optional embodiment, the first control data is used to read the interface state of the second GPIO interface in the plurality of GPIO interfaces.

[0095] In response to the received first control data, a first specified operation is performed on a GPIO interface corresponding to the first control data in the plurality of GPIO interfaces, including:

[0096] S21, in response to the received first control data, reading the interface state of the second GPIO interface to obtain interface state information of the second GPIO interface;

[0097] S22, transmitting the interface state information of the second GPIO interface to the extended chip via the front-end I3C bus through the first slave I3C interface.

[0098] Different programmable logic devices may have different GPIO configuration options and capabilities, whose states and functions depend on the technical manual of the selected device and user requirements.

[0099] In some embodiments, the GPIO interface state can include but is not limited to:

[0100] Input mode: GPIO as an input, can read the level state of external signal, such as high level (logic 1) or low level (logic 0).

[0101] Output mode: GPIO as output, can send level state (high or low) to external device.

[0102] Floating state: when GPIO is neither configured as output nor connected to valid input signal, it may be in floating state, which means its output level is uncertain.

[0103] Pull-up / pull-down state: in order to let GPIO have a determined level in floating state, internal or external pull-up or pull-down resistance can be configured to make it output high or low level when floating.

[0104] Tri-state logic: some GPIOs can be configured to tri-state logic state, which means they can output high, low or high impedance (equivalent to not connected).

[0105] Digital input / output: GPIO can be used for digital signal input and output, including simple switch signal, pulse signal, etc.

[0106] Analog input: some types of GPIO also have analog input function, which can read analog signal and convert it to digital signal.

[0107] Special function: according to specific application, GPIO can also be configured as special function interface, such as PWM (pulse width modulation) output, I2C interface, SPI, etc.

[0108] The first programmable logic device can read the interface state of the second GPIO interface in response to the received first control data to obtain interface state information of the second GPIO interface; and transmit the interface state information of the second GPIO interface to the extended chip via the front-end I3C bus through the first slave I3C interface.

[0109] As an optional embodiment, the first programmable logic device further comprises a register and a GPIO controller.

[0110] In response to the received first control data, performing a first specified operation on a GPIO interface corresponding to the first control data in the plurality of GPIO interfaces, comprising:

[0111] S31, in response to the received first control data, temporarily storing the first control data in the register;

[0112] S32, reading the first control data from the register through the GPIO controller, and performing a first specified operation on a GPIO interface indicated by the first control data in the plurality of GPIO interfaces.

[0113] The programmable logic device receives control data from the front-end I3C bus through the I3C interface, similar to the previous embodiment, the control data can include various instructions, settings or state information. The received data will be sent to the core logic part of the programmable logic device, here, the data will be parsed and recognized as a specific command or information; according to the received control data, the register in the programmable logic device will be updated, the register is usually used to store configuration parameters, state information, etc., so that the device can work normally according to the received instructions.

[0114] Correspondingly, once the register is updated, the GPIO controller will control the GPIO port according to the new register value. This may include setting the GPIO pin to input or output mode, configuring the level, rate and other attributes of the pin.

[0115] According to the updated register and GPIO settings, the programmable logic device will perform corresponding operations. This may include starting or stopping a specific function, adjusting the clock frequency, changing the data transmission rate, etc.

[0116] After performing the corresponding operation, the programmable logic device may feed back some state information or result data to the extended chip that sent the control data through the I3C interface, to ensure the reliability and synchronization of communication.

[0117] Through the embodiment, when the programmable logic device receives control data from the I3C interface, the register and the GPIO controller will work together to update the register, control the GPIO port, and perform corresponding operations according to the received data, so that the programmable logic device can flexibly respond to external instructions and realize complex and dynamic control functions.

[0118] As an optional embodiment, the above method further comprises:

[0119] S41, receiving an input signal of a third GPIO interface in the plurality of GPIO interfaces through the GPIO controller;

[0120] S42, performing metastable state processing on the input signal of the third GPIO interface through the GPIO controller, and temporarily storing the obtained input data in the register;

[0121] S43, reading the input data from the register through the first slave I3C interface, and transmitting the read input data to the extended chip via the front-end I3C bus.

[0122] Here, metastable state refers to a state in which a signal is neither 0 nor 1 for a certain uncertain time. This situation usually occurs when signal propagation delay or clock domain crossing occurs. The purpose of metastable state processing is to ensure stable transmission of signals in the system and prevent errors caused by metastable states.

[0123] Through the metastable state processing of the GPIO controller of the programmable logic device on the input signal of the GPIO interface, that is, in the programmable logic device, the GPIO controller will process the input signal to eliminate metastable states and ensure signal stability. The processed input data will be temporarily stored in the register for further processing or transmission when needed.

[0124] Through metastable state processing, it can be ensured that the signals of the GPIO interface remain stable during transmission, avoiding errors caused by metastable states. Temporarily storing the processed input data in the register can quickly access these data when needed, improving the response speed of the system.

[0125] Similar to the foregoing embodiments, after performing the corresponding operations based on the received control data, the programmable logic device can feed back some status information or result data to the extended chip that sent the control data through the slave I3C interface, to ensure the reliability and synchronization of communication, that is, reading the input data from the register through the first slave I3C interface, and transmitting the read input data to the extended chip via the front-end I3C bus.

[0126] Through this embodiment, by eliminating metastable states, the reliability of the system can be improved, and faults and errors caused by unstable signals can be reduced.

[0127] As an optional embodiment, the first control data transmitted by the extended chip via the front-end I3C bus is received through the first slave I3C interface, including:

[0128] S51, in the case that the front-end I3C bus is in the HDR (High-Speed Data Rate, high data rate) batch transmission mode, a set of preset mode frames transmitted by the extended chip via the front-end I3C bus is received through the first slave I3C interface, wherein the preset mode frame includes a start block and at least one data block, the start block of the preset mode frame carries a frame format command, and the first control data is carried in the data block of the set of preset mode frames.

[0129] In some embodiments, the I3C bus is a new type of serial communication protocol based on the I2C bus protocol, and the I3C bus has higher data transmission rate and more flexible configuration options. The I3C bus can work in two modes: standard mode and HDR mode.

[0130] When the I3C bus is in the HDR batch transmission mode, communication will be carried out at a higher data transmission rate. The HDR mode allows devices to communicate at a higher speed, which helps to improve system performance. In the HDR mode, devices can achieve faster data transmission rate at lower power consumption, thereby improving energy efficiency. The HDR mode provides more configuration options, making the system design more flexible and adaptable to various application requirements.

[0131] The frame format command is a special instruction that can be used to define the format and rules of the transmitted data on the I3C bus. The frame format command ensures that the data sender and receiver remain synchronized during data transmission to ensure that the data is not damaged or lost during transmission. The frame format command defines the structure of the data block, including the length, type and other information of the data, so that the receiver can correctly identify and parse the transmitted data.

[0132] In some embodiments, the frame format command can also contain some control information such as transmission rate, address, etc. The frame format command can also contain some information for error detection and processing such as checksum, sequence number, etc.

[0133] For example, in the present embodiment, the preset mode frame can be an HDR-BT mode frame, and the HDR-BT (High-Definition Range-Batch Transfer) mode frame is an efficient data transmission mode in the I3C bus standard. In this mode, a host device can exchange high-speed, batch data with a slave device through one or more preset mode frames (including a start block and a data block).

[0134] The HDR-BT mode allows the host device to transmit a large amount of data within one data frame, thereby reducing the overhead and delay in data transmission; the HDR-BT mode frame is suitable for programmable logic devices, which can be configured and reconfigured as needed to achieve different functions and performance; in the HDR-BT mode, a data frame includes a start block and at least one data block. The start block carries a frame format command, which defines the structure and transmission rules of the data frame; the data block contains the actual transmitted data; the frame format command in the start block helps to ensure synchronization between the data sender and receiver, as well as control during data transmission.

[0135] In some embodiments, the HDR-BT mode frame can contain information for error detection and processing, such as checksum, sequence number, etc., to improve the reliability of data transmission.

[0136] Through the present embodiment, high-speed and batch data exchange is achieved through the preset mode frame (start block and data block), while maintaining the reliability and flexibility of data transmission, and the frame format command carried in the start block helps to ensure synchronization, definition, control and reliability of data transmission.

[0137] As an optional embodiment, the preset mode frame further includes a check block, wherein the preset mode frame carries a check value in the check block.

[0138] In the process of receiving the first control data transmitted by the extended chip via the front-end I3C bus through the first slave I3C interface, the above method further includes:

[0139] S61, after receiving each preset mode frame, the received preset mode frame is taken as the current mode frame to perform the following processing operation:

[0140] Based on the current mode frame, a first check value corresponding to the current mode frame is generated, and the current mode frame is checked by comparing the first check value with a second check value carried in the check block of the current mode frame, to obtain a check result of the current mode frame;

[0141] The check result of the current mode frame is transmitted to the extended chip via the front-end I3C bus through the first slave I3C interface, so that the extended chip performs data transmission operation after the current mode frame based on the check result of the current mode frame.

[0142] Similar to the foregoing embodiments, the preset mode frame can contain information for error detection and processing, such as checksum, sequence number, etc., to improve the reliability of data transmission, and in the present embodiment, the preset mode frame further includes a check block, wherein the preset mode frame carries a check value in the check block.

[0143] The check block in the preset mode frame refers to a part for storing a check value. The check value is an error detection mechanism to ensure the integrity and correctness of data during transmission. The check value in the check block can help the receiver detect whether an error has occurred in the data during transmission. This can be achieved by comparing the check value of the received data frame with the check value calculated by the receiver itself.

[0144] The check value ensures that the data frame remains complete during transmission without losing any part. If the check fails, the receiver knows that the data may have been damaged. By using the check block, the reliability of data transmission can be improved. Even if interference or errors occur during data transmission, the check block can help ensure the correctness and integrity of the data.

[0145] The check value in the check block can be calculated by an algorithm such as CRC (Cyclic Redundancy Check), which generates a numerical value based on other information in the data frame, such as the content of the data block, which is stored in the check block. At the data receiver, the same algorithm is used to calculate the received data, and then compared with the check value in the check block to detect whether the data is correct.

[0146] Through the present embodiment, the accuracy, integrity and reliability of data transmission can be ensured by the check block and the check value carried therein.

[0147] In the case of obtaining the check result of the current mode frame, the programmable logic device can transmit the check result of the current mode frame to the extended chip via the front-end I3C bus through the I3C interface, so that the extended chip performs the data transmission operation after the current mode frame based on the check result of the current mode frame.

[0148] In some embodiments, the check result of the current mode frame can include check pass and check fail.

[0149] As an optional embodiment, after transmitting the check result of the current mode frame to the extended chip via the front-end I3C bus through the first slave I3C interface, the above method further includes:

[0150] S71, receiving the check result of the current mode frame transmitted by the first programmable logic device via the front-end I3C bus through the first master I3C interface;

[0151] S72, in the case that the check result of the current mode frame is check pass, releasing the first sub-control data cached in the cache area of the extended chip, wherein the first sub-control data is part of the first control data carried in the data block of the current mode frame;

[0152] S73, in the case that the second sub-control data exists in the cache area of the extended chip, generating a preset mode frame according to the second sub-control data, to obtain the first mode frame to be transmitted, wherein the second sub-control data is part of the data in the first control data that is not transmitted to the first programmable logic device, and part of the data in the second sub-control data is carried in the data block of the first mode frame;

[0153] S74, transmitting the first mode frame to the first programmable logic device via the front-end I3C bus through the first master I3C interface.

[0154] The extended chip can receive the check result of the current mode frame transmitted by the first programmable logic device via the front-end I3C bus through the first master I3C interface.

[0155] When the check result is a check pass, it means that the check value calculated by the receiver matches the check value carried in the preset mode frame by the sender. Therefore, it can be considered that no error occurs in the transmission process of the data, or the error that occurs can be detected by the check algorithm, and in this case, the receiver does not need to request the sender to retransmit the data, because the data is considered to have been correctly received, and the receiver can continue the subsequent data processing steps, such as data analysis, storage or further processing.

[0156] For example, in the case that the check result of the current mode frame is a check pass, the first sub-control data cached in the cache area of the extended chip is released, wherein the first sub-control data is part of the data in the first control data carried in the data block of the current mode frame; in the case that the second sub-control data exists in the cache area of the extended chip, a preset mode frame is generated according to the second sub-control data, to obtain the first mode frame to be transmitted, wherein the second sub-control data is part of the data in the first control data that is not transmitted to the first programmable logic device, and part of the data in the second sub-control data is carried in the data block of the first mode frame.

[0157] The extended chip can transmit the first mode frame to the first programmable logic device via the front-end 13C bus through the first master I3C interface. The first programmable logic device can receive the first mode frame through the first slave I3C interface.

[0158] For example, in the embodiment, the HDR-BT can let the receiver verify the transmission CRC value of each information frame with the CRC value calculated by the receiver. Based on this, the sender can determine whether the buffer area can be released and continue to send, or the data must be retransmitted (whether immediately or later).

[0159] Here, the buffer is a temporary storage area for data, used to temporarily store data during data transmission for error detection and processing. When the sender receives an acknowledgement signal from the receiver (i.e. the check passes), the buffer can determine that the data has been correctly received, at which point the sender can release the buffer for use in storing or transmitting other data.

[0160] Once the sender confirms that the data has been correctly received (i.e. the check passes), the buffer can continue to send the next data frame or perform other data transmission operations. This approach can improve the efficiency of data transmission, as the sender does not have to wait for each data frame to be confirmed before proceeding.

[0161] As an optional embodiment, after receiving the check result of the current mode frame transmitted by the first programmable logic device via the front-end I3C bus through the first master I3C interface, the above method further comprises:

[0162] S81, in the case where the check result of the current mode frame is a check failure, generating a preset mode frame according to the first sub-control data to obtain a second mode frame to be transmitted;

[0163] S82, transmitting the second mode frame to the first programmable logic device via the front-end I3C bus through the first master I3C interface.

[0164] For example, in this embodiment, similar to the previous embodiment, if the check fails, the sender may need to retain the buffer in order to resend the data frame when the receiver requests retransmission.

[0165] As an optional embodiment, during the process of receiving the first control data transmitted by the extended chip via the front-end I3C bus through the first slave I3C interface, the above method further comprises:

[0166] S91, after receiving each preset mode frame, in the case where the first indication information is received after the currently received preset mode frame, waiting to receive the next preset mode frame of the currently received preset mode frame, wherein the first indication information is used to indicate the restart of the HDR batch transmission mode;

[0167] S92, in the case where the second indication information is received after the currently received preset mode frame, terminating the data transmission with the extended chip, and controlling the first programmable logic device to enter a low-power state, wherein the second indication information is used to indicate the exit of the HDR batch transmission mode.

[0168] For example, in the present embodiment, FIG. 5 shows a typical HDR-BT (HDR Bulk Transport Mode) mode frame, containing two HDR-BT transmissions and related data. The technical terms involved in FIG. 5 are explained as follows:

[0169] 1. SDR, Standard Data Rate: Standard Data Rate.

[0170] 2. HDR, High Data Rate: High Data Rate.

[0171] 3. S or Sr, Start or Repeated Start: Start or Repeated Start.

[0172] 4. I3C Reserved byte (7'h7E) (R / W = 0), I3C reserved byte (7'h7E) (read / write = 0): I3C reserved byte (7'h7E) (read / write = 0).

[0173] 5. NACK, Not Acknowledge (NACK), denial, unconfirmed, or rejected confirmation. NACK is a signal used in communication protocols to indicate that the receiving party has not received or correctly received the sender's data. During a data transmission process, the sender sends data and waits for the receiving party to send an acknowledgment (ACK) signal. If the receiving party cannot correctly receive the data due to data errors, loss, or other reasons, it will send a NACK signal to the sender to inform the sender that the data needs to be re-sent.

[0174] 6. Enter HDR-BT CCC (Command Control Character) (ENTHDR3), Enter HDR-BT Command Control Character (ENTHDR3).

[0175] 7. HDR-BT Header (with Command), HDR-BT header (with command).

[0176] 8. HDR-BT Data (1 or more Blocks), HDR-BT data.

[0177] 9. HDR-BT CRC Block, HDR-BT CRC block.

[0178] 10. HDR Restart Pattern, HDR restart pattern.

[0179] 11. HDR Exit Pattern.

[0180] 12. From Controller to Target.

[0181] 13. Framing (START or STOP): Frame division (start or stop).

[0182] 14. From Controller to Master.

[0183] 15. Current I3C Mode (SDR or HDR): Current I3C mode (standard data rate or high data rate).

[0184] 16. Transition Bit (Parity Bit for CCC), the transition bit (parity check bit for general command codes).

[0185] 17. Bus Free (after STOP): The bus is free (after it has stopped).

[0186] 18. Common Command Codes.

[0187] 19. ACK: Acknowledge, confirmation.

[0188] Acknowledge (SDA Low): When SDA (data line) is low, it indicates that the receiver has successfully received the data and sent an acknowledgment signal.

[0189] 20.S: START Condition.

[0190] START Condition(S): When SCL (clock line) is high, SDA changes from high to low, indicating the start of communication.

[0191] 21.Sr: Repeated START Condition.

[0192] Repeated START Condition (Sr): When SCL is high, SDA changes from low to high and then back to low, indicating that a new round of communication begins without sending a stop condition.

[0193] 22. P: STOP Condition, stop condition.

[0194] STOP Condition (P): When SCL is high, SDA goes from low to high, indicating the end of communication.

[0195] 23. T: Transition Bit, transition bit, parity bit (Parity bit) for CCC.

[0196] Transition Bit (T): a signal used to indicate ACK (acknowledgment) or NACK (negation), transition bit alternative to ACK / NACK.

[0197] First, the CPU sends the address 7'h7E / W followed by the CCC command to start the HDR-BT mode. In a HDR-BT transmission. First, there is a HDR-BT start block (containing frame format commands), then one or more HDR-BT data blocks, and finally a HDR-BT CRC block. Then a HDR restart pattern is passed to continue the HDR mode, and another HDR-BT transmission with a similar flow follows. Finally, the bus can end the HDR-BT mode by HDR exit pattern and I3C stop.

[0198] The HDR restart pattern is a special transmission mode that allows dynamic changes to transmission parameters such as data rate, data width, etc. during HDR transmission without the need to restart a new transmission transaction. This mode can be implemented by sending a specific HDR restart pattern code, which will be recognized and responded to by the receiver. The function of the HDR restart pattern is to improve the flexibility of data transmission, allowing transmission parameters to be adjusted without interrupting transmission, thereby optimizing transmission efficiency.

[0199] The HDR exit pattern is a control mode used to end the HDR-BT transmission. When the data transmission is complete or needs to be terminated, the sender can notify the receiver by sending a specific HDR exit pattern code. The sending of the HDR exit pattern code will cause the I3C bus to return to the standard mode or stop transmission, thereby allowing other devices or transmission transactions to proceed.

[0200] Through the HDR restart mode and the HDR exit mode, the data transmission efficiency and flexibility in the HDR-BT mode are improved, allowing more dynamic and flexible data transmission management. By using the HDR restart mode and the HDR exit mode, the device can adjust the transmission parameters without interrupting the transmission, or quickly end the transmission when needed, thereby improving the overall system performance and response capability.

[0201] As an optional embodiment, before receiving the first control data transmitted by the extended chip via the front-end I3C bus through the first slave I3C interface, the above method further comprises:

[0202] S101, receiving the I3C broadcast address and the general command code command transmitted by the extended chip via the front-end I3C bus through the first slave I3C interface;

[0203] S102, in response to the received I3C broadcast address and general command code command, determining to start the HDR batch transmission mode of the front-end I3C bus.

[0204] In the case where the extended chip and the programmable logic device are connected through the I3C bus, starting the HDR batch transmission mode of the I3C bus can involve the following steps:

[0205] 1. Initialize the I3C bus: First, make sure the I3C bus is properly initialized, including configuring the I3C controller at the extended chip end and initializing the I3C interface at the programmable logic device end.

[0206] 2. Configure the programmable logic device: At the programmable logic device end, the corresponding registers need to be configured to support the HDR mode. This may include setting the data transmission rate, data width, address mode, etc.

[0207] 3. Send HDR transmission command: The extended chip needs to send a specific HDR transmission command to the programmable logic device to start the HDR batch transmission mode. This is usually achieved by sending a series of I3C instructions, including commands to set the HDR mode and commands to transmit data.

[0208] 4. Use I3C broadcast address: In some cases, if simultaneous communication or initialization with multiple devices is required, the I3C broadcast address may be used. The broadcast address allows a command to be sent to all devices connected to the bus.

[0209] 5. General command code: The general command code is used to perform specific operations such as reading or writing data. When starting the HDR mode, a specific command code may be needed to set the transmission parameters or initialize the transmission.

[0210] 6. Exchange protocol information: Some protocol information may need to be exchanged between the extended chip and the programmable logic device to ensure that both parties can understand and accept the transmission parameters of the HDR mode.

[0211] 7. Start transmission: Once all parameters are set, the extended chip can send data to the programmable logic device to start the HDR bulk transmission mode.

[0212] 8. Error handling: During transmission, error detection and handling mechanisms such as CRC checking may need to be implemented to ensure the reliability of data transmission.

[0213] 9. End transmission: After transmission is complete, a specific command or mode code needs to be sent to end the HDR mode and return to the normal I3C mode or perform other operations.

[0214] For example, in this embodiment, the extended chip can send a general command code (CCC) over the I3C bus to configure the I3C bus HDR mode. The configurable modes and corresponding commands are shown in Table 1. I3CBasic only contains HDR mode 0 (HDR-ddr) and HDR mode 3 (HDR-BT). This example is based on HDR mode 3 (HDR-BT), i.e. the extended chip sends 0x23 (ENTHDR3) command for configuration, and the programmable logic device responds.

[0215] Table 1

[0216] Using general command codes and broadcast addresses to enable HDR bulk transmission mode can simplify the programming process, as there is no need to remember separate command codes for each device. This can reduce the likelihood of programming errors and make it easier for developers to implement and maintain the system; by using broadcast addresses, commands can be sent to multiple devices without having to individually address each device separately; using HDR bulk transmission mode can improve system efficiency, as it allows multiple commands to be sent in a single transmission, which can save time and resources, especially in cases where multiple commands need to be sent to configure or control multiple devices. Using general command codes and broadcast addresses can improve system reliability, as the number of commands that need to be remembered and programmed is reduced, making the system easier to use and reducing the risk of programming errors.

[0217] By using I3C broadcast addresses and general command codes to enable HDR bulk transmission mode, this embodiment can improve system performance by simplifying the programming process, improving flexibility, efficiency, reliability and compatibility.

[0218] As an optional embodiment, the front-end I3C bus includes two serial data lines and one serial clock line;

[0219] In the case that the front-end I3C bus is in the HDR batch transfer mode, a set of preset mode frames transmitted by the extended chip via the front-end I3C bus is received by the first slave I3C interface, including:

[0220] S111, after receiving the I3C broadcast address and the general command code command, in the case that the clock signal in the serial clock line is detected to be stable, the data received through the two serial data lines is parsed according to a preset packaging manner to obtain a set of preset mode frames, wherein the preset packaging manner is a manner of packaging data using the two serial data lines.

[0221] In I3C communication, the serial clock line is used for synchronizing data transmission. Before data transmission starts, it is necessary to detect that the clock signal on the serial clock line SCL line is stable to ensure that the data can be correctly transmitted.

[0222] In I3C communication, the serial data line (SDA) is used for transmitting data.

[0223] The preset packaging manner can refer to a specific data organization and parsing rule for ensuring that the received data can be correctly interpreted in the expected manner; the preset mode frame can refer to the data frame obtained after parsing according to a specific packaging manner. In the I3C protocol, a frame can contain address, command and data information.

[0224] After receiving the broadcast address and the general command code through the I3C communication protocol, the system will parse the data received through the serial data line according to the pre-set rule (packaging manner) in the case that the clock signal on the serial clock line is detected to be stable, based on which the system can correctly understand and process the received data, thereby obtaining a set of frames organized according to the preset mode (i.e., preset mode frames), which can contain device address, command information and related data, for performing specific operations or responses.

[0225] For example, in the present embodiment, the data line is packaged using the double SDA line. The packaging format is shown in Table 2.

[0226] Table 2

[0227] Table 3 (Table 3) is data byte bit packaging: double channel.

[0228] Table 3

[0229] As an optional embodiment, the server further comprises a back-end communication bus, and the first programmable logic device further comprises a second master I3C interface, wherein the back-end communication bus is one of: an I3C bus, an I2C bus, and the back-end communication bus is configured to connect the second master I3C interface and a second slave I3C interface of a slave module of the first programmable logic device;

[0230] The method further comprises:

[0231] S602, receiving, by the first slave I3C interface, second control data transmitted by the extended chip via the front-end I3C bus, wherein the second control data is used to control a second specified operation on a specified slave device of the first programmable logic device;

[0232] S604, in response to the received second control data, transmitting, by the second master I3C interface, the second control data to the specified slave device via the back-end communication bus, so that the second specified operation is performed by the specified slave device.

[0233] In combination with FIG. 6, considering that the number of GPIO interfaces is limited and the specified slave device can not need high-speed communication, the second master I3C interface of the programmable logic device can be connected to the second slave I3C interface of the slave module of the first programmable logic device through the back-end communication bus.

[0234] The master I3C interface on the programmable logic device refers to the interface that controls the I3C bus and is responsible for managing data transmission and communication. The programmable logic device sends control commands and data to other devices (referred to as slave devices) connected to the back-end communication bus through its master I3C interface.

[0235] On the back-end communication bus (for example, the I3C bus), each device has a unique address. The master I3C interface of the programmable logic device can specify a specific device address to ensure that data and commands are only sent to that specific slave device.

[0236] After the slave device receives the data and commands sent by the programmable logic device, it will perform specific operations according to these information. These operations may include data reading, data writing, device configuration, status reporting, etc.

[0237] The back-end communication bus allows multiple devices to be connected to the same bus, making the system design more flexible and compact. If a GPIO interface is used, each slave device (e.g., temperature sensor) requires a separate GPIO line, which can consume a large number of GPIO resources when the number of devices is large; if more slave devices need to be added, only ensure that the maximum number of devices of the back-end communication bus is not exceeded, and although the speed of the back-end communication bus may not be as fast as that of some GPIO interfaces, for applications such as temperature sensors that do not require high-speed communication, the speed of the back-end communication bus is already sufficient. In addition, the power consumption of the back-end communication bus is relatively low, which helps to reduce the overall power consumption of the system.

[0238] Through this embodiment, the master I3C interface on the programmable logic device provides an efficient and flexible way to control and manage one or more peripheral devices connected to the back-end communication bus.

[0239] As an optional embodiment, the server further includes at least one memory bank, and the plurality of GPIO interfaces are divided into at least one GPIO interface group, and the GPIO interfaces in the at least one GPIO interface group are used to connect the memory banks in the at least one memory bank;

[0240] The slave module of the first programmable logic device includes at least one of the following: a second programmable logic device, a microcontroller, a serial presence detect hub on a memory bank in the at least one memory bank, a temperature sensor on a memory bank in the at least one memory bank, and a fan on a memory bank in the at least one memory bank.

[0241] A memory bank, also known as a RAM bank (Random Access Memory Module), is a hardware component used by computers and other digital devices for temporary storage of data. There are various types of memory banks, including but not limited to SDRAM (Synchronous DRAM), DDR (Double Data Rate Synchronous Dynamic Random Access Memory), and various versions thereof (such as DDR2, DDR3, DDR4, DDR5, etc.).

[0242] SPD is a technology used for storage devices (such as memory banks) that allows the motherboard to identify the specifications of the storage device, such as size, type, and speed, etc. A serial presence detect hub is a hardware device that connects multiple memory banks and centrally manages their SPD data, allowing the motherboard to access the status information of all memories through one interface. The serial presence detect hub can simplify memory management and improve the scalability and compatibility of the system.

[0243] The temperature sensor on the memory module is used to monitor the working temperature of the memory module in real time. In high-performance memory modules, due to high working frequency and high power consumption, the memory temperature may rise, affecting stability and lifespan. By monitoring the temperature, the system can take measures such as adjusting the fan speed for cooling or issuing a warning when the temperature is too high, thereby protecting the memory module and improving the stability of the system.

[0244] The fan on the memory module is used for active cooling, helping to reduce the temperature of the memory module. High-performance memory generates a lot of heat during operation, which may cause system instability or damage hardware if the heat dissipation is poor. The fan on the memory module can directly cool the memory module, improving the cooling efficiency and ensuring that the memory works in the best state.

[0245] Through this embodiment, the stability and reliability of the memory module during high-performance or high-load operation are ensured through the slave module of the programmable logic device. Through real-time monitoring and active cooling, it can help maintain the memory module within a safe working temperature range, protect the system from damage caused by high temperature, and improve overall performance.

[0246] As an optional embodiment, before receiving the first control data transmitted by the extended chip via the front-end I3C bus through the first slave I3C interface, the above method further comprises:

[0247] S121, in the case that the front-end I3C bus is in SDR mode, initializing the front-end I3C bus through the extended chip, and performing a discovery process to detect devices connected to the front-end I3C bus;

[0248] S122, obtaining the static address of the first programmable logic device transmitted by the first programmable logic device via the front-end I3C bus through the extended chip, wherein the static address of the first programmable logic device is pre-set in the first programmable logic device.

[0249] For example, in this embodiment, the extended chip initializes the I3C bus and performs a discovery process to detect all devices on the I3C bus. The I3C bus has a new dynamic address allocation function, but in this embodiment, the address of the extended programmable logic device is fixed and uses a static address. In addition to considering stability and predictability, devices with static addresses can run in I3C high-speed HDR mode and are backward compatible with I2C devices, increasing stability.

[0250] It should be noted that at this time the I3C bus is initialized and configured with an address in SDR mode.

[0251] SDR mode can refer to Single Data Rate mode, which is a data transmission rate configuration. In SDR mode, the data transmission rate is a fixed frequency, which is usually used for low-speed or regular data transmission needs.

[0252] Each device connected to the I3C bus needs to have a unique address so that the sender can identify and send data to a specific receiver; during initialization, the bus configures the communication parameters of the device, such as clock rate, data transmission rate, etc., to ensure that the device can exchange data at the expected rate and manner; the device may need to be configured after connecting to the bus, such as setting the working mode, input / output mode, etc. The configuration address allows these settings to be made through the I3C bus; through the configuration address, the bus controller can manage the devices on the network, including detecting new devices, configuring device parameters, maintaining a list of devices, etc.; the configuration address also supports broadcast and multicast communication, allowing the same command or data to be sent to multiple devices.

[0253] Through this embodiment, the initialization and configuration address in the SDR mode of the I3C bus can ensure that the device can correctly communicate on the bus and improve the efficiency and security of communication.

[0254] As an optional example embodiment, in this application, the extended chip is taken as the CPU, and the first programmable logic device is taken as the CPLD as an example to explain the data transmission method of the server in this application embodiment.

[0255] The application provides a system and method for extending the input / output of the CPLD with the I3C bus in the server. By using the I3C bus to link the extended CPLD with the extended chip, and performing relevant programming and pin configuration on the extended CPLD, the functions of GPIO extension and I3C extension of the chip are finally realized, and the extended CPLD has the advantages of high transmission rate, in-band interruption, hot joining, etc., and each pin on the CPLD can be set as input or output, and the extended chip can read or write these pins, achieving the effect of approximate physical connection.

[0256] This embodiment uses the CPLD to access the extended chip, and the topology of the I3C extended IO is as shown in FIG. 3. The extended CPLD code is modified, and communication is performed with the chip such as the BMC upwardly through the I3C, the read command is obtained, and the relevant information is transmitted through the fixed frame format. The pin information is read and controlled downwardly through the GPIO, and communication is performed with other modules (such as temperature sensors on the DDR5 memory) downwardly through the I3C.

[0257] In terms of the number of extensions, the extension GPIO pins of each CPLD extension chip are determined by the chip model and can be changed according to the needs and cost factors, and the CPLD can simulate I3C and I2C buses through built-in logic, can extend multiple downstream buses according to needs, and can also cascade chips such as MCUs on the downstream bus. In addition, multiple CPLDs can be selected for expansion, and they can be connected in a daisy chain manner, and the number of links is only limited by potential signal attenuation / distortion when too many pins are cascaded. According to the suggestion of the MIPI Association, the number of linked extension CPLDs can be no more than 11.

[0258] The application is further illustrated below through optional embodiments, and the GPIO of the CPU is expanded using a CPLD to link more memories on one CPU. The topology diagram is shown in FIG. 7.

[0259] Optionally, DDR5 introduces a sideband bus to access non-DRAM modules. The sideband bus is based on the MIPI I3C or I3C protocol. In addition to the sideband bus, as the number of components on DDR5 increases, there is also an SPD, a serial presence detection hub. The SPD is a standardized method of automatically accessing DDR3 / 4 / 5 memory module information. When the electronic system is powered on, it starts to automatically configure the system by identifying different hardware components. Through the expansion of the CPLD, the CPU can read the SPD on multiple DDR5 through a single I3C, and can control the pins of the DDR5, etc.

[0260] First, the CPU communicates with the CPLD through the front-end I3C bus, and configures and reads the internal registers of the CPLD through the addressing action of the CPLD. In the CPLD, the configuration logic module parses the configuration data of the front-end I3C, and stores and reads the data according to the pre-agreed frame format.

[0261] The optional steps of I3C interaction are as follows:

[0262] Step 1, initialization and device discovery: the CPU initializes the I3C bus and performs the discovery process to detect all devices on the I3C bus.

[0263] Step 2, address allocation: the I3C bus has a new dynamic address allocation function, but in this embodiment, the address of the extended CPLD is fixed, and a static address is used. In addition to considering stability and predictability, devices with static addresses can run in I3C high-speed HDR mode, and can be backward compatible with I2C devices, increasing stability. It should be noted that the I3C bus is initialized and the address is configured in SDR mode at this time.

[0264] Step 3, Configure High Speed Transfer Mode: The CPU sends a Generic Command Code (CCC) over the I3C bus to configure the I3C bus HDR mode. The configurable modes and corresponding commands are shown in Table 1. I3C Basic only contains HDR mode 0 (HDR-ddr) and HDR mode 3 (HDR-BT). This example is based on HDR mode 3 (HDR-BT), i.e. the CPU sends 0x23 (ENTHDR3) command for configuration, and the CPLD responds.

[0265] After the ENTHDR3 CCC, the SDA is driven after the t-bit is complete (i.e. on or after the falling edge of the SCL pulse of C9) to start the first structured protocol element in the HDR mode frame. From this point, the controller follows the general timing rules to start transmission in the HDR mode. It is noted that the I3C bus transitions from SDR mode to HDR mode after the falling edge of the SCL pulse of C9. Figure 8 shows the timing diagram of entering the general HDR mode after the ENTHDR3 CCC, where Controller drives Push-Pull refers to the controller driving the signal through push-pull output; T-Bit falling edge <= end of SCL pulse refers to the falling edge of the T-bit should be before the end of the clock signal SCL pulse; LOW SCL refers to the SCL signal is in low state; First BT edge refers to the edge of the first BT signal, which can be either rising or falling edge; Second BT edge refers to the edge of the second BT signal, which can be either rising or falling edge; HDR-BT Header Block (per Lane configuration) refers to the data header block related to the HDR-BT format, and the configuration of each lane can be different.

[0266] Step 5, Data Transfer: The CPU sends and receives data packets over the I3C bus to communicate with the CPLD. This includes reading or writing registers of the CPLD. In this embodiment, the I3C bus is in HDR Batch Transfer mode (HDR-BT), as shown in Figure 8, at which time the bus will utilize both edges of the clock to transfer data, i.e. 2 SDA lanes change when the SCL clock is stable, and are read on the next clock rising or falling edge. Since the CPLD only drives SDA and not SCL, SDA only changes after receiving / detecting the SCL change. With dual lanes, this transfer rate will be 48.5Mhz, which is close to the current server CPLD clock frequency.

[0267] Figure 5 shows a typical HDR-BT mode frame, including two HDR-BT transmissions and related data. First, the CPU sends an address 7'h7E / W followed by a CCC command to start the HDR-BT mode. In one HDR-BT transmission, first is an HDR-BT start block (including frame format command), then one or more HDR-BT data blocks, and finally an HDR-BT CRC block. Then an HDR restart mode is passed to continue the HDR mode, followed by another HDR-BT transmission with similar flow. Finally, the bus can end the HDR-BT mode with an HDR exit mode and an I3C stop.

[0268] Another advantage of using HDR-BT is that multiple SDA lines can be transmitted simultaneously. In this embodiment, two SDA lines are used to pack the data line. The packing format is shown in Table 2.

[0269] It should be noted that HDR-BT also allows the receiver to verify with the sender whether the transmission CRC value of each information frame is consistent with the CRC value calculated from the received data. In this way, the sender can determine whether to release the buffer and continue to send, or whether it must resend the data (whether immediately or later).

[0270] Step 6, control and status monitoring: the CPU can send control commands to the CPLD through the I3C bus and monitor its status. The CPLD can also use an in-band interrupt (IBI) signal to send an interrupt signal to the CPU. After receiving the transmission signal from the CPU, the CPLD transmits commands to the downstream device and controls the GPIO configuration and acceptance. In addition, the received information is transmitted back to the CPU. The internal functional topology of the CPLD is shown in Figure 2.

[0271] The expanded CPLD in this embodiment mainly includes four parts: I3C interface (slave), I3C interface (master), register, and GPIO controller. Among them:

[0272] The I3C interface (slave), i.e., the first slave I3C interface, is a bridge for communication between the CPLD and the uplink expanded chip, and is configured to perform functions such as data exchange, protocol information analysis, and reading and storing register information. The number is generally only one.

[0273] The I3C interface (master), i.e., the second master I3C interface, is used to link the CPLD and the downstream I3C device, and is configured to read and control the information of the downstream chip by the CPLD, and can have multiple.

[0274] The register is configured to temporarily store the data of the other three modules for easy reading and writing.

[0275] The GPIO controller controls the IO pins of the CPLD, and the output signal is set to tri-state (output high, low, or high impedance). The input signal is connected to the register module after internal metastable state processing, and is read by the I3C module. Since the I3C in this embodiment can transmit 32 bytes of data at a time, 32 IOs can be controlled at the same time. The byte width can be defined by the user. In this embodiment, 8 IOs are a group, and one DIMM is controlled. The IO setting is shown in FIG. 5.

[0276] Step 7, termination: after the communication is completed, the CPU can terminate the I3C session and put the CPLD into a low-power state as needed.

[0277] Through this embodiment, the chip GPIO and bus are expanded simultaneously through the CPLD and the I3C bus HDR batch transmission mode (HDR-BT), and only a single-channel I3C is required. It is fast, efficient, stable, and can be expanded to multiple CPLDs and bus numbers, and has very strong expandability.

[0278] Through this embodiment, the current bus expansion rate is improved. The HDR-BT format used for transmission uses a wide data block, which can be directly mapped to internal SRAM (Static RAM, static random access memory) (such as 32 bits, 64 bits, etc.), a wide internal bus (such as AXI (Advanced eXtensible Interface, Advanced eXtensible Interface), OCP (Open Core Protocol, Open Core Protocol), etc.), and encryption / decryption modes with inherent block sizes (such as 64 bits, 128 bits). The current motherboard CPLD frequency is 50Mhz, in addition to lower power consumption than I2C, increased CRC16 and other check functions, and very high expandability, which is very suitable for multiple DIMM application scenarios.

[0279] In addition to the HDR-BT mode, I3C also has other two-wire modes. The HDR-BT mode can also reduce one SDA line, but the rate will be halved. In addition, the bus data format in specific situations can be explored, such as fixed addresses in one-to-one, specific frames, etc. The control of multiple upstream chips on the expansion chip can also be explored.

[0280] The embodiment of the application also provides a computer readable storage medium, which stores a computer program, and the computer readable storage medium can be a non-volatile readable storage medium, wherein the computer program is set to execute the steps in any of the method embodiments described above when running.

[0281] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a ROM, a RAM, a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0282] Embodiments of the present application also provide an electronic device, which comprises a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the method embodiments described above.

[0283] In an example embodiment, the electronic device described above can further comprise a transmission device and an input and output device, wherein the transmission device is connected to the processor, and the input and output device is connected to the processor.

[0284] Optional examples in the embodiments can refer to the examples described in the above embodiments and exemplary implementation manners, and will not be described here again.

[0285] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, which can be realized by program codes executable by computing devices, so that they can be stored in storage devices and executed by computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps among them can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

[0286] The above is only optional embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A server, comprising: an extended chip, a front-end I3C bus and a first programmable logic device, the extended chip comprising a first master I3C interface, the first programmable logic device comprising a first slave I3C interface and a plurality of GPIO interfaces, the front-end I3C bus being an I3C bus connecting the first master I3C interface and the first slave I3C interface, the front-end I3C bus being configured to perform data transmission between the extended chip and the first programmable logic device, wherein the extended chip is configured to exchange data with the first programmable logic device via the front-end I3C bus to implement GPIO extension of the extended chip via the plurality of GPIO interfaces.

2. The server of claim 1, wherein the first programmable logic device further comprises a register and a GPIO controller, wherein the register is configured to temporarily store data received by the first slave I3C interface and transmitted by the extended chip to the GPIO controller for reading by the GPIO controller, and temporarily store data transmitted by the GPIO controller to the extended chip for reading by the first slave I3C interface and transmission to the extended chip via the front-end I3C bus; the GPIO controller is configured to control the plurality of GPIO interfaces and temporarily store data to be transmitted to the extended chip in the register.

3. The server of claim 2, wherein the server further comprises at least one memory bank, and the plurality of GPIO interfaces are divided into at least one GPIO interface group, wherein a GPIO interface group in the at least one GPIO interface group is configured to connect a memory bank in the at least one memory bank.

4. The server of claim 2, wherein the server further comprises a back-end communication bus, and the first programmable logic device further comprises a second master I3C interface, wherein the back-end communication bus is one of an I3C bus and an I2C bus, and the back-end communication bus is configured to connect the second master I3C interface and a second slave I3C interface of a slave module of the first programmable logic device.

5. The server of claim 4, wherein the server further comprises at least one memory bank, the plurality of GPIO interfaces are divided into at least one GPIO interface group, a GPIO interface group in the at least one GPIO interface group is configured to connect a memory bank in the at least one memory bank, and the slave module of the first programmable logic device comprises at least one of a second programmable logic device, a microcontroller, a serial presence detect hub on a memory bank in the at least one memory bank, a temperature sensor on a memory bank in the at least one memory bank, and a fan on a memory bank in the at least one memory bank.

6. The server of any one of claims 1 to 5, wherein ​ The first programmable logic device is a complex programmable logic device, and the number of the first programmable logic devices is multiple, and the multiple first programmable logic devices are connected in a daisy chain manner.

7. The server of claim 1, wherein, The first programmable logic device is configured to send an interrupt signal to the extended chip using an in-band interrupt signal.

8. A data transmission method of a server, comprising: The server comprises an extended chip, a front-end I3C bus and a first programmable logic device, the extended chip comprises a first master I3C interface, the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces, and the front-end I3C bus is an I3C bus connecting the first master I3C interface and the first slave I3C interface, and is used for data transmission between the extended chip and the first programmable logic device; The method comprises: receiving, through the first slave I3C interface, first control data transmitted by the extended chip via the front-end I3C bus, wherein the first control data is used to control a first specified operation performed on a GPIO interface of the first programmable logic device, and the GPIO interface of the first programmable logic device is used to extend a GPIO of the extended chip; in response to the received first control data, performing the first specified operation on the GPIO interface of the plurality of GPIO interfaces corresponding to the first control data.

9. The method of claim 8, wherein, the first control data is used to configure an interface mode of a first GPIO interface of the plurality of GPIO interfaces as an input mode or an output mode; in response to the received first control data, performing the first specified operation on the GPIO interface of the plurality of GPIO interfaces corresponding to the first control data, comprises: in response to the received first control data, performing a configuration operation on the interface mode of the first GPIO interface.

10. The method of claim 8, wherein, the first control data is used to read an interface state of a second GPIO interface of the plurality of GPIO interfaces; in response to the received first control data, performing the first specified operation on the GPIO interface of the plurality of GPIO interfaces corresponding to the first control data, comprises: in response to the received first control data, reading the interface state of the second GPIO interface to obtain interface state information of the second GPIO interface; transmitting, through the first slave I3C interface, the interface state information of the second GPIO interface to the extended chip via the front-end I3C bus.

11. The method of claim 8, wherein, the first programmable logic device further comprises a register and a GPIO controller. The method further comprises: storing the first control data into the register in response to the received first control data; reading the first control data from the register by the GPIO controller, and performing the first specified operation on the GPIO interface indicated by the first control data among the plurality of GPIO interfaces.

12. The method of claim 9, wherein the method further comprises: receiving, by the GPIO controller, an input signal of a third GPIO interface among the plurality of GPIO interfaces; performing metastable state processing on the input signal of the third GPIO interface by the GPIO controller, and storing the obtained input data into the register; reading the input data from the register by the first slave I3C interface, and transmitting the read input data to the extended chip via the front-end I3C bus.

13. The method of claim 8, wherein the receiving, by the first slave I3C interface, the first control data transmitted by the extended chip via the front-end I3C bus comprises: in a case that the front-end I3C bus is in an HDR bulk transmission mode, receiving, by the first slave I3C interface, a set of preset mode frames transmitted by the extended chip via the front-end I3C bus, wherein the preset mode frames comprise one start block and at least one data block, the start block of the preset mode frames carries a frame format command, and the first control data is carried in the data blocks of the set of preset mode frames.

14. The method of claim 13, wherein the preset mode frames further comprise one check block, and the check block of the preset mode frames carries a check value; in the process of receiving, by the first slave I3C interface, the first control data transmitted by the extended chip via the front-end I3C bus, the method further comprises: after receiving each preset mode frame, performing the following processing operations on the received preset mode frame as a current mode frame: generating a first check value corresponding to the current mode frame based on the current mode frame, and checking the current mode frame by comparing the first check value with a second check value carried in the check block of the current mode frame to obtain a check result of the current mode frame; transmitting, by the first slave I3C interface, the check result of the current mode frame to the extended chip via the front-end I3C bus, so that the extended chip performs a data transmission operation after the current mode frame based on the check result of the current mode frame.

15. The method of claim 14, wherein after the transmitting, by the first slave I3C interface, the check result of the current mode frame to the extended chip via the front-end I3C bus, the method further comprises: ​ ​ ​ ​ receive, through the first master I3C interface, a check result of the current mode frame transmitted by the first programmable logic device via the front-end I3C bus; in a case where the check result of the current mode frame is a check pass, release first sub-control data cached in the cache area of the extended chip, wherein the first sub-control data is part of the first control data carried in a data block of the current mode frame; in a case where there is second sub-control data in the cache area of the extended chip, generate the preset mode frame according to the second sub-control data to obtain a first mode frame to be transmitted, wherein the second sub-control data is part of the first control data that is not transmitted to the first programmable logic device, and part of data in the second sub-control data is carried in a data block of the first mode frame; transmit, through the first master I3C interface, the first mode frame to the first programmable logic device via the front-end I3C bus.

16. The method of claim 13, wherein, after the receiving, through the first master I3C interface, of the check result of the current mode frame transmitted by the first programmable logic device via the front-end I3C bus, the method further comprises: in a case where the check result of the current mode frame is a check fail, re-generate the preset mode frame according to the first sub-control data to obtain a second mode frame to be transmitted; transmit, through the first master I3C interface, the second mode frame to the first programmable logic device via the front-end I3C bus.

17. The method of claim 13, wherein, during the receiving, through the first slave I3C interface, of the first control data transmitted by the extended chip via the front-end I3C bus, the method further comprises: after each receiving of a preset mode frame, in a case where first indication information is received after the currently received preset mode frame, wait for receiving a next preset mode frame of the currently received preset mode frame, wherein the first indication information is used to indicate restarting of the HDR bulk transmission mode; in a case where second indication information is received after the currently received preset mode frame, terminate data transmission with the extended chip, and control the first programmable logic device to enter a low-power consumption state, wherein the second indication information is used to indicate exiting of the HDR bulk transmission mode.

18. The method of claim 13, wherein, before the receiving, through the first slave I3C interface, of the first control data transmitted by the extended chip via the front-end I3C bus, the method further comprises: receive, through the first slave I3C interface, an I3C broadcast address and a general command code command transmitted by the extended chip via the front-end I3C bus; in response to the received I3C broadcast address and the general command code command, determine to start the HDR bulk transmission mode of the front-end I3C bus.

19. The method of claim 18, wherein, the front-end I3C bus comprises two serial data lines and one serial clock line; the receiving, by the first slave I3C interface, the set of preset mode frames transmitted by the extended chip via the front-end I3C bus in the case that the front-end I3C bus is in the HDR bulk transfer mode comprises: after receiving the I3C broadcast address and the general command code command, in the case that a clock signal in the serial clock line is detected to be stable, parsing data received via the two serial data lines according to a preset packing manner to obtain a set of preset mode frames, wherein the preset packing manner is a manner of packing data using the two serial data lines.

20. The method of claim 8, wherein, the server further comprises a back-end communication bus, and the first programmable logic device further comprises a second master I3C interface, wherein the back-end communication bus is one of an I3C bus and an I2C bus, and the back-end communication bus is configured to connect the second master I3C interface and a second slave I3C interface of a slave module of the first programmable logic device; the method further comprises: receiving, by the first slave I3C interface, second control data transmitted by the extended chip via the front-end I3C bus, wherein the second control data is configured to control a second designated operation performed on a designated slave device of the first programmable logic device; and in response to the received second control data, transmitting, by the second master I3C interface, the second control data to the designated slave device via the back-end communication bus, so that the second designated operation is performed on the designated slave device.

21. The method of claim 20, wherein, the server further comprises at least one memory bank, and the plurality of GPIO interfaces are divided into at least one GPIO interface group, and a GPIO interface group in the at least one GPIO interface group is configured to connect a memory bank in the at least one memory bank, and the slave module of the first programmable logic device comprises at least one of a second programmable logic device, a microcontroller, a serial presence detect hub on a memory bank in the at least one memory bank, a temperature sensor on a memory bank in the at least one memory bank, and a fan on a memory bank in the at least one memory bank.

22. The method of any one of claims 8 to 21, wherein, before the receiving, by the first slave I3C interface, the first control data transmitted by the extended chip via the front-end I3C bus, the method further comprises: in the case that the front-end I3C bus is in an SDR mode, initializing, by the extended chip, the front-end I3C bus, and performing a discovery process to detect devices connected to the front-end I3C bus. acquire, by the extended chip, a static address of the first programmable logic device transmitted via the front-end I3C bus, wherein the static address of the first programmable logic device is preset in the first programmable logic device.

23. The method of claim 8, wherein, the first programmable logic device is configured to send an interrupt signal to the extended chip using an in-band interrupt signal.

24. A computer readable storage medium, comprising a computer program, wherein the computer program, when executed by a processor, implements the steps of the method of any one of claims 8 to 23. ​

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