A signal detection device, system and method

Abstract

The present disclosure provides a signal detection device, system and method. The device includes: a clock module, an input module, a detection module and an output module; the input module includes at least two analog-to-digital converters; the clock module is configured to sequentially provide clock signals to the analog-to-digital converters of the input module according to corresponding phases; the input module is configured to control each analog-to-digital converter to sample the current signal to be measured under the trigger of the corresponding clock signal, and perform analog-to-digital conversion to obtain corresponding digital signals; the obtained digital signals are combined according to the sampling timing to obtain a first digital signal; the detection module is configured to perform detection processing on the first digital signal to obtain a second digital signal; the output module is configured to perform real-time detection on the second digital signal, and if the second digital signal meets a preset jitter judgment condition after detection, output the second digital signal. Detect the signal in a complex noise environment to obtain the target signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of signal detection, and in particular, to a signal detection device, system and method. Background Art

[0002] In recent years, with the rapid development of technology, weak signal detection technology has also been increasingly enhanced and advanced. A weak signal refers to a weakened signal that is often submerged in background signals and is difficult to distinguish from natural or artificial interference. Weak signal detection technology is a technical means for capturing, identifying and analyzing weak signals in a complex noise environment. Weak signals have a wide range of applications in the development of modern technology, especially in the fields of medicine, biomedicine, environmental monitoring, geophysics, etc. The detection and identification of weak signals are of great significance for daily production and life. For example, in the field of medical imaging, weak signal technology can detect lesion areas in real time and efficiently, and accurately locate and analyze the causes of diseases. In the field of geophysical exploration, weak signal technology can also be used to search for resources such as oil and natural gas to assist in energy production. However, weak signal detection technology still faces many challenges in the application process. For example, the signal-to-noise ratio of weak signals is relatively low, and appropriate signal preprocessing technology and noise reduction technology often need to be adopted. In addition, weak signals often have a high degree of nonlinearity and complexity, and more complex and flexible algorithm technologies need to be used for processing and analysis. In addition, the cost of weak signal acquisition is relatively high, and it depends on high-end instrument equipment, which also increases the application difficulty of weak signal detection technology. Therefore, there are still many problems to be solved in the current detection of weak signals. Summary of the Invention

[0003] The present disclosure provides a signal detection device, system and method to solve the related problems existing in the existing solutions.

[0004] Based on the above problems, the present disclosure provides the following solutions.

[0005] In a first aspect, the present disclosure provides a signal detection device, including: a clock module, an input module, a detection module and an output module; the input module includes at least two analog-to-digital converters;

[0006] The clock module is configured to sequentially provide clock signals to the analog-to-digital converters of the input module according to corresponding phases; wherein, the division of different phases is related to the number of the analog-to-digital converters for parallel alternating sampling;

[0007] The input module is configured to control each analog-to-digital converter to sample the current signal to be measured under the trigger of the corresponding clock signal, and perform analog-to-digital conversion to obtain corresponding digital signals; and combine the obtained digital signals according to the sampling timing to obtain a first digital signal;

[0008] The detection module is configured to perform detection processing on the first digital signal to obtain a second digital signal;

[0009] The output module is configured to perform real-time detection on the second digital signal. If it is detected that the second digital signal meets a preset jitter judgment condition, the second digital signal is output.

[0010] In a possible implementation manner in combination with the first aspect, the device further includes a feedback module; the output module includes at least one digital-to-analog converter;

[0011] The clock module is further configured to sequentially provide clock signals to the digital-to-analog converters of the output module according to corresponding phases;

[0012] The output module is further configured to, if it is detected that the second digital signal does not meet the preset jitter judgment condition, control each digital-to-analog converter to perform digital-to-analog conversion on corresponding sub-signals of the second digital signal respectively under the trigger of the corresponding clock signal; and project the obtained analog signals into the same frequency domain according to the conversion timing sequence to obtain a feedback signal;

[0013] The feedback module is configured to mix the feedback signal and a new current signal to be measured to obtain a new mixed current signal to be measured; and feed back the new mixed current signal to be measured to the input module, and the input module performs the step of controlling each analog-to-digital converter to sample the new current signal to be measured and generate a first digital signal under the trigger of the corresponding clock signal.

[0014] In a possible implementation manner in combination with the first aspect, the input module is configured to control each analog-to-digital converter to sample a current signal to be measured under the trigger of the corresponding clock signal, and perform analog-to-digital conversion to obtain a digital signal with a corresponding preset number of bits; splice the obtained digital signals with the preset number of bits according to the sampling timing sequence to obtain a first digital signal;

[0015] The output module is configured to, if it is detected that the second digital signal does not meet the preset jitter judgment condition, control each digital-to-analog converter to sequentially obtain data with a preset number of bits from the second digital signal as sub-signals of the corresponding second digital signal, and perform digital-to-analog conversion on the obtained sub-signals; project the obtained analog signals into the same frequency domain in sequence according to the conversion timing sequence to obtain a combined feedback signal.

[0016] In a possible implementation manner in combination with the first aspect, the detection module includes: a reference signal module, a phase-locked module, a digital signal processor, an orthogonal digital phase-sensitive detector, and a digital low-pass filter;

[0017] The reference signal module is used to detect the frequency and phase of the signal to be measured and provide a reference signal with the same frequency as the signal to be measured;

[0018] The phase-locked module is used to adjust the phase of the reference signal through a phase-locked loop mechanism to make it consistent with the phase of the signal to be measured;

[0019] The multiplier is used to perform a multiplication operation on the first digital signal and the reference signal to obtain a composite signal containing information of the signal to be measured;

[0020] The quadrature digital phase-sensitive detector is used to decompose the composite signal to obtain an in-phase component and a quadrature component;

[0021] The digital low-pass filter is used to filter out high-frequency noise in the in-phase component and the quadrature component to obtain the in-phase component and the quadrature component after frequency difference; and use the in-phase component, the quadrature component, or a mixed signal obtained based on the in-phase component and the quadrature component as the second digital signal.

[0022] Combined with the first aspect, in a possible implementation manner, the clock module includes a temperature compensation module and a clock chip;

[0023] The temperature compensation module is used to monitor the ambient temperature in real time through a built-in temperature sensor, convert the detected temperature information into a corresponding electrical signal; calculate the required frequency compensation amount according to a pre-stored frequency-temperature characteristic curve in combination with the electrical signal; adjust the clock signal output by the clock chip based on the frequency compensation amount to make the clock chip output a stable clock signal;

[0024] The clock chip is used to sequentially provide clock signals to the analog-to-digital converter of the input module according to the corresponding phase;

[0025] The temperature compensation module is used to, if the temperature compensation module receives an external voltage control signal, monitor the ambient temperature in real time through a built-in temperature sensor, convert the detected temperature information into a corresponding electrical signal; obtain a frequency compensation amount based on the external voltage control signal and the electrical signal; adjust the clock signal output by the clock chip based on the frequency compensation amount to make the clock chip output a stable clock signal.

[0026] Combined with the first aspect, in a possible implementation manner, the device further includes: a preprocessing module, which is used to filter out signals that do not meet the preset frequency in the signal to be measured before sampling the signal to be measured, so that the upper frequency limit of the signal to be measured is limited to less than half of the sampling frequency.

[0027] In a second aspect, the present disclosure provides a signal detection system, including: the signal detection device as described in the first aspect and a host computer;

[0028] The signal detection device is configured to receive a signal to be measured and generate a reference signal based on the signal to be measured; the signal to be measured and the reference signal are subjected to phase-sensitive detection processing to obtain a second digital signal, and the stable second digital signal is output.

[0029] The host computer is configured to compensate the phase of the second digital signal to a preset range by means of curve fitting, measure and process the compensated second digital signal, complete corresponding unit conversion, and obtain relevant parameters corresponding to the signal to be measured.

[0030] In combination with the second aspect, in a possible implementation manner, the host computer is configured to perform frequency sweeping on the second digital signal within a preset range to obtain an actual phase-frequency response curve; with frequency as the abscissa and phase as the ordinate, fit the actual phase-frequency response curve to a pre-stored ideal phase-frequency response curve to obtain a compensation formula; substitute the phase value and frequency of the second digital signal into the compensation formula, and correspondingly adjust the second digital signal based on the new phase value obtained from the compensation formula to obtain a compensated second digital signal with the phase within the preset range.

[0031] In a third aspect, the present disclosure provides a signal detection method, including:

[0032] Controlling a clock module to sequentially provide clock signals to an analog-to-digital converter of an input module according to corresponding phases; wherein, the division of different phases is related to the number of the analog-to-digital converters for parallel alternating sampling;

[0033] Using the input module to control each analog-to-digital converter to sample a current signal to be measured under the trigger of the corresponding clock signal, and perform analog-to-digital conversion to obtain corresponding digital signals; combining the obtained digital signals according to a sampling timing sequence to obtain a first digital signal;

[0034] Controlling a detection module to perform detection processing on the first digital signal to obtain a second digital signal;

[0035] Performing real-time detection on the second digital signal through an output module, and if it is detected that the second digital signal meets a preset jitter judgment condition, outputting the second digital signal;

[0036] Compensating the phase of the output second digital signal to a preset range by means of curve fitting through a host computer, measuring and processing the compensated second digital signal, completing corresponding unit conversion, and obtaining relevant parameters corresponding to the signal to be measured.

[0037] Fourthly, the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the signal detection method as described in the third aspect or any possible implementation manner in combination with the third aspect.

[0038] The beneficial effects of the embodiments of the present disclosure include:

[0039] The present disclosure provides a signal detection device, system and method. With the close cooperation of each module, the device performs excellently in the field of signal detection. On the one hand, the clock module provides an accurate and stable clock reference, ensuring the timing accuracy of signal processing and greatly reducing the bit error rate; the detection module can accurately restore various complex modulation signals and efficiently extract useful information from the received signals. This enables the device to analyze and process the signal to be measured in any complex environment. On the other hand, the feedback and output module constitutes a closed-loop optimization mechanism, which can adjust the signal in real time according to the detection situation, eliminate noise during signal processing, and improve the operation stability in the automatic control system; coupled with the signal preprocessing and interference filtering capabilities, the device can adapt to complex electromagnetic environments, always accurately detect signals, and at the same time take into account efficient resource utilization and good integration, and can be integrated into multi-field systems to achieve collaborative work. Description of the Drawings

[0040] Figure 1 It is one of the schematic diagrams of a signal detection device provided by the embodiments of the present disclosure;

[0041] Figure 2 It is another schematic diagram of a signal detection device provided by the embodiments of the present disclosure;

[0042] Figure 3 It is the schematic diagram of the detection module provided by the embodiments of the present disclosure;

[0043] Figure 4 It is the schematic diagram of the clock module provided by the embodiments of the present disclosure;

[0044] Figure 5 It is the functional diagram of the temperature compensation module provided by the embodiments of the present disclosure;

[0045] Figure 6 It is the clock signal distribution diagram provided by the embodiments of the present disclosure;

[0046] Figure 7 It is the third schematic diagram of a signal detection device provided by the embodiments of the present disclosure;

[0047] Figure 8 It is the schematic diagram of a signal detection system provided by the embodiments of the present disclosure;

[0048] Figure 9Schematic diagram of the functional relationship of curve fitting provided by an embodiment of the present disclosure;

[0049] Figure 10 Relationship diagram of the phase and frequency of the compensated second digital signal provided by an embodiment of the present disclosure;

[0050] Figure 11 Flowchart of a signal detection method provided by an embodiment of the present disclosure. Detailed implementation manners

[0051] Embodiments of the present disclosure provide a signal detection device, system and method. The preferred embodiments of the present disclosure will be described below with reference to the accompanying drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. And without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0052] Embodiments of the present disclosure provide a signal detection device, as Figure 1 shown, including: a clock module 101, an input module 102, a detection module 103 and an output module 104; wherein the input module 102 includes at least two analog-to-digital converters;

[0053] The clock module 101 is configured to sequentially provide clock signals to the analog-to-digital converters of the input module 102 according to corresponding phases; wherein, the division of different phases is related to the number of analog-to-digital converters for parallel alternating sampling;

[0054] The input module 102 is configured to control each analog-to-digital converter to sample the current signal to be measured under the trigger of the corresponding clock signal, and perform analog-to-digital conversion to obtain corresponding digital signals; and combine the obtained digital signals according to the sampling timing to obtain a first digital signal;

[0055] The detection module 103 is configured to perform detection processing on the first digital signal to obtain a second digital signal;

[0056] The output module 104 is configured to perform real-time detection on the second digital signal, and if it is detected that the second digital signal meets a preset jitter judgment condition, output the second digital signal.

[0057] In an embodiment of the present disclosure, the above signal detection device is composed of a clock, an input, a detection, and an output module working together. The clock module 101 accurately divides the phase of the clock signal according to the number of analog-to-digital converters, and sends multiple parallel clock signals to each analog-to-digital converter, driving each converter of the input module 102 to perform synchronous sampling in sequence, thereby improving the sampling rate. Under the trigger of the clock, the input module 102 uses at least two converters to sample and convert the current signal to be measured in sequence according to the clock signal, and then combines them into a first digital signal according to the time sequence, making the first digital signal obtained by sampling more accurate and containing more information. For example, it can be implemented that for each analog-to-digital converter, when the rising edge (or falling edge) of the clock signal arrives, the analog-to-digital converter starts to sample the current signal to be measured, and then converts the sampled analog value into a digital value. However, since there are multiple converters working, the digital signals obtained by different analog-to-digital converters need to be combined in a certain time sequence. This sequence is determined by the clock signal or a pre-designed timing logic. For example, taking two 8-bit analog-to-digital converters as an example, it can be implemented that the 8-bit digital signal obtained by the first converter (for example, 10101010) is used as the high-order part, and the 8-bit digital signal obtained by the second converter (for example, 01010101) is used as the low-order part, and they are combined together to form a complete 16-bit digital signal (1010101001010101), that is, the first digital signal. The detection module 103 receives the first digital signal, and through detection processing, removes redundancy and extracts key information to obtain a second digital signal. The output module 104 screens the second digital signal in real time under a preset jitter condition, and only outputs the second digital signal that meets the preset jitter condition, ensuring the quality of the output signal and the stability and reliability of the signal.

[0058] In the embodiments of the present disclosure, the above-mentioned device can be applied in various scenarios. For example, in the communication field, in long-distance wireless communication, when 4G (the 4th Generation Mobile Communication Technology) or 5G (the 5th Generation Mobile Communication Technology) base stations receive signals from mobile terminals such as mobile phones, the signals received by the base stations are often very weak due to factors such as path loss, building blockage, and atmospheric attenuation during signal transmission. This device can help the base station receive and process these signals more accurately, improving communication quality and coverage. For example, in an urban environment with high-rise buildings, the signal becomes weak after multiple reflections and scatterings. By using weak signal detection devices such as low-noise amplifiers, the base station can enhance the signal strength, reduce the bit error rate, and ensure smooth voice calls and data transmission for users. In the biomedical field, there are various weak bioelectric signals inside the human body, such as electrocardiogram (ECG) for detecting the electrical activity of the heart, electroencephalogram (EEG) for detecting the electrical activity of brain neurons, and electromyogram (EMG) for detecting the electrical activity of muscles. The amplitudes of these signals are usually in the microvolt to millivolt range and are easily affected by external interference. This device can effectively extract these bioelectric signals for disease diagnosis and monitoring. For example, in the diagnosis of heart diseases, doctors can judge whether there are lesions such as arrhythmia and myocardial ischemia in the heart by analyzing the weak characteristic waves (such as P wave (atrial depolarization wave), QRS complex (ventricular depolarization complex), T wave (ventricular repolarization wave), etc.) in the electrocardiogram signal.

[0059] In another embodiment provided by the present disclosure, as Figure 2 shown, the above-mentioned device further includes a feedback module 105; the output module 104 includes at least one digital-to-analog converter;

[0060] The clock module 101 is further configured to sequentially provide clock signals to the digital-to-analog converters of the output module 104 according to corresponding phases;

[0061] The output module 104 is further configured to, if it is detected that the second digital signal does not meet the preset jitter judgment condition, control each digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal respectively under the trigger of the corresponding clock signal; and project the obtained analog signals into the same frequency domain according to the conversion timing sequence to obtain a feedback signal.

[0062] The feedback module 105 is configured to mix the feedback signal and the new current signal to be measured to obtain a new current signal to be measured after mixing; and feed back the new current signal to be measured after mixing to the input module 102, and the input module 102 executes the step of controlling each analog-to-digital converter to sample the new current signal to be measured and generate a first digital signal under the trigger of the corresponding clock signal.

[0063] In the embodiment of the present disclosure, the feedback module 105 in the device works in cooperation with the output module 104, the clock module 101 and the input module 102 to form a feedback loop. The clock module 101 provides a clock signal for the output module 104 to ensure the timing accuracy of digital-to-analog conversion. The output module 104 performs digital-to-analog conversion to obtain a feedback signal under specific conditions (the second digital signal does not meet the preset jitter judgment condition). The feedback module 105 sends the feedback signal back to the input module 102 for mixing with the original signal to be measured, that is, the feedback signal is superimposed or subtracted from the original signal to be measured. This feedback mechanism is to optimize the signal processing process and dynamically adjust the signal, which can ensure that the signal remains at a relatively constant level during the measurement process, helps to further suppress high-frequency noise and interference, and improves the accuracy of signal detection, so as to achieve a better processing effect.

[0064] Among them, the purpose of the clock module 101 to sequentially provide clock signals to the digital-to-analog converters of the output module 104 according to the corresponding phases is to ensure the synchronization and accuracy of the digital-to-analog conversion process. In a complex signal processing system, the clock signal provides an accurate time reference for each operation. The digital-to-analog conversion process needs to be carried out at specific time points to ensure the accuracy of the converted analog signal in terms of time and amplitude. In implementation, the clock module 101 can be implemented by an accurate clock chip and related control circuits. For example, a high-precision crystal oscillator is used as the clock source. When multiple digital-to-analog converters are used to increase the sampling rate, frequency division, frequency multiplication, and phase adjustment circuits are used to provide accurate clock signals for different digital-to-analog converters. For example, by setting the phase delay, clock signals with corresponding phases are provided for different digital-to-analog converters. If the output module 104 includes two digital-to-analog converters, the phase delay is set to 180 degrees. If the output module 104 includes three digital-to-analog converters, the phase delay is set to 120 degrees, and so on, to achieve providing multiple parallel clock signals for the output module 104 and clock synchronization. Similarly, the above clock module 101 provides clock signals for the analog-to-digital converter of the input module 102, which will not be elaborated here. In addition, the number of analog-to-digital converters and the number of digital-to-analog converters can be the same or different, which is not restricted here.

[0065] When the second digital signal does not meet the preset jitter judgment condition (the second digital signal shows periodic changes and there is no jitter), the output module 104 controls at least one digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal respectively. Among them, the above sub-signal is the digital code assigned to at least one digital-to-analog converter in the device when performing digital-to-analog conversion on the second digital signal. The main purpose of this step is to convert the digital signal back to the analog signal form for subsequent mixing with the new current signal to be measured. When integrating the corresponding sub-signals output by multiple digital-to-analog converters, the obtained analog signals can be projected into the same frequency domain according to the conversion timing to obtain a complete feedback signal.

[0066] The feedback module 105 performs signal superposition or subtraction on the feedback signal and the current signal to be measured input to the input module 102. The main purpose of this operation is to incorporate the information of the feedback signal into the new signal to be measured, so as to achieve dynamic adjustment and optimization of the signal. The new current signal to be measured after mixing is sampled and processed again to form a cycle. This cyclic feedback processing can continuously adjust the signal according to the actual situation of the device and the signal to be measured, adapting to different signal environments and processing requirements. Signal mixing can be achieved by an analog adder or subtractor, or by addition or subtraction operations in digital signal processing to superimpose or subtract two signals. In an analog system, the feedback signal and the new current signal to be measured are superimposed by an analog adder or subtracted by an analog subtractor to obtain the mixed signal. In a digital system, the digital codes corresponding to the feedback signal and the new current signal to be measured can be superimposed by an addition instruction or subtracted by a subtraction instruction in a digital signal processor (DSP, Digital Signal Processing). For example, in an adaptive equalizer of a digital communication system, the feedback module 105 adds and mixes the feedback signal and the new received signal in the digital domain using a DSP, and then sends the mixed signal back to the input module 102 for resampling and processing to continuously adjust the parameters of the equalizer and improve the equalization effect of the signal.

[0067] In another embodiment provided by the present disclosure, the input module 102 is configured to control each analog-to-digital converter to sample the current signal to be measured under the trigger of the corresponding clock signal, and perform analog-to-digital conversion to obtain a digital signal with a corresponding preset number of bits; splice the obtained digital signals with a preset number of bits according to the sampling timing to obtain a first digital signal;

[0068] The output module 104 is configured to, if it is detected that the second digital signal does not meet the preset jitter judgment condition, control each digital-to-analog converter to sequentially obtain data with a preset number of bits from the second digital signal as sub-signals of the corresponding second digital signal under the trigger of the corresponding clock signal, and perform digital-to-analog conversion on the obtained sub-signals; project the obtained analog signals into the same frequency domain in sequence according to the conversion timing to obtain a combined feedback signal.

[0069] In the embodiments of the present disclosure, the main purpose of the input module 102 is to convert the signal to be measured in analog form into a digital signal for subsequent digital signal processing. Its core lies in using an analog-to-digital converter (ADC) to perform sampling and conversion under the precise control of a clock signal. By sampling the analog signal at specific clock trigger moments, at the same time, the sampled digital signals are spliced into a first digital signal, providing a complete data basis for the subsequent processing flow. Each analog-to-digital converter samples under the trigger of the corresponding clock signal, which can ensure the timing accuracy of signal acquisition. By performing analog-to-digital conversion on the analog signal to obtain a digital signal with a preset number of bits, the continuous analog signal can be quantized into a discrete digital representation form, which is convenient for storage, transmission, and processing in a digital system. For example, for an 8-bit analog-to-digital converter, it can divide the amplitude range of the analog signal into 256 levels, thereby converting the analog signal into the corresponding digital code and storing it in the storage area in sequence. The storage area can be a RAM (Random-Access Memory) or a FIFO (First-In-First-Out). When the length of the digital code in the storage area reaches the preset length, the digital codes stored in sequence in the storage area are extracted to obtain a complete first digital signal, and subsequent detection and other processing are performed on the first digital signal. At this time, the storage area is cleared and at the same time, new digital codes obtained by analog-to-digital conversion are stored.

[0070] The main purpose of the output module 104 is to convert digital signals back into analog signals under specific conditions and combine these analog signals into a feedback signal. It is a prerequisite to detect whether the second digital signal meets the preset jitter judgment condition. The above preset jitter judgment condition can be implemented as follows: if the signal shows periodic changes in terms of time, amplitude, phase, etc., it is determined that the second digital signal meets the preset jitter judgment condition; if the signal does not show periodic changes in terms of time, amplitude, phase, etc., it is determined that the second digital signal does not meet the preset jitter judgment condition. It is required that the above output module 104 controls each digital-to-analog converter (DAC) to obtain data with a preset number of bits as sub-signals and perform digital-to-analog conversion under the trigger of the corresponding clock signal. Among them, the preset number of bits should be consistent with the number of bits of the digital-to-analog converter. The complete digital encoding of the second digital signal is divided according to the preset number of bits, and each digital encoding with the preset number of bits is a corresponding sub-signal. In implementation, if there is one digital-to-analog converter, multiple sub-signals are input into this digital-to-analog converter for digital-to-analog conversion. If there are multiple digital-to-analog converters, each digital-to-analog converter sequentially performs digital-to-analog conversion on a single sub-signal from front to back according to the trigger timing until all sub-signals are completely digitally converted. Then, according to the conversion timing, the obtained analog signals are sequentially projected into the same frequency domain to obtain the combined feedback signal, realizing the integration of multiple analog signals in the frequency domain. The implementation method can be to combine each analog sub-signal into a complete feedback signal within the same frequency range through signal superposition or other frequency domain synthesis methods.

[0071] In another embodiment provided by the present disclosure, as Figure 3 shown, the detection module 103 includes: a reference signal module 1031, a phase-locked module 1032, a multiplier 1033, an orthogonal digital phase-sensitive detector 1034, and a digital low-pass filter 1035;

[0072] The reference signal module 1031 is used to provide a reference signal with the same frequency as the signal to be measured;

[0073] The phase-locked module 1032 is used to adjust the phase of the reference signal through a phase-locked loop mechanism to keep it consistent with the phase of the signal to be measured;

[0074] The multiplier 1033 is used to perform a multiplication operation on the first digital signal and the reference signal to obtain a composite signal containing the information of the signal to be measured;

[0075] The orthogonal digital phase-sensitive detector 1034 is used to decompose the composite signal to obtain an in-phase component and a quadrature component;

[0076] The digital low-pass filter 1035 is used to filter out high-frequency noise in the in-phase component and the quadrature component, obtaining the in-phase component and the quadrature component after frequency difference; and using the in-phase component, the quadrature component, or a mixed signal obtained based on the in-phase component and the quadrature component as the second digital signal.

[0077] In the embodiments of the present disclosure, the detection module 103 is a complex signal processing unit, composed of a reference signal module 1031, a phase-locked module 1032, a multiplier 1033, a quadrature digital phase-sensitive detector 1034, and a digital low-pass filter 1035. Its main purpose is to extract useful information from the signal to be measured. Through a series of signal processing steps, the signal to be measured containing various frequency components and phase information is converted into a second digital signal that is easier to analyze and process.

[0078] The purpose of the reference signal module 1031 is to detect the frequency and phase of the signal to be measured and provide a reference signal with the same frequency as the signal to be measured. This step is the basis for subsequent precise detection. Accurately obtaining the frequency and phase information of the signal to be measured can provide a benchmark for subsequent signal processing, ensuring that the entire detection process can closely follow the characteristics of the signal to be measured. In implementation, a frequency counter and a phase comparator can be used. The frequency counter determines the frequency by calculating the number of signal cycles per unit time, and the phase comparator obtains the phase information by comparing the phase difference between the signal to be measured and a reference signal generated locally. Then, a signal generator (such as a direct digital frequency synthesizer - DDS) is used to generate a reference signal with the same frequency according to the detected frequency.

[0079] The phase-locked module 1032 adjusts the phase of the reference signal through a phase-locked loop mechanism to make it consistent with the phase of the signal to be measured. The consistency of the phase is crucial for accurately extracting information in the signal. In the subsequent processing of the signal, the phase difference between signals will directly affect the accuracy of the detection result. Keeping the phases of the reference signal and the signal to be measured consistent can maximize the sensitivity and accuracy of signal detection. Among them, the above phase-locked loop mechanism is mainly implemented by a phase detector, a loop filter, and a voltage-controlled oscillator (VCO, Voltage-Controlled Oscillator). The phase detector compares the phase difference between the reference signal and the signal to be measured, generating an error signal proportional to the phase difference. The loop filter filters the error signal to remove high-frequency noise, and then inputs the filtered signal into the VCO. The VCO adjusts the frequency and phase of its output signal according to the input signal, so that the phase of the reference signal gradually aligns with the phase of the signal to be measured.

[0080] Multiplier 1033 multiplies the first digital signal and the reference signal to obtain a composite signal containing the information of the signal to be measured. This is a spectrum shifting method. By multiplying the signal with the reference signal, the spectrum of the signal to be measured can be shifted to a new frequency position, facilitating subsequent filtering and signal extraction operations. For example, in the modulation and demodulation processes, multiplier 1033 is used to multiply the baseband signal with the carrier signal to achieve modulation, or multiply the received modulated signal with the local carrier to achieve demodulation. In implementation, it can be realized by digital circuits, such as using a digital multiplier chip or implementing the multiplication operation logic in a programmable logic device (FPGA, Field - Programmable Gate Array). Multiplier 1033 multiplies each sampling point of the first digital signal with the corresponding sampling point of the reference signal to obtain a sequence of sampling points of the composite signal.

[0081] The quadrature digital phase - sensitive detector 1034 decomposes the composite signal to obtain the in - phase component and the quadrature component. In signal processing, the in - phase component and the quadrature component contain the amplitude and phase information of the signal, and this decomposition method helps to analyze the signal more comprehensively and accurately. For example, when processing a signal with phase modulation, the in - phase component and the quadrature component can respectively represent the real part and the imaginary part of the signal, and the original phase information of the signal can be restored through their analysis. In implementation, the quadrature digital phase - sensitive detector 1034 can use trigonometric function relationships to achieve decomposition. Through digital signal processing algorithms, the above - mentioned composite signal is respectively multiplied with the in - phase reference signal (usually a cosine function) and the quadrature reference signal (usually a sine function), and then through operations such as low - pass filtering or integration, the in - phase component and the quadrature component are obtained.

[0082] The digital low-pass filter 1035 filters out high-frequency noise in the in-phase component and the quadrature component, obtains the in-phase component and the quadrature component after frequency difference, and uses the in-phase component, the quadrature component, or a mixed signal obtained based on the in-phase component and the quadrature component as the second digital signal. The high-frequency noise may come from factors such as interference during signal transmission and quantization noise. Filtering out these noises can improve the quality and recognizability of the signal. The obtained second digital signal is purer and more suitable for performing at least one of subsequent signal analysis and processing tasks including, for example, feature extraction and parameter measurement. In implementation, the digital low-pass filter 1035 can be implemented using a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter. The FIR filter realizes filtering by performing a convolution operation on the input signal by designing appropriate filter coefficients. The IIR filter uses a feedback structure and realizes filtering through recursive operations. According to the frequency range of the high-frequency noise to be filtered out and the performance requirements of the filter, an appropriate filter type and parameters can be selected. There is no limitation on which filter is specifically used here.

[0083] In another embodiment provided by the present disclosure, as Figure 4 shown, the clock module 101 includes a temperature compensation module 1011 and a clock chip 1012;

[0084] The temperature compensation module 1011 is configured to monitor the ambient temperature in real time through a built-in temperature sensor, convert the detected temperature information into a corresponding electrical signal; calculate the required frequency compensation amount based on the pre-stored frequency-temperature characteristic curve and the electrical signal; adjust the clock signal output by the clock chip 1012 based on the frequency compensation amount to make the clock chip 1012 output a stable clock signal;

[0085] The clock chip 1012 is configured to sequentially provide clock signals to the analog-to-digital converter of the input module 102 according to corresponding phases;

[0086] The temperature compensation module 1011 is configured to, if the temperature compensation module 1011 receives an external voltage control signal, monitor the ambient temperature in real time through a built-in temperature sensor, convert the detected temperature information into a corresponding electrical signal; obtain a frequency compensation amount based on the external voltage control signal and the electrical signal; adjust the clock signal output by the clock chip 1012 based on the frequency compensation amount to make the clock chip 1012 output a stable clock signal.

[0087] In the embodiments of the present disclosure, the clock module 101 operates in cooperation with two core components, namely, the temperature compensated module 1011 and the clock chip 1012. The temperature compensated module 1011 is responsible for dynamically monitoring the ambient temperature and precisely adjusting the clock signal output by the clock chip 1012 based on the temperature information to ensure the stability of the clock. The clock chip 1012 is responsible for orderly providing the clock signal to the analog-to-digital converter of the input module 102 at a specific phase, ensuring that the clocks of each ADC, DAC, and control chip are synchronized during the analog-to-digital conversion process, thereby maintaining the normal timing of the entire device.

[0088] The above-mentioned temperature compensated module 1011 can be implemented as a voltage-controlled temperature compensated crystal oscillator. When providing the clock signal for the ADC and DAC, it precisely regulates the output frequency by adjusting the externally applied voltage, thereby effectively compensating for the potential impact of temperature changes on frequency stability. For example, Figure 5 as shown, it specifically includes the following functions:

[0089] Power-on self-calibration: After the temperature compensated module 1011 is powered on, it first executes the initialization self-calibration program. This program captures the current ambient temperature information in real time through the built-in ambient temperature detection mechanism and dynamically adjusts the compensation parameters according to the preset advanced algorithm to ensure that its output frequency meets the predetermined accuracy requirements;

[0090] Temperature detection: The precision temperature sensor integrated inside the temperature compensated module 1011 continuously monitors the operating ambient temperature and converts the detected temperature information into corresponding electrical signals. Any slight temperature change will immediately trigger the adjustment mechanism of the compensation circuit to respond to the fluctuation of the ambient temperature. For example, for common temperature sensors such as thermistors, their resistance values change predictably with the ambient temperature. Utilizing this characteristic, the change in resistance value is converted into corresponding electrical signals through a simple circuit. For example, when the temperature rises, the resistance value of the thermistor decreases. Through the fixed resistor connected in series with it and a suitable voltage source, an electrical signal with a changing voltage value can be obtained at the connection point between the two, and this electrical signal reflects the current ambient temperature.

[0091] Frequency-Temperature Compensation Calculation: The compensation circuit receives the electrical signal from the temperature sensor and accurately calculates the required frequency compensation amount based on the frequency-temperature characteristic curve pre-stored in the non-volatile memory. Among them, the frequency-temperature characteristic curve can be obtained through a large number of test experiments on the clock chip 1012 at different temperatures. The test results are fitted to form a continuous or piecewise continuous curve and stored in the memory of the device. During actual operation, after obtaining the electrical signal corresponding to the current temperature, the corresponding frequency compensation amount is calculated based on the curve through the look-up table algorithm or interpolation algorithm. For example, if it is known that the frequency of a certain clock chip 1012 will decrease by 10 Hz at 20 °C, when the electrical signal corresponding to the monitored current temperature points to 20 °C, it can be known from the pre-stored curve that a frequency compensation amount of 10 Hz needs to be increased.

[0092] Dynamic Frequency Adjustment: Based on the calculated frequency compensation value, the compensation circuit automatically adjusts the capacitance value of the varactor diode, thereby changing the equivalent load capacitance in the oscillation circuit to achieve instant compensation and adjustment of the oscillation frequency. This dynamic adjustment mechanism based on real-time feedback ensures that the temperature compensation module 1011 can maintain a high degree of frequency stability throughout the operating temperature range. For example, one adjustment method is to use the digital phase-locked loop (DPLL, Digital Phase-Locked Loop) technology. There is a voltage-controlled oscillator (VCO) inside the DPLL. When receiving the frequency compensation amount (represented in the form of voltage) from the temperature compensation module 1011, the oscillation frequency of the VCO will change accordingly, and then adjust the frequency of the clock signal output by the clock chip 1012. For example, if it is calculated that the clock frequency needs to be increased, the DPLL will control the VCO to increase the oscillation frequency, so that the frequency of the clock signal output by the clock chip 1012 increases, achieving the purpose of stabilizing the clock.

[0093] Output Stable Frequency Signal: After precise temperature compensation and frequency adjustment, the temperature compensation module 1011 finally outputs a stable and accurate frequency signal. This signal not only has a high degree of frequency stability but also can effectively resist the negative impact of environmental temperature changes on frequency accuracy, providing a reliable clock signal for ADC and DAC.

[0094] In addition, if the temperature compensation module 1011 receives an external voltage control signal at the same time, the compensation circuit will comprehensively consider this signal and the output of the temperature sensor, and further adjust the frequency compensation value to achieve more precise frequency control; that is, when the temperature compensation module 1011 receives an external voltage control signal, the above-mentioned steps of temperature monitoring, frequency compensation amount calculation, and clock signal adjustment are repeated, which provides an additional clock adjustment mechanism for the device, and can meet higher requirements for clock accuracy or adapt to special application scenarios in special cases. During implementation, the ambient temperature is also monitored based on the built-in temperature sensor and converted into an electrical signal. The difference is that at this time, the calculation of the frequency compensation amount needs to comprehensively consider the external voltage control signal. For example, the external voltage control signal may indicate an additional increase or decrease in a certain frequency adjustment range on the basis of the current temperature compensation. The external voltage signal and the electrical signal corresponding to the temperature are combined through a preset algorithm to calculate the final frequency compensation amount, and then technologies such as DPLL are used to adjust the clock signal.

[0095] In summary, through a series of precise calibration, monitoring, calculation, and adjustment steps, the temperature compensation module 1011 realizes dynamic compensation for changes in ambient temperature, ensures high stability and accuracy of the output frequency, and further makes the clock signal output by the above-mentioned clock chip 1012 more precise and stable.

[0096] In the embodiment of the present disclosure, as Figure 6 shown, the above-mentioned clock chip 1012 provides corresponding clock signals to each multi-channel parallel analog-to-digital converter and digital-to-analog converter according to the corresponding phases, aiming to ensure precise synchronization of the clocks of multiple analog-to-digital converters and digital-to-analog converters in the device with the control chip. For example, in a digital signal processing system, analog-to-digital conversion is a key step in converting analog signals into digital signals. Only under the precise drive of the clock signal can the analog-to-digital converter sample the analog signal at the correct time point to ensure the accuracy of the sampled data. At the same time, the clock chip 1012 also provides precise clock signals to the control chip FPGA and the digital-to-analog converter in the output module 104.

[0097] In another embodiment provided by the present disclosure, as Figure 7 shown, the above-mentioned device further includes: a preprocessing module 106, which is used to filter out signals that do not meet the preset frequency in the signal to be measured before sampling the signal to be measured, so that the upper frequency limit of the signal to be measured is limited to less than half of the sampling frequency.

[0098] In the embodiments of the present disclosure, it is necessary to use the preprocessing module 106 to limit the upper frequency limit to less than half of the sampling frequency, based on the Nyquist-Shannon sampling theorem. This theorem states that in order to be able to recover the original continuous signal without distortion from the sampled discrete signal, the sampling frequency must be at least twice the highest frequency of the original signal. If this condition is not met, aliasing will occur. Aliasing means that high-frequency and low-frequency signals become indistinguishable after sampling, resulting in errors during signal reconstruction. For example, for a signal with a frequency of f 1 = 120 Hz, when the sampling frequency f s = 100 Hz, according to the formula calculation, the Nyquist criterion is not satisfied. In this case, this 120 Hz high-frequency signal may be wrongly treated as a low-frequency signal with a frequency of f 2 = (100 - (120 - 100)) Hz = 80 Hz, resulting in distortion after signal reconstruction. Therefore, it is necessary to set up the preprocessing module 106 to avoid the occurrence of false signals in the ADC signals.

[0099] In the embodiments of the present disclosure, the above-mentioned preprocessing module 106 is a component of the signal detection device provided by the present disclosure. Its main responsibility is to preprocess the signal before the operation of sampling the signal to be measured. The core action of the preprocessing is filtering, that is, screening the frequency components of the signal. Among them, filtering out the signals that do not meet the preset frequency means that the device has preset a frequency range (i.e., the preset frequency). For the components of the signal to be measured whose frequencies are not within this range, the preprocessing module 106 will remove them. For example, if the highest frequency of the signal to be measured is f max = 200 Hz, after filtering, the signal components in the signal to be measured that are higher than 100 Hz will be filtered out, thereby limiting the upper frequency limit to less than half of the sampling frequency in this way. The aliasing problem caused by too high frequency is avoided, so that in the subsequent sampling and processing process, the signal to be measured can be restored and processed more accurately.

[0100] Based on the same inventive concept, the embodiments of the present disclosure also provide a signal detection system and method. Since the principles of the problems solved by these systems and methods are similar to those of the aforementioned signal detection device, the implementation of these systems and methods can refer to the implementation of the aforementioned device, and the repeated parts will not be elaborated.

[0101] Corresponding to the above-mentioned Figure 1 shown signal detection device, the embodiments of the present disclosure also provide a signal detection system, as Figure 8 shown, including: the signal detection device 801 and the host computer 802 as described above;

[0102] The signal detection device 801 is used to receive the signal to be tested and generate a reference signal based on the signal to be tested; perform orthogonal phase-sensitive processing on the signal to be tested and the reference signal to obtain a second digital signal, and output a stable second digital signal;

[0103] The host computer 802 is used to compensate the phase of the second digital signal to within a preset range by curve fitting, and to measure and process the compensated second digital signal, complete corresponding unit conversion, and obtain relevant parameters corresponding to the signal to be measured.

[0104] In another embodiment provided by the present disclosure, the above-mentioned upper computer 802 is used to sweep the frequency of the second digital signal within a preset range to obtain an actual phase-frequency response curve; with frequency as the horizontal coordinate and phase as the vertical coordinate, the actual phase-frequency response curve is fitted to a pre-stored ideal phase-frequency response curve to obtain a compensation formula; the phase value and frequency of the second digital signal are substituted into the compensation formula, and the second digital signal is adjusted accordingly based on the new phase value obtained by the compensation formula to obtain a compensated second digital signal with a phase within the preset range.

[0105] In the disclosed embodiment, the host computer 802 performs a frequency sweep on the second digital signal within a preset range, and its core purpose is to fully understand the phase characteristics of the digital signal at different frequencies. Through the frequency sweep operation, the specific situation of the signal phase changing with the frequency can be obtained, thereby laying the foundation for subsequent signal processing and optimization. In many systems involving signal transmission and processing, the phase characteristics of the signal have a crucial impact on the overall performance. In the device, accurate phase information is related to the correct demodulation of the signal and the accurate restoration of the information. During implementation, the host computer 802 can send a control instruction to the above-mentioned signal detection device 801 to change the frequency of the signal within a preset frequency range according to the step size of the geometric series, and collect and record the phase information corresponding to each frequency point. For example, if the frequency sweep range is set to be from 1kHz to 5MHz and 1000 points are scanned, it will be divided into 1000 points according to the relationship of the geometric series within 1kHz to 5MHz, then the host computer 802 will control the device to output the signal at each frequency point in turn, and record the phase situation of the second digital signal corresponding to each frequency point, and finally summarize these data to form an actual phase-frequency response curve. Then, the actual phase-frequency response curve is fitted to the pre-stored ideal phase-frequency response curve in order to find out the deviation between the actual signal and the ideal state. The ideal phase-frequency response curve represents the relationship between the phase of the signal and the frequency under the optimal condition, while the actual signal often deviates from the ideal state due to various interference factors (such as noise, non-ideal characteristics of the equipment, etc.). By fitting the compensation formula, the actual signal can be adjusted in a targeted manner according to the formula to make it as close to the ideal state as possible, thereby improving the signal quality. For example, Figure 9 ,10 As shown, with frequency as the abscissa and phase as the ordinate, fitting the actual phase-frequency response curve to the pre-stored ideal phase-frequency response curve, a relational expression can be obtained, which is the functional relational expression for compensating the actual phase shift to the ideal phase shift. Substituting the fitted curve into the calibrated result gives: y = y 1 -0.0001604x + 180.1138, where y 1 is the original phase value of the second digital signal obtained by the host computer 802. Substituting the original phase value and frequency of the second digital signal into the above functional relational expression, the offset phase can be calibrated to the ideal result, and the compensated phase value y can be obtained.

[0106] Corresponding to the signal detection device shown above Figure 1 the present disclosure embodiment also provides a signal detection method, as Figure 11 shown, including:

[0107] S1101. Control the clock module to sequentially provide clock signals to the analog-to-digital converter of the input module according to the corresponding phases; wherein, the division of different phases is related to the number of analog-to-digital converters for parallel alternating sampling;

[0108] S1102. Use the input module to control each analog-to-digital converter to sample the current signal to be measured under the trigger of the corresponding clock signal, and perform analog-to-digital conversion to obtain the corresponding digital signals; combine the obtained digital signals according to the sampling timing to obtain the first digital signal;

[0109] S1103. Control the detection module to perform detection processing on the first digital signal to obtain the second digital signal;

[0110] S1104. Real-time detect the second digital signal through the output module. If it is detected that the second digital signal meets the preset jitter judgment condition, output the second digital signal;

[0111] S1105. Through the host computer, adopt the curve fitting method to compensate the phase of the output second digital signal to the preset range, and perform measurement and data processing on the compensated second digital signal, complete the corresponding unit conversion, and obtain the relevant parameters corresponding to the signal to be measured.

[0112] The present disclosure embodiment provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the signal detection method provided in any embodiment of the present disclosure. Wherein, the storage medium can be a volatile or non-volatile computer-readable storage medium.

[0113] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware or by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present disclosure.

[0114] Those skilled in the art can understand that the drawings are only schematic diagrams of a preferred embodiment, and the modules or processes in the drawings are not necessarily essential for implementing the present disclosure.

[0115] Those skilled in the art can understand that the modules in the devices in the embodiments can be distributed in the devices in the embodiments according to the description of the embodiments, or can be correspondingly changed to be located in one or more devices different from the embodiments. The modules of the above embodiments can be combined into one module, or can be further split into multiple sub-modules.

[0116] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0117] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A signal detection device, characterized in that: include: A clock module, an input module, a detection module, an output module and a feedback module; the input module includes at least two analog-to-digital converters; The output module includes at least one digital-to-analog converter; The clock module is used to provide clock signals to the analog-to-digital converters of the input module in sequence according to corresponding phases; wherein the division of different phases is related to the number of the analog-to-digital converters that are sampled alternately in parallel; The input module is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal; and combine the obtained digital signals according to the sampling timing to obtain a first digital signal; The detection module is used to perform detection processing on the first digital signal to obtain a second digital signal; The output module is used to perform real-time detection on the second digital signal, and output the second digital signal if the second digital signal meets a preset jitter judgment condition after detection; The clock module is also used to provide clock signals to the digital-to-analog converters of the output modules in sequence according to corresponding phases; The output module is further configured to control each digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal respectively under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection; and project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a feedback signal; The feedback module is used to mix the feedback signal and the new current signal to be tested to obtain a mixed new current signal to be tested; and feed the mixed new current signal to be tested back to the input module, and the input module executes the steps of controlling each analog-to-digital converter to sample the new current signal to be tested and generate a first digital signal under the triggering of a corresponding clock signal.

2. The device according to claim 1, characterized in that The input module is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal of a preset number of bits; splicing the obtained digital signals of each preset number of bits according to the sampling timing to obtain a first digital signal; The output module is used to control each digital-to-analog converter to sequentially obtain data of preset bits from the second digital signal as sub-signals corresponding to the second digital signal under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection, and perform digital-to-analog conversion on the obtained sub-signals; and sequentially project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a merged feedback signal.

3. The device according to claim 1, characterized in that The detection module includes: a reference signal module, a phase-locking module, a multiplier, an orthogonal digital phase-sensitive detector and a digital low-pass filter; The reference signal module is used to provide a reference signal with the same frequency as the signal to be measured; The phase-locked module is used to adjust the phase of the reference signal through a phase-locked loop mechanism so that the phase of the reference signal is consistent with the phase of the signal to be measured; The multiplier is used to perform a multiplication operation on the first digital signal and the reference signal to obtain a composite signal containing information of the signal to be measured; The orthogonal digital phase-sensitive detector is used to decompose the composite signal to obtain an in-phase component and an orthogonal component; The digital low-pass filter is used to filter out high-frequency noise in the in-phase component and the orthogonal component to obtain the in-phase component and the orthogonal component after difference frequency; and use the in-phase component, the orthogonal component or a mixed signal obtained based on the in-phase component and the orthogonal component as the second digital signal.

4. The device according to claim 1, characterized in that The clock module includes a temperature compensation module and a clock chip; The temperature compensation module is used to monitor the ambient temperature in real time through a built-in temperature sensor, convert the detected temperature information into a corresponding electrical signal; calculate the required frequency compensation amount based on the pre-stored frequency-temperature characteristic curve combined with the electrical signal; adjust the clock signal output by the clock chip based on the frequency compensation amount, so that the clock chip outputs a stable clock signal; The clock chip is used to provide clock signals to the analog-to-digital converter of the input module in sequence according to corresponding phases; The temperature compensation module is used to monitor the ambient temperature in real time through a built-in temperature sensor if the temperature compensation module receives an external voltage control signal, and convert the detected temperature information into a corresponding electrical signal; obtain a frequency compensation amount based on the external voltage control signal and the electrical signal; and adjust the clock signal output by the clock chip based on the frequency compensation amount so that the clock chip outputs a stable clock signal.

5. The device according to claim 1, characterized in that Also includes: The preprocessing module is used to filter out signals that do not meet the preset frequency in the signal to be tested before sampling the signal to be tested, so that the upper frequency limit of the signal to be tested is limited to less than half of the sampling frequency.

6. A signal detection system, characterized in that: include: The signal detection device and host computer as claimed in claim 1; The signal detection device is used to receive a signal to be tested and generate a reference signal based on the signal to be tested; the signal to be tested and the reference signal are processed by phase-sensitive detection to obtain a second digital signal, and output a stable second digital signal; The host computer is used to compensate the phase of the second digital signal to within a preset range by curve fitting, and to measure and process the compensated second digital signal, complete corresponding unit conversion, and obtain relevant parameters corresponding to the signal to be measured.

7. The system according to claim 6, characterized in that The host computer is used to perform frequency sweep on the second digital signal within a preset range to obtain an actual phase-frequency response curve; With frequency as the horizontal coordinate and phase as the vertical coordinate, the actual phase-frequency response curve is fitted to the pre-stored ideal phase-frequency response curve to obtain a compensation formula; the phase value and frequency of the second digital signal are substituted into the compensation formula, and the second digital signal is adjusted accordingly based on the new phase value obtained by the compensation formula to obtain a compensated second digital signal with a phase within a preset range.

8. A signal detection method, characterized in that: include: The control clock module provides clock signals to the analog-to-digital converters of the input module in sequence according to corresponding phases; wherein the division of different phases is related to the number of the analog-to-digital converters that perform parallel alternating sampling; Using the input module to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain the corresponding digital signal; merging the obtained digital signals according to the sampling timing to obtain the first digital signal; Controlling the detection module to perform detection processing on the first digital signal to obtain a second digital signal; Performing real-time detection on the second digital signal through the output module, and outputting the second digital signal if the second digital signal meets a preset jitter judgment condition after detection; The phase of the output second digital signal is compensated to a preset range by using a curve fitting method in the upper computer, and the compensated second digital signal is measured and data processed to complete the corresponding unit conversion to obtain the relevant parameters corresponding to the measured signal; Also includes: Controlling the clock module to provide clock signals to the digital-to-analog converters of the output modules in sequence according to corresponding phases; If it is detected that the second digital signal does not meet the preset jitter judgment condition, the output module controls each digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal under the triggering of the corresponding clock signal; and projects the obtained analog signals into the same frequency domain according to the conversion timing to obtain a feedback signal; The feedback signal and the new current signal to be tested are mixed by the feedback module to obtain a mixed new current signal to be tested; and the mixed new current signal to be tested is fed back to the input module, and the input module executes the step of controlling each analog-to-digital converter to sample the new current signal to be tested and generate a first digital signal under the triggering of the corresponding clock signal.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the signal detection method according to claim 8 are executed.

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