An experimental system for measuring electrical characteristics of a device in an irradiation environment

Abstract

The application provides an experimental system for measuring electrical characteristics of a device in an irradiation environment, wherein a trigger unit is connected to an avalanche test unit and a surge test unit respectively after analog-digital conversion, and generates a test trigger signal; the avalanche test unit and the surge test unit output corresponding test signals respectively and record electrical characteristic data of the device to be tested; a control signal processing unit realizes switch control of each test channel through signal comprehensive judgment; a self-checking comparison unit receives a self-checking current signal generated by a protection circuit and generates a corresponding signal output to the control signal processing unit; a judgment unit compares signal outputs of each test unit, and marks an abnormal unit; and an irradiation protection unit isolates the influence of a radiation environment on the test system. The application has the advantages of high integration, convenient and fast testing, intuitive display of abnormal conditions, and greatly reduced failure probability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device testing, and particularly relates to an experimental system for measuring electrical characteristics of a device in an irradiation environment. BACKGROUND

[0002] The third generation semiconductor material represented by gallium nitride (GaN) has important application prospects in the field of high frequency and high power density due to its wide band gap, high breakdown field, high thermal conductivity, large electron saturation velocity and excellent radiation resistance. However, in the irradiation environment, the electrical properties of these devices will be affected by radiation effects, resulting in performance degradation or even device failure.

[0003] The avalanche and surge characteristics of a semiconductor device are important indicators for its safe operation. Avalanche characteristic testing can be used to evaluate the performance of a device under overvoltage conditions, while surge testing is used to evaluate the stability of a device under transient high current impact. For these two tests, the traditional experimental system is usually built independently, which not only increases the testing cost, but also reduces the testing efficiency. Therefore, it is particularly important to design an experimental system that can simultaneously test the avalanche and surge characteristics and is suitable for the irradiation environment. SUMMARY

[0004] The present application provides an experimental system for measuring electrical characteristics of a device in an irradiation environment to solve the technical problem that the existing test system cannot simultaneously test the avalanche and surge characteristics in the irradiation environment.

[0005] To solve the above technical problems, the present application provides an experimental system for measuring electrical characteristics of a device in an irradiation environment, comprising a trigger unit, an avalanche test unit, a surge test unit, a control signal processing unit, a self-checking comparison unit, a determination unit and an irradiation protection unit.

[0006] The trigger unit is used to generate a test signal and is connected to the avalanche test unit and the surge test unit through a unified test channel.

[0007] The avalanche test unit is connected to the semiconductor device under test through an avalanche test channel, outputs an avalanche test signal and displays the test data of the semiconductor device under test.

[0008] The surge test unit is connected to the semiconductor device under test through a surge test channel, outputs a surge test signal and displays the test data of the device.

[0009] The control signal processing unit controls the working state of the avalanche test unit and the surge test unit to ensure that the avalanche test channel and the surge test channel are not enabled at the same time, and generates a conversion signal to switch the test circuit.

[0010] The self-checking comparison unit is configured to receive output signals of the avalanche test unit and the surge test unit, perform self-checking, determine whether the protection circuit is working normally, and transmit a self-checking result to the control signal processing unit.

[0011] The determination unit is configured to compare output signals of the avalanche test circuit and the surge test circuit, identify abnormal signals, and drive a red LED lamp to prompt an operator.

[0012] The irradiation protection unit is configured to wrap all the units with an anti-irradiation material and expose them to an irradiation environment.

[0013] Preferably, the avalanche test unit comprises a power supply, an oscilloscope, and an avalanche test circuit, the avalanche test circuit is connected to the trigger unit through a first channel, and is connected to a G terminal, a D terminal, and an S terminal of the semiconductor device to be tested through a second channel, a third channel, and a fourth channel respectively, wherein the first channel is used to trigger an avalanche test signal, and the second channel, the third channel, and the fourth channel are used to input the test signal to the device to be tested.

[0014] Preferably, the avalanche test circuit comprises a protection circuit, a control circuit, and a test circuit, wherein the protection circuit is used to protect the device to be tested from high current damage, the control circuit is used to send a self-checking signal and transmit a self-checking result to the self-checking comparison unit, and the test circuit performs an avalanche test operation.

[0015] Preferably, the surge test unit comprises a power supply, an oscilloscope, and a surge test circuit, the surge test circuit is connected to the trigger unit through a fifth channel, and is connected to the G terminal, the D terminal, and the S terminal of the semiconductor device to be tested through a sixth channel, a seventh channel, and an eighth channel respectively, wherein the fifth channel is used to trigger a surge test signal, and the sixth channel, the seventh channel, and the eighth channel are used to input the test signal to the device to be tested.

[0016] Preferably, the surge test circuit comprises a protection circuit, a control circuit, and a test circuit, wherein the protection circuit is used to protect the device to be tested from high current damage, the control circuit is used to send a self-checking signal and transmit a self-checking result to the self-checking comparison unit, and the test circuit performs a surge test operation.

[0017] Preferably, the control signal processing unit comprises a signal generator, an FPGA, and a Bluetooth module, the signal generator is used to control switching of test signal input channels of the avalanche test unit and the surge test unit, and generate a conversion signal to switch a test line.

[0018] Preferably, the control signal processing unit controls the first channel of the avalanche test unit and the fifth channel of the surge test unit to turn on and off through one channel of the signal generator; the control signal processing unit controls the second to fourth channels and the sixth to eighth channels through two channels of the signal generator; and the signal generator generates a conversion signal to switch the main test line and the backup test line.

[0019] Preferably, the self-test comparison unit receives the output signals of the avalanche test unit and the surge test unit, and judges the self-test result of the protection circuit. If an abnormality is found in the protection circuit or other test circuits, a fault signal is output to the control signal processing unit, which then switches the test line or sends an alarm signal to the remote computer.

[0020] Preferably, the avalanche test unit is provided with several avalanche test circuits, the surge test unit is provided with several surge test circuits, and the determination unit includes NAND gates, XOR gates and SR latches, which are respectively connected to the output terminals of the several avalanche test circuits and surge test circuits, for comparing output signals and driving red LEDs to display abnormal output signals that are different from other signals.

[0021] Preferably, the first, second, third, and fourth channels include MEMS switches and inverters; the fifth, sixth, seventh, and eighth channels include MEMS switches.

[0022] The beneficial effects of the present invention include at least the following:

[0023] 1) The invention achieves electrical and spatial isolation of semiconductor devices in avalanche and surge testing, avoiding mutual interference between the two test circuits, and enabling simultaneous avalanche and surge testing;

[0024] 2) The determination circuit designed in this invention can intuitively monitor whether the test circuit is in normal working condition and switch the abnormal test circuit to a normal working test circuit.

[0025] 3) The avalanche and surge protection circuit designed in this invention can perform self-testing, monitor whether the test circuit is working properly in a timely manner, and transmit the results to a remote computer through the self-test comparison unit, so that operators can obtain abnormal information and analyze the damage of the test circuit.

[0026] 4) In order to reduce the impact of radiation on the test circuit and the chip under test, the entire experimental system is distributed in the radiation protection unit. The radiation protection unit can effectively prevent space particles in the radiation environment from affecting the active devices in the entire experimental system.

[0027] 5) This invention has the advantages of high integration, convenient and quick testing, intuitive display of abnormal conditions, and significant reduction of failure probability. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the experimental system according to an embodiment of the present invention;

[0029] Figure 2 This is a circuit diagram of the avalanche test circuit according to an embodiment of the present invention;

[0030] Figure 3 This is a circuit diagram of the surge test circuit according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic circuit diagram of the determination unit in an embodiment of the present invention;

[0032] Figure 5 This is a circuit diagram of the conversion unit according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the temperature control system according to an embodiment of the present invention;

[0034] Figure 7 This is a flowchart illustrating the protection circuit and its self-test method according to an embodiment of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0036] like Figure 1 As shown, this embodiment of the invention provides an experimental system for measuring the electrical characteristics of a device under irradiation conditions, including a triggering unit, an avalanche testing unit, a surge testing unit, a control signal processing unit, a self-test comparison unit, a judgment unit, and an irradiation protection unit.

[0037] The triggering unit is used to generate test signals and connect to the avalanche test unit and surge test unit through a unified test channel.

[0038] Specifically, the triggering unit uses three identical waveform generators, which are converted from analog to digital and then connected to the first channel of the avalanche test unit and the fifth channel of the surge test unit through the judgment unit and the conversion unit, respectively. When the main circuit in the triggering unit is determined to be working normally by the judgment unit, the trigger signal is transmitted to the avalanche test circuit or the surge test circuit through the first channel or the fifth channel, respectively.

[0039] The avalanche test unit is connected to the semiconductor device under test (DUT) through the avalanche test channel, outputs the avalanche test signal, and displays the test data of the DUT.

[0040] Specifically, the avalanche test unit includes a power supply, an oscilloscope, a Hall current sensor, a transformer, and an avalanche test circuit. The avalanche test circuit includes a protection circuit, a test circuit, and a control circuit. The avalanche test channels include a first channel, a second channel, a third channel, and a fourth channel. The avalanche test unit is connected to a trigger module via the first channel, to the gate (G) terminal of the semiconductor device under test (DUT) via the second channel, to the drain (D) terminal of the DUT via the third channel, and to the source (S) terminal of the DUT, which is also grounded, via the fourth channel. The G and S terminals of the DUT are also connected to the oscilloscope. The D and S terminals of the DUT are connected to the oscilloscope via the transformer, and the leads from either the D or S terminal of the DUT are connected to the Hall current sensor. The protection circuit can perform a self-test before testing, and the control circuit transmits the self-test signal to the self-test comparison unit.

[0041] The protection circuit includes avalanche diodes D21 and D22 and a MOS switch connected in parallel with them. D21 and D22 are selected as diodes with high critical avalanche voltages, which should be higher than the expected critical avalanche voltage of the chip under test. The protection circuit is connected in parallel with the device under test. In this embodiment, the redundancy of the protection circuit can be further increased or decreased.

[0042] When performing an avalanche test on the device under test (DUT), one channel of the oscilloscope is connected to the G and S terminals of the DUT, and the second channel is connected to the D and S terminals of the DUT via a transformer. A current sensor is connected to either the D or S terminal of the DUT. The gate-source voltage V of the DUT is then displayed. gs Drain-source voltage V ds Drain current I ds The curve. During self-test, the connection between the device under test (DUT) and the test unit is disconnected. During self-test and formal testing, an oscilloscope is connected to both ends of the avalanche diode in the protection circuit to acquire the voltage signal flowing through the avalanche diode. A current sensor is used to acquire the current signal flowing through the avalanche diode.

[0043] During the self-test of the test unit, the control signal generator first controls all three MOSFET switches shown in the diagram to turn on. At this time, the inductor L... surgeThe circuit is directly connected for charging. After a period of time, all three MOSFET switches in the control diagram are turned off. At this time, the inductor, diode D1, and avalanche diodes D21 and D22 form a circuit, and the energy stored in the inductor is released through avalanche diodes D21 and D22. The magnitude of the avalanche energy can be controlled by controlling the on-time of the three MOSFET switches. The voltage and current signals of D21 and D22 at this time represent the avalanche characteristics. If one of the avalanche diodes fails, the avalanche energy can still be released through the other avalanche diode without damaging other parts of the circuit. The measured avalanche characteristic information of D21 and D22 is sent to the self-test comparison unit for comparison with the known characteristics of D21 and D22 to determine whether the test circuit and protection circuit are working properly. If not, this avalanche test unit is marked as damaged, and the judgment unit will later select an undamaged unit for testing the device under test.

[0044] When testing the device under test (DUT), the MOSFET switch in the protection circuit is off. The control signal generator first controls the MOSFET switch connected in series with the power supply and the DUT to turn on, as shown in the diagram. At this time, the inductor L... surge The circuit is directly connected for charging. After a period of time, the MOSFET switch and the device under test (DUT) are turned off. At this point, the inductor, diode D1, and DUT form a circuit, and the energy stored in the inductor is released through the DUT. The magnitude of the avalanche energy can be controlled by adjusting the on-time of the MOSFET switch. Measuring the voltage and current signals of the DUT at this point gives the avalanche characteristic. Similarly, if the DUT fails, diode D1, avalanche diodes D21 and D22 can still form a circuit, and the avalanche energy can be released through the protection circuit without damaging other parts of the circuit.

[0045] The surge test unit connects to the semiconductor device under test through the surge test channel, outputs surge test signals, and displays the device's test data.

[0046] Specifically, such as Figure 3 As shown, the surge test unit includes a power supply, an oscilloscope, and a surge test circuit. The surge test channels include the fifth, sixth, seventh, and eighth channels. A Hall current sensor measures the current between the drain (D) and source (S) terminals of the semiconductor device under test.

[0047] The surge test unit includes a power supply, an oscilloscope, and surge test circuitry. The surge test channels include the fifth, sixth, seventh, and eighth channels. A Hall current sensor measures the current between the drain (D) and source (S) terminals of the semiconductor device under test.

[0048] When performing surge testing on the device under test (DUT), one channel of the oscilloscope is connected to the drain (D) and source (S) terminals of the DUT, and the current sensor is connected to either the D or S terminal of the DUT. The surge voltage (V) of the DUT is then displayed. dsI ds Curve. During self-test, the connection between the device under test (DUT) and the test unit is disconnected. During self-test and formal testing, an oscilloscope is connected to both ends of the diode in the protection circuit to acquire the voltage signal flowing through the avalanche diode. A current sensor is used to acquire the current signal flowing through the avalanche diode.

[0049] During the self-test of the test unit, the control signal generator turns on the two MOSFET switches shown in the diagram. At this time, the diode in the self-test circuit and the capacitor and inductor in the test circuit form an oscillating circuit, generating a sinusoidal voltage. The voltage and current signals of the diode at this time are the surge characteristics. The measured surge characteristic information is sent to the self-test comparison unit for comparison with the known characteristics of the diode to determine whether the test circuit is working properly. If it is not normal, this surge test unit is marked as damaged, and the judgment unit will select an undamaged unit to test the device under test later.

[0050] When testing the device under test (DUT), the MOSFET switch in the self-test circuit is turned off. The control signal generator turns on the DUT, and the capacitors and inductors in the test circuit form an oscillating circuit, generating a sinusoidal voltage. Measuring the voltage and current signals of the DUT at this time provides the surge characteristics.

[0051] In this embodiment, before testing, a self-test of the test circuit is performed. The channel of the chip under test is closed, and the control circuit turns on the MOS switch connected in series with D11 and D12. At this time, it is equivalent to performing an avalanche test on D11 and D12 and extracting the corresponding test parameters. If the test cannot be completed, or the test parameters are significantly different from the known parameters of D11 and D12, it indicates that the MOS switch is damaged, or D11 and D12 are damaged and cannot play the role of protecting the circuit. At this time, the control signal generation module sends a signal that the test module cannot work properly.

[0052] Since the critical avalanche voltage of the avalanche diode in the protection circuit is higher than the avalanche voltage of the device under test, no current will flow through the protection circuit during normal testing, so it has no effect on the chip under test.

[0053] If the chip under test (DUT) suddenly becomes open-circuited during the test, the avalanche energy can be released through D11 or D12. Similarly, if D11 or D12 is damaged during the aforementioned self-test, the avalanche energy can be released through another undamaged component, thus protecting the power supply. At this time, by extracting the current information of the protection circuit, if current flows through the protection circuit, it indicates that the DUT has become open-circuited.

[0054] The self-test comparison unit is used to receive the output signals of the avalanche test unit and the surge test unit and perform self-test to determine whether the protection circuit is working properly, and transmit the self-test results to the control signal processing unit.

[0055] The control signal processing unit controls the working status of the avalanche test unit and the surge test unit to ensure that the avalanche test channel and the surge test channel are not activated at the same time, and generates a conversion signal to switch the test lines.

[0056] Specifically, the control signal processing unit includes a signal generator, an FPGA, and a Bluetooth module. One channel of the signal generator is used to control the on / off state of the first and fifth channels, and a second channel of the signal generator is used to control the second, third, or fourth channel, and the sixth, seventh, and eighth channels. The control signal processing unit can control the first channel to be on while simultaneously controlling the fifth channel to be off, and vice versa. The control signal processing unit can also control the second, third, and fourth channels to be on or off simultaneously, and simultaneously control the sixth, seventh, and eighth channels to be on or off simultaneously. It includes four test modes: when the first channel is on, the fifth channel is off, the second, third, and fourth channels are off, and the sixth, seventh, and eighth channels are on. When the avalanche test circuit self-test is performed, and when the first channel is on, the fifth channel is off, and the second, third, and fourth channels are on while the sixth, seventh, and eighth channels are off, an avalanche test is performed. When the first channel is off, the fifth channel is on, and the second, third, and fourth channels are off while the sixth, seventh, and eighth channels are on, a surge test is performed. When the first channel is off, the fifth channel is on, and the second, third, and fourth channels are on while the sixth, seventh, and eighth channels are off, a surge test circuit self-test is performed. The three channels of the signal generator are controlled by programming the FPGA, allowing it to make a comprehensive judgment based on the signals generated by the self-test comparison unit and the judgment unit, generating a conversion signal and switching the main test line to the normal operating line. In this embodiment, the first, second, third, or fourth channel may include MEMS switches and inverters; the fifth, sixth, seventh, and eighth channels may include MEMS switches.

[0057] During the self-test operation of the avalanche or surge test unit, if the output of one of the three identical avalanche or surge test circuits is different from the other two, a conversion signal is generated and the conversion circuit is controlled to switch the test line.

[0058] The judgment unit is used to compare the output signals of the avalanche test circuit and the surge test circuit, identify abnormal signals, and drive a red LED light to alert the operator.

[0059] Specifically, such as Figure 4As shown, the determination unit includes a NAND gate, an XOR gate, an SR latch, and a red LED. These are connected to the output terminals of three identical avalanche test circuits and three identical surge test circuits, respectively. The unit compares the three inputs, outputs the majority of the input signals, identifies the possible input terminals that are different from the other two, and lights up the corresponding red LED.

[0060] The decision unit mainly consists of the following parts:

[0061] 1. NAND Gate: NAND gates can be used to eliminate redundant signals, simplify subsequent logic judgments, and ensure that a low level is output only when all signals are the same.

[0062] 2. XOR Gate: The XOR gate is used to detect the difference between three sets of input signals.

[0063] 3. The SR latch is used to maintain the current comparison state, ensuring that the output state remains unchanged until the next valid input signal arrives.

[0064] 4. Red LED light: The red LED light is used as a visual indicator. When a difference in the input signal is detected, the LED light will light up, making it easy for operators to quickly understand the system status.

[0065] In this embodiment, the avalanche or surge test circuit can be configured as several circuits. We will describe three circuits for each circuit. The outputs of these three circuits are denoted as S1, S2, and S3. Each circuit output is connected to the input of a NAND gate. The specific connection method is as follows:

[0066] The first NAND gate: S1 and S2;

[0067] The second NAND gate: S2 and S3;

[0068] The third NAND gate: S1 and S3;

[0069] The outputs of three NAND gates are connected to a single NAND gate. The second-stage NAND gate is then used to synthesize and evaluate the output of the first-stage NAND gate to determine if there are any differences in the input signals.

[0070] Let the output of the second-stage NAND gate be W. Connect the output of the second-stage NAND gate to the inputs of the three XOR gates respectively, as follows:

[0071] The first XOR gate: S1 AND W;

[0072] The second XOR gate: S2 AND W;

[0073] The third XOR gate: S3 and W;

[0074] Connect the output of the XOR gate to the S terminal of the SR latch, while the R terminal can be connected to a reset signal, such as a button or timer, for manual or automatic reset of the latch state.

[0075] Connect the output Q of the SR latch to the anode of the red LED, with the cathode grounded. When Q is high, the LED lights up; otherwise, it turns off.

[0076] The system receives outputs from three avalanche test circuits and three surge test circuits. These output signals are converted into corresponding digital signals after analog-to-digital conversion. When the XOR gate output is high, the S terminal of the SR latch is activated, and the latch output Q will be high (1), thus lighting up the red LED. When the XOR gate output is low, the R terminal of the latch can be triggered, Q will be reset to low (0), and the LED will turn off.

[0077] Consider the following signal states:

[0078] 1. S1 = 0, S2 = 1, S3 = 1. The first NAND gate outputs 1, the second NAND gate outputs 1, then the XOR gate connected to S1 outputs a high level, the red LED lights up, indicating that S1 is different from the other two inputs, and the other two LEDs are off.

[0079] 2. When S1 = 1, S2 = 1, and S3 = 1, the output of the second-stage NAND gate is 1, then the output of all XOR gates is low, and all LEDs are off.

[0080] 3. When S1 = 1, S2 = 0, and S3 = 0, the output of the second-stage NAND gate is 0. Then, the XOR gate connected to S1 outputs a high level, and the red LED lights up, indicating that S1 is different from the other two inputs. The other two LEDs turn off.

[0081] 4. When S1 = 0, S2 = 0, and S3 = 0, the output of the second-stage NAND gate is 0. Therefore, the output of all XOR gates is low, and all LEDs are turned off.

[0082] The above describes how, during line switching, the process involves... Figure 5 The conversion module shown performs line switching. The conversion module includes MOSFETs and diodes. When the backup line detects the conversion signal, it switches to the main line, and the other two lines are turned off and become backup.

[0083] The radiation protection unit encases all the above units in a radiation-resistant material and is exposed to the radiation environment.

[0084] Specifically, the protective material of the irradiation protection unit should be selected according to the specific environment and requirements, and the thickness should be determined according to I = I0 × e. -μεThe formula is used for calculation; where I represents the radiation intensity through the protective layer; I0 represents the radiation source intensity; μ represents the linear attenuation coefficient of the material; and ε represents the thickness of the protective layer.

[0085] The present invention also provides a temperature control system such as Figure 6 As shown, it includes a power supply, a microcontroller, a driver module, a step-down module, a temperature sensing module, a heating element, and a cooling element. The power supply is connected to the driver module, and the power supply is connected to the microcontroller via the step-down module to power the microcontroller. The temperature sensing module is connected to the microcontroller and is used to collect temperature and output a trigger signal. The microcontroller is also connected to the heating element and the cooling element respectively. After comparing the collected temperature with the preset temperature, the microcontroller controls the heating element or the cooling element to work to adjust the ambient temperature to the preset temperature.

[0086] Based on the above system, this invention provides a protection circuit and a self-testing method for measuring the electrical characteristics of devices under irradiation conditions, such as... Figure 7 As shown, the methods and steps include:

[0087] S1: Establishes communication between the test personnel, the remote computer, and the control signal processing unit via a remote connection.

[0088] S2: The tester selects either avalanche or surge test and controls the opening and closing of the corresponding channels for avalanche and surge through the control signal processing unit.

[0089] S3: The system performs a self-test on the avalanche or surge test circuit, detects the avalanche characteristics of the avalanche diode in the avalanche protection circuit or the surge characteristics of the diode in the self-test circuit of the surge test circuit, and sends the results to the self-test comparison unit. By comparing with the avalanche and surge characteristics of known devices, it determines whether the test system and protection circuit are damaged.

[0090] S4: Transmit the self-test results to the control signal processing unit. Then, the tester can view the self-test results on a remote computer and select the test circuit that is working properly. The device under test can be connected to the test circuit remotely through the control signal processing unit to perform avalanche or surge tests.

[0091] S5: During avalanche testing, the current flowing through the protection circuit of the avalanche test circuit is detected, and the result is sent to the self-test comparison unit. The test device is then compared with a preset threshold to determine whether it is damaged.

[0092] S6: Transmit the self-test results to the control signal processing unit. Then, the tester can view the self-test results through a remote computer. If there is a protection current, it means that the device under test is damaged. Because there is a protection circuit, the overall test system is not damaged. If there is no protection current, it means that the device under test is working normally. At this time, save and record the avalanche or surge test data.

[0093] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; only preferred embodiments of the present invention are illustrated. The descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. As long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0094] It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of this invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An experimental system for measuring the electrical properties of a device under irradiation conditions, characterized in that: It includes a triggering unit, an avalanche testing unit, a surge testing unit, a control signal processing unit, a self-test comparison unit, a judgment unit, and an irradiation protection unit; The triggering unit is used to generate test signals and connect to the avalanche test unit and the surge test unit through a unified test channel; The avalanche test unit is connected to the semiconductor device under test through the avalanche test channel, outputs the avalanche test signal and displays the test data of the semiconductor device under test; The surge test unit is connected to the semiconductor device under test through a surge test channel, outputs a surge test signal, and displays the test data of the device; The control signal processing unit controls the working status of the avalanche test unit and the surge test unit to ensure that the avalanche test channel and the surge test channel are not activated at the same time, and generates a conversion signal to switch the test line. The self-test comparison unit is used to receive the output signals of the avalanche test unit and the surge test unit and perform self-test to determine whether the protection circuit is working properly, and transmit the self-test result to the control signal processing unit. The determination unit is used to compare the output signals of the avalanche test circuit and the surge test circuit, identify abnormal signals, and drive a red LED light to alert the operator. The radiation protection unit is constructed by encasing all the aforementioned units in a radiation-resistant material and exposing them to the radiation environment.

2. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 1, characterized in that: The avalanche test unit includes a power supply, an oscilloscope, and an avalanche test circuit. The avalanche test circuit is connected to the trigger unit through a first channel, and connected to the G terminal, D terminal, and S terminal of the semiconductor device under test through a second channel, a third channel, and a fourth channel, respectively. The first channel is used to trigger the avalanche test signal, and the second, third, and fourth channels are used to input the test signal to the device under test.

3. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 2, characterized in that: The avalanche test circuit includes a protection circuit, a control circuit, and a test circuit. The protection circuit is used to protect the device under test from high current damage, the control circuit is used to send a self-test signal and transmit the self-test result to the self-test comparison unit, and the test circuit performs the avalanche test operation.

4. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 3, characterized in that: The surge test unit includes a power supply, an oscilloscope, and a surge test circuit. The surge test circuit is connected to the trigger unit through the fifth channel, and is connected to the G terminal, D terminal, and S terminal of the semiconductor device under test through the sixth, seventh, and eighth channels, respectively. The fifth channel is used to trigger the surge test signal, and the sixth, seventh, and eighth channels are used to input the test signal to the device under test.

5. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 4, characterized in that: The surge test circuit includes a protection circuit, a control circuit, and a test circuit. The protection circuit is used to protect the device under test from damage caused by excessive current. The control circuit is used to send a self-test signal and transmit the self-test result to the self-test comparison unit. The test circuit performs surge test operations.

6. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 5, characterized in that: The control signal processing unit includes a signal generator, an FPGA, and a Bluetooth module. The signal generator is used to control the switching of the test signal input channels of the avalanche test unit and the surge test unit, and to generate conversion signals to switch the test circuit.

7. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 6, characterized in that: The control signal processing unit controls the first channel of the avalanche test unit and the fifth channel of the surge test unit to turn on and off through one channel of the signal generator. The control signal processing unit controls the second to fourth channels and the sixth to eighth channels through two channels of the signal generator. The three channels of the signal generator are used to generate conversion signals to switch between the main test line and the backup test line.

8. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 1, characterized in that: The self-test comparison unit receives the output signals from the avalanche test unit and the surge test unit, and judges the self-test result of the protection circuit. If an abnormality is found in the protection circuit or other test circuits, a fault signal is output to the control signal processing unit, which then switches the test line or sends an alarm signal to the remote computer.

9. The experimental system for measuring the electrical characteristics of a device under irradiation conditions according to claim 7, characterized in that: The avalanche test unit is equipped with several avalanche test circuits, and the surge test unit is equipped with several surge test circuits. The determination unit includes NAND gates, XOR gates, and SR latches, which are respectively connected to the output terminals of the several avalanche test circuits and surge test circuits. They are used to compare the output signals and drive red LEDs to display abnormal output signals that are different from other signals.

10. The experimental system for measuring the electrical properties of a device under irradiation conditions according to claim 7, characterized in that: The first, second, third, and fourth channels include MEMS switches and inverters; the fifth, sixth, seventh, and eighth channels include MEMS switches.

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