A batch automated testing method and system for chip flip-chip interconnect connectivity

Abstract

This application discloses a batch automatic testing method and system for flip-chip interconnect connectivity. The method includes: calibrating and setting target adjustment parameters according to pre-set alignment and pin positions; sending a start signal to a control device, causing the control device to generate a test signal in response to the received start signal; iteratively executing the following steps until all candidate chips under test in the chip carrier have completed testing: receiving the test signal sent by the control device, the test signal including target chip under test information, the target chip under test being any one of the batch of candidate chips under test; according to a pre-generated automatic identification template, target chip under test information, and target adjustment parameters, moving the device until the readout circuit pad of the target chip under test contacts the probe on the probe card to obtain electrical connectivity test data of the target chip under test; and sending the test data to the control device. This method can significantly improve testing efficiency, save time and costs, and improve test consistency.

Description

Technical Field

[0001] This application belongs to the field of infrared detector technology, and in particular relates to a batch automatic testing method and system for the interconnection status of flip-chips. Background Technology

[0002] Third-generation focal plane infrared detectors are developing towards high integration, lightweight design, and low cost. The infrared focal plane chip, as the core component of the detector, mainly consists of an infrared focal plane array and readout circuitry. With the continuous expansion of pixel array size, flip-chip interconnect technology has become a key process technology in the manufacturing of infrared focal plane chips. To increase the yield of infrared focal plane chips, electrical testing can be introduced after the flip-chip interconnect process to quickly and accurately determine the interconnect connectivity, effectively identifying qualified chips suitable for assembly. Simultaneously, it allows for effective monitoring and feedback of problems in the flip-chip interconnect process, providing an effective detection method for the technical analysis of flip-chip interconnect process quality.

[0003] However, in the current process of testing the electrical connectivity of flip-chip interconnects of infrared focal plane array chips, a large number of chips are individually aligned with the corresponding pads on the chip readout circuit by human eye, and physical contact is achieved by manually inserting the probes. This will undoubtedly increase the probability of chip damage, result in poor test consistency, and reduce test efficiency, failing to meet the needs of high-efficiency testing of large batches of chips. Summary of the Invention

[0004] This application provides a batch automatic testing method and system for the interconnect connectivity of flip-chip chips, which at least solves the problems of poor test consistency and low test efficiency in related technologies, and cannot meet the needs of efficient testing of large batches of chips.

[0005] In a first aspect, embodiments of this application provide a batch automatic testing method for the connectivity of flip-chip interconnects, applied to a probe station. The probe station is a four-axis motion mechanism. The probe station includes a chip carrier, which includes several position slots. A batch of candidate chips of the same type are fixed in each position slot. The candidate chips correspond one-to-one with the position slots. The candidate chips are infrared focal plane array chips after the flip-chip interconnect process has been completed.

[0006] The method includes:

[0007] The target adjustment parameters are calibrated and set according to the preset alignment and needle insertion positions;

[0008] A start signal is sent to the control device, so that the control device generates a test signal in response to receiving the start signal;

[0009] The following steps are performed iteratively until all candidate chips under test within the chip carrier have completed testing:

[0010] The system receives a test signal sent by the control device, the test signal including information about the target chip under test, the target chip under test being any one of the batch of candidate chips under test;

[0011] Based on the pre-generated automatic identification template, target chip information, and target adjustment parameters, the probe card moves to contact the readout circuit pad of the target chip and the probe on the probe card to obtain the electrical connectivity test data of the target chip. The probe card is set above the probe station and the type of the probe card is matched with the candidate chip.

[0012] The test data is sent to the control device.

[0013] Secondly, embodiments of this application provide a batch automated testing system for the interconnect connectivity of flip-chip chips, comprising:

[0014] The probe station is a four-axis motion mechanism, including a chip carrier. The chip carrier includes several position slots. A batch of candidate chips of the same type are fixed in each position slot. The candidate chips correspond one-to-one with the position slots. The candidate chips are infrared focal plane chips after the flip-chip interconnect process has been completed.

[0015] A probe card is disposed above the probe station. The probe card is matched with the type of the candidate chip to be tested, and probes are provided on the probe card.

[0016] Control device;

[0017] A signal processing interface board is connected to the probe card and the control device, respectively.

[0018] The probe station is used for: calibrating and setting target adjustment parameters according to a pre-set alignment position and pin insertion position; sending a start signal to a control device so that the control device generates a test signal in response to receiving the start signal; iteratively executing the following steps until all candidate chips under test in the chip carrier have completed testing: receiving a test signal sent by the control device, the test signal including target chip under test information, the target chip under test being any one of the batch of candidate chips under test; moving to contact the probe on the probe card with the readout circuit pad of the target chip under test according to a pre-generated automatic identification template, target chip under test information, and target adjustment parameters to obtain electrical connectivity test data of the target chip under test; and sending the test data to the control device.

[0019] The batch automatic testing method and system for flip-chip interconnect connectivity of this application embodiment, based on a pre-generated automatic identification template and adjustment parameters, controls a probe station through a control device to perform testing, automatically aligning the chip position, making contact between the probe and the chip, and outputting the chip's test data; after the current chip completes the test, the control device sends a signal to the probe station, and the probe station moves to automatically align and make contact with the probe for the next chip, thereby iteratively realizing batch automatic testing until all the chips under test in the chip carrier have been tested, greatly improving testing efficiency and increasing yield; and it can effectively avoid manually making physical contact between the probe and the chip readout circuit one by one, reducing the probability of chip damage, and ensuring good test consistency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of an exemplary chip carrier provided in an embodiment of this application;

[0022] Figure 2 This is a flowchart illustrating a batch automatic testing method for chip flip-chip interconnect connectivity provided in an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the contact between the chip under test and the probe provided in an embodiment of this application;

[0024] Figure 4 This is an exemplary grayscale image of a target chip under test provided in an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of the structure of a batch automatic testing system for the interconnect connectivity of flip-chip chips, provided in an embodiment of this application. Detailed Implementation

[0026] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0027] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0028] Third-generation focal plane infrared detectors are developing towards high integration, lightweight design, and low cost. The infrared focal plane chip, as the core component of the detector, mainly consists of an infrared focal plane array and readout circuitry. With the continuous expansion of pixel array size, flip-chip interconnect technology has become a key process technology in the manufacturing of infrared focal plane chips. To increase the yield of infrared focal plane chips, electrical testing can be introduced after the flip-chip interconnect process to quickly and accurately determine the interconnect connectivity, effectively identifying qualified chips suitable for assembly. Simultaneously, it allows for effective monitoring and feedback of problems in the flip-chip interconnect process, providing an effective detection method for the technical analysis of flip-chip interconnect process quality.

[0029] However, in the current process of testing the electrical connectivity of flip-chip interconnects of infrared focal plane array chips, a large number of chips are individually aligned with the corresponding pads on the chip readout circuit by human eye, and physical contact is achieved by manually inserting the probes. This will undoubtedly increase the probability of chip damage, result in poor test consistency, and reduce test efficiency, failing to meet the needs of high-efficiency testing of large batches of chips.

[0030] To address the problems in the related technologies, this application provides a batch automatic testing method and system for the interconnect connectivity of flip-chip chips.

[0031] The following description, in conjunction with the accompanying drawings, details the batch automatic testing method for chip flip-chip interconnect connectivity provided in this application through specific embodiments and application scenarios.

[0032] It should be noted that, in the embodiments of this application, the chips used for batch automatic testing are infrared focal plane array chips that have completed the flip-chip interconnect process, and they are all chips of the same type. In the following description, they are simply referred to as candidate chips to be tested.

[0033] It should be noted that the batch automatic testing method for chip flip-chip interconnect connectivity in this application embodiment is applied to a probe station.

[0034] Optionally, the probe stage is a four-axis motion mechanism. That is, the probe stage includes a first moving stage corresponding to the horizontal plane (XY plane) formed by the first direction axis (X-axis) and the second direction axis (Y-axis), a second moving stage corresponding to the third direction axis (Z-axis), and a third moving stage corresponding to the θ-axis. The first direction axis (X-axis), the second direction axis (Y-axis), and the third direction axis (Z-axis) are perpendicular to each other. Specifically, the direction of the third direction axis (Z-axis) is consistent with the vertical direction, and the third direction axis (Z-axis) is perpendicular to the horizontal plane (XY plane). The first direction axis (X-axis) and the second direction axis (Y-axis) intersect, and both intersect with the vertical direction.

[0035] Optionally, the probe station may include a chip carrier.

[0036] refer to Figure 1 This is a schematic diagram of an exemplary chip carrier according to an embodiment of this application. Figure 1 As shown, the chip carrier includes several position slots ( Figure 1 The chip carrier is a 6×4 array, and batches of identical candidate chips to be tested are fixed in their respective slots, with each candidate chip to be tested corresponding to a slot. It is understood that the fixture is detachable, and the chip carrier can also be replaced with 2×6, 4×3, etc., but this embodiment does not specifically limit this.

[0037] Optionally, a probe card is provided above the probe station, and the probe card matches the type of the candidate chip to be tested. Taking the 640×512 area array infrared focal plane chip of mercury cadmium telluride provided in this embodiment as an example, it has the corresponding circuit of the chip, and the probe card is designed according to the circuit. It should be noted that the types of chip and probe card can be replaced accordingly according to the actual use, and this embodiment does not specifically limit this.

[0038] Based on the probe station Figure 2 A flowchart illustrating an embodiment of this application shows a batch automated testing method for chip flip-chip interconnect connectivity. Figure 2 As shown, the batch automated testing method for the flip-chip interconnect connectivity of this chip may specifically include the following steps:

[0039] S201. Based on the preset alignment position and needle insertion position, calibrate and set the target adjustment parameters;

[0040] S202. Send a start signal to the control device so that the control device generates a test signal in response to receiving the start signal;

[0041] S203. Iteratively execute the following steps until all candidate chips under test within the chip carrier have completed testing:

[0042] The system receives a test signal sent by the control device, the test signal including information about the target chip under test, the target chip under test being any one of the batch of candidate chips under test;

[0043] Based on the pre-generated automatic identification template, target chip information, and target adjustment parameters, the probe card moves to contact the readout circuit pad of the target chip and the probe on the probe card to obtain the electrical connectivity test data of the target chip. The probe card is set above the probe station and the type of the probe card is matched with the candidate chip.

[0044] The test data is sent to the control device.

[0045] Therefore, based on pre-generated automatic identification templates and adjustment parameters, the probe station is controlled by a control device to perform testing, automatically aligning the chip and making contact between the probe and the chip, and outputting the chip's test data. After the current chip completes the test, the control device sends a signal to the probe station, which then moves to automatically align and make contact with the probe for the next chip, thus iteratively achieving batch automatic testing until all the chips under test in the chip carrier have been tested, significantly improving testing efficiency and increasing yield. Furthermore, it effectively avoids manually making physical contact between the probe and the chip readout circuit one by one, reducing the probability of chip damage and ensuring good test consistency.

[0046] The specific implementation methods for each of the above steps are described below.

[0047] As an optional embodiment, such as Figure 1 As shown, each position slot is equipped with a vacuum adsorption hole. Additionally, a vacuum pump is located below the probe station. Therefore, before S201, a batch of similar candidate chips can be picked up using a suction pen and placed into each position slot, ensuring the candidate chips cover the vacuum adsorption holes. The vacuum pump is then operated to use pressure to adsorb and fix the candidate chips in the position slots. This ensures that a batch of candidate chips are firmly adsorbed in their respective position slots.

[0048] In some embodiments, in S201, the real-time position information of the probe station is determined by the detection device; the first movable stage is adjusted according to the real-time position information so that the position of at least one candidate chip under test conforms to a preset alignment position, and the second and third movable stages are adjusted so that the position of at least one candidate chip under test conforms to the needle insertion position; and when the alignment position and needle insertion position are conformed, a target adjustment parameter is determined.

[0049] In addition, in some embodiments, the first size information of the candidate chip to be tested and the second size information of the chip carrier can be determined by a detection device; an automatic identification template is generated based on the first size information, the second size information and the array information of the chip carrier, wherein the array information of the chip carrier includes the number of rows and columns of a plurality of position slots in the chip carrier.

[0050] Optionally, the detection device may be positioned above the probe card, including a microscope or a recognition camera.

[0051] In practice, the chip is moved to the alignment position by observing with a camera and operating a semi-automatic probe station placed on the chip carrier. The height of the probe station in the Z-axis direction is adjusted to complete the chip positioning. The number of rows / columns of the chip carrier is set according to the carrier used to create a template for automatic chip identification. The chip size X / Y parameter measurement and setting and the chip carrier X / Y parameter measurement and setting are completed by the identification camera, that is, the first size information and the second size information are determined.

[0052] In practice, the alignment position is set, which is the position of the first chip to be measured; the pin position is set, which is the corresponding contact position between the probe and the readout circuit pad; the probe stage is observed and raised through a microscope, and the probe stage is precisely aligned and contacted with the chip readout circuit pad by adjusting the θ axis of the probe stage; then the contact height parameter is fixed, which is the target adjustment parameter.

[0053] refer to Figure 3 This is a schematic diagram showing the contact between the chip under test and the probe. For example... Figure 3 As shown, the probe card has probes corresponding to the positions of the chip readout circuit pads. Moving the probe station ensures precise alignment and contact between the probes and the chip readout circuit pads. Otherwise, inaccurate contact will affect the accuracy of the test.

[0054] In this way, by aligning a candidate chip to be tested, the target adjustment parameters are determined and an automatic identification template is established, so that other chips can be automatically identified, aligned, and needled.

[0055] In some embodiments, in S202, the probe station sends a start signal to the control module of the control device to initiate testing. The control device's test software platform then generates a test signal and sends it to the probe station. Subsequently, the test software platform controls the probe station to begin testing, i.e., S203 is executed.

[0056] In some embodiments, in S203, the testing can be performed in the order of the arrangement positions of the chips, or not in order. For example, if it is found that the chip corresponding to the position slot in the second column of the first row in the chip carrier may have a test anomaly caused by an operation error, the testing can jump back to this abnormal chip for retesting after the current tested chip has completed the test. That is to say, the target chip to be tested information included in the test signal sent by the control device can be the position information (i.e., which row and which column) corresponding to any one of the batch of alternative chips to be tested.

[0057] During specific implementation, if the testing is performed in the order of the arrangement positions of the chips, taking Figure 1 the 6×4 array chip carrier used as an example, then according to the pre-generated automatic recognition template, during the automatic movement of the probe station, six chips in a corresponding row are sequentially moved horizontally, and then moved to the next row for automatic recognition.

[0058] During specific implementation, according to the pre-generated automatic recognition template, the target chip to be tested information, and the target adjustment parameters, the distance to be moved in each direction can be determined each time, that is, the adjustment information corresponding to the first moving workbench, the second moving workbench, and the third moving workbench each time.

[0059] During specific implementation, the control module of the control device provides a bias voltage and a working pulse for the chip to be tested. Specifically, a voltage is applied to the chip to be tested through the signal processing interface board; the output (i.e., test data) of the chip to be tested after applying the voltage is transmitted to the control device through the signal processing interface board.

[0060] Further, in some embodiments, after S203, the control device can perform imaging display according to the test data to obtain the imaging grayscale map corresponding to the target chip to be tested; according to the imaging grayscale map, it is determined whether the target chip to be tested is a qualified chip suitable for assembly and use.

[0061] Refer to Figure 4 , which is an exemplary imaging grayscale map of the test result of a target chip to be tested. As Figure 4 shown, the marked circles represent the unqualified areas, so that it can be determined whether the target chip to be tested is qualified according to the number and size of the unqualified areas. Thus, based on the judgment result, the chips are taken out for subsequent process treatment.

[0062] In another embodiment, another batch automatic testing method for the flip-chip interconnection and connection situation of chips is provided. Specifically, this another batch automatic testing method for the flip-chip interconnection and connection situation of chips includes the following steps.

[0063] After the infrared focal plane array chip completes the flip-chip interconnect process, batches of identical test chips are picked up using a suction pen and fixed in the chip carrier's positioning slots. A vacuum pump is run to firmly attach the chips to the slots. Probe cards corresponding to the chip type are fixed above the probe station and connected to the signal processing interface board. Through camera observation, the semi-automatic probe station is operated to move the chips placed on the probe station carrier to the alignment position. The Z-axis height of the sample stage is adjusted to complete the chip positioning. The number of rows / columns of the chip carrier is set according to the carrier used, creating a template for automatic chip identification. Then, the X / Y parameters of the chip size and the X / Y parameters of the chip carrier are measured and set using the identification camera. The alignment position is set, i.e., the position of the first chip to be measured. The probe placement position is set, i.e., the contact position between the probe and the readout circuit pad. The probe station is observed under a microscope and raised, and the θ-axis of the probe station is adjusted to achieve precise alignment and contact between the probe and the chip readout circuit pad. The contact height parameters are then fixed.

[0064] Next, the probe station and control device are connected via serial port. The probe station sends a start signal to the control module of the control device to begin testing. The test software platform in the control device controls the probe station to start testing, automatically aligning the chip and making contact with the chip. The data acquisition module outputs the chip data, which is then imaged and displayed by the software. After the current chip is tested, the control device sends a signal to the probe station to separate the probe from the chip, and then moves to the next chip position to automatically align and make contact with the probe. This process is repeated to achieve batch automatic testing until all the chips under test in the carrier have been tested. After the batch testing is completed, the chip's qualification is determined based on the test result image, and the chip is removed for subsequent processing.

[0065] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0066] Based on the same technical concept, corresponding to any of the above embodiments, this application also provides a batch automatic testing system for the interconnect connectivity of flip-chip chips.

[0067] like Figure 5 As shown, the batch automated test system for the flip-chip interconnect connectivity includes: a probe station, a probe card, a control device, and a signal processing interface board.

[0068] In some embodiments, the probe station is a four-axis motion mechanism, including a chip carrier, the chip carrier including a plurality of position slots, a batch of candidate chips of the same type are fixed in each position slot, the candidate chips correspond one-to-one with the position slots, and the candidate chips are infrared focal plane chips after flip-chip interconnection process.

[0069] In some embodiments, a probe card is disposed above the probe station, the probe card being matched to the type of the alternative chip to be tested, and the probe card being provided with probes.

[0070] In some embodiments, the signal processing interface board is connected to both the probe card and the control device.

[0071] Specifically, the probe station is used for: calibrating and setting target adjustment parameters according to a pre-set alignment position and pin insertion position; sending a start signal to the control device so that the control device generates a test signal in response to receiving the start signal; iteratively executing the following steps until all candidate chips under test in the chip carrier have completed testing: receiving the test signal sent by the control device, the test signal including target chip under test information, the target chip under test being any one of the batch of candidate chips under test; moving to contact the probe on the probe card with the readout circuit pad of the target chip under test according to the pre-generated automatic identification template, the target chip under test information, and the target adjustment parameters, to obtain the electrical connectivity test data of the target chip under test; and sending the test data to the control device.

[0072] In some optional embodiments, the control device includes a control module, a host chassis, a processor board, a display, and a test software platform. The control module provides bias voltage and operating pulses to the candidate chip under test; the test software platform controls the automatic testing progress of the probe station, for example, but not limited to, controlling the automatic testing progress of the probe station by sending commands.

[0073] Optionally, the control device uses a data acquisition card to convert the received analog signals output by the chip into digital signals for processing and display.

[0074] In some optional embodiments, the batch automated testing system for chip flip-chip interconnect connectivity further includes a detection device disposed above the probe card. Specifically, the detection device is used to determine the real-time position information of the probe station; determine the first dimension information of the candidate chip under test and the second dimension information of the chip carrier.

[0075] Optionally, the detection device includes a microscope or a recognition camera.

[0076] In another embodiment, the probe station consists of X, Y, Z, and θ stages, a microscope, a recognition camera, and other auxiliary mechanisms to form a basic four-axis motion mechanism that can automatically move the chip placed on the probe station to the alignment position and probe card position, and control the probe to make precise contact with the chip readout circuit.

[0077] Optional, a multi-chip carrier (which can be replaced according to actual usage requirements) is provided on the chip carrier, which is equipped with a position slot and a vacuum suction hole.

[0078] Optional, probe card (the type of probe card can be changed according to actual usage requirements), the probe card is equipped with probes corresponding to the positions of the chip readout circuit pads.

[0079] Optionally, one end of the probe card is used to contact the chip readout circuit pads, while the other end is connected to the signal processing interface board.

[0080] Therefore, the batch automatic testing system for flip-chip interconnect connectivity of the present application embodiment can realize batch automatic testing of flip-chip interconnect connectivity of infrared focal plane array chips, and has high accuracy, simple operation and good test consistency.

[0081] In other words, the batch automated testing system for flip-chip interconnect connectivity can solve the following problems in related technologies: Currently, the electrical connectivity testing process after the completion of the flip-chip interconnect process for infrared focal plane array chips involves manually aligning probes with corresponding pads on the chip readout circuit and manually inserting probes to achieve physical contact, increasing the probability of chip damage; the degree of contact between the probes and the chip readout circuit pads is manually controlled, resulting in poor test consistency; and the testing efficiency for large batches of similar chips is low. Therefore, using this batch automated testing system for flip-chip interconnect connectivity can significantly improve testing efficiency, save time and costs, and improve test consistency.

[0082] It should be noted that, for ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing this application, the functions of each module can be implemented in one or more software and / or hardware.

[0083] The apparatus described above is used to implement the batch automatic testing method for the interconnection status of chips in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0084] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0085] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0086] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0087] The aspects of this application have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0088] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for bulk automatic testing of flip-chip interconnect connectivity, comprising: The probe station is a four-axis motion mechanism, and the probe station comprises a chip carrier, wherein the chip carrier comprises a plurality of position slots, and a plurality of same type of candidate test chips are respectively fixed in the position slots, the candidate test chips correspond to the position slots one by one, and the candidate test chips are infrared focal plane chips after completion of flip-chip interconnection process; The method comprises: According to the pre-set alignment position and the needle position, the target adjustment parameter is calibrated and set; The control device is sent to the starting signal, so that the control device generates a test signal in response to receiving the starting signal; Iteratively execute the following steps until all candidate test chips in the chip carrier complete the test: Receive the test signal sent by the control device, the test signal includes target test chip information, and the target test chip is any one of the batch candidate test chips; According to the pre-generated automatic identification template, the target test chip information and the target adjustment parameter, the readout circuit pad of the target test chip is contacted with the probe on the probe card to obtain the electrical connection test data of the target test chip, the probe card is arranged above the probe station, and the probe card is matched with the type of the candidate test chip; The test data is sent to the control device; The probe station comprises a first moving workbench corresponding to a horizontal plane formed by a first direction shaft and a second direction shaft, a second moving workbench corresponding to a third direction shaft, and a third moving workbench corresponding to a theta shaft, and the first direction shaft, the second direction shaft and the third direction shaft are perpendicular to each other; According to the pre-set alignment position and the needle position, the target adjustment parameter is calibrated and set, comprising: The real-time position information of the probe station is determined by the detection device; According to the real-time position information, the first moving workbench is adjusted so that the position of at least one candidate test chip conforms to the pre-set alignment position, and the second moving workbench and the third moving workbench are adjusted so that the position of at least one candidate test chip conforms to the needle position; The target adjustment parameter is determined when the alignment position and the needle position are met; After the target adjustment parameter is calibrated and set according to the pre-set alignment position and the needle position, before the starting signal is sent to the control device, the method further comprises: The first size information of the candidate test chip and the second size information of the chip carrier are determined by the detection device; According to the first size information, the second size information and the array information of the chip carrier, an automatic identification template is generated, and the array information of the chip carrier comprises the number of rows and columns of the plurality of position slots arranged in the chip carrier; After the test data is sent to the control device, the method further comprises: An imaging gray scale diagram corresponding to the target test chip is obtained by imaging display of the control device according to the test data; According to the imaging gray scale diagram, it is judged whether the target test chip is a qualified chip suitable for assembly and use.

2. The method of claim 1, wherein, A vacuum pump is arranged below the probe station, and each position slot is provided with a vacuum adsorption hole. Before the target adjustment parameter is set according to the preset alignment position and the pinning position, the method further comprises: The same type of candidate test chips are taken to the respective position slots by the suction pen, so that the candidate test chips cover the vacuum adsorption holes; The vacuum pump is operated to fix the candidate test chips in the position slots by pressure adsorption.

3. A system for batch automatic testing of flip chip interconnect connectivity, comprising: The system is applied to the batch automatic test method of the flip-chip interconnection communication condition as claimed in any one of claims 1-2, and the system comprises: A probe station is a four-axis motion mechanism, which comprises a chip carrier comprising a plurality of position slots, and the same type of candidate test chips are fixed in the respective position slots, the candidate test chips correspond to the position slots one by one, and the candidate test chips are infrared focal plane chips after the completion of the flip-chip interconnection process; A probe card is arranged above the probe station, the probe card matches the type of the candidate test chips, and the probe card is provided with probes; A control device; A signal processing interface board is connected with the probe card and the control device respectively; The probe station is used for: setting the target adjustment parameter according to the preset alignment position and the pinning position; sending a start signal to the control device to make the control device generate a test signal in response to receiving the start signal; iteratively performing the following steps until all candidate test chips in the chip carrier complete the test: receiving the test signal sent by the control device, the test signal comprising target test chip information, the target test chip being any one of the batch candidate test chips; moving to the contact between the readout circuit pad of the target test chip and the probe on the probe card according to the automatically generated identification template, the target test chip information and the target adjustment parameter to obtain the electrical communication test data of the target test chip; and sending the test data to the control device.

4. The system of claim 3, wherein, The control device comprises a control module, a host chassis, a processor board, a display and a test software platform; The control module is used for providing a bias voltage and a working pulse for the candidate test chips; The test software platform is used for controlling the automatic test progress of the probe station.

5. The system of claim 3, wherein, The system further comprises a detection device arranged above the probe card; The detection device is used for determining real-time position information of the probe station, first size information of the candidate test chips and second size information of the chip carrier.

6. The system of claim 5, wherein, The detection device comprises a microscope or an identification camera.

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