Checking method and system of chip packaging structure, terminal and storage medium

Abstract

The invention relates to the technical field of semiconductors, and particularly provides a chip packaging structure verification method and system, a terminal and a storage medium, and the method comprises the steps: collecting an initial image and initial thermal resistance test data of a chip packaging structure, and recognizing an initial pin spacing from the initial image; carrying out a vibration environment test on the chip packaging structure, re-collecting an image of the chip packaging structure, and identifying a pin spacing from the image; performing a failure test on the chip packaging structure, and re-collecting thermal resistance test data; calculating a pin error between the initial pin spacing and the pin spacing and a thermal resistance error between the initial thermal resistance test data and the thermal resistance test data; and matching the pin error with the thermal resistance error, and analyzing the defect of the chip packaging structure based on a matching result. According to the invention, pin information is identified by using an image identification technology, pin defects are detected, thermal resistance test data are analyzed based on a detection result, and interference of the pin defects is eliminated.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure verification method, system, terminal and storage medium. Background Art

[0002] The results of chip thermal resistance test are usually presented in the form of temperature-time curve. By analyzing the slope of the curve, the thermal resistance value of the chip can be calculated. The smaller the thermal resistance value, the better the heat dissipation ability of the chip.

[0003] ‌ In semiconductor packaging structures, pin defects can affect thermal resistance testing. ‌ Pin defects can cause incomplete or poor thermal conduction paths in the package, thus affecting accurate thermal resistance measurements.

[0004] The impact of pin defects on thermal resistance testing For example: improper pin design, such as inappropriate size or unreasonable layout, may cause heat to not be effectively conducted, affecting the thermal resistance measurement results. Poor connection between the pin and the chip or package will cause heat to not be transferred smoothly, increasing the thermal resistance value during measurement.

[0005] It can be seen that pin defects will affect the results of the thermal resistance test, which will cause the thermal resistance test to be unable to effectively verify the chip packaging structure. Summary of the invention

[0006] In view of the above-mentioned deficiencies in the prior art, the present invention provides a chip packaging structure verification method, system, terminal and storage medium to solve the above-mentioned technical problems.

[0007] In a first aspect, the present invention provides a chip packaging structure verification method, comprising: Collecting an initial image and initial thermal resistance test data of a chip packaging structure, and identifying an initial pin spacing from the initial image; Performing a vibration environment test on the chip packaging structure, re-collecting an image of the chip packaging structure, and identifying a pin spacing from the image; Conduct failure tests on the chip packaging structure and re-collect thermal resistance test data;[5][6] Calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data; The pin error is matched with the thermal resistance error, and the chip packaging structure defects are analyzed based on the matching result.

[0008] In an optional embodiment, collecting an initial image and initial thermal resistance test data of a chip packaging structure, and identifying an initial pin spacing from the initial image includes: Acquire an initial image collected by an electron microscope, generate a timestamp for the initial image, and save the initial image in a folder named with the sample number of the chip packaging structure; Using a thermal resistance tester to collect thermal resistance test data of the chip packaging structure, generating a timestamp for the thermal resistance test data, and saving the thermal resistance test data in a folder named after the sample number of the chip packaging structure; An initial pin spacing is identified from the initial image using image recognition technology.

[0009] In an optional embodiment, the thermal resistance test data includes a multi-segment layer structure curve.

[0010] In an optional implementation, performing a vibration environment test on the chip packaging structure, re-collecting an image of the chip packaging structure, and identifying the pin spacing from the image includes: Placing the substrate where the chip packaging structure is located on a vibration device and timing it, and if the timing reaches a set time threshold, controlling the vibration device to stop vibrating; Reusing the electron microscope to collect an image of the chip packaging structure; Performing grayscale processing on the image and identifying the chip outline based on the grayscale value; Using a convolutional neural network to identify a pin outline from the chip outline, and generating a number tag for the identified pin outline; Generate a coordinate system in the image, and obtain the coordinates of the pin outline in the coordinate system; The maximum spacing and the minimum spacing of adjacent pins are calculated based on the coordinates of the pin outlines, and the number marks of the adjacent pins and the maximum spacing and the minimum spacing are saved as structured data.

[0011] In an optional embodiment, the method further comprises: Calculating the distance difference between the maximum spacing and the minimum spacing in the structured data, and if the distance difference reaches a set distance threshold, marking the structured data as abnormal data; Traverse all structured data to obtain multiple abnormal data, match the multiple abnormal data, and divide the abnormal data with the same number mark into the same group; The same number mark of abnormal data of the same group is output as the number mark of the inclined pin.

[0012] In an optional implementation, calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data includes: The structured data with the same number mark as the initial pin spacing is divided into matching data, and the spacing difference of the matching data is calculated to obtain the pin error; The initial thermal resistance test data and the thermal resistance test data are divided into multiple layer structure curves, and numbers are generated for each layer structure curve of the initial thermal resistance test data and the thermal resistance test data according to a preset numbering rule, and characteristic values ​​of each layer structure curve are calculated, wherein the characteristic values ​​include a starting value, an end value, a maximum value, a minimum value and a slope; the characteristic values ​​of the layer structure curves with the same number are compared, and the difference between the corresponding characteristic values ​​is output as a thermal resistance error.

[0013] In an optional implementation, matching the pin error with the thermal resistance error, and analyzing the chip packaging structure defect based on the matching result, includes: Determine whether the pin error exceeds a preset pin error range: If yes, a pre-trained prediction model is used to generate thermal resistance error prediction data based on the pin error. If the thermal resistance error does not exceed the thermal resistance error prediction data, it is determined that there is a pin defect. If the thermal resistance error exceeds the thermal resistance error prediction data, it is determined that there is both a pin defect and a package defect. If not, the thermal resistance error is compared with a preset thermal resistance error threshold. If the thermal resistance error does not exceed the thermal resistance error threshold, it is determined that there is no defect. If the thermal resistance error exceeds the thermal resistance error threshold, it is determined that the chip packaging structure has failed.

[0014] In a second aspect, the present invention provides a chip packaging structure verification system, comprising: An initial test module, used to collect an initial image of a chip packaging structure and initial thermal resistance test data, and identify an initial pin spacing from the initial image; [7][8] An image verification module, used to perform a vibration environment test on the chip packaging structure, re-collect an image of the chip packaging structure, and identify the pin spacing from the image; A failure test module, used for performing a failure test on the chip packaging structure and recollecting thermal resistance test data; An error calculation module, used for calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data; The error analysis module is used to match the pin error with the thermal resistance error and analyze the chip packaging structure defects based on the matching result.

[0015] In a third aspect, a terminal is provided, including: A memory, used for storing a verification program of a chip packaging structure; The processor is used to implement the steps of the chip packaging structure verification method provided in the first aspect when executing the chip packaging structure verification program.

[0016] In a fourth aspect, a computer-readable storage medium is provided, on which a verification program for a chip packaging structure is stored. When the verification program for the chip packaging structure is executed by a processor, the steps of the verification method for the chip packaging structure provided in the first aspect are implemented.

[0017] The beneficial effects of the present invention lie in that the chip packaging structure verification method, system, terminal and storage medium provided by the present invention utilize image recognition technology to identify pin information, detect pin defects, analyze thermal resistance test data based on the detection results, eliminate interference from pin defects, and thereby achieve effective verification of the chip packaging structure.

[0018] In addition, the invention has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention.

[0021] Figure 2 is a schematic block diagram of a system according to an embodiment of the present invention.

[0022] Figure 3 A schematic diagram of the structure of a terminal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0025] The chip packaging structure verification method provided by the embodiment of the present invention is executed by a computer device, and accordingly, the chip packaging structure verification system runs in the computer device.

[0026] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention. Figure 1 The execution subject may be a chip packaging structure verification system. According to different requirements, the order of the steps in the flow chart may be changed, and some may be omitted.

[0027] like Figure 1 As shown, the method includes: Step 110, collecting an initial image and initial thermal resistance test data of the chip packaging structure, and identifying an initial pin spacing from the initial image; Step 120, performing a vibration environment test on the chip packaging structure, re-collecting an image of the chip packaging structure, and identifying a pin spacing from the image; Step 130, performing a failure test on the chip packaging structure and recollecting thermal resistance test data; Step 140, calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data; Step 150, matching the pin error with the thermal resistance error, and analyzing chip packaging structure defects based on the matching result.

[0028] To facilitate understanding of the present invention, the verification method for the chip packaging structure provided by the present invention is further described below based on the principle of the verification method for the chip packaging structure of the present invention and in combination with the process of verifying the chip packaging structure in the embodiment.

[0029] Specifically, the chip packaging structure verification method includes: S1. Collecting an initial image and initial thermal resistance test data of a chip packaging structure, and identifying an initial pin spacing from the initial image.

[0030] S101, obtaining an initial image captured by an electron microscope, generating a timestamp for the initial image, and saving the initial image in a folder named after the sample number of the chip packaging structure; and identifying an initial pin spacing from the initial image using image recognition technology.

[0031] In one example, the initial image is obtained as follows: First, the chip package structure is carefully observed and photographed using a high-precision electron microscope to obtain a high-quality initial image. This step requires ensuring that the microscope's resolution, magnification, and lighting conditions are properly set to capture clear, distortion-free image details. During the acquisition process, the microscope's focal length and the position of the sample stage need to be adjusted to ensure that the image covers the entire chip package structure or a specific area of ​​interest.

[0032] When acquiring each initial image, the system automatically records the current date and time and generates a timestamp accurate to the second (or even millisecond). This timestamp is crucial for subsequent data management and traceability, helping to distinguish images acquired at different time points and ensure the timeliness and accuracy of the data.

[0033] The generated initial image file is saved to a server or local storage system, and a meaningful file name or path is assigned to it. Here, the image files are organized in folders named after the sample number of the chip package structure, which greatly facilitates subsequent retrieval and management. The file name or path can also contain part of the timestamp to further distinguish images collected at different times under the same sample number.

[0034] Before image recognition, the initial image is preprocessed, such as denoising, contrast enhancement, and color balance adjustment, to improve the accuracy and efficiency of the image recognition algorithm. The preprocessing step is customized according to the specific image quality and recognition requirements, and may include the use of image filtering, histogram equalization, edge detection, and other techniques.

[0035] With the help of deep learning models, the pins on the chip package structure are automatically identified from the preprocessed images. The pixel distance between adjacent pins is calculated and converted into the actual pin spacing by combining parameters such as the microscope magnification and pixel size. During the recognition process, multiple factors such as pin shape, arrangement, background interference, etc. need to be considered to ensure the accuracy and robustness of recognition.

[0036] Output the identified pin spacing results as a report or data file for subsequent analysis and use. Verify the identification results by manual inspection, comparison with other measurement methods (such as laser rangefinder), etc. to ensure the accuracy of the results.

[0037] All relevant image files, recognition results, verification records and other data are stored in a secure and reliable storage system and backed up regularly to prevent data loss or damage.

[0038] S102, using a thermal resistance tester to collect thermal resistance test data of the chip packaging structure, generating a timestamp for the thermal resistance test data, and saving the thermal resistance test data in a folder named after the sample number of the chip packaging structure.

[0039] The packaging structure mainly includes the following key components: Substrate: As the foundation of the package structure, the substrate is usually made of insulating materials such as ceramics, glass ceramics or organic polymers, etc., which are used to support and fix other layers. The substrate is usually designed with circuit patterns to achieve the transmission and distribution of electrical signals.

[0040] First solder layer: This layer is located on one side of the substrate and firmly combines the first metal layer with the substrate through welding technology. The first solder layer not only provides a good electrical connection, but also ensures the mechanical stability of the package structure.

[0041] First metal layer: Located on the first solder layer, it is usually made of metal materials with good electrical conductivity such as copper and aluminum. The first metal layer acts as a bridge for heat dissipation and conduction, transferring heat from the semiconductor chip to the substrate and realizing the transmission of electrical signals at the same time.

[0042] Ceramic layer: The ceramic layer is located on the first metal layer. It has good insulation performance and certain mechanical strength, which can effectively isolate the electrical signal between the first metal layer and the second metal layer to prevent the occurrence of short circuit. At the same time, the ceramic layer also has a certain thermal conductivity, which is conducive to the transfer of heat.

[0043] Second metal layer: This layer is located above the ceramic layer and includes a first portion and a second portion that are electrically insulated from each other. The first portion of the second metal layer is usually used to make electrical connections with the semiconductor chip, while the second portion may be used to connect with other circuit elements or external devices. Through clever design, the second metal layer realizes complex circuit connections within the package structure.

[0044] Second solder layer: located on the first part of the second metal layer, the semiconductor chip and the second metal layer are firmly combined by welding technology. The second solder layer ensures good electrical connection and mechanical stability between the semiconductor chip and the packaging structure.

[0045] Semiconductor chip: This is the core part of the package structure, which contains circuits and components that realize specific functions. The semiconductor chip is connected to the second metal layer through the second solder layer, thereby realizing signal transmission and power exchange with the external circuit.

[0046] Leads: Leads are used to electrically connect the semiconductor chip and the second part of the second metal layer. They are usually made of conductive materials such as metal wires or metal strips. The existence of leads enables the package structure to be connected to other circuit components or external devices, realizing the practical application of semiconductor devices.

[0047] In order to evaluate the thermal performance of this packaging structure, we used a thermal resistance tester for testing. A thermal resistance tester is an instrument specifically used to measure the thermal resistance of semiconductor device packaging structures. It can accurately measure the change in thermal resistance of the packaging structure during temperature changes.

[0048] When conducting the test, we place the semiconductor device package structure to be tested on the test bench of the thermal resistance tester and connect and set it up according to the operating instructions of the tester. The tester will then apply a certain amount of heat to the package structure and monitor its temperature changes. By collecting and analyzing the data during the test process, we can obtain the differential thermal resistance structure function curve of the semiconductor device package structure. This curve reflects the change in thermal resistance of the package structure at different temperatures, thus providing an important reference for us to evaluate its thermal performance and optimize the package design.

[0049] When collecting thermal resistance test data, the system automatically records the current date and time and generates a timestamp accurate to seconds (or even milliseconds). The generation of timestamps is crucial for subsequent data management and traceability. It can help us distinguish data collected at different time points and ensure the timeliness and accuracy of the data.

[0050] The collected thermal resistance test data is saved to the server or local storage system. In order to facilitate subsequent retrieval and management, the data is organized in folders named after the sample number of the chip package structure. Within the folder, subfolders can be further created according to information such as test date and test batch to achieve classified storage of data. The data file can be in a format that is easy to identify and parse, such as CSV, Excel or database files, for subsequent data processing and analysis.

[0051] Before saving the data, perform an integrity check on the data to ensure that there is no missing or erroneous data. Check the format, scope, and consistency of the data to ensure that they meet the expected test requirements. Perform regular backups of the saved thermal resistance test data to prevent data loss or damage. The backup data is stored on an external hard drive, cloud storage, etc. At the same time, formulate data access rights and security policies to ensure the security and confidentiality of the data.

[0052] S2. Perform a vibration environment test on the chip packaging structure, re-collect an image of the chip packaging structure, and identify the pin spacing from the image.

[0053] The substrate where the chip packaging structure is located is placed on a vibration device and timed. If the time reaches a set time threshold, the vibration device is controlled to stop vibrating; the electron microscope is used again to collect an image of the chip packaging structure; the image is gray-scaled and the chip outline is identified based on the gray-scale value; a convolutional neural network is used to identify the pin outline from the chip outline and a number mark is generated for the identified pin outline; a coordinate system is generated in the image and the coordinates of the pin outline in the coordinate system are obtained; the maximum spacing and the minimum spacing of adjacent pins are calculated based on the coordinates of the pin outline, and the number marks of adjacent pins and the maximum spacing and the minimum spacing are saved as structured data.

[0054] In one example, the vibration test and image recognition process includes: S201, vibration test preparation: Place the substrate where the chip packaging structure is located on the vibration device to ensure that the substrate is firmly fixed to prevent displacement or falling off during the vibration process. The vibration device should be calibrated in advance to ensure that the vibration frequency, amplitude and other parameters meet the test requirements.

[0055] Set a reasonable time threshold, which should be determined based on the characteristics of the chip package structure and the test purpose, to ensure that the vibration test can effectively simulate the vibration impact in the actual working environment without causing damage to the chip package structure.

[0056] S202, start vibration test: Press the start button of the vibration device to start the test. The vibration device will vibrate the substrate according to the set parameters. At the same time, start the timer to start recording the vibration test time.

[0057] S203, vibration test ends: When the time displayed by the timer reaches the set time threshold, the vibration device will automatically stop vibrating. At this time, it should be ensured that the substrate and the chip packaging structure on it are stable and no longer vibrate significantly.

[0058] S204, re-collecting images: Use a high-resolution electron microscope to re-photograph the chip package structure to obtain its image after the vibration test. During the shooting process, ensure that the microscope's focus, magnification and other parameters are set appropriately to capture clear, distortion-free image details.

[0059] S205, image grayscale processing: Import the acquired image into the image processing software for grayscale processing. Grayscale processing is the process of converting a color image into a grayscale image, which helps to simplify the image information and improve the accuracy and efficiency of subsequent image recognition. During the grayscale processing, ensure that the brightness and contrast of the image are properly adjusted to better identify the chip outline.

[0060] S206, chip outline recognition: Based on the grayscale value, the edge detection algorithm is used to identify the outline of the chip in the image. The identified chip outline should be clear and accurate, and can fully reflect the shape and size of the chip.

[0061] S207, pin outline identification and numbering marking: The chip outline is further analyzed using a convolutional neural network (CNN) to identify the pin outline. CNN is a deep learning model that can extract features from images and perform classification and recognition. The recognition results should contain the location information (such as coordinates) of each pin.

[0062] According to the pin location information, the identified pins are sorted. The sorting rules can be determined according to the chip package type and pin layout. For example, the dual in-line package (DIP) is usually sorted from top left to bottom right, while the quad flat package (QFP) may be sorted in a counterclockwise direction.

[0063] Assign a unique number to each pin after sorting. The number can start from 1 and increase in sequence, or be assigned according to the pin definition and function of the chip.

[0064] The designed numbered mark is superimposed on the identified pin position. The superposition process should ensure that the mark does not block the key features of the pin and does not affect the identification of other pins.

[0065] S208, generate a coordinate system and obtain coordinates: Generate a coordinate system in the image. The coordinate system should take a characteristic point of the chip outline (such as the center point, the upper left corner point, etc.) as the origin and determine the directions of the X-axis and Y-axis.

[0066] The position information of the pins in the image recognition results is converted into coordinate system coordinates, and these coordinate values ​​will be used for the subsequent calculation of the pin spacing.

[0067] S209, Pin spacing calculation: Based on the coordinate values ​​of the pin outlines, the maximum and minimum spacings between adjacent pins are calculated.

[0068] The calculation of the maximum spacing and the minimum spacing can be achieved by comparing the distances between the coordinates of adjacent pins, and the specific method may include Euclidean distance, Manhattan distance, etc.

[0069] S210, saving structured data: Save information such as the number markings of adjacent pins, maximum spacing, and minimum spacing as structured data. Structured data usually refers to data organized in a table format, which facilitates subsequent data processing and analysis. The saved data should contain enough information to accurately trace and verify the test results when necessary.

[0070] In one embodiment of the present invention, pin abnormality identification can be performed based on the spacing data between adjacent pins. The specific identification method includes: For each piece of structured data (i.e., the pin spacing information of each chip packaging structure), calculate the distance difference between its maximum spacing and minimum spacing. Set a distance threshold, which should be determined based on the chip packaging standard, working environment requirements, and test purpose. If the spacing difference of a piece of structured data reaches or exceeds the set distance threshold, the structured data is marked as abnormal data. Abnormal data may indicate that the chip packaging structure has problems such as pin deformation, displacement, or tilt after the vibration test.

[0071] Traverse all structured data and find all data marked as abnormal. Match these abnormal data and divide the abnormal data with the same number mark into the same group. This means that these abnormal data may correspond to similar problems of the same pin in multiple chip packaging structures.

[0072] For each set of abnormal data, the pin number marks contained therein are analyzed. If the pin number marks in a set of abnormal data are repeated in other abnormal data, and the corresponding spacing differences are large (exceeding a certain threshold), the pin number mark is output as the number mark of the tilted pin. This means that the pin has tilted or deformed problems in multiple chip packaging structures, which may be a potential defect in the design, manufacturing or testing process.

[0073] If there is an inclined pin, the subsequent test will not be performed. If there is no inclined pin, the subsequent test will continue to be performed.

[0074] S3. Perform a failure test on the chip packaging structure and re-collect thermal resistance test data.

[0075] The failure test includes: high and low temperature impact test, power cycle test, and high pressure cooking test. The thermal resistance test data is recollected using the thermal resistance test method in step S1.

[0076] S4. Calculate a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data.

[0077] S401, dividing the structured data having the same number mark as the initial pin spacing into matching data, calculating the spacing difference of the matching data, and obtaining the pin error.

[0078] Among all the saved structured data, identify the data records with the same number tags in the initial pin spacing and the pin spacing in the subsequent test. Classify these data records with the same number tags and comparable corresponding pin spacing as matching data. Matching data refers to data with comparable spacing values ​​for the same pin number under different test conditions (such as before and after vibration testing).

[0079] For each set of matching data, the difference between the initial spacing and the subsequent test spacing is calculated. This difference reflects the change in the pin spacing during the test. The spacing difference can be calculated by a simple subtraction operation, that is, the subsequent test spacing minus the initial spacing.

[0080] S402, dividing the initial thermal resistance test data and the thermal resistance test data into multiple layer structure curves, and generating numbers for each layer structure curve of the initial thermal resistance test data and the thermal resistance test data according to a preset numbering rule, calculating characteristic values ​​of each layer structure curve, the characteristic values ​​including a starting value, an end value, a maximum value, a minimum value and a slope; comparing the characteristic values ​​of the layer structure curves with the same number, and outputting the difference between the corresponding characteristic values ​​as a thermal resistance error.

[0081] The initial thermal resistance test data is the first differential thermal resistance structure function curve containing 7-segment layer structure curves, and the thermal resistance test data is also the second differential thermal resistance structure function curve containing 7-segment layer structure curves. The first differential thermal resistance structure function curve and the second differential thermal resistance structure function curve are respectively divided into 7-segment layer structure curves using a breakpoint detection algorithm, and a number is generated for each layer structure curve according to the numbering rule.

[0082] For each layer structure curve, the following eigenvalues ​​are calculated: Starting point value: The thermal resistance value at the starting point of the curve.

[0083] End point value: The thermal resistance value at the end point of the curve.

[0084] Maximum value: The maximum thermal resistance value on the curve.

[0085] Minimum value: The minimum thermal resistance value on the curve.

[0086] Slope: The slope of a curve, reflecting the rate at which thermal resistance changes with temperature or other variables.

[0087] For the layer structure curves with the same number (i.e. the corresponding curves in the initial test and the subsequent test), their characteristic values ​​are compared. The differences between the corresponding characteristic values ​​are calculated, and these differences reflect the degree of change of thermal resistance under different test conditions.

[0088] The calculated eigenvalue difference is used as the measurement output of the thermal resistance error. The thermal resistance error reflects the change of the thermal resistance characteristics during the test process and is an important indicator for evaluating the thermal management performance of the chip packaging structure.

[0089] If the thermal resistance error exceeds a preset threshold (this threshold can be determined based on the chip packaging standards, working environment requirements, and test purposes), it may indicate that the chip packaging structure has thermal management problems during the test, such as poor heat dissipation, increased thermal resistance, etc.

[0090] S5. Match the pin error with the thermal resistance error, and analyze chip packaging structure defects based on the matching result.

[0091] Determine whether the pin error exceeds a preset pin error range: if so, generate thermal resistance error prediction data based on the pin error using a pre-trained prediction model; if the thermal resistance error does not exceed the thermal resistance error prediction data, determine that a pin defect exists; if the thermal resistance error exceeds the thermal resistance error prediction data, determine that both a pin defect and a package defect exist; if not, compare the thermal resistance error with a preset thermal resistance error threshold; if the thermal resistance error does not exceed the thermal resistance error threshold, determine that no defect exists; if the thermal resistance error exceeds the thermal resistance error threshold, determine that the chip packaging structure has failed.

[0092] In one example, a method for generating thermal resistance error prediction data based on the pin error using a pre-trained prediction model includes: The relationship between pin error and thermal resistance error is mined using a pre-trained linear regression model, and then the thermal resistance error is generated based on the current pin error. Specifically, the following steps are included: Collect historical data, including corresponding records of pin error (obtained from the difference between the measured value of pin spacing and the standard value) and thermal resistance error (obtained from the difference between the thermal resistance test value and the standard value). Ensure the accuracy and completeness of the data to avoid inaccurate model training due to data errors.

[0093] The linear regression algorithm is selected as the basis of the model because it is suitable for describing the linear relationship between two variables. Using historical data as a training set, the linear regression model is fitted by the least squares method or other optimization algorithms, that is, the best linear equation is found to describe the relationship between the pin error and the thermal resistance error.

[0094] Evaluate the goodness of fit of the model, such as using indicators such as R² (coefficient of determination) to quantify how well the model fits the data. If the R² value is close to 1, it means that the model fits well.

[0095] Use methods such as cross-validation to validate the model to ensure that it has good generalization ability. Adjust model parameters, such as the coefficients of linear equations, based on the validation results to improve the model's prediction accuracy. If the model prediction effect is not good, you may need to consider using other algorithms or adding feature variables to improve the model.

[0096] When there is new pin error data, it is input into the trained linear regression model. The model calculates the corresponding thermal resistance error prediction value according to the linear equation based on the input pin error data. The predicted thermal resistance error value is output for subsequent defect determination or further analysis.

[0097] Based on the thermal resistance error prediction data obtained by the above method, the thermal resistance error is analyzed. The specific method is as follows: The actual thermal resistance error is compared with the thermal resistance error prediction data. If the thermal resistance error does not exceed the thermal resistance error prediction data, it is determined that a pin defect exists. If the thermal resistance error exceeds the thermal resistance error prediction data, it is determined that both a pin defect and a package defect exist.

[0098] If the pin error does not exceed the pin error range, it means that the pin is normal and will not interfere with the thermal resistance detection, so it is only necessary to analyze the thermal resistance test data. That is, the thermal resistance error is compared with the preset thermal resistance error threshold. If the thermal resistance error does not exceed the thermal resistance error threshold, it is determined that there is no defect. If the thermal resistance error exceeds the thermal resistance error threshold, it is determined that the chip packaging structure is invalid.

[0099] In some embodiments, the chip package structure verification system may include multiple functional modules composed of computer program segments. The computer program of each program segment in the chip package structure verification system may be stored in a memory of a computer device and executed by at least one processor to perform (see Figure 1 Description) The function of verifying the chip packaging structure.

[0100] In this embodiment, the chip packaging structure verification system can be divided into multiple functional modules according to the functions it performs, such as Figure 2As shown. The functional modules of the system 200 may include: an initial test module 210, an image verification module 220, a failure test module 230, an error calculation module 240, and an error analysis module 250. The module referred to in the present invention refers to a series of computer program segments that can be executed by at least one processor and can complete fixed functions, which are stored in a memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0101] An initial test module, used to collect an initial image and initial thermal resistance test data of a chip packaging structure, and identify an initial pin spacing from the initial image; An image verification module, used to perform a vibration environment test on the chip packaging structure, re-collect an image of the chip packaging structure, and identify the pin spacing from the image; A failure test module, used for performing a failure test on the chip packaging structure and recollecting thermal resistance test data; An error calculation module, used for calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data; The error analysis module is used to match the pin error with the thermal resistance error and analyze the chip packaging structure defects based on the matching result.

[0102] Optionally, as an embodiment of the present invention, collecting an initial image and initial thermal resistance test data of a chip packaging structure, and identifying an initial pin spacing from the initial image includes: Acquire an initial image collected by an electron microscope, generate a timestamp for the initial image, and save the initial image in a folder named with the sample number of the chip packaging structure; Using a thermal resistance tester to collect thermal resistance test data of the chip packaging structure, generating a timestamp for the thermal resistance test data, and saving the thermal resistance test data in a folder named after the sample number of the chip packaging structure; An initial pin spacing is identified from the initial image using image recognition technology.

[0103] Optionally, as an embodiment of the present invention, the thermal resistance test data includes a multi-segment layer structure curve.

[0104] Optionally, as an embodiment of the present invention, a vibration environment test is performed on the chip packaging structure, an image of the chip packaging structure is recaptured, and a pin spacing is identified from the image, including: Placing the substrate where the chip packaging structure is located on a vibration device and timing it, and if the timing reaches a set time threshold, controlling the vibration device to stop vibrating; Reusing the electron microscope to collect an image of the chip packaging structure; Performing grayscale processing on the image and identifying a chip outline based on the grayscale value; Using a convolutional neural network to identify a pin outline from the chip outline, and generating a number tag for the identified pin outline; Generate a coordinate system in the image, and obtain the coordinates of the pin outline in the coordinate system; The maximum spacing and the minimum spacing of adjacent pins are calculated based on the coordinates of the pin outlines, and the number marks of the adjacent pins and the maximum spacing and the minimum spacing are saved as structured data.

[0105] Optionally, as an embodiment of the present invention, it further includes: Calculate the distance difference between the maximum spacing and the minimum spacing in the structured data, and if the distance difference reaches a set distance threshold, mark the structured data as abnormal data; Traverse all structured data to obtain multiple abnormal data, match the multiple abnormal data, and divide the abnormal data with the same number mark into the same group; The same number mark of abnormal data of the same group is output as the number mark of the inclined pin.

[0106] Optionally, as an embodiment of the present invention, calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data includes: The structured data with the same number mark as the initial pin spacing is divided into matching data, and the spacing difference of the matching data is calculated to obtain the pin error; The initial thermal resistance test data and the thermal resistance test data are divided into multiple layer structure curves, and numbers are generated for each layer structure curve of the initial thermal resistance test data and the thermal resistance test data according to a preset numbering rule, and characteristic values ​​of each layer structure curve are calculated, wherein the characteristic values ​​include a starting value, an end value, a maximum value, a minimum value and a slope; the characteristic values ​​of the layer structure curves with the same number are compared, and the difference between the corresponding characteristic values ​​is output as a thermal resistance error.

[0107] Optionally, as an embodiment of the present invention, matching the pin error with the thermal resistance error, and analyzing the chip packaging structure defect based on the matching result includes: Determine whether the pin error exceeds a preset pin error range: If yes, a pre-trained prediction model is used to generate thermal resistance error prediction data based on the pin error. If the thermal resistance error does not exceed the thermal resistance error prediction data, it is determined that there is a pin defect. If the thermal resistance error exceeds the thermal resistance error prediction data, it is determined that there is both a pin defect and a package defect. If not, the thermal resistance error is compared with a preset thermal resistance error threshold. If the thermal resistance error does not exceed the thermal resistance error threshold, it is determined that there is no defect. If the thermal resistance error exceeds the thermal resistance error threshold, it is determined that the chip packaging structure has failed.

[0108] Figure 3 The present invention provides a schematic diagram of the structure of a terminal 300 according to an embodiment of the present invention. The terminal 300 may be used to execute the chip packaging structure verification method according to an embodiment of the present invention.

[0109] The terminal 300 may include: a processor 310, a memory 320 and a communication unit 330. These components communicate via one or more buses. Those skilled in the art will appreciate that the server structure shown in the figure does not limit the present invention, and it may be a bus structure or a star structure, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0110] The memory 320 can be used to store the execution instructions of the processor 310. The memory 320 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. When the execution instructions in the memory 320 are executed by the processor 310, the terminal 300 can perform some or all of the steps in the following method embodiments.

[0111] The processor 310 is the control center of the storage terminal, and uses various interfaces and lines to connect various parts of the entire electronic terminal. It runs or executes software programs and / or modules stored in the memory 320, and calls data stored in the memory to perform various functions of the electronic terminal and / or process data. The processor can be composed of an integrated circuit (IC), for example, it can be composed of a single packaged IC, or it can be composed of multiple packaged ICs with the same or different functions. For example, the processor 310 can only include a central processing unit (CPU). In the embodiment of the present invention, the CPU can be a single computing core or multiple computing cores.

[0112] The communication unit 330 is used to establish a communication channel so that the storage terminal can communicate with other terminals, receive user data sent by other terminals or send user data to other terminals.

[0113] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and when the program is executed, the program may include some or all of the steps in each embodiment provided by the present invention. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0114] Therefore, the present invention uses image recognition technology to identify pin information, detect pin defects, analyze thermal resistance test data based on the detection results, eliminate the interference of pin defects, and thus achieve effective verification of chip packaging structure. The technical effects that can be achieved by this embodiment can be found in the above description and will not be repeated here.

[0115] Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution in the embodiments of the present invention, in essence or in other words, the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes, including several instructions for enabling a computer terminal (which can be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention.

[0116] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

[0117] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or modules, which can be electrical, mechanical or other forms.

[0118] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0120] Although the present invention has been described in detail with reference to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person of ordinary skill in the art may easily think of changes or substitutions within the technical scope disclosed by the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. A chip packaging structure verification method, characterized in that: include: Collecting an initial image and initial thermal resistance test data of a chip packaging structure, and identifying an initial pin spacing from the initial image; Performing a vibration environment test on the chip packaging structure, re-collecting an image of the chip packaging structure, and identifying a pin spacing from the image; Performing a failure test on the chip packaging structure and recollecting thermal resistance test data; Calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data; The pin error is matched with the thermal resistance error, and the chip packaging structure defects are analyzed based on the matching result.

2. The method according to claim 1, characterized in that Collecting an initial image and initial thermal resistance test data of a chip packaging structure, and identifying an initial pin spacing from the initial image, including: Acquire an initial image captured by an electron microscope, generate a timestamp [1][2] for the initial image, and save the initial image to a folder named with the sample number of the chip packaging structure; Using a thermal resistance tester to collect thermal resistance test data of the chip packaging structure, generating a timestamp for the thermal resistance test data, and saving the thermal resistance test data in a folder named after the sample number of the chip packaging structure; An initial pin spacing is identified from the initial image using image recognition technology.

3. The method according to claim 2, characterized in that The thermal resistance test data includes multiple layer structure curves.

4. The method according to claim 1, characterized in that: Performing a vibration environment test on the chip packaging structure, re-collecting an image of the chip packaging structure, and identifying the pin spacing from the image, including: Placing the substrate where the chip packaging structure is located on a vibration device and timing it, and if the timing reaches a set time threshold, controlling the vibration device to stop vibrating; Reusing the electron microscope to collect an image of the chip packaging structure; Performing grayscale processing on the image and identifying a chip outline based on the grayscale value; Using a convolutional neural network to identify a pin outline from the chip outline, and generating a number tag for the identified pin outline; Generate a coordinate system in the image, and obtain the coordinates of the pin outline in the coordinate system; The maximum spacing and the minimum spacing of adjacent pins are calculated based on the coordinates of the pin outlines, and the number marks of the adjacent pins and the maximum spacing and the minimum spacing are saved as structured data.

5. The method according to claim 4, characterized in that The method further comprises: Calculate the distance difference between the maximum spacing and the minimum spacing in the structured data, and if the distance difference reaches a set distance threshold, mark the structured data as abnormal data; Traverse all structured data to obtain multiple abnormal data, match the multiple abnormal data, and divide the abnormal data with the same number mark into the same group; The same number mark of abnormal data of the same group is output as the number mark of the inclined pin.

6. The method according to claim 4, characterized in that Calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data, including: The structured data with the same number mark as the initial pin spacing is divided into matching data, and the spacing difference of the matching data is calculated to obtain the pin error; The initial thermal resistance test data and the thermal resistance test data are divided into multiple layer structure curves, and numbers are generated for each layer structure curve of the initial thermal resistance test data and the thermal resistance test data according to a preset numbering rule, and characteristic values ​​of each layer structure curve are calculated, wherein the characteristic values ​​include a starting value, an end value, a maximum value, a minimum value and a slope; the characteristic values ​​of the layer structure curves with the same number are compared, and the difference between the corresponding characteristic values ​​is output as a thermal resistance error.

7. The method according to claim 6, characterized in that Matching the pin error with the thermal resistance error, and analyzing the chip packaging structure defect based on the matching result, including: Determine whether the pin error exceeds a preset pin error range: If so, a pre-trained prediction model [3][4] is used to generate thermal resistance error prediction data based on the pin error. If the thermal resistance error does not exceed the thermal resistance error prediction data, it is determined that a pin defect exists. If the thermal resistance error exceeds the thermal resistance error prediction data, it is determined that both a pin defect and a package defect exist. If not, the thermal resistance error is compared with a preset thermal resistance error threshold. If the thermal resistance error does not exceed the thermal resistance error threshold, it is determined that there is no defect. If the thermal resistance error exceeds the thermal resistance error threshold, it is determined that the chip packaging structure has failed.

8. A chip packaging structure verification system, characterized in that: include: An initial test module, used to collect an initial image and initial thermal resistance test data of a chip packaging structure, and identify an initial pin spacing from the initial image; An image verification module, used to perform a vibration environment test on the chip packaging structure, re-collect an image of the chip packaging structure, and identify the pin spacing from the image; A failure test module, used for performing a failure test on the chip packaging structure and recollecting thermal resistance test data; An error calculation module, used for calculating a pin error between an initial pin spacing and the pin spacing and a thermal resistance error between initial thermal resistance test data and the thermal resistance test data; The error analysis module is used to match the pin error with the thermal resistance error and analyze the chip packaging structure defects based on the matching result.

9. A terminal, characterized in that: include: A memory, used for storing a verification program of a chip packaging structure; A processor is used to implement the steps of the chip packaging structure verification method according to any one of claims 1 to 7 when executing the chip packaging structure verification program.

10. A computer-readable storage medium storing a computer program, characterized in that: The readable storage medium stores a verification program for a chip packaging structure, and when the verification program for the chip packaging structure is executed by a processor, the steps of the verification method for a chip packaging structure according to any one of claims 1 to 7 are implemented.

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