LDO circuit with low static power consumption

Abstract

The invention discloses an LDO circuit with low static power consumption. The LDO circuit mainly solves the problem that an existing LDO circuit is poor in stability under the condition that static current is reduced. The circuit comprises a bias circuit, an error amplifier, a transconductance linear ring, a CLASS-AB output stage, a resistance feedback network and an output end load which are connected in sequence. And the error amplifier is also connected with the resistance feedback network. According to the LDO structure, the CLASS-AB output stage is adopted, the two adjusting tubes are used, and the LDO can meet the charging and discharging requirements at the same time. According to the LDO structure, the transconductance linear ring bias CLASS-AB output stage is adopted, and it can be guaranteed that the quiescent current is reduced, and meanwhile fast load response is achieved. According to the LDO structure, the output end of the error amplifier is set as a main pole, a parallel negative feedback mechanism is ingeniously introduced to the output end, the output impedance of the LDO is reduced, the pole of the output end of the LDO is pushed to high frequency, and the stability of a loop can be guaranteed while the LDO drives large capacitance and small resistance.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an LDO circuit with low static power consumption. Background Art

[0002] High-precision ADCs require switches and capacitors. For example, Sigma-delta ADC is a digital signal that can convert analog signals into discrete time and amplitude signals. Its structure mainly consists of two parts: sigma-delta modulator and digital filter. According to the working principle of Sigma-delta ADC, LDO is required to provide the high, low and common-mode levels required for switch switching. The signal input circuit of Sigma-delta ADC is as follows: Figure 1 As shown, the output voltage VOUT of the LDO is required to provide the common mode voltage VCM required for the capacitor to switch. In order to meet the principle of charge conservation, energy flows between capacitors, and charging and discharging requirements are put forward for the reference voltage VCM provided by the LDO.

[0003] However, if Figure 2 As shown, the output stage of the traditional LDO structure often adopts a CLASS-A structure, using only a single adjustment tube, which cannot achieve the charging and discharging requirements at the same time.

[0004] In addition, the main pole of the traditional LDO structure is located at the output end of the adjustment tube. The position of the main pole will shift with the change of load, which will cause stability problems of the LDO.

[0005] Low quiescent power consumption means smaller quiescent current, but the reduction of quiescent current will inevitably cause poor transient response of LDO. Therefore, it is also important for LDO structure to reduce quiescent current while having good output voltage control and fast load transient response. Summary of the invention

[0006] The purpose of the present invention is to provide an LDO circuit with low static power consumption, mainly to solve the problems that the existing LDO circuit has poor stability when the static current is reduced and cannot have the ability to output and absorb current at the same time.

[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0008] A low static power consumption LDO circuit comprises a bias circuit, an error amplifier, a translinear loop, a CLASS-AB output stage, a resistor feedback network and an output load which are connected in sequence; the error amplifier is also connected to the resistor feedback network;

[0009] The translinear loop is composed of a PMOS translinear loop and an NMOS translinear loop, a current source mirror tube MN7, a current source mirror tube MP14 and a resistor R3; the translinear loop receives the error signal amplified by the error amplifier, and its output signal is used to drive the CLASS-AB output stage;

[0010] The PMOS translinear loop is composed of PMOS tubes MP11, MP12, and MP13; wherein the gate of the PMOS tube MP11 is connected to the drain, the gate of the PMOS tube MP12 is connected to the drain, the gate of the PMOS tube MP12 is connected to the gate of the PMOS tube MP13, and the source of the PMOS tube MP13 is connected to the gate of the PMOS tube MP16; the source of the PMOS tube MP11 is connected to the error amplifier, the drain of the PMOS tube MP12 is connected to the drain of the current source mirror tube MN7, and the drain of the PMOS tube MP13 is connected to the NMOS translinear loop; the source of the PMOS tube MP13 is connected to one end of the resistor R3; and the other end of the resistor R3 is connected to the source of the PMOS tube MP11;

[0011] The NMOS translinear loop is composed of NMOS tubes MN8, MN10, and MN11; wherein the gate and drain of the NMOS tube MN8 are connected, the source of the NMOS tube MN8 is connected to the power ground terminal GND, the drain of the NMOS tube MN8 is connected to the source of the NMOS tube MN10, the gate of the NMOS tube MN10 is connected to the gate of the NMOS tube MN11, the drain of the NMOS tube MN11 is connected to the source of the PMOS tube MP13, the gate and drain of the NMOS tube MN10 are connected and then connected to the drain of the current source mirror tube MP14, the drain of the NMOS tube MN9 is connected to the source of the NMOS tube MN11, the gate of the current source mirror tube MP14 is connected to the bias circuit, and the source of the current source mirror tube MP14 is connected to the power supply VCC terminal.

[0012] Further, in the present invention, the bias circuit includes a low-voltage common-source common-gate current mirror structure composed of PMOS tubes MP1-MP6 and an NMOS tube MN1; wherein the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP2, the source of the PMOS tube MP1 is connected to the drain of the PMOS tube MP2, the source of the PMOS tube MP2 is connected to the source of the PMOS tube MP3, the source of the PMOS tube MP3 is connected to the source of the PMOS tube MP4, the gate of the PMOS tube MP3 is connected to the gate of the PMOS tube MP4, the source of the PMOS tube MP3 is connected to the source of the PMOS tube MP4 and both are connected to the power supply VCC terminal, the gate of the PMOS tube MP3 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP5, The gate of the PMOS tube MP6 is connected to the gate of the PMOS tube MP5, the drain of the PMOS tube MP4 is connected to the source of the PMOS tube MP6, and the drain of the NMOS tube MN1 is connected to the gate; the drain of the PMOS tube MP6 is connected to the drain of the NMOS tube MN1, the gate and drain of the PMOS tube MP1 are connected and serve as the port IB_N1 for receiving the external bias current, the drain of the MOS tube MP5 serves as the port IB_N2 for receiving the external bias current, the source of the NMOS tube MN1 is the grounding GND port, and the source of the PMOS tube MP2 is the VDD access port; the gate of the PMOS tube MP4 and the gate of the NMOS tube MN1 are both connected to the error amplifier, the translinear loop, the CLASS-AB output stage and the source, and the gate of the PMOS tube MP5 is connected to the error amplifier.

[0013] Further, in the present invention, the error amplifier is composed of NMOS tubes MN2 to MN6, PMOS tubes MP7 to MP10 and NMOS tube MN13; wherein the gate of NMOS tube MN2 is connected to the gate of NMOS tube MN1, the source of NMOS tube MN3 is connected to the drain of NMOS tube MN2, the source of NMOS tube MN4 is connected to the drain of NMOS tube MN2, the source of NMOS tube MN5 is connected to the source of NMOS tube MN2, the source of NMOS tube MN6 is connected to the source of NMOS tube MN5, the gate of NMOS tube MN6 is connected to the gate of NMOS tube MN5, the gate of PMOS tube MP7 is connected to the gate of PMOS tube MP4, the gate of PMOS tube MP7 is connected to the gate of PMOS tube MP8, the source of PMOS tube MP10 is connected to the drain of PMOS tube MP8 and the drain of NMOS tube MN4, the gate of PMOS tube MP9 is connected to the gate of PMOS tube MP10, and the gate of PMOS tube MP11 is connected to the gate of PMOS tube MP12. The drain of the PMOS tube MP9 is connected to the drain of the NMOS tube MN6; the drain of the PMOS tube MP9 is connected to the drain of the NMOS tube MN5, the source of the PMOS tube MP9 is connected to the drain of the PMOS tube MP7 and the drain of the NMOS tube MN3; the gate of the NMOS tube MN3 is connected to the reference voltage VREF, the sources of the PMOS tubes MP7 and MP8 are connected to the source of the PMOS tube MP4, and the gate and drain of the NMOS tube MN5 are connected; the gate of the NMOS tube MN13 is connected to the drain of the PMOS tube MP10 and the CLASS-AB output stage, the drain of the PMOS tube MP16 is connected to the CLASS-AB output stage, the drain of the NMOS tube MN9 is connected to the CLASS-AB output stage, the gate of the NMOS tube MN2 is connected to the gate of the NMOS tube M7, the sources of the PMOS tubes MP7 and MP8 are connected to the sources of the PMOS tubes MP4 and MP11; the gate of the NMOS tube MN4 is connected to the resistor feedback network.

[0014] Further, in the present invention, the CLASS-AB output stage includes PMOS tubes MP15 and MP16 and NMOS tubes MN9 and MN12; wherein the gate of the PMOS tube MP15 is connected to the drain of the PMOS tube MP10, the source of the PMOS tube MP15 is connected to the source of the PMOS tube MP16, and the drain of the PMOS tube MP15 is connected to the drain of the NMOS tube MN9; the gate of the NMOS tube MN12 is connected to the drain of the NMOS tube MN9, and the drain of the NMOS tube MN12 is connected to the drain of the PMOS tube MP16. The source of the NMOS tube MN12 is connected to the source of the NMOS tube MN9; the PMOS tube MP16 is used as the PMOS output adjustment tube of CLASS-AB, and its source is connected to the power supply VCC terminal; the NMOS tube MN12 is used as the NMOS output adjustment tube of CLASS_AB, and its source is connected to the power supply ground GND terminal; the drain of the PMOS tube MP16 is connected to the drain of the NMOS tube MP12 and serves as the VOUT port; the drain of the NMOS tube MN12 is connected to the resistor feedback network, and the source of the NMOS tube MN12 is connected to the resistor feedback network.

[0015] Furthermore, in the present invention, the resistor feedback network is composed of voltage-dividing resistors R1 and R2, one end of the voltage-dividing resistor R1 is connected to the source of the PMOS tube MP15, the other end of the voltage-dividing resistor R1 is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the source of the NMOS tube MN12, and the common end of the voltage-dividing resistors R1 and R2 is also connected to the gate of the NMOS tube MN4.

[0016] Furthermore, in the present invention, the output end load comprises a load resistor RL and a load capacitor CL connected in parallel; wherein two ends of the load resistor RL are respectively connected to the source of the NMOS transistor MN12 and the source of the PMOS transistor MP15.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The LDO structure of the present invention adopts a CLASS-AB output stage and uses two adjustment tubes, so that the LDO can simultaneously achieve the charging and discharging requirements. The LDO structure of the present invention adopts a translinear loop bias CLASS-AB output stage, which can ensure a fast load response while reducing the quiescent current. The LDO structure of the present invention sets the output end of the error amplifier as the main pole, and cleverly introduces a parallel negative feedback mechanism at the output end to reduce the LDO output impedance and push the pole of the LDO output end to a high frequency, so that the LDO can drive large capacitors and small resistors while ensuring loop stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1This is a signal input circuit structure of a Sigma-delta ADC in the prior art.

[0020] Figure 2 It is a traditional LDO architecture.

[0021] Figure 3 Schematic diagram of the LDO circuit structure of the present invention.

[0022] Figure 4 FIG. 4 is a diagram of the LDO architecture of the present invention.

[0023] Figure 5 The figure is a graph showing the input-output characteristic of the LDO structure of the present invention.

[0024] Figure 6 The figure is a comparison curve of the linear adjustment capability between the traditional LDO structure and the LDO structure of the present invention.

[0025] Figure 7 It is a comparison curve diagram of the power supply rejection ratio between the traditional LDO structure and the LDO structure of the present invention.

[0026] Figure 8 It is a temperature characteristic comparison curve diagram of the traditional LDO structure and the LDO structure of the present invention.

[0027] Fig. 9 The graph is a loop amplitude-frequency characteristic and phase-frequency characteristic curve of the LDO of the present invention.

[0028] Fig.10 It is a load transient response curve diagram of the LDO structure of the present invention.

[0029] Fig.11 The figure is a comparison diagram of the load transient response curve of the traditional LDO structure and the load transient response curve of the LDO structure of the present invention. DETAILED DESCRIPTION

[0030] The present invention is further described below in conjunction with the accompanying drawings and embodiments. The embodiments of the present invention include but are not limited to the following embodiments.

[0031] Example

[0032] like Figure 3 , 4 As shown, a low static power consumption LDO circuit disclosed in the present invention comprises a bias circuit, an error amplifier, a translinear loop, a CLASS-AB output stage, a resistor feedback network and an output load which are connected in sequence; the error amplifier is also connected to the resistor feedback network.

[0033] The bias circuit adopts a low-voltage cascode current mirror structure to provide accurate current for circuits such as error amplifiers and translinear loops. The low-voltage cascode structure has a larger output impedance, a stable output current, and a larger output voltage swing. In this embodiment, the bias circuit includes a low-voltage cascode current mirror structure composed of PMOS tubes MP1-MP6 and an NMOS tube MN1; wherein the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP2, the source of the PMOS tube MP1 is connected to the drain of the PMOS tube MP2, the source of the PMOS tube MP2 is connected to the source of the PMOS tube MP3, the source of the PMOS tube MP3 is connected to the source of the PMOS tube MP4, the gate of the PMOS tube MP3 is connected to the gate of the PMOS tube MP4, the source of the PMOS tube MP3 is connected to the source of the PMOS tube MP4 and both are connected to the power supply VCC terminal, the gate of the PMOS tube MP3 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP5, and the PMOS tube MP4 is connected to the gate of the PMOS tube MP5. The gate of S transistor MP6 is connected to the gate of PMOS transistor MP5, the drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP6, and the drain of NMOS transistor MN1 is connected to the gate; the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN1, the gate and drain of PMOS transistor MP1 are connected and serve as port IB_N1 for receiving bias current provided externally, the drain of MOS transistor MP5 serves as port IB_N2 for receiving bias current provided externally, the source of NMOS transistor MN1 is the ground GND port, and the source of PMOS transistor MP2 is the VDD access port; the gate of PMOS transistor MP4 and the gate of NMOS transistor MN1 are both connected to the error amplifier, the translinear loop, the CLASS-AB output stage and the source, and the gate of PMOS transistor MP5 is connected to the error amplifier. The IB_N1 port receives the bias current provided externally, and the current flows through MP1 and MP2, providing bias voltage for the gates of MP5 and MP6 to ensure that MP5 and MP6 work in the saturation region.

[0034] The main function of the error amplifier is to compare the voltage fed back by the resistor feedback network with the reference voltage as the input, amplify the error between the two, and output it to the translinear loop. The error amplifier adopts a folded common source and common gate structure, has a large output swing, and only needs one stage of op amp to obtain a relatively high low-frequency gain; it has a high output impedance, which can improve the power supply rejection capability of the circuit. In this embodiment, the error amplifier is composed of NMOS tubes MN2 to MN6, PMOS tubes MP7 to MP10 and NMOS tube MN13; wherein the gate of NMOS tube MN2 is connected to the gate of NMOS tube MN1, the source of NMOS tube MN3 is connected to the drain of NMOS tube MN2, the source of NMOS tube MN4 is connected to the drain of NMOS tube MN2, the source of NMOS tube MN5 is connected to the source of NMOS tube MN2, the source of NMOS tube MN6 is connected to the source of NMOS tube MN5, the gate of NMOS tube MN6 is connected to the gate of NMOS tube MN5, the gate of PMOS tube MP7 is connected to the gate of PMOS tube MP4, the gate of PMOS tube MP7 is connected to the gate of PMOS tube MP8, the source of PMOS tube MP10 is connected to the drain of PMOS tube MP8 and the drain of NMOS tube MN4, the gate of PMOS tube MP9 is connected to the gate of PMOS tube MP10, and the gate of PMOS tube MP10 is connected to the gate of PMOS tube MP11. The drain is connected to the drain of the NMOS tube MN6; the drain of the PMOS tube MP9 is connected to the drain of the NMOS tube MN5, the source of the PMOS tube MP9 is connected to the drain of the PMOS tube MP7 and the drain of the NMOS tube MN3; the gate of the NMOS tube MN3 is connected to the reference voltage VREF, the sources of the PMOS tubes MP7 and MP8 are connected to the source of the PMOS tube MP4, and the gate and drain of the NMOS tube MN5 are connected; the gate of the NMOS tube MN13 is connected to the drain of the PMOS tube MP10 and the CLASS-AB output stage, the drain of the PMOS tube MP16 is connected to the CLASS-AB output stage, the drain of the NMOS tube MN9 is connected to the CLASS-AB output stage, the gate of the NMOS tube MN2 is connected to the gate of the NMOS tube M7, the sources of the PMOS tubes MP7 and MP8 are connected to the sources of the PMOS tubes MP4 and MP11; the gate of the NMOS tube MN4 is connected to the resistor feedback network. Among them, MN2, as a mirror tube, "copies" the current of the branch where MN1 is located in proportion, which is equivalent to the tail current source of the error amplifier folding stage. MN3 and MN4 are differential input pairs, and the gate of MN3 is used as the reverse input terminal of the error amplifier, connected to the external reference voltage; the gate of MN4 is used as the non-inverting input terminal of the error amplifier, connected to the resistor feedback network. MP7~MP10 constitute a common source and common gate current mirror, and its gate bias voltage is provided by the low-voltage common source and common gate current mirror bias circuit.MN5 and MN6 form a current mirror structure as an active load of the error amplifier. The source terminal of MP10 is connected to the drain terminal of MN6 as the output terminal of the error amplifier.

[0035] The gate of MN13 is connected to the output of the error amplifier, and the source, drain, and substrate of MN13 are all grounded, which is equivalent to a MOS capacitor. The function of MN13 is to introduce a large capacitor at the output node of the error amplifier, so that the pole here is pushed to a low frequency, serving as the main pole, thereby improving the loop stability of the LDO.

[0036] The translinear loop is composed of a PMOS translinear loop and an NMOS translinear loop, a current source mirror tube MN7, a current source mirror tube MP14 and a resistor R3; the translinear loop receives the error signal amplified by the error amplifier, and its output signal is used to drive the CLASS-AB output stage. The translinear loop receives the error signal amplified by the error amplifier, and its output signal is used to drive the output power tubes PMOS and NMOS of the CLASS-AB structure of the output stage. The translinear loop can not only set the quiescent current of the LDO output stage to achieve very low quiescent power consumption, but also improve the output slew rate of the LDO output stage, and provide a large charging current for the gate capacitance of the output power tube when the output power tube is transiently switched, thereby improving the transient response speed of the LDO to the load. In this embodiment, the PMOS translinear loop is composed of PMOS tubes MP11, MP12, and MP13, and shares the PMOS tube MP16 in the CLASS-AB output stage; wherein the gate of the PMOS tube MP11 is connected to the drain, the gate of the PMOS tube MP12 is connected to the drain, the gate of the PMOS tube MP12 is connected to the gate of the PMOS tube MP13, and the source of the PMOS tube MP13 is connected to the gate of the PMOS tube MP16; the source of the PMOS tube MP11 is connected to the error amplifier, the drain of the PMOS tube MP12 is connected to the drain of the current source mirror tube MN7, and the drain of the PMOS tube MP13 is connected to the NMOS translinear loop; the source of the PMOS tube MP13 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to the source of the PMOS tube MP11;

[0037] The NMOS translinear loop is composed of NMOS transistors MN8, MN10, and MN11, and shares the NMOS transistor MN9 in the CLASS-AB output stage; wherein the gate and drain of the NMOS transistor MN8 are connected, the source of the NMOS transistor MN8 is connected to the power ground terminal GND, the drain of the NMOS transistor MN8 is connected to the source of the NMOS transistor MN10, the gate of the NMOS transistor MN10 is connected to the gate of the NMOS transistor MN11, the drain of the NMOS transistor MN11 is connected to the source of the PMOS transistor MP13, the gate and drain of the NMOS transistor MN10 are connected and then connected to the drain of the current source mirror transistor MP14, the drain of the NMOS transistor MN9 is connected to the source of the NMOS transistor MN11, the gate of the current source mirror transistor MP14 is connected to the bias circuit, and the source of the current source mirror transistor MP14 is connected to the power supply VCC terminal.

[0038] The CLASS-AB output stage has the advantages of low static power consumption, low distortion, and high efficiency. In this embodiment, the CLASS-AB output stage includes PMOS transistors MP15 and MP16 and NMOS transistors MN9 and MN12; wherein the gate of the PMOS transistor MP15 is connected to the drain of the PMOS transistor MP10, the source of the PMOS transistor MP15 is connected to the source of the PMOS transistor MP16, and the drain of the PMOS transistor MP15 is connected to the drain of the NMOS transistor MN9; the gate of the NMOS transistor MN12 is connected to the drain of the NMOS transistor MN9, the drain of the NMOS transistor MN12 is connected to the drain of the PMOS transistor MP16, and the drain of the NMOS transistor MN12 is connected to the drain of the NMOS transistor MN9. The source of MOS tube MN12 is connected to the source of NMOS tube MN9; PMOS tube MP16 is used as the PMOS output adjustment tube of CLASS-AB, and its source is connected to the power supply VCC terminal; NMOS tube MN12 is used as the NMOS output adjustment tube of CLASS_AB, and its source is connected to the power supply ground GND terminal; the drain of PMOS tube MP16 is connected to the drain of NMOS tube MP12 and serves as the VOUT port; the drain of NMOS tube MN12 is connected to the resistor feedback network, and the source of NMOS tube MN12 is connected to the resistor feedback network. The working state of the CLASS-AB output stage is between CLASS-A and CLASS-B, so that the two power tubes work in a push-pull mode, which makes up for the shortcomings of large static power consumption of the CLASS-A output stage and distortion of the CLASS-B output stage. In order to achieve different load conditions, the PMOS power tube is turned on when it is necessary to output current outward, and the NMOS power tube is turned on when it is necessary to absorb current inward.

[0039] The resistor feedback network is composed of two voltage-dividing sampling resistors. By sampling the voltage change at the output end of the LDO, it is fed back to the input end of the error amplifier in time, compared with the reference voltage and amplified, and output to the gate of the power tube through the translinear loop, thereby adjusting the working state of the power tube, changing the output current of the power tube, and finally keeping the output voltage of the LDO stable. In this embodiment, the resistor feedback network is composed of voltage-dividing resistors R1 and R2, one end of the voltage-dividing resistor R1 is connected to the source of the PMOS tube MP15, the other end of the voltage-dividing resistor R1 is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the source of the NMOS tube MN12, and the common end of the voltage-dividing resistors R1 and R2 is also connected to the gate of the NMOS tube MN4.

[0040] The output load is composed of a load resistor and a load capacitor, which are used to simulate different load conditions, including no load, light load, and heavy load. The load capacitor is equivalent to the built-in capacitor of the LDO, which can filter and stabilize the output voltage of the LDO, so no external capacitor is required for the LDO. The output load is composed of a parallel load resistor RL and a load capacitor CL; wherein the two ends of the load resistor RL are respectively connected to the source of the NMOS tube MN12 and the source of the PMOS tube MP15.

[0041] In this embodiment, the output terminal of the error amplifier is connected to the gate of MP15, and MP15 converts the output voltage signal of the error amplifier into a current signal as the input of the translinear loop.

[0042] For a PMOS translinear loop:

[0043] PMOS tubes MP11, MP12, MP13, and MP16 form a translinear loop, and their gate-source voltages have the following relationship:

[0044] V GS，MP11 +V GS，MP12 =V GS，MP13 +V GS，MP16

[0045] Without considering the secondary effects such as channel length modulation effect and body effect, if the current ratio of MP12 and MP13 is designed to be equal to the ratio of their width-to-length ratios, that is:

[0046]

[0047] According to the current formula of the PMOS tube working in the saturation region:

[0048]

[0049] We can get:

[0050] V GS，MP12 =VGS，MP13

[0051] So:

[0052] V GS，MP16 =V GS，MP11

[0053] That is, the gate-source voltage of the output tube MP16 is equal to the gate-source voltage of MP11. If the width-to-length ratio of MP16 is M times the width-to-length ratio of MP11, then the current flowing through MP16 is also M times the current flowing through MP11.

[0054] The current source mirror tube MN7 of MP11 is "copied" and is recorded as IB7. Then the static circuit of the output stage NMOS tube MN12 is M*IB7.

[0055] For an NMOS translinear loop:

[0056] NMOS tubes MN8, MN10, MN11, and MN12 form a translinear loop, and their gate-source voltages have the following relationship:

[0057] V GS，MN8 +V GS，MN10 =V GS，MN11 +V GS，MN12

[0058] Without considering the secondary effects such as channel length modulation effect and body effect, if the current ratio of MN10 and MN11 is designed to be equal to the ratio of their width-to-length ratios, that is:

[0059]

[0060] According to the current formula of NMOS tube working in saturation region:

[0061]

[0062] We can get:

[0063] V GS，MN10 =V GS，MN11

[0064] So:

[0065] V GS，MN8 =V GS，MN12

[0066] That is, the gate-source voltage of the output tube MN12 is equal to the gate-source voltage of MN8. If the width-to-length ratio of MN12 is M times the width-to-length ratio of MN8, then the current flowing through MN12 is also M times the current flowing through MN8.

[0067] The current source mirror tube MP14 of MN8 is "copied" and recorded as IB14. Then the static circuit of the output stage NMOS tube MN12 is M*IB14.

[0068] In summary, the translinear loop structure determines the quiescent current of the output stage and can achieve low quiescent power consumption.

[0069] like Figure 3 As shown in the figure, when the LDO needs to output a current, the output voltage decreases, and is fed back to the input of the error amplifier through the feedback network of R1 and R2, and then output to the translinear loop of the next stage, so that the voltage at point B decreases, the power tube MN12 is turned off, and the current drawn by the power tube MN12 decreases. At the same time, the voltage at point A decreases, so that the PMOS tube MP13 is turned off.

[0070] like Figure 3 As shown in the figure, when the LDO needs to extract a current, the output voltage increases, and is fed back to the input of the error amplifier through the feedback network of R1 and R2, and then output to the translinear loop of the next stage, so that the voltage at point A increases, the power tube MP16 is turned off, and the output current of the power tube MP16 decreases. At the same time, the voltage at point B increases, so that the NMOS tube MN11 is turned off.

[0071] Therefore, the LDO structure of the present invention can meet the requirements of charging and discharging.

[0072] For the stability and fast transient response analysis of the entire LDO:

[0073] The LDO structure of the present invention has two loops, namely a current loop and a voltage loop. Figure 3 The blue line shows that when the load resistance R L When the resistance value decreases instantaneously, the output voltage VOUT of the LDO will be pulled down, so that the feedback voltage generated by the resistors R1 and R2 on the VOUT voltage division will be reduced. After being adjusted by the error amplifier, the output voltage of the error amplifier will increase, that is, the gate voltage of MP15 will increase, the voltage at point B will decrease, and the power tube MN12 will be cut off. At the same time, the voltage at point A decreases, which increases the degree of opening of the power tube MP16, further increasing the load capacity of the LDO and making the output voltage VOUT of the LDO stable. When the load resistor R L When the resistance value increases instantaneously, the output voltage VOUT of the LDO will be increased, so that the feedback voltage generated by the resistors R1 and R2 for the VOUT voltage division will increase. After being adjusted by the error amplifier, the output voltage of the error amplifier will decrease, that is, the gate voltage of MP15 will decrease, so that the voltage at point A will be above, and the power tube MP16 will be turned off. At the same time, the voltage at point B will increase, so that the opening degree of the power tube MN12 will increase, further reducing the load capacity of the LDO, and making the output voltage VOUT of the LDO stable.

[0074] Voltage loop such as Figure 3 The red line in the middle shows that when the load resistance R L When the resistance value decreases instantaneously, the output voltage VOUT of the LDO will be pulled down, so that the feedback voltage generated by the resistors R1 and R2 for the VOUT voltage division will be reduced. After being adjusted by the error amplifier, the output voltage of the error amplifier will increase, that is, the gate voltage of MP15 will increase, so the source voltage of MP15 will also increase, which can quickly offset the reduction of VOUT caused by the load change, so that the output voltage VOUT of the LDO will quickly stabilize. L When the resistance value increases instantaneously, the output voltage VOUT of the LDO will be increased, causing the feedback voltage generated by the resistors R1 and R2 on the VOUT voltage division to increase. After being adjusted by the error amplifier, the output voltage of the error amplifier will decrease, that is, the gate voltage of MP15 will decrease, so the source voltage of MP15 will also decrease, which can quickly offset the increase in VOUT caused by the load change, so that the output voltage VOUT of the LDO will quickly stabilize.

[0075] Therefore, the existence of the two loops greatly improves the stability and fast transient response capability of the LDO structure of the present invention.

[0076] The structure loop of the LDO of the present invention mainly has three poles, namely P1, P2, and P3, and the positions are as follows: Figure 3 shown.

[0077]

[0078]

[0079]

[0080] Where R eq,1 is the total output resistance of the error amplifier, C eq,1 is the total equivalent capacitance of the MP15 gate node, including the equivalent capacitance of MN13 and other parasitic capacitances at this node. eq,2 is the total equivalent resistance of the gate node of power tube MP16, C eq,2 is the total equivalent capacitance of the gate node of power tube MP16. eq,3 is the total equivalent resistance of the output node VOUT, C eq,3 is the total equivalent capacitance of the output node VOUT.

[0081] MN13 is introduced at the output node of the error amplifier. MN13 is relatively large, which is equivalent to a large capacitor, making C eq,1 The P1 frequency is pushed to a low frequency. The size of MN13 is set appropriately to ensure that P1 is the dominant pole in the full load range.

[0082] Since the resistance of R3 is much smaller than the impedance r of the MOS current source o , then the resistance of the equivalent resistor Req,2 is approximately equal to R3, that is,

[0083] R eq，2 ≈R3

[0084] By setting the resistance value of R3 reasonably, P2 can be pushed to high frequency to ensure that the main pole is P1.

[0085] The structures MP15, MP16, MN9, and MN12 of the LDO of the present invention are equivalent to parallel negative feedback structures. The additional parallel negative feedback mechanism can make the output impedance R of the VOUT node out Further reduce.

[0086]

[0087] R eq，3 =R out / / R L / / R FB

[0088] R out The reduction of R eq,3 Reduced, so that the secondary point frequency position of the output node can be pushed to a higher frequency, ensuring that the main pole is P1.

[0089] Compared with the main pole position of the traditional LDO structure, the change of the main pole of the LDO structure of the present invention can reduce the influence of the load on the stability of the entire circuit. Therefore, the LDO structure of the present invention has good stability.

[0090] The simulation results of the technical solution of the present invention are described in detail below in conjunction with the accompanying drawings.

[0091] based on Figure 3 The simulation results of the example show that:

[0092] The input and output characteristics of the LDO structure of the present invention are as follows: Figure 5 As shown, when the VDD voltage is 4.2V, the VOUT output voltage is 4.1871V, and when the VDD voltage is 6V, the VOUT output voltage is 4.18727V.

[0093] The simulation results of the traditional LDO structure example show that:

[0094] Comparison of the linear adjustment capabilities of the conventional LDO structure and the LDO structure of the present invention Figure 6 The linear adjustment curve of the traditional LDO structure is shown as a dotted line, and the linear adjustment curve of the LDO structure of the present invention is shown as a solid line.

[0095] The linear regulation rate of the traditional LDO structure is:

[0096]

[0097] The linear adjustment rate of the LDO structure of the present invention is:

[0098]

[0099] The smaller the linear regulation rate is, the smaller the impact of the input voltage change on the output voltage is. Therefore, the linear regulation performance of the LDO structure of the present invention is greatly improved.

[0100] The power supply rejection ratio comparison between the conventional LDO structure and the LDO structure of the present invention is as follows: Figure 7 The power rejection ratio of the conventional LDO structure is shown by the dotted line, and the power rejection ratio of the LDO structure of the present invention is shown by the solid line.

[0101] When the frequency is low, about 10 Hz, the power supply rejection ratio of the conventional LDO structure is about -56.2546 dB, and the power supply rejection ratio of the LDO structure of the present invention is about -92.1917 dB. Therefore, the power supply rejection capability of the LDO structure of the present invention is greatly improved.

[0102] The temperature characteristics of the conventional LDO structure and the LDO structure of the present invention are compared as follows: Figure 8 The temperature characteristic curve of the traditional LDO structure is shown as a dotted line, and the temperature characteristic curve of the LDO structure of the present invention is shown as a solid line.

[0103] When the temperature changes from -40°C to 125°C, the output voltage of the conventional LDO structure changes from 4.188152V to 4.196709V, and the output voltage changes with temperature by 8.557mV; the output voltage of the LDO structure of the present invention changes from 4.187138V to 4.187155V, and the output voltage changes with temperature by only 17.2μV. Therefore, the temperature characteristics of the LDO structure of the present invention are better, and the temperature coefficient is lower.

[0104] The loop amplitude-frequency characteristic and phase-frequency characteristic of the LDO of the present invention are as follows: Fig. 9 The dotted line represents the change of the loop gain with frequency in the form of dB20, and the solid line represents the change of the loop phase with frequency.

[0105] Depend on Fig. 9 It can be obtained that the low-frequency gain of the LDO of the present invention is about 75.7046 dB, and the phase margin is about 87.28°.

[0106] Therefore, the LDO structure of the present invention has better loop stability, and good amplitude-frequency characteristic and phase-frequency characteristic indicators.

[0107] The load transient response curve of the LDO structure of the present invention is as follows: Fig.10 As shown. The dotted line is the step change curve of the load current from -30mA to 30mA at 30mA / μs, and the solid line is the transient response curve of the output voltage as the load current changes. When the load current changes from -30mA to 0A, the output voltage deviation of the LDO structure of the present invention is only 24.50903mV, and the settling time is about 2μs; when the load current changes from 0A to 30mA, the output voltage deviation of the LDO structure of the present invention is 20.719228mV, and the settling time is about 1.8μs.

[0108] Comparison of the load transient response curve of the traditional LDO structure and the load transient response curve of the LDO structure of the present invention Fig.11 As shown, the dotted line I_Load represents the load current positive and negative step change from 100μA to 100mA at 100mA / μs, the dotted line Traditional_LDO_VOUT represents the load transient response curve of the traditional LDO structure, and the solid line LDO_VOUT represents the load transient response curve of the LDO structure of the present invention.

[0109] When the load current changes from 100μA to 100mA within 1μs, the output voltage deviation of the traditional LDO structure is about 781.263mV, and the settling time is about 2.5μs; the output voltage deviation of the LDO structure of the present invention is only 88.7536mV, and the settling time is about 2.1μs.

[0110] When the load current changes from 100mA to 100μA within 1μs, the output voltage deviation of the traditional LDO structure is about 810.057mV, and the settling time is about 3μs; the output voltage deviation of the LDO structure of the present invention is only 102.677mV, and the settling time is about 2μs.

[0111] Therefore, the structure of the LDO of the present invention has better load transient response.

[0112] The above embodiment is only one of the preferred implementation modes of the present invention and should not be used to limit the protection scope of the present invention. Any changes or modifications that are made to the main design concept and spirit of the present invention and have no substantive significance, and the technical problems they solve are still consistent with the present invention, should be included in the protection scope of the present invention.

Claims

1. A low static power consumption LDO circuit, characterized in that: It includes a bias circuit, an error amplifier, a translinear loop, a CLASS-AB output stage, a resistor feedback network and an output load which are connected in sequence; the error amplifier is also connected to the resistor feedback network; The translinear loop is composed of a PMOS translinear loop and an NMOS translinear loop, a current source mirror tube MN7, a current source mirror tube MP14 and a resistor R3; the translinear loop receives the error signal amplified by the error amplifier, and its output signal is used to drive the CLASS-AB output stage; The PMOS translinear loop is composed of PMOS tubes MP11, MP12, and MP13; wherein the gate of the PMOS tube MP11 is connected to the drain, the gate of the PMOS tube MP12 is connected to the drain, the gate of the PMOS tube MP12 is connected to the gate of the PMOS tube MP13, and the source of the PMOS tube MP13 is connected to the gate of the PMOS tube MP16; the source of the PMOS tube MP11 is connected to the error amplifier, the drain of the PMOS tube MP12 is connected to the drain of the current source mirror tube MN7, and the drain of the PMOS tube MP13 is connected to the NMOS translinear loop; the source of the PMOS tube MP13 is connected to one end of the resistor R3; and the other end of the resistor R3 is connected to the source of the PMOS tube MP11; The NMOS translinear loop is composed of NMOS tubes MN8, MN10, and MN11; wherein the gate and drain of the NMOS tube MN8 are connected, the source of the NMOS tube MN8 is connected to the power ground terminal GND, the drain of the NMOS tube MN8 is connected to the source of the NMOS tube MN10, the gate of the NMOS tube MN10 is connected to the gate of the NMOS tube MN11, the drain of the NMOS tube MN11 is connected to the source of the PMOS tube MP13, the gate and drain of the NMOS tube MN10 are connected and then connected to the drain of the current source mirror tube MP14, the drain of the NMOS tube MN9 is connected to the source of the NMOS tube MN11, the gate of the current source mirror tube MP14 is connected to the bias circuit, and the source of the current source mirror tube MP14 is connected to the power supply VCC terminal.

2. A low static power consumption LDO circuit according to claim 1, characterized in that: The bias circuit includes a low-voltage common-source common-gate current mirror structure composed of PMOS tubes MP1-MP6 and an NMOS tube MN1; wherein the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP2, the source of the PMOS tube MP1 is connected to the drain of the PMOS tube MP2, the source of the PMOS tube MP2 is connected to the source of the PMOS tube MP3, the source of the PMOS tube MP3 is connected to the source of the PMOS tube MP4, the gate of the PMOS tube MP3 is connected to the gate of the PMOS tube MP4, the source of the PMOS tube MP3 is connected to the source of the PMOS tube MP4 and both are connected to the power supply VCC terminal, the gate of the PMOS tube MP3 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP5, and the gate of the PMOS tube MP4 is connected to the gate of the PMOS tube MP5. The gate of MP6 is connected to the gate of PMOS tube MP5, the drain of PMOS tube MP4 is connected to the source of PMOS tube MP6, and the drain of NMOS tube MN1 is connected to the gate; the drain of PMOS tube MP6 is connected to the drain of NMOS tube MN1, the gate and drain of PMOS tube MP1 are connected and serve as port IB_N1 for receiving external bias current, the drain of MOS tube MP5 serves as port IB_N2 for receiving external bias current, the source of NMOS tube MN1 is the grounding GND port, and the source of PMOS tube MP2 is the VDD access port; the gate of PMOS tube MP4 and the gate of NMOS tube MN1 are both connected to the error amplifier, the translinear loop, the CLASS-AB output stage and the source, and the gate of PMOS tube MP5 is connected to the error amplifier.

3. A low static power consumption LDO circuit according to claim 2, characterized in that: The error amplifier is composed of NMOS tubes MN2 to MN6, PMOS tubes MP7 to MP10 and NMOS tube MN13; wherein the gate of NMOS tube MN2 is connected to the gate of NMOS tube MN1, the source of NMOS tube MN3 is connected to the drain of NMOS tube MN2, the source of NMOS tube MN4 is connected to the drain of NMOS tube MN2, the source of NMOS tube MN5 is connected to the source of NMOS tube MN2, the source of NMOS tube MN6 is connected to the source of NMOS tube MN5, the gate of NMOS tube MN6 is connected to the gate of NMOS tube MN5, the gate of PMOS tube MP7 is connected to the gate of PMOS tube MP4, the gate of PMOS tube MP7 is connected to the gate of PMOS tube MP8, the source of PMOS tube MP10 is connected to the drain of PMOS tube MP8 and the drain of NMOS tube MN4, the gate of PMOS tube MP9 is connected to the gate of PMOS tube MP10, the drain of PMOS tube MP10 is connected to the gate of PMOS tube MP11, and the gate of PMOS tube MP12 is connected to the gate of PMOS tube MP4. The gate of the NMOS tube MN3 is connected to the reference voltage VREF, the sources of the PMOS tubes MP7 and MP8 are connected to the source of the PMOS tube MP4, and the gate and drain of the NMOS tube MN5 are connected; the gate of the NMOS tube MN13 is connected to the drain of the PMOS tube MP10 and the CLASS-AB output stage, the drain of the PMOS tube MP16 is connected to the CLASS-AB output stage, the drain of the NMOS tube MN9 is connected to the CLASS-AB output stage, the gate of the NMOS tube MN2 is connected to the gate of the NMOS tube M7, the sources of the PMOS tubes MP7 and MP8 are connected to the sources of the PMOS tubes MP4 and MP11; the gate of the NMOS tube MN4 is connected to the resistor feedback network.

4. The low static power consumption LDO circuit according to claim 3, characterized in that: The CLASS-AB output stage includes PMOS tubes MP15 and MP16 and NMOS tubes MN9 and MN12; wherein the gate of the PMOS tube MP15 is connected to the drain of the PMOS tube MP10, the source of the PMOS tube MP15 is connected to the source of the PMOS tube MP16, and the drain of the PMOS tube MP15 is connected to the drain of the NMOS tube MN9; the gate of the NMOS tube MN12 is connected to the drain of the NMOS tube MN9, the drain of the NMOS tube MN12 is connected to the drain of the PMOS tube MP16, and the NMOS The source of the transistor MN12 is connected to the source of the NMOS transistor MN9; the PMOS transistor MP16 is used as the PMOS output adjustment transistor of CLASS-AB, and its source is connected to the power supply VCC terminal; the NMOS transistor MN12 is used as the NMOS output adjustment transistor of CLASS_AB, and its source is connected to the power supply ground GND terminal; the drain of the PMOS transistor MP16 is connected to the drain of the NMOS transistor MP12 and serves as the VOUT port; the drain of the NMOS transistor MN12 is connected to the resistor feedback network, and the source of the NMOS transistor MN12 is connected to the resistor feedback network.

5. The low static power consumption LDO circuit according to claim 4, characterized in that: The resistor feedback network is composed of voltage-dividing resistors R1 and R2. One end of the voltage-dividing resistor R1 is connected to the source of the PMOS tube MP15, the other end of the voltage-dividing resistor R1 is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the source of the NMOS tube MN12, and the common end of the voltage-dividing resistors R1 and R2 is also connected to the gate of the NMOS tube MN4.

6. A low static power consumption LDO circuit according to claim 5, characterized in that: The output end load comprises a load resistor RL and a load capacitor CL connected in parallel; wherein two ends of the load resistor RL are respectively connected to the source of the NMOS transistor MN12 and the source of the PMOS transistor MP15.

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