Low-power-consumption maximum voltage selection circuit with fast switching function

Abstract

The invention provides a low-power-consumption maximum voltage selection circuit with a fast switching function, and the circuit comprises a detection circuit which is used for comparing a first voltage signal with a second voltage signal, and outputting a comparison signal to an acceleration comparison circuit and the input end of a first logic gate circuit through a first node; the acceleration comparison circuit comprises a third control tube, a second logic gate circuit and a discharging circuit, the grid electrode of the third control tube is connected with a comparison signal, and the output end is connected to the input end of the second logic gate circuit through a second node; the second logic gate circuit outputs a first level signal to the discharge circuit along with the voltage rise / drop state of the second node so as to switch on a discharge loop of the first node. Through the acceleration comparison circuit and the quick response control circuit, the change of the input source voltage can be quickly responded, and the highest voltage output can be quickly selected, so that the effects of improving the reliability of the anti-backflow power tube substrate switching chip and not increasing extra quiescent current power consumption are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power consumption maximum voltage selection circuit with a fast switching function. Background Art

[0002] In the field of chip design, the power chip needs to switch the substrate voltage of the power tube to the highest voltage of the circuit for anti-backflow application considerations. Fast and low-power switching to the highest voltage helps improve the chip's performance and application reliability. Figure 1 , Figure 1 The invention is a commonly used maximum voltage selection circuit, which includes a detection circuit, a driving circuit and a selection circuit. The detection circuit includes resistors R1 and R2, common gate differential pairs MP1 and MP2, current mirror tubes MN1-MN4, switch tubes MNS1 and MNS2 and logic gates of the V_MAX domain; the driving circuit is composed of logic gates of the V_MAX domain and has a dead zone control processing function; the selection circuit is composed of M1 tube and M2 tube connected back to back, and the M1 tube and M2 tube output the maximum selection voltage V_MAX, which is the maximum voltage of the input voltage signals V1 and V2. Among them, resistors R1 and R2 can be used to set the thresholds of input voltage signals V1 and V2 and prevent electrostatic discharge (ESD); the common gate differential pair MP1 and MP2 and the current mirrors MN2 and MN3 constitute a common gate comparator; the switch tubes MNS2 and MN4 control the comparison threshold hysteresis voltage of the input voltage signals V1 and V2; the switch tube MNS1 controls the static current of the input source V1; the control signal SEL_V1 output by the detection circuit generates the maximum selection voltage V_MAX through the circuit drive and selection devices M1 and M2.

[0003] Among them, when the input voltage signal V2 has no voltage, only the input bias current (IBIAS) of the MN1 tube generates static power consumption. By controlling the bias current of the current mirrors MN2 and MN3, the static power consumption of the detection circuit can be controlled. Therefore, when the input voltage signal V2 has no voltage, the maximum voltage selection circuit has lower static power consumption. However, when the change amplitude of the input voltage signals V1 and V2 is relatively small, the delay time from the change of the input voltage signal to the control signal SEL_V1 is inconsistent at the rising edge and the falling edge. See Figure 2 , Figure 2This is a waveform diagram of the node voltage when the input amplitude of the low static current detection circuit changes slightly. It can be seen that the rising edge delay of the control signal SEL_V1 is large, and its falling edge delay is small, which results in a relatively long time for the maximum selection voltage V_MAX to switch from V2 to V1. Among them, the rising delay time of the control signal SEL_V1 is controlled by the discharge speed of the OUT_CMP node voltage (that is, controlled by the bias current of the MN3 tube). However, due to the low power consumption design of the circuit, the bias current of the MN3 tube is small, and the falling threshold of the Schmitt inverter is lower than V_MAX / 2, so the rising delay time of the control signal SEL_V1 is long, which leads to a long time for the maximum selection voltage V_MAX to switch from V2 to V1. However, if the delay time is reduced by increasing the current of the MN3 tube, the static current power consumption of the circuit will increase, which will be contrary to the original intention of the low static power consumption design.

[0004] In addition, in some special multi-voltage domain low static power design, Figure 1 The bias current IBIAS in the detection circuit shown will be equal to zero in some special cases, such as when the bias current IBIAS is generated by a voltage domain other than the V1 / V2 / V_MAX domain, and the voltage domain is not powered at this time. At this time, the common gate comparator composed of MP1 / MP2 and MN2 / MN3 will fail, and may generate an erroneous control signal SEL_V1, resulting in the output voltage V_MAX not being the maximum value. At this time, for power devices in the chip that require substrate switching, if their substrate voltage V_MAX is not the maximum value, the anti-backflow function will fail; at the same time, there may also be leakage of power tubes through parasitic diodes, and the conduction of parasitic PN junctions may induce latch-up and other problems that affect circuit reliability.

[0005] Therefore, it is necessary to design a maximum voltage selection circuit that can reduce switching delay time, achieve fast switching, improve circuit reliability and have lower static power consumption. Summary of the invention

[0006] The present invention provides a low-power maximum voltage selection circuit with a fast switching function, which is mainly used to solve the problems of inconsistent switching speed, long unilateral switching delay time, and reduced circuit reliability in a no-bias current scenario in the existing maximum voltage selection circuit in low-power design scenarios when the input source amplitude changes slightly, thereby achieving the effect of reducing the switching delay time, realizing fast switching, improving circuit reliability and having lower static power consumption.

[0007] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0008] A low-power maximum voltage selection circuit with a fast switching function includes a detection circuit, a drive circuit and a selection circuit, wherein the detection circuit inputs a first voltage signal and a second voltage signal respectively and is provided with a first logic gate circuit, and the selection circuit includes a first switch connected to the first voltage signal and a second switch connected to the second voltage signal, and further includes:

[0009] An accelerated comparison circuit and a fast response control circuit, wherein the detection circuit is used to compare the first voltage signal and the second voltage signal, and output a comparison signal to the input end of the accelerated comparison circuit and the first logic gate circuit through the first node; the accelerated comparison circuit includes a third control tube, a second logic gate circuit and a discharge circuit, the gate of the third control tube is connected to the comparison signal, and the output end thereof is connected to the input end of the second logic gate circuit through the second node; the second logic gate circuit outputs a first level signal to the discharge circuit according to the voltage rise / fall state of the second node to connect the discharge loop of the first node; the first logic gate circuit is used to output a second level signal to the drive circuit according to the voltage amplitude of the first node; the fast response control circuit includes a first drive control circuit and a second drive control circuit, and the drive circuit outputs a first drive signal and a second drive signal with opposite level logic to the first drive control circuit and the second drive control circuit respectively according to the second level signal; the first drive control circuit outputs a first control signal to the control end of the first switch, which is used to control the first switch to be turned on so as to output the first voltage signal as the maximum voltage; the second drive control circuit outputs a second control signal to the control end of the second switch, which is used to control the second switch to be turned on so as to output the second voltage signal as the maximum voltage.

[0010] Among them, the first drive control circuit is provided with a first threshold voltage, which is the absolute value of the second voltage signal, and is used to control the first switch to be turned off when the amplitude of the first voltage signal is lower than the first threshold voltage; the second drive control circuit is provided with a second threshold voltage, which is the absolute value of the first voltage signal, and is used to control the second switch to be turned off when the amplitude of the second voltage signal is lower than the second threshold voltage.

[0011] A further solution is that the detection circuit also includes a comparison circuit and a first bias circuit, the comparison circuit includes a first control tube and a second control tube forming a common gate differential pair, the sources of the first control tube and the second control tube are respectively connected to the first voltage signal and the second voltage signal, and their drains are connected to the first bias circuit.

[0012] A further solution is that the accelerated comparison circuit also includes a third switch tube and a second bias circuit, the gate of the third control tube is connected to the drain of the second control tube through the first node, and its drain is connected to the second bias circuit through the third switch tube, and the gate of the third switch tube is connected to the second voltage signal to shut down the static current of the circuit when the second voltage signal is not input.

[0013] A further solution is that the second logic gate circuit includes a first Schmitt inverter and a first NOR gate, the input end of the first Schmitt inverter is connected to the drain of the third control tube, and its output end is connected to the first input end of the first NOR gate, the second input end of the first NOR gate is connected to the second level signal, and its output end outputs the first level signal.

[0014] A further solution is that the discharge circuit includes a fifth switch tube and a seventh control tube, the gate of the fifth switch tube is connected to the output end of the first NOR gate, the drain is connected to the input end of the first logic gate circuit, and the source is connected to the drain of the seventh control tube; the gate of the seventh control tube is connected to the bias current, and the source is grounded.

[0015] A further solution is to increase the bias current input to the seventh control tube to increase the voltage drop speed of the first node during discharge, thereby shortening the rise time of the second level signal.

[0016] A further solution is that the first drive control circuit includes a first push-pull circuit, a first fast response control tube, and a third logic gate circuit. The first drive signal is processed by the first push-pull circuit and then output to the input end of the third logic gate circuit. The gate of the first fast response control tube is connected to the first voltage signal, the source thereof is connected to the second voltage signal, the drain thereof is connected to the input end of the third logic gate circuit, and the third logic gate circuit outputs the first control signal.

[0017] The second drive control circuit includes a second push-pull circuit, a second fast response control tube, and a fourth logic gate circuit. The second drive signal is processed by the second push-pull circuit and then output to the input end of the fourth logic gate circuit. The gate of the second fast response control tube is connected to the second voltage signal, the source thereof is connected to the first voltage signal, the drain thereof is connected to the input end of the fourth logic gate circuit, and the fourth logic gate circuit outputs the second control signal.

[0018] A further solution is that the fast response control circuit further includes two inverting level shift circuits with hysteresis, and the inverting level shift circuits are connected to the driving circuit for controlling the dead time of the driving circuit.

[0019] A further solution is that the driving circuit also includes a zero bias control circuit, which sets a control and judgment mechanism for the bias current through a logic gate circuit, and is used to output a third level signal to the driving circuit when the bias current is zero, and switch the first control signal and the second control signal to a high level output through the fast response control circuit.

[0020] A further solution is that the zero bias circuit control circuit includes a fourth control tube, a third Schmitt inverter, a first XNOR gate, a first NOT gate and a first AND gate, the third Schmitt inverter is connected to the first voltage signal through the fourth control tube, and its output end is connected to the first input end of the first XNOR gate, the second input end of the first XNOR gate is connected to the second level signal, and its output end is connected to the first input end of the AND gate, the second input end of the AND gate is connected to the bias current state signal through the NOT gate, and its output end outputs the third level signal.

[0021] It can be seen that the present invention has the following beneficial effects:

[0022] 1. The present invention accelerates the comparison circuit. When the first voltage signal V1 and the second voltage signal V2 of the input source change slightly, the first node voltage is quickly discharged by turning on the discharge circuit. Compared with the traditional maximum voltage selection circuit, the delay time from the change of the input source to the rising edge of the second Schmitt inverter outputting the second level signal SEL_V1 can be reduced, and then the maximum voltage V_MAX can be quickly switched from the second voltage signal V2 to the first voltage signal V1 output through the driving circuit.

[0023] 2. The acceleration comparison circuit of the present invention can be quickly turned off through the third switch tube MNS3 when the input source loses power, so no static power consumption is generated, and it only works intermittently during the flipping process of the second Schmitt inverter; at the same time, by setting the bias current of the MN7 tube, the circuit has lower static power consumption. It can be seen that this solution accelerates the switching speed of the maximum output voltage while the static power consumption of the circuit is also lower, which solves the design contradiction between low static power consumption and switching speed in the traditional solution.

[0024] 3. The present invention introduces the output source first voltage signal V1 and second voltage signal V2 into the output stage of the driving module for direct power supply through a fast response control circuit, thereby further accelerating the switching speed of the maximum voltage V_MAX when the first voltage signal V1 and the second voltage signal V2 change greatly, thereby improving the reliability of the anti-backflow power tube substrate switching chip without increasing additional static current power consumption.

[0025] 4. The present invention aims at special low-power application scenarios where the bias current may be zero. The zero bias current control circuit identifies the erroneous state of the output level SEL_V1 of the second Schmitt inverter when the bias current is zero, and superimposes the logic control of the fast response control module to ensure the correct output of the maximum voltage V_MAX.

[0026] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a maximum voltage selection circuit in the prior art.

[0028] Figure 2 It is a voltage waveform diagram of a key node in a maximum voltage selection circuit in the prior art when the input signal changes slightly.

[0029] Figure 3 Schematic diagram of a maximum voltage selection circuit for low power consumption and fast switching in an embodiment of the present invention.

[0030] Figure 4 It is a schematic diagram of a maximum voltage selection circuit for low power consumption and fast switching in an embodiment of the present invention.

[0031] Figure 5 It is a voltage waveform diagram of a key node in the circuit when the input signal changes slightly in an embodiment of the present invention.

[0032] Figure 6 It is a schematic diagram of the first drive control circuit / the second drive control circuit in an embodiment of the present invention.

[0033] Figure 7 It is a flow chart of the zero bias current control judgment mechanism in an embodiment of the present invention.

[0034] Figure 8 It is an equivalent circuit of the maximum voltage selection circuit in the embodiment of the present invention when the zero bias is recognized as an error state. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] A low power consumption maximum voltage selection circuit embodiment with fast switching function

[0037] See also Figure 3-4 The present invention relates to a low-power maximum voltage selection circuit with a fast switching function, comprising a detection circuit 10, a drive circuit 20 and a selection circuit 30. The detection circuit 10 inputs a first voltage signal V1 and a second voltage signal V2 respectively, and is provided with a first logic gate circuit. The selection circuit 30 includes a first switch M1 connected to the first voltage signal V1, a second switch M2 connected to the second voltage signal V2, and further includes:

[0038] The acceleration comparison circuit 40 and the fast response control circuit 50, the detection circuit 10 is used to compare the first voltage signal V1 and the second voltage signal V2, and output the comparison signal to the input end of the acceleration comparison circuit 40 and the first logic gate circuit respectively through the first node OUT_CMP; the acceleration comparison circuit 40 includes a third control tube MP3, a second logic gate circuit and a discharge circuit, the gate of the third control tube MP3 is connected to the comparison signal, and the output end thereof is connected to the input end of the second logic gate circuit through the second node OUT_FAST; the second logic gate circuit outputs a first level signal SPD to the discharge circuit to connect the discharge loop of the first node OUT_CMP according to the voltage rise / fall state of the second node OUT_FAST; the first logic gate circuit is used to output a first level signal SPD to the discharge circuit according to the voltage rise / fall state of the first node OUT_CMP The voltage amplitude outputs a second level signal SEL_V1 to the driving circuit 20; the fast response control circuit 50 includes a first driving control circuit 51 and a second driving control circuit 52. The driving circuit 20 outputs a first driving signal and a second driving signal with opposite level logics to the first driving control circuit 51 and the second driving control circuit 52 respectively according to the second level signal SEL_V1; the first driving control circuit 51 outputs a first control signal DRV_M1 to the control end of the first switch M1, which is used to control the first switch M1 to be turned on so as to output the first voltage signal V1 as the maximum voltage V_MAX; the second driving control circuit 52 outputs a second control signal DRV_M2 to the control end of the second switch M2, which is used to control the second switch M2 to be turned on so as to output the second voltage signal V2 as the maximum voltage V_MAX.

[0039] Among them, the first drive control circuit 51 is provided with a first threshold voltage, which is the absolute value of the second voltage signal V2, and is used to control the first switch M1 to be turned off when the amplitude of the first voltage signal V1 is lower than the first threshold voltage; the second drive control circuit 52 is provided with a second threshold voltage, which is the absolute value of the first voltage signal V1, and is used to control the second switch M2 to be turned off when the amplitude of the second voltage signal V2 is lower than the second threshold voltage.

[0040] In this embodiment, the detection circuit 10 also includes a comparison circuit and a first bias circuit. The comparison circuit includes a first control tube MP1 and a second control tube MP2 forming a common gate differential pair. The sources of the first control tube MP1 and the second control tube MP2 are respectively connected to the first voltage signal V1 and the second voltage signal V2, and the drains are connected to the first bias circuit.

[0041] Specifically, in this embodiment, the first control transistor MP1 , the second control transistor MP2 , and the third control transistor MP3 are all PMOS transistors.

[0042] Specifically, the comparison circuit of this embodiment also includes a first resistor R1, a second resistor R2 and a first switch tube MNS1, the first resistor R1 is connected to the source of the first control tube MP1, and the comparison threshold of the input first voltage signal V1 is changed by adjusting the resistance value of the first resistor R1; the second resistor R2 is connected to the source of the first control tube, and the comparison threshold of the input second voltage signal V2 is changed by adjusting the resistance value of the second resistor R2; the gate of the first switch tube MNS1 is connected to the second voltage signal V2, and is used to shut down the static current of the circuit when the second voltage signal V2 is not input.

[0043] Specifically, the first bias circuit of this embodiment includes MN1-MN4 transistors constituting a current mirror, MN1-MN4 transistors are all NMOS transistors, their gates are all connected to the bias current IBIAS, and their sources are all grounded. The drain of MN2 transistor is connected to the source of the first switch transistor MNS1, and the drain of MN3 transistor is connected to the drain of the second control transistor MP2 via the first node OUT_CMP.

[0044] Specifically, the first logic gate circuit of this embodiment includes a second Schmitt inverter U2 and a second switch tube MNS2. The input end of the second Schmitt inverter U2 is connected to the first node OUT_CMP and to the drain of the fifth switch tube MNS5. The drain and gate of the second switch tube MNS2 are connected in parallel to the input and output ends of the second Schmitt inverter U2, and its source is connected to the drain of the MN4 tube.

[0045] In this embodiment, the acceleration comparison circuit 40 further includes a third switch tube MNS3 and a second bias circuit. The gate of the third control tube MP3 is connected to the drain of the second control tube MP2 through the first node OUT_CMP, and the drain is connected to the second bias circuit through the third switch tube MNS3. The gate of the third switch tube MNS3 is connected to the second voltage signal V2, so as to shut down the quiescent current of the circuit when the second voltage signal V2 is not input.

[0046] In this embodiment, the second logic gate circuit includes a first Schmitt inverter U1 and a first NOR gate NOR1, the input end of the first Schmitt inverter U1 is connected to the drain of the third control tube MP3, and the output end is connected to the first input end of the first NOR gate NOR1, the second input end of the first NOR gate NOR1 is connected to the second level signal SEL_V1, and the output end outputs the first level signal SPD.

[0047] Specifically, the acceleration comparison circuit 40 of this embodiment also includes a fourth switch tube MNS4, which is a hysteresis control switch tube, whose gate is connected to the first input terminal of the first NOR gate NOR1, whose drain is connected to the source of the third switch tube MNS3, and whose source is connected to the second bias circuit, and is used to introduce a hysteresis characteristic to maintain the stability of the circuit output state and avoid frequent switching of the output first level signal SPD state due to small amplitude signal fluctuations.

[0048] Specifically, the second bias circuit of this embodiment includes MN5 and MN6 transistors constituting a current mirror, both of which are NMOS transistors, whose gates are connected to the bias current IBIAS, and whose sources are grounded. The drain of MN5 is connected to the source of the third switch tube MNS3, and the drain of MN6 is connected to the source of the fourth switch tube MNS4, for setting their operating points.

[0049] In this embodiment, the discharge circuit includes a fifth switch tube MNS5 and a seventh control tube MN7. The gate of the fifth switch tube MNS5 is connected to the output end of the first NOR gate NOR1, the drain of the fifth switch tube MNS5 is connected to the input end of the first logic gate circuit, and the source of the fifth switch tube MNS5 is connected to the drain of the seventh control tube MN7. The gate of the seventh control tube MN7 is connected to the bias current IBIAS, and the source of the fifth switch tube MN7 is grounded.

[0050] In this embodiment, the bias current input to the seventh control transistor MN7 is increased to increase the voltage drop speed of the first node OUT_CMP during discharge, thereby shortening the rising time of the second level signal SEL_V1.

[0051] Specifically, the working process of the acceleration comparison circuit 40 in this embodiment is as follows:

[0052] When the voltage of the first node OUT_CMP drops to a value lower than the V_MAX voltage minus the absolute threshold voltage of the third control tube MP3, the third control tube MP3 is turned on. At this time, the voltage of the second node OUT_FAST rises rapidly, and the first level signal SPD output by the second logic gate circuit turns high rapidly, thereby turning on the fifth switch tube MNS5. At this time, the voltage of the first node OUT_CMP is discharged rapidly through the current mirror discharge path.

[0053] See also Figure 5The voltage drop speed of the first node OUT_CMP is controlled by the current of the MN3 tube and the MN7 tube. Considering the low power design, without increasing the current of the MN3 tube, the bias current IBIAS of the MN7 tube is increased to make the first node OUT_CMP drop quickly below the falling threshold of the second Schmitt inverter U2 of the next stage, thereby reducing the delay time from the change of the input source voltage to the high change of the second level signal SEL_V1; at the same time, when the second voltage signal V2 is not input, the static current of the circuit is turned off by the third switch tube MNS3, thereby reducing the static power consumption of the circuit in the discharge state.

[0054] See also Figure 6 In this embodiment, the first drive control circuit 51 includes a first push-pull circuit, a first fast response control tube, and a third logic gate circuit. The first drive signal is processed by the first push-pull circuit and then output to the input end of the third logic gate circuit. The gate of the first fast response control tube is connected to the first voltage signal V1, the source thereof is connected to the second voltage signal V2, and the drain thereof is connected to the input end of the third logic gate circuit. The third logic gate circuit outputs a first control signal DRV_M1.

[0055] The second drive control circuit 52 includes a second push-pull circuit, a second fast response control tube, and a fourth logic gate circuit. The second drive signal is processed by the second push-pull circuit and then output to the input end of the fourth logic gate circuit. The gate of the second fast response control tube is connected to the second voltage signal V2, the source thereof is connected to the first voltage signal V1, the drain thereof is connected to the input end of the fourth logic gate circuit, and the fourth logic gate circuit outputs a second control signal DRV_M2.

[0056] Specifically, the circuit structures of the first push-pull circuit and the second push-pull circuit in this embodiment are consistent. Figure 6 A push-pull circuit with P at the top and N at the bottom is used to invert and amplify the first drive signal or the second drive signal and then output it to the input end of the fourth logic gate circuit through the third node INB.

[0057] Specifically, in this embodiment, the common drain connection line of the upper and lower tubes in the first push-pull circuit and the second push-pull circuit is connected in series with a current limiting resistor R LIM .

[0058] Specifically, the third logic gate circuit and the fourth logic gate circuit of this embodiment both include two first-stage inverters and second-stage inverters connected in series.

[0059] Specifically, the control tube in this embodiment includes but is not limited to a MOS tube / a transistor BJT.

[0060] Specifically, this embodiment takes the initial V_MAX=V2 as an example to illustrate the working process of the fast response control circuit 50 as follows:

[0061] See also Figure 6 At this time, the MPS tube in the figure is the second fast response control tube, Vx=V2, the first voltage signal V1 is input to the power supply end, the first control signal DRV_M1 output by the first drive control circuit 51 is high level, that is, DRV_M1=V2, and the second control signal DRV_M2 output by the second drive control circuit 52 is low level; when the second voltage signal V2 is rapidly reduced to the threshold voltage of the second fast response control tube (that is, the absolute value of the first voltage signal V1), the second fast response control tube is turned on, and at this time the voltage of the third node INB is forcibly pulled up, the second control signal DRV_M2 is switched to a high level, that is, DRV_M2=V1, and the second switch M2 is turned off; at the same time, the first control signal DRV_M1 output by the first drive control signal is switched to a low level, the first switch M1 is turned on, so that the maximum voltage is switched to the first voltage signal V1 output, that is, V_MAX=V1.

[0062] Among them, when the comparison result of the previous stage does not respond in time, the input second drive signal is still at a high level. At this time, there is a second fast response control tube through the current limiting resistor R LIM The conduction path to the second push-pull circuit NMOS tube is set by setting the current limiting resistor R LIM The resistance value is:

[0063] R LIM +R dson_MNS >>R dson_MPS

[0064] Among them, R LIM is the current limiting resistor R LIM Value, R dson_MNS is the on-resistance of the NMOS tube of the second push-pull circuit, R dson_MPS is the on-resistance of the second fast response control tube.

[0065] That is, the voltage of the third node INB can be pulled to an effective high level to prevent the second-stage inverter from leaking electricity and reduce the power consumption of the first-stage inverter.

[0066] Among them, when the second level signal SEL_V1 output by the current stage detection circuit 10 becomes high, the first control signal DRV_M1 output after the driving circuit 20 and the fast response control circuit 50 is low level, and the second control signal DRV_M2 is also high level and equal to the first voltage signal V1, so the second driving control circuit 52 has no static current power consumption.

[0067] The above working process is vice versa. When V_MAX=V1 at the beginning, when the first voltage signal V1 drops rapidly to a voltage lower than the threshold voltage of the first fast response control tube (i.e., the absolute value of the second voltage signal V2), the first control signal DRV_M1 switches to a high level, i.e., DRV_M1=V2, and the first switch M1 is turned off; at the same time, the second control signal DRV_M2 switches to a low level, and the second switch M2 is turned on, so that the maximum voltage is switched to the second voltage signal V2 output, i.e., V_MAX=V2.

[0068] In this embodiment, the fast response control circuit 50 further includes two inverting level shift circuits with hysteresis, and the inverting level shift circuits are connected to the driving circuit 20 for controlling the dead time of the driving circuit 20 .

[0069] Specifically, the driving circuit 20 of this embodiment includes a second NOT gate NOT2, a first driving circuit and a second driving circuit with the same circuit structure, and the second level signal SEL_V1 is connected to the second driving circuit and connected to the first driving circuit through the second NOT gate NOT2.

[0070] Wherein, the first driving circuit comprises a second NOR gate NOR2, a third NOT gate NOT3 and a fourth NOR gate NOR4, a first input end of the second NOR gate NOR2 is connected to the output end of the first NOT gate NOT1, a second input end thereof is connected to the output end of the second driving control circuit 52 through an inverting level shift circuit, an output end thereof is connected to the first input end of the fourth NOR gate NOR4 through the third NOT gate NOT3, and a second input end of the fourth NOR gate NOR4 is connected to the third level signal ERROR outputted from the zero bias control circuit 60;

[0071] Among them, the second driving circuit includes a third NOR gate NOR3, a fourth NOT gate NOT4 and a fifth NOR gate NOR5, the first input end of the third NOR gate NOR3 is connected to the second level signal SEL_V1, the second input end is connected to the output end of the first driving control circuit 51 through another inverting level shift circuit, the output end is connected to the first input end of the fifth NOR gate NOR5 through the fourth NOT gate NOT4, and the second input end of the fifth NOR gate NOR5 is connected to the third level signal ERROR output from the zero bias control circuit 60.

[0072] In this embodiment, the driving circuit 20 also includes a zero bias control circuit 60, which sets a control judgment mechanism for the bias current IBIAS through a logic gate circuit, and is used to output a third level signal ERROR to the driving circuit 20 when the bias current IBIAS is zero, and switch the first control signal DRV_M1 and the second control signal DRV_M2 to high level output through the fast response control circuit 50.

[0073] In this embodiment, the zero bias circuit control circuit includes a fourth control tube MP4, a third Schmitt inverter U3, a first XNOR gate X1, a first NOT gate NOT1 and a first AND gate A1. The third Schmitt inverter U3 is connected to the first voltage signal V1 through the fourth control tube MP4, and its output end is connected to the first input end of the first XNOR gate X1. The second input end of the first XNOR gate X1 is connected to the second level signal SEL_V1, and its output end is connected to the first input end of the AND gate. The second input end of the AND gate is connected to the bias current IBIAS state signal through the NOT gate, and its output end outputs the third level signal ERROR.

[0074] Specifically, this embodiment further includes a MN8 tube, the drain of the MN8 tube is connected to the drain of the fourth control tube MP4, and the gate and source of the MN8 tube are grounded.

[0075] Specifically, when the bias current IBIAS in the detection circuit 10 is 0, the voltage of the first node OUT_CMP has no current mirror discharge path. Only when the input second voltage signal V2 is low, the voltage of the first node OUT_CMP will be discharged to the outside through the parasitic PN junction diode of the second control tube MP2. Accordingly, the present embodiment introduces the bias current IBIAS judgment signal IBIAS_OK, and the zero bias current judgment logic is: when IBIAS_OK=0, SEL_V1=1, and the error judgment result signal IBIAS_OKB=1 is output; at the same time, the state of the input source first voltage signal V2 is detected and the detection signal SEL_V2 is output, the first XNOR gate X1 inputs the second level signal SEL_V1 and the detection signal SEL_V2 and outputs the control signal ERR_ZB, and the control signal ERR_ZB and the error judgment result signal IBIAS_OKB pass through the first AND gate A1 and then output the third level signal ERROR, and its zero bias current judgment logic is shown in Table 1.

[0076] Table 1 Zero bias current judgment logic table

[0077] SEL_V2 SEL_V1 OUT_PUT 0 0 ERROR 0 1 SEL_V1 1 0 SEL_V1 1 1 ERROR

[0078] When the third level signal ERROR is at a high level, the first drive signal outputted by the fourth NOR gate NOR4 in the drive circuit 20 is at a high level, that is, DRV_M1=V2, and the second drive signal outputted by the fifth NOR gate NOR5 is also at a high level, that is, DRV_M2=V1. At this time, the equivalent circuit of the drive stage and the selection circuit 30 is as follows: Figure 8As shown in the figure, the selection circuit 30 is equivalent to the simplest comparator circuit architecture without bias current IBIAS, and the maximum voltage can still normally select the maximum voltage output when the voltage difference between the first voltage signal V1 and the second voltage signal V2 of the input source is large, so as to ensure that the output voltage is the maximum value between the first voltage signal V1 and the second voltage signal V2.

[0079] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A low-power maximum voltage selection circuit with a fast switching function, comprising a detection circuit, a drive circuit and a selection circuit, wherein the detection circuit inputs a first voltage signal and a second voltage signal respectively and is provided with a first logic gate circuit, and the selection circuit comprises a first switch connected to the first voltage signal and a second switch connected to the second voltage signal, characterized in that: Also includes: An accelerated comparison circuit and a fast response control circuit, wherein the detection circuit is used to compare the first voltage signal and the second voltage signal, and output a comparison signal to the input ends of the accelerated comparison circuit and the first logic gate circuit respectively through the first node; the accelerated comparison circuit comprises a third control tube, a second logic gate circuit and a discharge circuit, the gate of the third control tube is connected to the comparison signal, and the output end thereof is connected to the input end of the second logic gate circuit through the second node; the second logic gate circuit outputs a first level signal to the discharge circuit to connect the discharge loop of the first node according to the voltage rise / fall state of the second node; the first logic gate circuit is used to output a second level signal to the drive circuit according to the voltage amplitude of the first node; The fast response control circuit comprises a first drive control circuit and a second drive control circuit, wherein the drive circuit outputs a first drive signal and a second drive signal with opposite level logics to the first drive control circuit and the second drive control circuit respectively according to the second level signal; The first drive control circuit outputs a first control signal to the control end of the first switch, so as to control the first switch to be turned on so as to output the first voltage signal as the maximum voltage; The second drive control circuit outputs a second control signal to the control end of the second switch, so as to control the second switch to be turned on so as to output the second voltage signal as the maximum voltage; Among them, the first drive control circuit is provided with a first threshold voltage, which is the absolute value of the second voltage signal, and is used to control the first switch to be turned off when the amplitude of the first voltage signal is lower than the first threshold voltage; the second drive control circuit is provided with a second threshold voltage, which is the absolute value of the first voltage signal, and is used to control the second switch to be turned off when the amplitude of the second voltage signal is lower than the second threshold voltage.

2. The maximum voltage selection circuit for low power consumption and fast switching according to claim 1, characterized in that: The detection circuit also includes a comparison circuit and a first bias circuit. The comparison circuit includes a first control tube and a second control tube forming a common-gate differential pair. The sources of the first control tube and the second control tube are respectively connected to the first voltage signal and the second voltage signal, and their drains are connected to the first bias circuit.

3. The maximum voltage selection circuit for low power consumption and fast switching according to claim 2, characterized in that: The accelerated comparison circuit also includes a third switch tube and a second bias circuit. The gate of the third control tube is connected to the drain of the second control tube through the first node, and its drain is connected to the second bias circuit through the third switch tube. The gate of the third switch tube is connected to the second voltage signal to shut down the static current of the circuit when the second voltage signal is not input.

4. The maximum voltage selection circuit for low power consumption and fast switching according to claim 1, characterized in that: The second logic gate circuit includes a first Schmitt inverter and a first NOR gate, the input end of the first Schmitt inverter is connected to the drain of the third control tube, and the output end is connected to the first input end of the first NOR gate, the second input end of the first NOR gate is connected to the second level signal, and the output end outputs the first level signal.

5. The maximum voltage selection circuit for low power consumption and fast switching according to claim 4, characterized in that: The discharge circuit includes a fifth switch tube and a seventh control tube. The gate of the fifth switch tube is connected to the output end of the first NOR gate, the drain of the fifth switch tube is connected to the input end of the first logic gate circuit, and the source of the fifth switch tube is connected to the drain of the seventh control tube. The gate of the seventh control tube is connected to the bias current, and the source of the fifth switch tube is grounded.

6. The maximum voltage selection circuit for low power consumption and fast switching according to claim 5, characterized in that: By increasing the bias current input to the seventh control tube, the voltage drop speed of the first node during discharge is increased, thereby shortening the rising time of the second level signal.

7. The maximum voltage selection circuit for low power consumption and fast switching according to claim 1, characterized in that: The first drive control circuit includes a first push-pull circuit, a first fast response control tube, and a third logic gate circuit. The first drive signal is processed by the first push-pull circuit and then output to the input end of the third logic gate circuit. The gate of the first fast response control tube is connected to the first voltage signal, the source of the first fast response control tube is connected to the second voltage signal, and the drain of the first fast response control tube is connected to the input end of the third logic gate circuit. The third logic gate circuit outputs the first control signal. The second drive control circuit includes a second push-pull circuit, a second fast response control tube, and a fourth logic gate circuit. The second drive signal is processed by the second push-pull circuit and then output to the input end of the fourth logic gate circuit. The gate of the second fast response control tube is connected to the second voltage signal, the source thereof is connected to the first voltage signal, the drain thereof is connected to the input end of the fourth logic gate circuit, and the fourth logic gate circuit outputs the second control signal.

8. The maximum voltage selection circuit for low power consumption and fast switching according to claim 7, characterized in that: The fast response control circuit also includes two inverting level shift circuits with hysteresis, and the inverting level shift circuits are connected to the driving circuit and are used for dead time control of the driving circuit.

9. The maximum voltage selection circuit for low power consumption and fast switching according to any one of claims 1 to 8, characterized in that: The driving circuit also includes a zero bias control circuit, which sets a control judgment mechanism for the bias current through a logic gate circuit, and is used to output a third level signal to the driving circuit when the bias current is zero, and switch the first control signal and the second control signal to a high level output through the fast response control circuit.

10. The maximum voltage selection circuit for low power consumption and fast switching according to claim 9, characterized in that: The zero bias circuit control circuit includes a fourth control tube, a third Schmitt inverter, a first XNOR gate, a first NOT gate and a first AND gate. The third Schmitt inverter is connected to the first voltage signal through the fourth control tube, and its output end is connected to the first input end of the first XNOR gate. The second input end of the first XNOR gate is connected to the second level signal, and its output end is connected to the first input end of the AND gate. The second input end of the AND gate is connected to the bias current state signal through the NOT gate, and its output end outputs the third level signal.

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