Reset system for SOC chip
By introducing a clock switch module and a first synchronization module in the SOC chip reset system, the problems of high power consumption and metastable state during reset in the prior art are solved, and a lower power consumption and a more stable reset process is achieved.
Patent Information
- Application Number
- CN202411516523.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-28
AI Technical Summary
The existing SOC chip reset circuits are prone to problems of metastable state and increased power consumption when the voltage is unstable in the initial power supply.
A reset system is designed, including a reset signal generation module, a first AND gate, a clock switch module and a first synchronization module. During reset, the input of the external clock signal is controlled through the clock switch module to ensure that the clock signal is allowed to enter the system only after the reset signal is stable, power consumption is reduced, and the synchronization of the external reset signal and the clock signal is achieved through the first synchronization module.
It effectively reduces the power consumption of the system during the reset process, eliminates the metastable problem, and improves the application range of the reset system.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and more particularly to a reset system for a SOC chip. Background Art
[0002] With the development of integrated circuit technology, SOC (System on Chip) design has become mainstream. In SOC chips, reset circuits are widely used to restart the power supply when it is powered on or off, to restore the initial state of the system module, and to ensure that it can enter a normal working state. The function of the existing reset circuit is that when the system is powered on, the POR (Power On Reset) module inside the system generates a reset signal, which has an uncertain phase relationship with the clock signal and is an asynchronous signal relative to the clock signal. Therefore, the reset release is prone to metastable problems. In addition, in the existing reset circuit, the reset signal is usually output when the power supply voltage reaches the threshold. When the power supply is just started, the power supply voltage is unstable and will generate pulse-shaped interference signals, which requires frequent reset operations, making the reset operation cumbersome and the reset time prolonged; and during the reset process, the clock enters the system, generating power consumption, which increases the power consumption of the entire SOC chip.
[0003] Therefore, it is necessary to provide a reset system for a SOC chip to overcome the above defects. Summary of the invention
[0004] The purpose of the present invention is to provide a reset system for a SOC chip. When resetting, the external clock signal cannot enter the system, thereby reducing the power consumption of the entire system, eliminating the metastable state of the system, and improving the application range of the system.
[0005] To achieve the above-mentioned purpose, the present invention provides a reset system for a SOC chip, which includes a reset signal generating module, a first AND gate, a clock switch module and a first synchronization module. The reset signal generating module generates a reset analog signal and a reset digital signal according to the input external analog voltage and the digital voltage. The reset analog signal and the reset digital signal are both digital signals. The reset analog signal and the reset digital signal are both input into the first AND gate. The first AND gate performs a logic AND on the input signal and outputs a clock control signal to the clock switch module. An external clock signal is input into the clock switch module. When the clock control signal is valid, the clock switch module inputs the external clock signal into the first synchronization module, and the external reset signal is input into the first synchronization module. When the external clock signal is received, the first synchronization module outputs the external reset signal to synchronize the external reset signal with the external clock signal to form a first reset control signal, and inputs the first reset signal into the SOC chip to reset the SOC chip.
[0006] Preferably, the reset system for the SOC chip also includes a delay counting module, a second AND gate and a third AND gate. The delay counting module is respectively connected to the reset signal generating module and the clock switch module. When the delay counting module receives an external clock signal, it delays the reset digital signal according to a set time to obtain a delayed digital signal. The delayed digital signal and the reset analog signal are both input into the second AND gate. The second AND gate performs a logic AND operation on the input signal and outputs a second reset control signal. The second reset control signal and the external reset signal are both input into the third AND gate. The third AND gate performs a logic AND operation on the input signal and outputs a third reset control signal to the first synchronization module.
[0007] Preferably, after receiving the first reset control signal, the SOC chip starts loading the firmware and outputs a chip clock signal and a mark signal after the firmware is loaded. The chip clock signal is the operating clock signal of the SOC chip itself, and the mark signal is used to indicate that the firmware of the SOC chip has been loaded.
[0008] Preferably, the reset system for the SOC chip also includes a second synchronization module, which is connected between the first synchronization module and the SOC chip. The second synchronization module receives the first reset control signal, the chip clock signal and the mark signal. When the mark signal is valid, the second synchronization module outputs the first reset control signal according to the chip clock signal and forms a reset enable signal. The reset enable signal is input to the SOC chip to reset the SOC chip.
[0009] Preferably, the first synchronization module synchronizes the third reset control signal with an external clock signal to obtain the first reset control signal.
[0010] Preferably, when the flag signal is valid, the second synchronization module synchronizes the first reset control signal with a chip clock signal to obtain the reset enable signal.
[0011] Preferably, the second reset control signal is input to an external circuit, and the external circuit detects the second reset control signal to determine whether the operation of the reset signal generating module is normal.
[0012] Preferably, the delay time of the delay counting module is greater than the time from when the external crystal oscillator is powered on to when it outputs a stable external clock signal and the time from when the system is powered on to when the reset signal generating module outputs a stable reset analog signal and reset digital signal.
[0013] Compared with the prior art, the reset system for SOC chip of the present invention is provided with a first AND gate and a clock switch module. The first AND gate generates a valid clock control signal only when the analog reset signal and the digital reset signal generated by the reset signal generating module are both valid, and the clock switch module inputs the external clock signal into the system when the clock control signal is valid, so that the external clock signal cannot enter the system during reset, reducing the power consumption of the entire system; in addition, the first synchronization module outputs the external reset signal when receiving the external clock signal, that is, the first synchronization module synchronizes the external reset signal with the external clock signal, realizes asynchronous reset and synchronous release of the external reset signal, and eliminates the metastable state of the system.
[0014] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 The figure is a structural block diagram of the reset system for SOC chip of the present invention. DETAILED DESCRIPTION
[0016] The embodiments of the present invention are now described with reference to the accompanying drawings, in which like element numbers represent like elements. As described above, the present invention provides a reset system for a SOC chip, in which an external clock signal cannot enter the system during reset, thereby reducing the power consumption of the entire system, eliminating the metastable state of the reset system, and improving the application range of the reset system.
[0017] Please refer to Figure 1 , Figure 1 FIG. 1 is a structural block diagram of a reset system for a SOC chip according to the present invention. Figure 1As shown, the reset system for SOC chip of the present invention includes a reset signal generating module, a first AND gate, a clock switch module and a first synchronization module; after the system is powered on, the reset signal generating module generates a reset analog signal a1 and a reset digital signal b1 according to the input external analog voltage a0 and the digital voltage b0, and the reset analog signal a1 and the reset digital signal b1 are both digital signals. Although the reset analog signal a1 and the reset digital signal b1 are both digital signals, they can still correspond to the voltage changes of the input analog voltage a0 and the digital voltage b2, that is, the reset signal generating module only changes the expression forms of the input analog voltage a0 and the digital voltage b2, and does not change the changes of their voltage values. ; The reset analog signal a1 and the reset digital signal b1 generated by the reset signal generating module are both input into the first AND gate, and the first AND gate performs a logic AND on the input reset analog signal a1 and the reset digital signal b1 to generate a clock control signal c1, and outputs the clock control signal c1 to the clock switch module, that is, when the reset analog signal a1 and the reset digital signal b1 are both 1, the clock control signal c1 is 1 (valid), otherwise the clock control signal c1 is 0 (invalid), that is, when the clock control signal c1 is valid, it indicates that the reset analog signal a1 and the reset digital signal b1 output by the reset signal generating module are stable and reliable; the external clock signal c1 generated by the external crystal oscillator (not shown) k1 is input into the clock switch module. When the clock control signal c1 (is 1) is valid, the clock switch module is controlled to be opened so that the clock switch module inputs the external clock signal cl k1 into the first synchronization module. At this point, the external clock signal cl k1 is input into the system, and at this time, the reset signal generating module has generated a stable reset signal (the clock control signal c1 is valid only when the reset analog signal a1 and the reset digital signal b1 are both 1). Therefore, before the reset signal is generated, no clock signal enters the reset system, thereby reducing the power consumption during the system reset period. The external reset signal rst0 is input to the first synchronization module, and the first synchronization module outputs the external reset signal rst0 when receiving the external clock signal clk1, forms the first reset control signal d2, and inputs the first reset signal d2 to the SOC chip to reset the SOC chip; the first reset control signal d2 is formed when the first synchronization module receives the external clock signal clk1, so that the rising edge of the first reset control signal d2 is aligned (synchronized) with the rising edge of the external clock signal clk1, that is, the first synchronization module synchronizes the external reset signal rst0 with the external clock signal clk1, realizes asynchronous reset and synchronous release of the external reset signal rst0, and eliminates the metastable state of the system.
[0018] As a preferred embodiment of the present invention, the reset system for the SOC chip also includes a delay counting module, a second AND gate and a third AND gate; the delay counting module is connected to the reset signal generating module and the clock switch module respectively, and when the delay counting module receives the external clock signal clk1, the reset digital signal b1 is delayed according to the set time to obtain the delayed digital signal b2, and the delayed digital signal b2 and the reset analog signal a1 are both input to the second AND gate, and the second AND gate performs a logical AND operation on the input delayed digital signal b2 and the reset analog signal a1, thereby obtaining a second reset control signal c2, that is, the second reset control signal c2 is the same as the clock control signal c1, but is delayed by the delay time of the delay counter compared to the clock control signal c1; the second reset control signal c2 and the external reset signal rst0 are both input to the third AND gate, and the third AND gate performs a logical AND operation on the second reset control signal c2 and the external reset signal rst0 to form a third reset control signal d1, and the third reset The control signal d1 is output to the first synchronization module, so that the external reset signal rst0 can be input into the reset system only after the external clock signal clk1 is input, and is also delayed by the delay counting module (the second reset control signal c2 is delayed); thereby, the first reset control signal generated by the first synchronization module is also delayed on the basis of the external reset signal rst0, thereby shielding the interference signal generated during the reset process and ensuring the accurate reset of the SOC chip; and also, the first synchronization module synchronizes the third reset control signal d1 with the external clock signal clk1 to obtain the first reset control signal d2, that is, the first reset control signal d2 is obtained by synchronizing the third reset control signal d1 with the external clock signal clk1, and no matter whether it is the first reset control signal d2 or the third reset control signal d1, they are actually the external reset signal rst0, but there is a change in timing, so that the external reset signal rst0 can reset the system more accurately after being input into the system. Among them, the delay time of the delay counting module is greater than the time from the external crystal oscillator being powered on to the output of the stable external clock signal clk1 and the time from the system being powered on to the reset signal generating module outputting the stable reset analog signal a1 and the reset digital signal b1; that is, by setting the delay counter, the reset analog signal a1 and the reset digital signal b1 generated by the reset signal generating module are input into the system only after they are completely stable to assist the system in resetting, thereby achieving accurate reset of the SOC chip; at the same time, it also delays the external clock signal clk1 from entering the system, thereby solving the problems of frequency deviation and delayed start-up of the external crystal oscillator.
[0019] After receiving the first reset control signal d2, the SOC chip starts to load the firmware. During the firmware loading process, most modules of the entire reset system are in a reset state, and only some modules (firmware-related) can work normally, so the firmware is loaded on these modules before the system is reset; and after the firmware is loaded, the SOC chip outputs a chip clock signal clk2 and a mark signal e1; wherein, the chip clock signal clk2 is the operating clock of the SOC chip itself, and the mark signal e1 is used to indicate that the firmware of the SOC chip has been loaded, and it will only be generated and output after the firmware of the SOC chip has been loaded.
[0020] Furthermore, the reset system for SOC chip of the present invention further comprises a second synchronization module, wherein the second synchronization module is connected between the first synchronization module and the SOC chip, and the second synchronization module receives the first reset control signal d2, the chip clock signal clk2 and the mark signal e1, and when the mark signal e1 is valid, the second synchronization module outputs the first reset control signal d2 according to the chip clock signal clk2, and forms a reset enable signal rst1, and the reset enable signal rst1 is input to the SOC chip to reset the SOC chip; that is, in the present invention, when the SOC chip receives the first reset control signal d2, it loads the firmware, and only after the firmware is loaded does it output the chip clock signal clk2 and the mark signal e1 to the second synchronization module. 1. The second synchronization module generates the reset enable signal rst1 to reset the SOC chip only after receiving the chip clock signal clk2 and the mark signal e1. That is, the SOC chip first loads the firmware and then resets the system during the entire reset process. Moreover, when the mark signal e1 is valid, the second synchronization module synchronizes the reset enable signal rst1 with the chip clock signal, and realizes asynchronous reset and synchronous release of the first reset control signal d2. The first reset control signal d2 is obtained after multiple timing adjustments of the external reset signal rst0, but the first reset control signal d2 is actually still the external reset signal rst0. Therefore, the external reset signal rst0 is asynchronously reset and synchronously released, eliminating the metastable state of the system.
[0021] In addition, as a preferred embodiment of the present invention, Figure 1 As shown, the second reset control signal c2 is input to the external circuit, and the external circuit detects the second reset control signal c2 to determine whether the reset signal generating module operates normally; for example, an oscilloscope can be used to observe the waveform of the second reset control signal c2 to verify whether the reset signal generating module operates normally.
[0022] In summary, the reset system for SOC chip of the present invention delays the external reset signal rst0 and filters the interference signal through the reset stretching function of the delay counter; during the system reset process, the clock switch module is in the off state, and the external clock signal clk1 cannot enter the system, thereby reducing the power consumption of the reset system; in addition, the reset signal generated by the reset signal generating module is output to the external circuit in real time, and the reset function is tested by the external circuit to see whether it is normal.
[0023] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.
Claims
1. A reset system for a SOC chip, characterized in that: It includes a reset signal generating module, a first AND gate, a clock switch module and a first synchronization module. The reset signal generating module generates a reset analog signal and a reset digital signal according to the input external analog voltage and the digital voltage. The reset analog signal and the reset digital signal are both digital signals. The reset analog signal and the reset digital signal are both input to the first AND gate. The first AND gate performs logic AND on the input signal and outputs a clock control signal to the clock switch module. The external clock signal is input to the clock switch module. When the clock control signal is valid, the clock switch module inputs the external clock signal to the first synchronization module, and the external reset signal is input to the first synchronization module. When the external clock signal is received, the first synchronization module outputs the external reset signal to synchronize the external reset signal with the external clock signal to form a first reset control signal, and the first reset signal is input to the SOC chip to reset the SOC chip.
2. The reset system for SOC chip according to claim 1, characterized in that: It also includes a delay counting module, a second AND gate and a third AND gate. The delay counting module is connected to the reset signal generating module and the clock switch module respectively. When the delay counting module receives an external clock signal, the reset digital signal is delayed according to the set time to obtain a delayed digital signal. The delayed digital signal and the reset analog signal are both input to the second AND gate. The second AND gate performs a logic AND on the input signal and outputs a second reset control signal. The second reset control signal and the external reset signal are both input to the third AND gate. The third AND gate performs a logic AND on the input signal and outputs a third reset control signal to the first synchronization module.
3. The reset system for SOC chip according to claim 2, characterized in that: After receiving the first reset control signal, the SOC chip starts to load the firmware and outputs a chip clock signal and a mark signal after the firmware is loaded. The chip clock signal is the operating clock signal of the SOC chip itself, and the mark signal is used to indicate that the firmware of the SOC chip has been loaded.
4. The reset system for SOC chip according to claim 3, characterized in that: It also includes a second synchronization module, which is connected between the first synchronization module and the SOC chip. The second synchronization module receives the first reset control signal, the chip clock signal and the mark signal. When the mark signal is valid, the second synchronization module outputs the first reset control signal according to the chip clock signal and forms a reset enable signal. The reset enable signal is input to the SOC chip to reset the SOC chip.
5. The reset system for SOC chip according to claim 2, characterized in that: The first synchronization module synchronizes the third reset control signal with an external clock signal to obtain the first reset control signal.
6. The reset system for SOC chip according to claim 4, characterized in that: When the flag signal is valid, the second synchronization module synchronizes the first reset control signal with a chip clock signal to obtain the reset enable signal.
7. The reset system for SOC chip according to claim 2, characterized in that: The second reset control signal is input to an external circuit, and the external circuit detects the second reset control signal to determine whether the operation of the reset signal generating module is normal.
8. The reset system for SOC chip according to claim 1, characterized in that: The delay time of the delay counting module is greater than the time from the external crystal oscillator being powered on to outputting a stable external clock signal and the time from the system being powered on to the reset signal generating module outputting a stable reset analog signal and a reset digital signal.