Chip working voltage adjusting method and system and electronic equipment

Abstract

The invention discloses a chip working voltage adjusting method and system and electronic equipment. The method comprises the steps that in response to a received working voltage adjusting instruction of a chip, a plurality of detection values of the chip are collected, and the different detection values are obtained by detecting the chip through different types of sensors; the multiple detection values are predicted through a voltage model, the frequency voltage mapping relation of the chip is obtained, and the frequency voltage mapping relation is used for describing the corresponding minimum working voltages of the chip under different working frequencies; the voltage model is obtained by training according to a plurality of sample detection values corresponding to the sample chips in different working frequencies and a sample minimum working voltage; and adjusting the current working voltage of the chip based on the frequency-voltage mapping relation and the target working frequency of the chip. According to the invention, the technical problems of relatively low working voltage regulation efficiency of a chip in the related technology and relatively high power consumption of the chip in the related technology are solved.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular, to a chip operating voltage regulation method, system and electronic device. The present application relates to a chip operating voltage regulation method, system and electronic device. Background Art

[0002] With the development of semiconductor process technology and the increasing complexity of system design, the importance of power consumption in integrated circuit design has become increasingly prominent. High power consumption brings many serious challenges, such as increasing the operating temperature of the chip, reducing the reliability of the chip, and increasing the cost of the chip.

[0003] Due to the differences in chip manufacturing and working processes, the performance of chips with the same design in different production batches and different working environments will be different, making it difficult to detect the specific relationship between chip performance and various influencing factors, resulting in difficulty in effectively adjusting the chip's operating voltage, which in turn causes the chip's power consumption to be higher.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a chip operating voltage regulation method, system and electronic device, so as to at least solve the technical problems of low chip operating voltage regulation efficiency and high chip power consumption in related technologies.

[0006] According to one aspect of an embodiment of the present application, a chip operating voltage adjustment method is provided, including: in response to receiving a chip operating voltage adjustment instruction, collecting multiple detection values ​​of the chip, wherein different detection values ​​are used to detect the chip through different types of sensors; using a voltage model to predict the multiple detection values ​​to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies; adjusting the current operating voltage of the chip based on the frequency-voltage mapping relationship and the target operating frequency of the chip, wherein the target operating frequency is the operating frequency to be achieved by the chip.

[0007] According to one aspect of an embodiment of the present application, a chip operating voltage regulation system is provided, including: multiple sensors connected to the chip, used to detect the chip and obtain multiple detection values; a voltage regulation device, connected to the multiple sensors, used to collect multiple detection values ​​after receiving the chip operating voltage regulation instruction, and use a voltage model to predict the multiple detection values ​​to obtain the frequency-voltage mapping relationship of the chip, and the current operating voltage of the chip based on the frequency-voltage mapping relationship and the target operating frequency of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained according to multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies, and the target operating frequency is the operating frequency to be achieved by the chip.

[0008] According to another aspect of the embodiments of the present application, an electronic device is further provided, including: a memory storing an executable program; and a processor for running the program, wherein the method of each embodiment of the present application is executed when the program is running.

[0009] According to another aspect of an embodiment of the present application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in each embodiment of the present application.

[0010] According to another aspect of the embodiments of the present application, a computer program product is also provided, including a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0011] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0012] According to another aspect of the embodiments of the present application, a computer program is also provided, and when the computer program is executed by a processor, the methods in the various embodiments of the present application are implemented.

[0013] In an embodiment of the present application, in response to receiving an operating voltage adjustment instruction of a chip, multiple detection values ​​of the chip are collected, wherein different detection values ​​are used to detect the chip through different types of sensors; a voltage model is used to predict multiple detection values ​​to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies; the current operating voltage of the chip is adjusted based on the frequency-voltage mapping relationship and the target operating frequency of the chip, wherein the target operating frequency is the operating frequency to be achieved by the chip, The purpose of improving the chip's operating voltage regulation efficiency is achieved; it is easy to notice that the present application obtains a voltage model by training in advance based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies. After collecting multiple detection values ​​of the chip, the voltage model can be used to quickly calculate the mapping relationship between frequency and voltage, and based on the frequency-voltage mapping relationship and the chip's target operating frequency, the current operating voltage of the chip is automatically adjusted to ensure that the chip operates in the lowest power consumption state at the target operating frequency, thereby improving the chip's operating voltage regulation efficiency, so as to effectively reduce the chip's power consumption, and further solving the technical problem of low chip operating voltage regulation efficiency in related technologies.

[0014] It is easy to notice that the above general description and the following detailed description are only for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 It is a hardware structure block diagram of a RISC-V system for implementing a chip operating voltage adjustment method according to an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application;

[0018] Figure 3 is a flow chart of a chip operating voltage adjustment method according to the present application;

[0019] Figure 4 is a structural schematic diagram of an adaptive voltage regulation process according to an embodiment of the present application;

[0020] Figure 5 is a schematic diagram of a chip operating voltage regulating device according to an embodiment of the present application;

[0021] Figure 6 It is a schematic diagram of a chip operating voltage regulation system according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0025] Adaptive Voltage Scaling (AVS) is a chip operation management method that can automatically adjust the chip's supply voltage according to the current chip load and operating conditions. Its purpose is to minimize power consumption while meeting performance requirements.

[0026] Dynamic Voltage and Frequency Scaling (DVFS) is an energy efficiency management method that allows the system to dynamically adjust the frequency and voltage of the processor (Central Processing Unit, CPU) at runtime to respond to different workloads. By reducing the voltage and frequency, DVFS can significantly reduce the power consumption of the chip, while increasing the voltage and frequency to increase the computing speed when high performance is required. AVS is a component of DVFS and is specifically responsible for voltage regulation.

[0027] Chip process, voltage, temperature, aging (PVTA for short), these four parameters represent the main environmental and manufacturing factors that affect chip performance and power consumption. Process refers to the technical node in the chip manufacturing process. Chips at different process nodes may have different performance and power consumption. Voltage refers to the power supply voltage of the chip, which directly affects the chip power consumption and performance. Temperature refers to the temperature of the chip during operation. Temperature changes will significantly affect the power consumption and performance of the chip. Aging means that the chip will gradually age during use, resulting in performance degradation and increased power consumption. Aging is determined by material properties and operating conditions.

[0028] Machine learning model (ML-Model for short) refers to a machine learning model used to process and analyze data. The training of machine learning models is usually based on a large amount of historical data or test data.

[0029] The Automatic Test Equipment (ATE) system is an automated system for testing integrated circuits (ICs). It can include hardware and software components to detect the function, performance, and reliability of chips. ATE is very important in the chip manufacturing process. It can help identify and remove defective chips to ensure product quality. In this technical solution, ATE is used to collect test data of chips under different PVTA conditions for training ML-Model.

[0030] There are currently many ways to adjust the operating voltage of the chip. The first method is to provide a voltage value at which each chip can work normally under the most severe PVTA conditions; the second method is to perform ATE testing on each chip, record the lowest operating voltage of different chips at different operating frequencies, and save it in the chip's storage device (efuse); the third method is to detect the leakage current value of the chip and adjust the chip's operating voltage based on the corresponding relationship between the leakage current value and the operating voltage.

[0031] However, for the first method mentioned above, power consumption is wasted more seriously. For the second method mentioned above, the chip test success is increased. For the third method mentioned above, the impact of chip aging is not taken into account. Chip aging will also cause an increase in current. When the chip ages, the correspondence between the leakage current and the chip operating voltage will become inaccurate, which may cause the chip to work abnormally or increase power consumption.

[0032] According to an embodiment of the present application, a chip operating voltage adjustment method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] The method embodiment provided in Embodiment 1 of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 1 1 is a hardware structure block diagram of a RISC-V system for implementing a chip operating voltage adjustment method according to an embodiment of the present application. Figure 1 As shown, the RISC-V system 100 can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system 100 also includes a tool chain 107 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0034] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including a basic instruction set and an extended instruction set, wherein the basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0035] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0036] The operating system layer 104 is located at the hardware level and provides a hardware abstraction layer and management mechanism, so that applications can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0037] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communications and graphical user interfaces.

[0038] The application layer 106 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0039] The tool chain 107 is a key component that connects the underlying hardware to the upper-level software. Various tools in the tool chain 107 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0040] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0041] In an optional embodiment, Figure 2 Shown using the above Figure 1 Schematic diagram of the RISC-V architecture system on chip (SOC). Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application, such as Figure 2 As shown, the SOC includes at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0042] Under the above operating environment, this application provides Figure 3 The chip working voltage regulation method is shown. Figure 3 is a flow chart of a chip operating voltage adjustment method according to the present application. Figure 3 As shown, the method includes:

[0043] Step S302 , in response to receiving an operating voltage adjustment instruction of the chip, collecting multiple detection values ​​of the chip.

[0044] Among them, different detection values ​​are obtained by detecting the chip through different types of sensors.

[0045] The chip operating voltage adjustment instructions mentioned above refer to instructions issued by the chip control logic or upper-level software, which are used to adjust the operating voltage of the power management module inside the chip to adapt to different working environments and performance requirements. When the system detects that the chip load is reduced or the temperature is increased, it can issue instructions through the DVFS (dynamic voltage frequency adjustment) algorithm to require the chip to reduce the operating voltage to reduce power consumption.

[0046] The above-mentioned multiple detection values ​​refer to the values ​​collected by different types of sensors that reflect the current state of the chip, including but not limited to the process characteristics, operating voltage, temperature and aging degree of the chip. The process characteristic sensor (Process sensor) can reflect the current process characteristics of the chip, the voltage sensor (Voltage sensor) can reflect the voltage condition of the chip (including voltage drop), the temperature sensor (Temperature sensor) can reflect the temperature of the chip, and the aging sensor (Aging sensor) can reflect the aging degree of the chip.

[0047] The above-mentioned different types of sensors refer to hardware components used to detect different states of the chip, which may be temperature sensors, voltage monitors, process characteristic detectors or chip aging monitors, etc. There is no limitation on the different types of sensors here, and sensors can be added or reduced according to actual needs. There is no limitation on the number of the above-mentioned sensors.

[0048] For example, the four types of sensors P, V, T, and A correspond to process characteristic sensors (such as Vth cell oscillation rings), voltage sensors, temperature sensors, and aging sensors. For example, the temperature sensor can be a thermistor, the voltage sensor can be a varistor, the process characteristic sensor can be an oscillation ring circuit based on different threshold voltages (Vth cell, and the aging sensor can indirectly reflect the degree of chip aging by monitoring the threshold voltage changes of the transistor.

[0049] When the chip receives an operating voltage adjustment instruction, it activates multiple built-in sensors, such as process characteristic sensor (P sensor), voltage sensor (V sensor), temperature sensor (T sensor) and aging sensor (Asensor), to collect data reflecting the current state of the chip. These data are used to evaluate the performance requirements of the chip in the current environment in real time, and then calculate a more suitable operating voltage through a machine learning model to achieve the goal of lower power consumption and higher performance.

[0050] In response to receiving the chip's operating voltage adjustment instruction, the chip will start its built-in PVTA sensor to collect the chip's current process characteristics (P), operating voltage (V), temperature (T), aging degree (A) and other status information. This information will be used to evaluate the chip's real-time performance requirements.

[0051] Step S304, predicting multiple detection values ​​using a voltage model to obtain a frequency-voltage mapping relationship of the chip;

[0052] The frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies.

[0053] The voltage model is a model used to evaluate and predict the minimum operating voltage requirement of a chip under different conditions (such as different frequencies, temperatures, processes, etc.). It is usually based on a machine learning algorithm, such as a neural network, to learn the relationship between chip performance and environmental conditions through training. The voltage model can be an adaptive voltage model, and by inputting multiple detection values ​​into the adaptive voltage model, the frequency-voltage mapping relationship of the chip can be inferred.

[0054] In an optional embodiment, the voltage model is a machine learning model (ML-Model) obtained through offline training, which is used to predict in real time the minimum operating voltage of the chip under the current process, voltage, temperature and aging (PVTA) conditions. For example, a multi-layer perceptron (MLP) can be used as the basis of the voltage model, and trained by collecting the operating data of the chip under different conditions to accurately predict the minimum operating voltage of the chip under any given condition.

[0055] During the startup phase of the chip, the values ​​of P-sensor (process conditions), Vsensor (voltage), T-sensor (temperature) and Asensor (aging conditions) can be read through the chip software system. For example, the read P-sensor value may be 120MHz, the Vsensor value is 0.2V voltage drop, the T-sensor value is 35°C, and the Asensor value is 1000 hours of chip usage time. The values ​​here are only for example description and are not specifically limited. They can be measured according to actual conditions.

[0056] The sample chips mentioned above are representative chips selected for testing and data collection during the design and manufacturing process in order to build and verify the model. During the ATE test phase, different corner chips can be selected as sample chips to train the voltage model. These chips reflect different states of process variation, aging, and temperature, thereby ensuring the wide applicability and accuracy of the model.

[0057] The frequency-voltage mapping relationship (FV Mapping) is a relationship table that describes the correlation between the chip's operating frequency and its minimum operating voltage requirement, which allows automatic voltage adjustment at different frequencies to optimize power consumption and performance. The FV mapping relationship can be obtained during the offline model training phase, and the minimum operating voltage value of the chip at different operating frequencies can be stored as a table or part of the model to adjust the voltage in real time when the chip is working.

[0058] During the chip startup or operation phase, the PVTA sensor values ​​are first read and input into the pre-trained voltage model. The voltage model predicts the minimum operating voltage of the chip under the current conditions based on these input values. The predicted voltage is combined with different operating frequencies to form a frequency-voltage mapping relationship (FV). The FV mapping relationship describes the minimum operating voltage required by the chip at different operating frequencies, thereby minimizing power consumption while ensuring the normal operation of the chip.

[0059] By using the voltage model to test multiple detection values ​​of the chip (including process, voltage, temperature and aging status), the frequency-voltage mapping relationship (FV) obtained can adjust the chip's operating voltage in real time. A better voltage supply can be provided according to the current state of the chip, avoiding waste of power consumption, and since the construction of the model does not require ATE testing of each chip, the chip testing cost is greatly reduced. For example, when the chip is started, the system can automatically read the PVTA sensor value and input it into ML-Mode l to obtain the FV mapping relationship of the specific chip under the current conditions. Subsequently, the voltage and frequency can be dynamically adjusted according to the FV table to ensure that the chip works in a better state, while reducing power consumption and improving energy efficiency.

[0060] Step S306: adjusting the current operating voltage of the chip based on the frequency-voltage mapping relationship and the target operating frequency of the chip.

[0061] The target operating frequency is the operating frequency that the chip wants to achieve.

[0062] The target operating frequency mentioned above refers to the operating frequency that the chip expects or needs to achieve in a specific application or task state. The higher the operating frequency, the faster the chip's processing speed, but at the same time the power consumption and heat will also increase.

[0063] The above-mentioned current operating voltage refers to the operating voltage of the chip when it is actually running at a certain moment. The current operating voltage can be provided by a power management unit or a voltage regulator to ensure the stable operation of the chip.

[0064] During the operation of the chip, the frequency-voltage mapping relationship obtained by offline training ML-Mode l can be referred to, and the chip's operating voltage can be automatically adjusted to adapt to the target operating frequency in combination with the current chip's environmental conditions (such as temperature, voltage drop, aging degree) and process conditions. This process is designed to ensure that the chip meets performance requirements while minimizing power consumption and improving energy efficiency.

[0065] By adjusting the current operating voltage of the chip based on the frequency-voltage mapping relationship and the chip's target operating frequency, refined voltage management can be achieved to maximize power efficiency. When the chip needs to be upgraded to a higher frequency to cope with more complex computing tasks, the adaptive voltage adjustment method can analyze the chip status and environmental conditions in real time to find the lowest operating voltage that can support the frequency, avoiding unnecessary power consumption. At the same time, it reduces the dependence on ATE testing, reduces testing costs, and improves chip production efficiency and market competitiveness.

[0066] Exemplarily, ML-Mode l can be pre-trained offline, and the model can accurately predict the minimum operating voltage of the chip at different operating frequencies based on the current process, temperature, voltage drop and aging conditions. During the use of the chip, for example, when running an AI reasoning task, the upper-level software detects that the CPU frequency needs to be increased to 1.5GHz to meet the computing requirements. At this time, the values ​​of the PVTA sensors, including P sensor (process conditions), V sensor (voltage drop conditions), T sensor (temperature conditions) and A sensor (aging conditions), can be read, and these values ​​can be input into ML-Mode l for calculation. Based on these real-time parameters, ML-Mode l determines that the minimum operating voltage that can ensure stable operation of the chip at a frequency of 1.5GHz is 1.2V. Subsequently, the software updates the frequency voltage table of the DVFS system and sends the target frequency voltage pair (1.5GHz, 1.2V) to the hardware FV controller to achieve synchronous adjustment of frequency and voltage. This process not only ensures that the chip can efficiently complete the computing task, but also reduces power consumption by reducing the operating voltage, prolongs the service life of the chip, and avoids high-cost ATE testing, significantly reducing production costs.

[0067] Through the above steps, in response to receiving the chip's working voltage adjustment instruction, multiple detection values ​​of the chip are collected, wherein different detection values ​​are used to detect the chip through different types of sensors; multiple detection values ​​are predicted using a voltage model to obtain the frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum working voltage corresponding to the chip at different working frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum working voltages corresponding to sample chips at different working frequencies; the current working voltage of the chip is adjusted based on the frequency-voltage mapping relationship and the target working frequency of the chip, wherein the target working frequency is the working frequency to be achieved by the chip, thereby improving the chip The purpose of improving the working voltage regulation efficiency is to improve the working voltage regulation efficiency. It is easy to notice that the present application obtains a voltage model by training in advance according to multiple sample detection values ​​and sample minimum working voltages corresponding to sample chips at different working frequencies. After collecting multiple detection values ​​of the chip, the voltage model can be used to quickly calculate the mapping relationship between frequency and voltage. Based on the frequency-voltage mapping relationship and the target working frequency of the chip, the current working voltage of the chip is automatically adjusted to ensure that the chip works in the lowest power consumption state at the target working frequency, thereby improving the working voltage regulation efficiency of the chip, so as to effectively reduce the power consumption of the chip, thereby solving the technical problem that the working voltage regulation efficiency of the chip in the related art is low and the power consumption of the chip in the related art is high.

[0068] In the above embodiments of the present application, the current operating voltage of the chip is adjusted based on the frequency-voltage mapping relationship and the target operating frequency of the chip, including: adjusting the current operating frequency of the chip to the target operating frequency, wherein the target operating frequency is determined based on the current load of the chip; selecting the lowest operating voltage corresponding to the target operating frequency from the frequency-voltage mapping relationship; and adjusting the current operating voltage of the chip based on the lowest operating voltage.

[0069] The above frequency-voltage mapping relationship refers to the set of the lowest operating voltages at which the chip can operate stably at different operating frequencies. This mapping relationship reflects the balance between chip performance and power consumption and is the basis for implementing dynamic voltage and frequency adjustment strategies.

[0070] The target operating frequency of the above chip refers to the optimal operating frequency that the chip is planned to run at based on the current task load and performance requirements. The target operating frequency can be a key parameter that determines the chip performance adjustment in the dynamic adjustment strategy.

[0071] For example, when the chip is processing some lightweight tasks, such as word processing or web browsing, the target operating frequency can be set lower to reduce power consumption; when processing high-load tasks, such as video rendering or machine learning calculations, the target operating frequency should be higher to improve performance.

[0072] The above minimum operating voltage refers to the minimum voltage level at which the chip can ensure stable operation at a specific operating frequency. The minimum operating voltage is closely related to the current load, ambient temperature, manufacturing process and other conditions of the chip.

[0073] Adjusting the current operating frequency of the chip to the target operating frequency belongs to frequency modulation control, where frequency modulation control refers to automatically adjusting the operating frequency of the chip according to the system load or performance requirements to achieve the purpose of power consumption or performance optimization. For example, if the system detects that the currently executed program has a low load on the CPU, the frequency modulation control will dynamically reduce the operating frequency of the chip from 1.5GHz to 1.2GHz to reduce unnecessary power consumption.

[0074] Adjusting the current operating voltage of the chip based on the minimum operating voltage belongs to voltage regulation control, where voltage regulation control refers to automatically adjusting the operating voltage of the chip according to the working state of the chip to reduce power consumption while ensuring the stability and performance of the chip. For example, when the frequency modulation control reduces the operating frequency of the chip from 1.5GHz to 1.2GHz, the voltage regulation control will reduce the operating voltage from 1.1V to 0.9V to achieve a better energy efficiency ratio.

[0075] In an optional embodiment, a target operating frequency can be determined according to the current load of the chip; then, the minimum operating voltage under the target frequency is found based on the frequency-voltage mapping relationship; finally, the current operating voltage of the chip is adjusted to this minimum operating voltage through voltage regulation control, so as to achieve the purpose of reducing power consumption while ensuring performance. By real-time monitoring of the chip's process, voltage, temperature, and aging (PVTA) status, based on a pre-built machine learning model (ML-Model l), the minimum operating voltage of each chip under different conditions can be accurately predicted. This not only avoids the problem of power waste in traditional methods, but also saves the cost of ATE testing of each chip. It is an energy-saving and economical solution.

[0076] Exemplarily, the chip is performing an image processing task and the system load is high. At this time, the operating frequency of the chip is 1.5GHz, but the detected PVTA conditions show that the chip is in favorable conditions in terms of process, temperature and aging. Based on the frequency-voltage mapping relationship and offline trained ML-Mode l, the system determines that the minimum operating voltage at a frequency of 1.4GHz is 1.0V, and predicts that under the current PVTA conditions, the chip can still maintain stable operation. Therefore, through frequency modulation control, the operating frequency of the chip is adjusted from 1.5GHz to 1.4GHz; at the same time, through voltage regulation control, the operating voltage is reduced from 1.1V to 1.0V, which not only reduces power consumption, but also saves operating costs, while the performance of the chip still meets the task requirements. The above values ​​are for example only and are not specifically limited.

[0077] In the above embodiments of the present application, the current operating voltage is adjusted based on the minimum operating voltage, including: obtaining the voltage margin of the chip, wherein the voltage margin is used to offset the model error caused by the voltage model; determining the target operating voltage based on the sum of the minimum operating voltage and the voltage margin; and adjusting the current operating voltage of the chip to the target operating voltage.

[0078] The above voltage margin is an additional voltage value added on the basis of determining the minimum operating voltage to cope with model errors, chip parameter errors or environmental errors to ensure the stability and reliability of chip operation. For example, assuming that the minimum operating voltage predicted by ML-Mode 1 is 0.9V, considering the possible errors of the model and other uncertain factors, the voltage margin of 0.05V can be increased so that the actual operating voltage is set to 0.95V. The values ​​here are only for example and are not limited.

[0079] The above target operating voltage is the actual operating voltage set for the chip calculated by combining the minimum operating voltage and the voltage margin. For example, if the minimum operating voltage is 0.8V and the voltage margin is 0.1V, the target operating voltage is 0.9V. The values ​​here are only for example and are not limited.

[0080] The above-mentioned current operating voltage may be the actual voltage at which the chip is running, which may be higher than or equal to the minimum operating voltage. By adjusting the current operating voltage of the chip to the target operating voltage, power consumption optimization can be achieved.

[0081] In an optional embodiment, the voltage margin of the chip can be obtained, and the voltage margin can be used to indicate the accuracy of the model, the range of variation of chip parameters, and the fluctuation of the working environment. The target operating voltage is determined based on the sum of the minimum operating voltage and the voltage margin, so as to accurately adjust the chip operating voltage to ensure that the chip can operate stably even under adverse conditions. The current operating voltage of the chip is adjusted to the target operating voltage to minimize power consumption.

[0082] The embodiments of the present application not only offset the possible errors in voltage model prediction by introducing voltage margin, but also take into account the uncertainty of chip parameters and changes in the working environment, thereby ensuring the stability and reliability of the chip in actual operation. At the same time, by accurately adjusting the working voltage to the target value, it can effectively reduce chip power consumption, reduce chip heating, extend chip service life, significantly reduce chip testing costs, and provide a more efficient and economical solution for chip design and manufacturing.

[0083] Exemplarily, during the chip use phase, the values ​​detected by the sensor are: the Psensor value indicates that the current process is tt angle, the Vsensor value is 0.05V (indicating the voltage drop), the Tsensor value is 25°C, and the Asensor value indicates that the chip aging is low. Through ML-Model l reasoning, the minimum operating voltage of the chip at the current 1GHz operating frequency is 0.8V. Considering the uncertainty of model errors and chip parameters, 0.1V can be used as the voltage margin. Therefore, the target operating voltage is set to 0.8V+0.1V=0.9V. At this time, the current operating voltage of the chip can be adjusted to 0.9V to ensure that the chip runs stably in the current environment and achieves better control of power consumption. This process significantly reduces power consumption and improves energy efficiency compared to the traditional fixed voltage power supply solution, while ensuring the stability of the chip operation, and provides strong support for high-performance, low-power chip design. The values ​​here are only for example and are not limited.

[0084] In the above embodiment of the present application, the voltage model is obtained by adjusting the model parameters of the initial voltage model through the loss function. The loss function is constructed based on the test working voltage and the sample minimum working voltage. The test working voltage is obtained by predicting multiple sample detection values ​​by the initial voltage model.

[0085] The above-mentioned initial voltage model can be a model in the field of machine learning, which is usually defined by a series of parameters and is used to predict the operating voltage of the chip under specific conditions. Among them, the initial voltage model can be a multi-layer perceptron model, which can be preliminarily trained based on the initial data set of chip design to predict the minimum operating voltage of the chip under different PVTA (process, voltage, temperature, aging) conditions. It should be noted that the initial voltage model can be a voltage model that has not been trained, or a voltage model that has not completed training.

[0086] The above model parameters refer to the mathematical variables used to adjust the model's predictive ability in the machine learning model.

[0087] During the model training process, the model parameters to be adjusted may include but are not limited to weights and biases. The above model parameters are updated through the training process to improve the accuracy of the model in predicting the minimum operating voltage.

[0088] The above loss function is a function used in machine learning to measure the difference between the model's predicted output and the actual target output. The loss function can be the mean square error (MSE), which can calculate the square of the difference between the predicted minimum operating voltage and the actual tested minimum operating voltage, and then find the average. The lower the function value of the loss function, the more accurate the model's prediction.

[0089] The above test working voltage is the voltage value at which the chip can operate stably under given conditions. Through ATE (Automatic Test Equipment) testing, the working voltage of the chip under specific frequency, temperature, voltage drop and aging conditions can be obtained. These voltage values ​​are the test working voltage.

[0090] The above sample minimum operating voltage can be the minimum voltage at which the chip can operate stably under specific PVT (process, voltage, temperature) and aging conditions. Among the chips with different operating speeds tested by ATE, the minimum operating voltages of different chips under different conditions are recorded as the output value of the training sample.

[0091] In an optional embodiment, the initial voltage model is first trained with a large amount of sample data, which includes the PVTA detection value of the chip and the corresponding minimum operating voltage. The model parameters are optimized through a loss function, which calculates the difference between the test operating voltage predicted by the model and the actual minimum operating voltage of the sample. By updating the model parameters, the initial model gradually evolves into a more accurate voltage model that can accurately predict the minimum operating voltage of the chip under different PVTA conditions.

[0092] The voltage model constructed by optimizing the model parameters and loss function can be highly adaptive to the actual operating environment of the chip. This means that when the chip is in different operating frequencies, temperatures, voltage drops and aging states, the model can dynamically predict the minimum voltage at which the chip can operate stably, thereby avoiding the waste of power consumption caused by using fixed voltage values ​​in traditional methods. In addition, this application does not require expensive ATE testing of each chip, saving testing costs, significantly reducing the power consumption of the chip, improving energy efficiency, and reducing the economic burden of chip testing.

[0093] In the above embodiments of the present application, in response to receiving an operating voltage adjustment instruction of the chip, multiple detection values ​​of the chip are collected, including: in response to receiving an operating voltage adjustment instruction of the chip, calling software interfaces of different types of sensors to read multiple detection values.

[0094] The above-mentioned operating voltage adjustment instruction can be issued by the software system or the hardware control unit, and the purpose is to adjust the operating voltage of the chip to optimize performance or power consumption. Optionally, when the chip is started or during the operation of the chip, the upper operating system sends an instruction to the voltage adjustment module according to the current load and performance requirements, requesting to adjust the operating voltage.

[0095] The operating voltage of the above-mentioned chip refers to the power supply voltage required for the chip to operate normally, which can affect the power consumption and performance of the chip.

[0096] The software interface of the above-mentioned sensor is an interface that follows a specific communication protocol. The software interface allows software programs to exchange data with hardware devices (such as sensors). By calling a specific software interface, the upper-level software system can access and read the real-time data of the P, V, T, and A sensors on the chip, such as the temperature value of the temperature sensor and the voltage drop value of the voltage drop sensor.

[0097] In an embodiment of the present application, when the chip receives an instruction to adjust the operating voltage, the upper-level software system will activate software interfaces with different types of sensors to collect key parameters reflecting the current state of the chip. These parameters include the chip's process characteristics, voltage drop, temperature, and aging. The collected detection values ​​will be used to adjust the chip's operating voltage to ensure that power consumption is reduced as much as possible while meeting performance requirements.

[0098] After receiving the chip's operating voltage adjustment instruction, the present application actively reads the parameters reflecting the current chip status from the PVTA sensor on the chip. In this way, the chip can adjust its operating voltage in real time and intelligently to adapt to the current process, voltage, temperature and aging conditions. Compared with providing a fixed voltage, this method significantly reduces chip power consumption; compared with ATE testing of multiple chips, it greatly reduces testing costs; compared with adjusting the voltage only according to the leakage current value, it more accurately considers the circuit aging factor and improves the accuracy of the chip performance model.

[0099] The design of the software interface above separates the hardware sensor from the upper-layer software, which means that even if new sensor types need to be added or replaced later, only the corresponding software interface needs to be updated without large-scale modification of the hardware of the entire chip. This greatly enhances the flexibility and scalability of the system, facilitating future technology upgrades or the introduction of new performance monitoring parameters.

[0100] The above software interface can provide a standardized data reading method, so that the upper-level software can efficiently and uniformly access various sensor data. This avoids the complexity and inefficiency that may be caused by direct interaction with hardware, and ensures the speed and accuracy of data reading.

[0101] Data interaction through software interfaces simplifies the direct coupling between upper-level software and hardware sensors, reducing the complexity of system design. This allows the upper-level software to focus more on algorithm optimization and function implementation without having to pay too much attention to the specific hardware implementation details of the sensor.

[0102] Optionally, the general software interface will include data verification and error handling mechanisms to ensure the integrity and accuracy of the sensor data read. In addition, additional data processing logic can be added through the software interface, such as data filtering, outlier detection, etc., to further ensure the reliability of voltage regulation decisions based on sensor data.

[0103] The design of the above software interface follows certain standards and specifications, so that on different hardware platforms, as long as the corresponding interface standards are implemented, the upper-layer software can seamlessly read and process sensor data, enhance the cross-platform compatibility of the solution, and facilitate the wide deployment and application of this application. By adding software interfaces, the efficiency of the data reading process can be improved, and the flexibility, security, reliability and cross-platform compatibility of data reading can be enhanced, which is an indispensable key component for realizing adaptive voltage regulation.

[0104] For example, when running a high-load task, the software system detects the task requirements and sends an operating voltage adjustment instruction. The system then calls the software interface of the P, V, T, and A sensors on the chip to read real-time detection values ​​reflecting the current process conditions, voltage drop, temperature, and aging. This series of detection values ​​is input into the pre-trained ML-Model l, and the model calculates the minimum operating voltage suitable for the current task load and performance requirements based on the current PVTA conditions. The software system updates the frequency-voltage table (FV table le) and notifies the hardware voltage controller to adjust the voltage. By adjusting the operating voltage in real time, it is possible to ensure that while meeting the performance of high-load tasks, power consumption is reduced and energy efficiency is improved, while reducing the need for ATE testing and reducing production costs.

[0105] Figure 4 is a structural diagram of an adaptive voltage regulation process according to an embodiment of the present application, such as Figure 4As shown, in the processor system of the hardware system-on-chip (System on Chip, referred to as SOC), different types of sensors are integrated, including process sensors, voltage sensors, temperature sensors and aging sensors. The above-mentioned sensors are connected to the machine learning model (ML-Mode l). After the chip is started, the value of the sensor can be read by calling the relevant software interface of the sensor, and the read value is used as the input of the machine learning model to infer the minimum operating voltage value of the chip suitable for the current temperature, voltage drop, and life cycle at different frequency points. The obtained frequency-voltage mapping relationship can be used to update the table storage unit of the dynamic voltage-frequency adjustment framework. During the operation of the hardware system-on-chip and the execution of the dynamic voltage-frequency adjustment framework, a target frequency-voltage correspondence (FV) suitable for the current load can be selected as the frequency-voltage point of the system, and the target frequency-voltage correspondence is sent to the frequency-voltage controller (FV controller) to complete the frequency and voltage control of the chip. The power management circuit can be controlled to adjust the voltage to obtain the target voltage, and the clock management circuit can be controlled to adjust the frequency to obtain the target frequency.

[0106] The above-mentioned adaptive voltage scaling flow (AVSFLOW) can be executed in the chip startup phase, the chip normal operation phase and different stages of the chip life cycle. It should be noted that the adaptive voltage scaling flow proposed in this application can use but is not limited to the values ​​detected by the four sensors mentioned above, and any factors that affect chip performance can also be used as inputs to the machine learning model that implements the adaptive voltage scaling flow.

[0107] In the chip ATE test phase, a certain number of different corner chips can be selected, and the minimum operating voltage can be tested under the combination of different frequency points, temperatures, voltage drops, and aging conditions, that is, multiple groups of {process ring oscillator values, voltage values, temperature values, aging values} are collected as input sample values, and the minimum operating voltage (Vmin) is used as the target output value. A suitable initial machine learning model can be selected for training, and a machine learning model suitable for the current processor system can be constructed offline. Among them, the machine learning model can be a multi-layer perceptron (Multi-Layer Perceptron, referred to as MLP), but is not limited to this, and the type of machine learning model can be set according to actual conditions. It should be noted that, considering the accuracy of the machine learning model, the reliability of the chip can be guaranteed by increasing the voltage margin in hardware or software.

[0108] The above content emphasizes that in the process of applying machine learning models to adaptively adjust the chip operating voltage, in order to ensure the accuracy of the algorithm model and guarantee the reliability of chip operation, it can be achieved by increasing the voltage margin. The voltage margin refers to the additional voltage above the minimum voltage required for the normal operation of the chip to cope with uncertain factors such as model prediction errors, environmental changes or chip performance fluctuations, ensuring that the chip can operate stably under various conditions.

[0109] Specifically, even if the machine learning model is fully trained, the predicted minimum operating voltage value may deviate from the actual situation, especially in non-standard situations such as chip aging and changes in environmental conditions. In order to prevent such deviations from causing unstable chip operation or performance degradation, a safety margin, namely the voltage margin, can be added to the voltage value predicted by the model. This margin can be adjusted according to the specific application scenario of the chip, the requirements for stability, and the prediction accuracy of the model.

[0110] At the hardware level, the voltage margin can be increased by designing a voltage regulator to ensure that the actual operating voltage of the chip is always above the predicted value, and sufficient performance and stability can be maintained even under the most unfavorable conditions. At the software level, a voltage margin parameter can be built into the algorithm that controls the chip's operating voltage. By adjusting this parameter, the operating voltage in the actual application can be controlled to be higher than the minimum value predicted by the model. Increasing the voltage margin is a strategy to ensure stable operation of the chip during the adaptive voltage regulation process. In this way, even if there are prediction errors or environmental uncertainties, the chip performance can be ensured to be unaffected while maintaining a low power consumption level.

[0111] The above-mentioned corner chips may include but are not limited to slow corner chips (S low Corner, referred to as ss), typical corner chips (Typical Corner, referred to as tt), and fast corner chips (Fast Corner, referred to as ff), wherein the running speed of the slow corner chip will be slower than expected, usually due to factors such as process deviation, low power supply voltage or low temperature. The normal operating state of the typical corner chip is expected during design, that is, the chip behavior when the parameters are at their average or typical values. The running speed of the fast corner chip is faster than expected, which may be caused by factors such as process deviation, high power supply voltage or high temperature.

[0112] The process sensor (P sensor) mentioned above is used to characterize the process condition of the current chip circuit, and can be realized by an oscillation loop composed of different threshold voltage units (Vth cell), interconnection types (wire), etc.; the voltage sensor (V sensor) is used to characterize the voltage of the current circuit, and then characterize the voltage drop (voltage drop) from the chip power supply voltage to the current circuit. The voltage value of the voltage sensor can be directly characterized as the voltage drop; the temperature sensor (T sensor) can be used to characterize the temperature of the circuit; the aging sensor (Asensor) can be used to characterize the aging of the chip.

[0113] The Vth cell and wire type oscillator rings in the P sensor are implemented, which means that the sensor uses oscillator rings with different threshold voltages and interconnection characteristics to monitor the process conditions of the circuit. Since different process conditions (such as uneven distribution of impurities during manufacturing, temperature changes, etc.) will affect the threshold voltage of the Vth cell and the signal transmission characteristics of the wire type, by measuring the frequency of the oscillator ring, the current process status of the circuit can be indirectly reflected, and it can be used as one of the inputs of the above-mentioned machine learning model to adjust the operating voltage and frequency to achieve the purpose of reducing power consumption and improving performance.

[0114] The above-mentioned threshold voltage unit refers to a unit that characterizes the threshold voltage (Vth) of a circuit through a specific unit structure (such as a transistor) in integrated circuit design. The threshold voltage is an important parameter for measuring the on and off states of a transistor. Different Vth values ​​mean that the transistor has different on and off characteristics, which affects the power consumption and performance of the circuit. In the design, units with different Vth can be used to adjust the power consumption and performance of the circuit as needed. For example, a low Vth unit can provide higher performance, but with higher power consumption; while a high Vth unit has lower power consumption, but the performance may be limited.

[0115] The above interconnection types refer to the physical characteristics and design methods of signal lines in integrated circuits. Signal lines (interconnections) connect different parts of the circuit, and their design has an important impact on the performance and power consumption of the circuit. Interconnection types generally include the width, length, number of layers, and resistance and capacitance characteristics of metal lines. In chip design, different interconnection strategies affect the transmission speed and energy loss of signals. For example, thicker metal lines can reduce resistance and thus power consumption, but may also increase chip area and manufacturing costs; while finer metal lines can save space, but may increase signal delay and power consumption.

[0116] The present application proposes a method for adaptively adjusting the operating voltage of a chip. The method comprehensively considers factors such as process, voltage, temperature, aging (PVTA) of chip performance, and constructs chip performance through an offline trained machine learning model (ML-Mode l), that is, the relationship between the minimum operating voltage at different frequencies and various influencing factors. The machine learning model is applied to an actual chip device, and the minimum operating voltage value of each chip under different PVTA conditions at different frequencies is automatically found by real-time detection of the sensor value of each PVTA, thereby reducing chip power consumption and saving testing costs.

[0117] In this application, the minimum operating voltage of different chips can be effectively determined through an adaptive voltage adjustment method, thereby effectively reducing the power consumption of different chips. This application can detect the sensor detection value of each PVTA in real time, automatically find out the minimum operating voltage value of different chips under different frequency points and different PVTA conditions, and reduce the power consumption of each chip. There is no need to perform ATE testing on each chip, which greatly reduces the testing cost. Taking into account the impact of circuit aging on chip performance, the chip performance model is more accurate.

[0118] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0119] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0120] Through the description of the above implementation modes, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware.

[0121] According to an embodiment of the present application, a chip operating voltage regulating device for implementing the above chip operating voltage regulating method is also provided. Figure 5is a schematic diagram of a chip operating voltage regulating device according to an embodiment of the present application, such as Figure 5 As shown, the device 500 includes: a collection module 502 , a prediction module 504 , and an adjustment module 506 .

[0122] Among them, the acquisition module 502 is used to collect multiple detection values ​​of the chip in response to receiving the chip's working voltage adjustment instruction, wherein different detection values ​​are used to detect the chip through different types of sensors; the prediction module 504 is used to predict the multiple detection values ​​using the voltage model to obtain the frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum working voltage corresponding to the chip at different working frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum working voltages corresponding to sample chips at different working frequencies; the adjustment module 506 is used to adjust the current working voltage of the chip based on the frequency-voltage mapping relationship and the target working frequency of the chip, wherein the target working frequency is the working frequency to be achieved by the chip.

[0123] It should be noted that the acquisition module 502, prediction module 504, and adjustment module 506 correspond to steps S302 to S306 in Example 1, and the three modules and the corresponding steps implement the same examples and application scenarios, but are not limited to the contents disclosed in the above-mentioned Example 1. It should be noted that the above-mentioned modules or units may be hardware components or software components stored in a memory (e.g., memory 104) and processed by one or more processors (e.g., processors 102a, 102b, ..., 102n), and the above-mentioned modules may also be part of the device and may be run in the computer terminal 10 provided in Example 1.

[0124] In the above embodiments of the present application, the adjustment module is also used to adjust the current operating frequency of the chip to the target operating frequency, wherein the target operating frequency is determined based on the current load of the chip; select the lowest operating voltage corresponding to the target operating frequency from the frequency-voltage mapping relationship; and adjust the current operating voltage of the chip based on the lowest operating voltage.

[0125] In the above embodiments of the present application, the adjustment module is also used to obtain the voltage margin of the chip, wherein the voltage margin is used to offset the model error caused by the voltage model; determine the target operating voltage based on the sum of the minimum operating voltage and the voltage margin; and adjust the current operating voltage of the chip to the target operating voltage.

[0126] In the above embodiment of the present application, the voltage model is obtained by adjusting the model parameters of the initial voltage model through the loss function. The loss function is constructed based on the test working voltage and the sample minimum working voltage. The test working voltage is obtained by predicting multiple sample detection values ​​by the initial voltage model.

[0127] In the above embodiments of the present application, the acquisition module is used to call the software interfaces of different types of sensors to read multiple detection values ​​in response to receiving an operating voltage adjustment instruction of the chip.

[0128] It should be noted that the preferred implementation scheme involved in the above embodiments of the present application is the same as the scheme provided in Example 1, as well as the application scenario and implementation process, but is not limited to the scheme provided in Example 1.

[0129] The present application provides a chip operating voltage regulation system. Figure 6 is a schematic diagram of a chip operating voltage regulation system according to an embodiment of the present application, such as Figure 6 As shown, the system 600 includes: multiple sensors 602, connected to the chip 604, for detecting the chip and obtaining multiple detection values; a voltage regulation device 606, connected to the multiple sensors, for collecting multiple detection values ​​after receiving the chip's operating voltage regulation instruction, and using the voltage model to predict the multiple detection values ​​to obtain the frequency-voltage mapping relationship of the chip, and the current operating voltage of the chip based on the frequency-voltage mapping relationship and the target operating frequency of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies, and the target operating frequency is the operating frequency to be achieved by the chip.

[0130] The above multiple sensors are the basic components of the system, distributed in different key positions of the chip, and are used to monitor the PVTA (process, voltage, temperature, aging) characteristics of the chip in real time. The process sensor is used to monitor the manufacturing process changes of the chip. The voltage sensor is used to measure the actual operating voltage of the chip or its local block, as well as the voltage drop. The temperature sensor is used to detect the real-time temperature of the chip. The aging sensor is used to monitor the degree of chip aging over time.

[0131] The voltage regulator is responsible for receiving the operating voltage adjustment instructions from the software layer, and according to the real-time detection value of the sensor, calculates the minimum operating voltage value of the chip under the current conditions through the voltage model. The voltage regulator applies the adjusted voltage to the chip to ensure that it runs stably at the target operating frequency.

[0132] The entire system initiates the operating voltage adjustment instruction through the software layer, triggering the voltage adjustment device to make adjustments. The software layer determines the value to which the chip's operating voltage should be adjusted based on the target operating frequency and the frequency-voltage mapping relationship. The prediction results of the voltage model are used to update the frequency-voltage table (FV table le) to guide the DVFS (dynamic voltage-frequency adjustment) system to dynamically adjust the voltage and frequency to achieve the purpose of power optimization and performance maximization. The adaptive adjustment process is dynamic and can be executed at different stages of chip startup and operation, as well as throughout the life cycle of the chip. As the chip ages, the sensor data will reflect the changes, and the model will adjust the prediction based on the new data to ensure that the operating voltage setting is always good.

[0133] Through the above structure and mechanism, the system can dynamically adjust the operating voltage without sacrificing chip performance and stability, thereby minimizing power consumption and reducing testing costs.

[0134] In the above embodiment of the present application, multiple sensors include: a process sensor, which is used to detect the manufacturing process of the chip and obtain a process detection value, wherein the process detection value is used to represent the deviation value of the chip caused by the manufacturing process; a voltage sensor, which is used to detect the current voltage of the circuit corresponding to the chip and obtain a voltage detection value, wherein the voltage detection value is used to represent the voltage drop from the power supply voltage of the chip to the circuit; a temperature sensor, which is used to detect the current temperature of the chip and obtain a temperature detection value; an aging sensor, which is used to detect the aging state of the chip and obtain an aging detection value, wherein the aging detection value is used to represent the deviation value caused by the change of the chip over time.

[0135] In the embodiment of the present application, the method and device for adaptively adjusting the chip operating voltage realizes comprehensive monitoring of the chip status through multiple sensors (P, V, T, A sensors) integrated inside the chip, so as to dynamically adjust the operating voltage to achieve the purpose of reducing power consumption and improving energy efficiency. Below, I will explain in detail the functions of these sensors and their role in the method in combination with the structure:

[0136] The above-mentioned process sensors are usually composed of special circuits designed on the chip, such as an oscillator ring (RingOscillator). These circuits contain transistors with different threshold voltages (Vth cell) and different types of metal wires (wire). They are sensitive to process changes and can reflect deviations in the chip manufacturing process, such as changes in the threshold voltage of transistors and changes in the resistance of metal wires. Process sensors are used to monitor the manufacturing process of the chip in real time and obtain process detection values. These detection values ​​reflect the performance differences of the chip due to manufacturing process deviations (such as different wafer batches, process nodes, etc.). The process detection values ​​help identify the performance status of the chip under the current process conditions, thereby adjusting the operating voltage to a better state.

[0137] The voltage sensor described above is designed to detect the real-time voltage of the chip's internal circuit, usually by monitoring the difference (voltage drop) between the chip's power supply voltage and the actual operating voltage of the circuit. In the design, the voltage sensor may contain a precision voltage comparator and an analog-to-digital converter to ensure accurate measurement. The voltage sensor is used to detect the real-time voltage of the chip's internal circuit and obtain a voltage detection value, i.e., a voltage drop value, which reflects the distribution and change of the chip's internal voltage. The voltage detection value is used to evaluate the voltage drop from the chip's power supply voltage to the internal circuit, which is crucial to determining the actual operating voltage of the circuit, so that the voltage setting can be optimized under different loads and conditions.

[0138] The above-mentioned temperature sensor can be a thermistor, diode or dedicated temperature detection circuit integrated on the chip, which can sense the temperature change of the chip, and usually changes the resistance value or voltage value as the temperature rises. The temperature sensor is used to monitor the temperature of the chip in real time and obtain the temperature detection value. Temperature is an important factor affecting the performance and power consumption of the chip. Changes in the temperature detection value will cause fluctuations in the performance of the chip. By monitoring the temperature in real time and adjusting the operating voltage, it can be ensured that the chip can maintain relatively good performance and minimum power consumption under various temperature conditions.

[0139] The above-mentioned aging sensor is used to monitor the aging state of the chip over time, which may include monitoring the threshold voltage change of the transistor, the degradation of the capacitor, etc. These changes will gradually accumulate as the chip is used. The aging sensor is used to detect the aging degree of the chip and obtain the aging detection value, which reflects the performance degradation of the chip due to long-term use. The aging detection value takes into account the impact of the chip's use cycle to ensure that even if the chip ages, its performance can be maintained by adjusting the operating voltage to avoid power consumption or premature failure.

[0140] The above-mentioned multiple sensors together constitute a chip status monitoring network. By acquiring dynamic information about the chip in terms of process, voltage, temperature, aging, etc. in real time, ML-Model can be used to predict and adjust the operating voltage that best suits the current state of the chip. This can significantly reduce power consumption and save testing costs while ensuring chip performance, thereby improving the overall energy efficiency and reliability of the chip.

[0141] In the above embodiment of the present application, the process sensor includes: multiple oscillation rings, the oscillation rings include threshold voltage units and interconnected unit rings, which are used to output oscillation frequencies according to the output current of the threshold voltage units and the signal propagation time of the interconnected unit rings, wherein the oscillation frequency is used to represent the process detection value, the threshold voltage power supply is used to reflect the manufacturing process according to transistors with different threshold voltages, and the interconnected unit rings are used to reflect the manufacturing process according to the layout between different signal lines.

[0142] By using multiple oscillation rings, each oscillation ring contains a threshold voltage unit and an interconnection unit ring. The output current of the threshold voltage unit can reflect the threshold voltage of the transistor, while the signal propagation time of the interconnection unit ring can reflect the layout between the signal lines, both of which are key parameters in the chip manufacturing process. Different manufacturing processes will cause changes in threshold voltage and interconnection characteristics, and this change will be directly reflected in the oscillation frequency. Therefore, by monitoring the oscillation frequency, the manufacturing process of the chip can be reflected very accurately, including process fluctuations and process differences between different chips.

[0143] The above process sensor design does not require any modification or damage to the chip circuit, but integrates an oscillation ring at the edge or non-critical area of ​​the chip, which can avoid affecting the chip function and ensure the long-term stability of the sensor. According to the design of the process sensor, the process sensor can continuously monitor the process status of the chip without interfering with the normal operation of the chip.

[0144] As the chip is used, the circuit will gradually age, which will further affect the threshold voltage and the interconnect characteristics of the signal line. The process sensor can detect the process changes caused by aging by continuously monitoring the oscillation frequency, so that the chip can still accurately adjust the operating voltage during the aging process, ensuring performance while reducing power consumption.

[0145] Since the process sensor can monitor the process status of the chip in real time, it can be closely integrated with the dynamic voltage frequency adjustment (DVFS) system to achieve real-time dynamic adjustment of the chip operating voltage. This means that the chip can automatically adjust to the best operating voltage under different workloads, temperatures and aging levels, thereby minimizing power consumption while ensuring performance.

[0146] This application builds a voltage model to pre-train the relationship between chip performance and factors such as process, voltage, temperature, and aging. During the use of the chip, the process status fed back by the process sensor in real time can quickly calculate the minimum operating voltage suitable for the current state, which not only reduces the testing cost, but also improves the power consumption efficiency and performance stability of the chip.

[0147] The design of the above-mentioned process sensor can provide accurate process status feedback and support adaptive voltage regulation of the chip. It can not only adapt to fluctuations in the manufacturing process and chip aging, but also achieve dynamic power consumption optimization. At the same time, it also has significant advantages in testing costs.

[0148] In the above embodiment of the present application, the system further includes: a voltage regulator, used to determine the voltage margin of the chip, wherein the voltage margin is used to offset the model error caused by the voltage model.

[0149] In the embodiment of the present application, a voltage regulator is added to determine the voltage margin of the chip. The introduction of this structure has the following beneficial effects:

[0150] Since ML-Mode l is trained offline based on data from specific test conditions and environments, when the model is applied to the actual chip, it may encounter situations that are different from the training data set, resulting in model errors. The voltage margin setting can be used as a safety mechanism to ensure that the chip can still work stably even when the model prediction is not completely accurate, and will not experience performance degradation or functional failure due to low voltage.

[0151] In actual working environment, the chip may face dynamic changing factors such as process deviation, temperature fluctuation, uncertainty of aging degree, etc. The voltage regulator monitors these factors in real time and dynamically adjusts the voltage margin according to the monitoring results, so that the chip can maintain a relatively good working state in various environments and further optimize the power consumption performance.

[0152] By introducing a voltage regulator, it can be used as a means of correcting the voltage model corresponding to the test results. By combining real-time monitoring data and preset voltage margins, the prediction accuracy and stability under different working conditions can be improved to ensure high chip performance. By accurately adjusting the chip operating voltage, the overvoltage caused by model errors in traditional methods is avoided, thereby effectively reducing the power consumption of the chip and extending the battery life of the device.

[0153] The voltage regulator mentioned above can be used as an independent hardware module, which is easy to integrate into the existing hardware structure. At the same time, its strategy and parameters can be optimized and upgraded according to the feedback from actual applications to maintain the advancement and competitiveness of the system. The addition of the voltage regulator not only enhances the robustness and accuracy of the model, but also simplifies the test process, reduces power consumption, and improves the reliability and efficiency of the entire system.

[0154] An embodiment of the present application may provide a system on chip, including: a system according to any one of the above embodiments.

[0155] The embodiment of the present application may provide an electronic device, which may be any electronic device in a group of electronic devices. Optionally, in this embodiment, the electronic device may also be replaced by a terminal device such as a mobile terminal.

[0156] Optionally, in this embodiment, the electronic device may be located in at least one of a plurality of network devices of a computer network. The electronic device includes a processor storing an executable program. The processor is used to run the program, wherein the program executes any one of the methods in the above embodiments when it is run.

[0157] In this embodiment, the computer terminal can execute the program code in the method.

[0158] The memory can be used to store software programs and modules, such as program instructions / modules corresponding to the methods and devices in the embodiments of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implementing the methods in the above embodiments. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the terminal A via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0159] The processor can call the information and application programs stored in the memory through the transmission device to perform the following steps: in response to receiving the chip's operating voltage adjustment instruction, collect multiple detection values ​​of the chip, wherein different detection values ​​are used to detect the chip through different types of sensors; use the voltage model to predict the multiple detection values ​​to obtain the frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies; adjust the chip's current operating voltage based on the frequency-voltage mapping relationship and the chip's target operating frequency, wherein the target operating frequency is the operating frequency to be achieved by the chip.

[0160] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0161] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0162] Optionally, in this embodiment, the above storage medium may be located in any electronic device in a group of electronic devices in a computer network, or in any mobile terminal in a group of mobile terminals.

[0163] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: in response to receiving an operating voltage adjustment instruction of the chip, collecting multiple detection values ​​of the chip, wherein different detection values ​​are used to detect the chip through different types of sensors; using a voltage model to predict the multiple detection values ​​to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies; adjusting the current operating voltage of the chip based on the frequency-voltage mapping relationship and the target operating frequency of the chip, wherein the target operating frequency is the operating frequency to be achieved by the chip.

[0164] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program, and the computer program implements the method provided in the embodiment when executed by a processor.

[0165] The embodiments of the present application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store a computer program, and when the computer program is executed by a processor, the method provided in the embodiments is implemented.

[0166] The embodiment of the present application further provides a computer program or instruction. Optionally, in this embodiment, when the computer program is executed by a processor, the method provided in the above embodiment is implemented.

[0167] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0168] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0170] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0171] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0172] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or CD-ROM and other media that can store program codes.

[0173] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A chip operating voltage adjustment method, characterized in that: include: In response to receiving an operating voltage adjustment instruction of a chip, collecting a plurality of detection values ​​of the chip, wherein different detection values ​​are obtained by detecting the chip through different types of sensors; The multiple detection values ​​are predicted using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum operating voltage corresponding to the chip at different operating frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum operating voltages corresponding to sample chips at different operating frequencies; The current operating voltage of the chip is adjusted based on the frequency-voltage mapping relationship and the target operating frequency of the chip, wherein the target operating frequency is the operating frequency to be achieved by the chip.

2. The chip operating voltage adjustment method according to claim 1, characterized in that: Adjusting the current operating voltage of the chip based on the frequency-voltage mapping relationship and the target operating frequency of the chip includes: adjusting the current operating frequency of the chip to the target operating frequency, wherein the target operating frequency is determined based on the current load of the chip; Selecting the minimum operating voltage corresponding to the target operating frequency from the frequency-voltage mapping relationship; The current operating voltage of the chip is adjusted based on the lowest operating voltage.

3. The chip operating voltage adjustment method according to claim 2, characterized in that: Adjusting the current operating voltage based on the minimum operating voltage includes: Acquiring a voltage margin of the chip, wherein the voltage margin is used to offset a model error caused by the voltage model; Determining a target operating voltage based on a sum of the minimum operating voltage and the voltage margin; The current operating voltage of the chip is adjusted to the target operating voltage.

4. The chip operating voltage adjustment method according to claim 1, characterized in that: The voltage model is obtained by adjusting the model parameters of the initial voltage model through a loss function, wherein the loss function is constructed based on a test working voltage and a minimum working voltage of the sample, and the test working voltage is obtained by predicting the multiple sample detection values ​​by the initial voltage model.

5. The chip operating voltage adjustment method according to claim 1, characterized in that: In response to receiving an operating voltage adjustment instruction of a chip, collecting a plurality of detection values ​​of the chip, including: In response to receiving the operating voltage adjustment instruction of the chip, the software interfaces of the different types of sensors are called to read the multiple detection values.

6. A chip operating voltage regulation system, characterized in that: include: A plurality of sensors are connected to the chip and are used to detect the chip and obtain a plurality of detection values; A voltage regulating device is connected to the multiple sensors, and is used to collect the multiple detection values ​​after receiving the working voltage adjustment instruction of the chip, and use the voltage model to predict the multiple detection values ​​to obtain the frequency-voltage mapping relationship of the chip, and the current working voltage of the chip based on the frequency-voltage mapping relationship and the target working frequency of the chip, wherein the frequency-voltage mapping relationship is used to describe the minimum working voltage corresponding to the chip at different working frequencies, and the voltage model is trained based on multiple sample detection values ​​and sample minimum working voltages corresponding to sample chips at different working frequencies, and the target working frequency is the working frequency to be achieved by the chip.

7. The chip operating voltage regulation system according to claim 6, characterized in that: The plurality of sensors include: A process sensor, used to detect the manufacturing process of the chip to obtain a process detection value, wherein the process detection value is used to represent a deviation value of the chip caused by the manufacturing process; A voltage sensor, used to detect the current voltage of the circuit corresponding to the chip to obtain a voltage detection value, wherein the voltage detection value is used to represent the voltage drop from the power supply voltage of the chip to the circuit; A temperature sensor is used to detect the current temperature of the chip and obtain a temperature detection value; The aging sensor is used to detect the aging state of the chip to obtain an aging detection value, wherein the aging detection value is used to represent the deviation value caused by the change of the chip over time.

8. The chip operating voltage regulation system according to claim 7, characterized in that: The process sensor comprises: A plurality of oscillation rings, wherein the oscillation rings include a threshold voltage unit and an interconnected unit ring, and are used to output an oscillation frequency according to an output current of the threshold voltage unit and a signal propagation time of the interconnected unit ring, wherein the oscillation frequency is used to represent the process detection value, the threshold voltage power supply is used to reflect the manufacturing process according to transistors with different threshold voltages, and the interconnected unit ring is used to reflect the manufacturing process according to the layout between different signal lines.

9. The chip operating voltage regulation system according to claim 6, characterized in that: The system further comprises: A voltage regulator is used to determine a voltage margin of the chip, wherein the voltage margin is used to offset a model error caused by the voltage model.

10. A system on chip, characterized in that: include: A system as claimed in any one of claims 7 to 9.

11. An electronic device, characterized in that: include: A memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 1 to 6 when running.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is run, the device where the storage medium is located is controlled to execute the method according to any one of claims 1 to 6.

13. A computer program product, characterized in that The method comprises a computer program or instructions, which implements the method according to any one of claims 1 to 6 when the computer program is executed by a processor.

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