Chip design method and device, electronic equipment, readable storage medium and program product

Abstract

The invention relates to a chip design method and device, electronic equipment, a readable storage medium and a program product. When the chip is in a low-power-consumption mode and the vehicle is detected to be started, awakening the low-power-consumption mode of the chip based on a preset awakening event, controlling the chip to enter a transition mode, and when the power supply voltage is detected to be greater than a preset under-voltage threshold value, configuring the clock frequency of the chip based on the working requirement of the chip, the method comprises the following steps: enabling each power supply module in the chip to be powered on, pulling up a reset pin, controlling the chip to enter a normal working mode, and triggering the chip to enter a safety mode under the condition that an abnormal event is detected according to a preset detection logic. According to the invention, response to different application scene requirements can be realized, reduction of system power consumption is facilitated, and each state index of the chip is monitored in real time in a normal working mode, so that the stability of the chip can be improved, and the safety is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a chip design method, device, electronic device, readable storage medium and program product. Background Art

[0002] With the continuous development of automotive electronic technology, the role of automotive electronic chips in automobiles is becoming more and more important. Automotive electronic chips are mainly used to realize various functions of automobiles, such as controlling automobile engines, transmissions, braking systems, etc.

[0003] However, automotive electronic chips need to be powered by batteries, and the battery power is limited. Therefore, how to effectively reduce the power consumption of automotive electronic chips and extend the service life of batteries has become an important topic in the field of automotive electronic technology. At the same time, various faults may occur in the process of operation of automotive electronic chips, such as abnormal clock frequency, abnormal power supply voltage, abnormal temperature, etc. If these faults are not handled in a timely and correct manner, they may cause the performance of automotive electronic chips to decline, and even affect the stability and safety of the body control system. Therefore, how to effectively monitor and handle faults in automotive electronic chips has also become an important topic in the field of automotive electronic technology. Summary of the invention

[0004] Based on this, it is necessary to provide a chip design method, device, electronic device, computer-readable storage medium and computer program product that can reduce power consumption and perform exception processing in order to address the above technical problems.

[0005] In a first aspect, the present application provides a chip design method, wherein the chip is applied to a vehicle, and the method comprises:

[0006] When the chip is in a low power consumption mode and a vehicle is detected to be started, waking up the low power consumption mode of the chip based on a preset wake-up event, and controlling the chip to enter a transition mode;

[0007] When it is detected that the power supply voltage is greater than a preset undervoltage threshold, the clock frequency of the chip is configured based on the working requirements of the chip, each power module in the chip is powered on and the reset pin is pulled high, and the chip is controlled to enter a normal working mode;

[0008] When an abnormal event is detected according to a preset detection logic, the chip is triggered to enter a safe mode.

[0009] In one of the embodiments, after triggering the chip to enter the safe mode, the method further includes: repairing the abnormal event, and when it is determined that the abnormal event has been repaired, enabling power on each power module in the chip to allow the chip to enter the normal working mode.

[0010] In one of the embodiments, after triggering the chip to enter the safe mode, the method further includes: controlling the chip to enter a low power consumption mode when it is detected that the power supply voltage is less than or equal to a preset sleep voltage threshold, and the preset sleep voltage threshold is less than the preset undervoltage threshold; or, controlling the chip to enter a low power consumption mode when a clear instruction for a wake-up flag is detected, and the wake-up flag is generated when it is detected that the power supply voltage is greater than a preset undervoltage threshold; or, controlling the chip to enter a low power consumption mode when it is detected that the abnormal event has timed out and has not been handled.

[0011] In one of the embodiments, after controlling the chip to enter a normal working mode, the method further includes: controlling the chip to enter a low power consumption mode when it is detected that the power supply voltage is less than or equal to a preset sleep voltage threshold, and the preset sleep voltage threshold is less than the preset undervoltage threshold; or, controlling the chip to enter a low power consumption mode when a clear instruction for a wake-up flag is detected, and the wake-up flag is generated when it is detected that the power supply voltage is greater than a preset undervoltage threshold.

[0012] In one of the embodiments, after controlling the chip to enter the transition mode, the method further includes: controlling the chip to enter a low power consumption mode when it is detected that the supply voltage is less than or equal to a preset undervoltage threshold.

[0013] In one of the embodiments, the chip is divided into different power domains according to different power modules; the method also includes: in the low power mode, controlling the chip to turn off the enable signal of the peripheral module and setting the low power enable signal; performing power-off processing on the power module based on a preset power-off sequence, and triggering each functional module in the corresponding power-off power domain to perform a logical reset; determining the isolation value from the power-off power domain to the non-power-off power domain based on signal interaction requirements; performing clock gating management on the clock structure of the chip, turning off the high-speed clock source, and flipping the low-speed clock when the wake-up event is detected.

[0014] In one embodiment, the detection logic includes at least one of the following: detecting the clock frequency of the chip according to the frequency requirement when the chip is working normally; detecting the voltage of each power module of the chip according to the voltage requirement when the chip is working normally; detecting the temperature at different positions of the chip according to the temperature requirement when the chip is working normally; detecting the working state of the chip according to the working state of the chip when it is working normally.

[0015] In a second aspect, the present application provides a chip design device, wherein the chip is applied to a vehicle, and the device comprises:

[0016] A wake-up module, used for waking up the low power consumption mode of the chip based on a preset wake-up event when the chip is in the low power consumption mode and detects that the vehicle is started, and controlling the chip to enter the transition mode;

[0017] A mode configuration module, configured to configure the clock frequency of the chip based on the working requirements of the chip when it is detected that the power supply voltage is greater than a preset undervoltage threshold, enable each power module in the chip to be powered on and pull up the reset pin, and control the chip to enter a normal working mode;

[0018] The abnormality detection module is used to trigger the chip to enter a safe mode when an abnormal event is detected according to a preset detection logic.

[0019] In a third aspect, the present application provides a chip, which is applied to a vehicle and is designed using the above-mentioned method.

[0020] In a fourth aspect, the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0021] In a fifth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps of the above method when executed by a processor.

[0022] In a sixth aspect, the present application provides a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0023] The chip design method, device, electronic device, computer-readable storage medium and computer program product described above, when the chip is in low-power mode and detects that the vehicle is started, wakes up the chip from low-power mode based on a preset wake-up event, controls the chip to enter transition mode, and configures the chip clock frequency based on the chip's working requirements when the power supply voltage is detected to be greater than a preset undervoltage threshold, enables each power module in the chip to power on and pulls up the reset pin, controls the chip to enter normal working mode, and triggers the chip to enter safe mode when an abnormal event is detected according to the preset detection logic. It can respond to different application scenario requirements, help reduce system power consumption, and monitor various chip status indicators in real time in normal working mode and safe mode, thereby improving the chip's stability to ensure safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of a chip design method according to an embodiment;

[0026] Figure 2 A schematic diagram of a chip design method according to another embodiment;

[0027] Figure 3 A structural block diagram of a chip design device in one embodiment;

[0028] Figure 4 FIG. 4 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0030] In one embodiment, Figure 1 As shown, a chip design method is provided, comprising the following steps:

[0031] Step 102 , when the chip is in a low power consumption mode and a vehicle startup is detected, the low power consumption mode of the chip is awakened based on a preset wake-up event, and the chip is controlled to enter a transition mode.

[0032] Among them, the chip can be an ASIC (Application Specific Integrated Circuit) chip used in vehicles. Low power mode is an operating state of the chip, which is characterized by reducing the power consumption of the chip as much as possible to extend battery life or reduce energy consumption. In this embodiment, different power domains can be divided according to the operating voltage range of each module of the chip, and the circuits that do not need to work can be powered off through power gating technology to reduce power consumption; isolation technology can also be used to set the isolation value of the power-off domain signal to the non-power-off domain to ensure that the normal operation of the non-power-off domain circuit is not affected; clock gating technology can also be used to reduce the flipping of logic units to reduce power consumption; power consumption can also be reduced by turning off the enable signal of each module and setting the low power enable signal; according to the power consumption analysis results, the layout and wiring of the circuit can be optimized without affecting the function and timing to reduce power consumption.

[0033] Transition mode is also a running state of the chip, which is the stage before the chip enters the normal working mode, that is, the chip is in a state between low power mode and normal working mode. In this mode, the chip can perform certain logic processing to determine whether to enter the normal working mode or the low power mode. The preset wake-up event can be a pre-set external event for waking up the chip, which can specifically be raising a pin of the chip, or an interactive implementation with the chip.

[0034] In this embodiment, when the chip is in a low power consumption mode and a vehicle start is detected, the low power consumption mode of the chip can be awakened based on a preset wake-up event to control the chip to enter a transition mode.

[0035] Step 104, when it is detected that the power supply voltage is greater than the preset undervoltage threshold, the clock frequency of the chip is configured based on the working requirements of the chip, each power module in the chip is enabled to power on and pull up the reset pin, and the control chip enters the normal working mode.

[0036] The normal working mode refers to a state in which the chip can work normally. The supply voltage is the supply voltage of the battery that powers the chip. The preset undervoltage threshold can be a voltage threshold pre-set based on the minimum supply voltage of the battery when the chip works normally.

[0037] In this embodiment, when the chip is in transition mode, the battery supply voltage can be detected. When it is detected that the supply voltage is greater than the preset undervoltage threshold, the chip clock frequency is configured based on the chip's working requirements, and each power module in the chip is enabled to power on and pull up the reset pin, thereby controlling the chip to enter normal working mode.

[0038] Step 106: When an abnormal event is detected according to the preset detection logic, trigger the chip to enter a safe mode.

[0039] Safe mode is also an operating state of the chip. In safe mode, based on the specific type of abnormal event, a reset event may or may not be triggered; the digital logic of the entire chip may or may not be reset; the control register will be reset and restored to the initial state accordingly, and all peripheral modules or power modules that generate communication may or may not be turned off. The preset detection logic is the relevant logic that is pre-set to monitor various status indicators in the normal working mode of the chip. Abnormal events can be abnormal or erroneous status indicators.

[0040] In this embodiment, when the chip is in the normal working mode, abnormal events in the working process of the chip can be detected according to the preset detection logic, and when the abnormal events are detected, the chip is triggered to enter the safe mode.

[0041] In the above chip design method, when the chip is in low power mode and the vehicle is detected to be started, the low power mode of the chip is awakened based on a preset wake-up event, and the chip is controlled to enter a transition mode. When the power supply voltage is detected to be greater than the preset undervoltage threshold, the chip clock frequency is configured based on the chip's working requirements, and each power module in the chip is enabled to power on and pull up the reset pin, and the chip is controlled to enter a normal working mode. When an abnormal event is detected according to the preset detection logic, the chip is triggered to enter a safe mode. It can respond to the needs of different application scenarios, help reduce system power consumption, and monitor various status indicators of the chip in real time in normal working mode and safe mode, thereby improving the stability of the chip to ensure safety.

[0042] In an exemplary embodiment, in step 106, after triggering the chip to enter the safe mode, the above method may also include: repairing the abnormal event, and when it is determined that the abnormal event has been repaired, enabling each power module in the chip to power on so that the chip enters the normal working mode.

[0043] Among them, the repair process refers to the process of repairing the abnormal event to make it normal. Specifically, according to the different error states of the abnormal event, it can be selected whether to turn off the power module, whether to trigger the reset, whether to turn off the relevant peripheral modules, whether to reset the relevant control registers, and whether to perform switch processing on each module of the system, so as to realize the repair process of the abnormal event. In this embodiment, after the chip is triggered to enter the safe mode due to the abnormal event, the abnormal event can be repaired, and when it is determined that the abnormal event has been repaired, the power modules in the chip can be powered on, so that the chip can resume the normal working mode.

[0044] In an exemplary embodiment, in step 106, after triggering the chip to enter the safe mode, the above method may also include: controlling the chip to enter the low power consumption mode when it is detected that the power supply voltage is less than or equal to the preset sleep voltage threshold; or, controlling the chip to enter the low power consumption mode when a clear instruction for the wake-up flag is detected, wherein the wake-up flag is generated when it is detected that the power supply voltage is greater than the preset undervoltage threshold; or, controlling the chip to enter the low power consumption mode when it is detected that an abnormal event has timed out and has not been handled.

[0045] The preset sleep voltage threshold may be a voltage threshold preset based on the maximum power supply voltage provided by the battery when the chip is operating in low power consumption mode. Specifically, the preset sleep voltage threshold is less than the preset undervoltage threshold. For example, in one scenario, the preset sleep voltage threshold may be 3.6V, and the preset undervoltage threshold may be 6.3V.

[0046] Specifically, after the chip is triggered to enter the safe mode due to an abnormal event, the chip can also enter the low power mode based on the chip's handling of the abnormal event in the safe mode and the external triggering event. Specifically, if the battery supply voltage is reduced, when the chip detects that the supply voltage is less than or equal to the preset sleep voltage threshold, the chip can be controlled to enter the low power mode. Alternatively, if a clear instruction for the wake-up flag is sent to the chip, the chip can be controlled to enter the low power mode when it receives the corresponding clear instruction. Alternatively, when the chip detects that the processing of the abnormal event has timed out, the chip can be controlled to enter the low power mode. Thereby further reducing the power consumption of the chip and extending the battery life.

[0047] In an exemplary embodiment, in step 104, after the control chip enters the normal working mode, the above method may also include: when it is detected that the power supply voltage is less than or equal to the preset sleep voltage threshold, the control chip enters the low power consumption mode; or, when it is detected that a clear instruction for the wake-up flag is generated, the control chip enters the low power consumption mode, wherein the wake-up flag is generated when it is detected that the power supply voltage is greater than the preset undervoltage threshold.

[0048] Among them, the preset sleep voltage threshold is less than the preset undervoltage threshold. Specifically, after the chip enters the normal working mode, it can also be triggered to enter the low power mode by external events based on the needs of the actual scenario. For example, the battery supply voltage can be reduced, and when the chip detects that the supply voltage is less than or equal to the preset sleep voltage threshold, the chip can be controlled to enter the low power mode. It is also possible to send a clear instruction for the wake-up flag to the chip, and when the chip receives the corresponding clear instruction, it can control the chip to enter the low power mode. Thereby, it can adapt to different application scenarios to improve the application flexibility of the chip.

[0049] In an exemplary embodiment, in step 102, after the chip is controlled to enter the transition mode, the method may further include: when it is detected that the power supply voltage is less than or equal to a preset undervoltage threshold, the chip is controlled to enter the low power consumption mode. Specifically, when the chip is in the transition mode, if it is detected that the battery power supply voltage is less than or equal to the preset undervoltage threshold, the chip is controlled to enter the low power consumption mode, thereby protecting the chip and extending the battery life.

[0050] In an exemplary embodiment, Figure 2 As shown, the above chip design method is further described below, which may specifically include the following steps:

[0051] Step 202: Chip initialization.

[0052] Specifically, after the chip is powered on for the first time, it performs initialization processing. For example, it waits for the power-on reset to be released, enables the power supply module inside the chip for generating strong drive analog power supply and digital power supply, then enables the clock of the EFUSE (a non-volatile storage device for storing information and protecting the chip) module and releases the reset, and performs the initial EFUSE LOAD operation (this operation is used to load the system configuration parameters).

[0053] Step 204, low power consumption configuration.

[0054] Specifically, after EFUSE LOAD is completed, the clock is turned off and the chip enters a low-power configuration. For example, EFUSE output isolation is set, the strong drive analog power supply and digital power supply modules are turned off, and each power supply module is turned off in a certain power-off sequence, so that the chip can enter a low-power mode to reduce system power consumption.

[0055] Step 206, low power consumption mode.

[0056] After the low power configuration in the above steps, the chip directly enters the low power mode.

[0057] Step 208, transition mode.

[0058] Specifically, when the chip is in a low power consumption mode and it is detected that the vehicle is started, the low power consumption mode of the chip is awakened based on a preset wake-up event, thereby controlling the chip to enter a transition mode.

[0059] Step 210: Detect whether the supply voltage is greater than a preset undervoltage threshold.

[0060] Specifically, if the supply voltage is detected to be greater than the preset undervoltage threshold, step 212 is executed to configure the working mode to enter the normal working mode. If the supply voltage is detected to be less than or equal to the preset undervoltage threshold, step 206 is returned to the low power consumption mode.

[0061] Step 212, working mode configuration.

[0062] If it is detected that the power supply voltage is greater than the preset undervoltage threshold, the working mode configuration is performed. Specifically, by enabling the strong drive analog and digital power supply, the EFUSE output isolation is released, and the EFUSE clock is enabled, so that the EFUSE performs the RELOAD (reload) operation. After the RELOAD is completed, the internal high-speed crystal oscillator is enabled, and the high-speed crystal oscillator is selected as the system clock. At this time, the clock is ready. According to the functions of each power module and the dependencies between them, the hardware enables each power module in a certain power-on sequence. After the power is ready, wait for the system reset to be released, and pull up the reset pin to communicate with the external MCU (Microcontroller Unit) so that the MCU can know that the ASIC chip is ready and can interact with it. Then the chip can enter the normal working mode to achieve the corresponding function control.

[0063] Step 214, normal working mode.

[0064] After the working mode configuration in the above steps, the chip directly enters the normal working mode.

[0065] Step 216: Whether an abnormal event is detected.

[0066] When the chip is in normal working condition, the overall working state of the chip may be disturbed due to the influence of external environmental factors or sudden abnormalities of internal modules. Therefore, the monitoring of various abnormal indicators of the chip and the error handling after the failure greatly affect the safety and stability of the chip.

[0067] Based on this, in this embodiment, when the chip is in a normal working mode, the working status indicators of the chip can be detected according to a preset detection logic. If an abnormal event (i.e., an abnormal indicator or a fault) is detected, step 218 is executed to enter the safe mode; if no abnormal event is detected, step 224 is executed to detect whether there is a low power mode triggering event.

[0068] In this embodiment, the detection logic may include at least one of the following:

[0069] According to the frequency requirements of the chip when it is working normally, the clock frequency of the chip is tested. For example, the calibrated, high-precision low-speed crystal oscillator inside the chip can be used as a reference clock to count and compare the system clock. When the counting result shows that the system clock exceeds or is lower than a certain range of the center frequency, it means that an abnormal event has been detected.

[0070] According to the voltage requirements of the chip during normal operation, the voltage of each power module of the chip is detected. For example, the internally generated bandgap reference voltage can be used to detect the chip power supply, IO (input and output) power supply, internal analog power supply, digital power supply, and external power supply, etc., and different voltage detection ranges can be set according to the application scope and design accuracy of each power supply. When overvoltage or undervoltage detection is triggered, it means that an abnormal event has been detected.

[0071] According to the temperature requirements of the chip during normal operation, the temperature of different locations of the chip is detected. For example, the temperature detection system built into the chip can be used to monitor the core area of ​​the chip, each power module, and each peripheral module, and different high temperature thresholds can be set according to the possible impact of temperature on each component and module. When overtemperature is triggered, it means that an abnormal event has been detected.

[0072] According to the working status of the chip when it is working normally, the working status of the chip is detected. For example, the chip's interactive system can be monitored by using the watchdog module inside the chip to monitor the interactive system with the external MCU. When the interaction between the ASIC chip and the external MCU is abnormal, the watchdog cannot be fed normally, and a timeout error event is triggered, indicating that an abnormal event has been detected. The chip's logic self-test system can also be monitored by using the DFT (Design For Test) strategy generated inside the chip to monitor the logic self-test system of the entire chip. When the logic self-test is in operation or fails to run, it means that an abnormal event has been detected.

[0073] Step 218, safe mode.

[0074] Specifically, when the chip is in a normal working mode, if an abnormal event is detected, it triggers entry into a safe mode.

[0075] In safe mode, abnormal events can be repaired and processed, and different processing can be performed based on different abnormal events. For example, the peripheral modules driven by the clock can be turned off, the control registers related to the peripheral modules can be reset, and the closed modules can be turned on after the clock frequency returns to the normal value. After sending software instructions to clear the error status flag, the system can return to normal mode and resume operation.

[0076] It is understandable that in safe mode, the chip's working status indicators can also be monitored in real time. Since a small number of abnormal events may cause the power module to be shut down in safe mode, the voltage detection enable will also be turned off when the power module is shut down, so the remaining indicators that can be monitored will be retained in safe mode. At this time, if some abnormal events are eliminated and the power module is powered on again, the voltage detection enable will be turned on again even if the system is still in safe mode.

[0077] Step 220: Repair the abnormal event.

[0078] Specifically, in the safe mode, different abnormal events may cause different impacts and results. Therefore, the chip can also perform corresponding repair processing according to the specific abnormal events.

[0079] For example, in response to abnormal clock frequency events, the clock-driven peripheral modules can be shut down, the control registers related to the peripheral modules can be reset, and after the clock frequency returns to normal, the shut-down modules can be opened and software instructions can be sent to clear the error status flags.

[0080] For abnormal events of power module voltage, the processing methods can be differentiated according to different event categories and event urgency, such as shutting down all power supplies or only shutting down the faulty power supply itself, or only alarming, or selectively triggering reset events, selectively shutting down peripheral modules related to the faulty power supply and resetting the corresponding control registers. Until the voltage abnormality event disappears, each power module can be started in a certain power-on sequence, and after waiting for the chip reset to be released, the chip can start working normally.

[0081] For abnormal temperature events, all power supplies can be selectively turned off or the faulty power supply itself can be turned off according to the over-temperature conditions triggered by different components, or only an alarm can be issued. A reset event can also be selectively triggered, and peripheral modules related to the faulty power supply can be selectively turned off and the corresponding control registers can be reset. Until the over-temperature abnormal event disappears, each power supply can wait for a period of time and then start in a certain power-on sequence. After the chip reset is released, the chip can start working normally.

[0082] For abnormal events in the working state, a reset event can be triggered to reset the digital logic of the entire chip, shut down each peripheral module, and leave the power module unaffected. After a period of time, the system reset is released, the restart is completed, and the chip resumes normal operation. Alternatively, each peripheral module can be shut down, the corresponding control registers can be reset, and the power module does not need to be processed; until the next logic self-test process is started and runs successfully, the system can automatically return to normal mode and the chip starts to work normally.

[0083] It should be noted that various abnormality detection and abnormality repair processing mechanisms for the chip in this embodiment can be completed through hardware logic, thereby improving the stability of the system and the convenience of operation.

[0084] Step 222, determining whether the abnormal event is repaired within a set time.

[0085] Specifically, if the abnormal event has been repaired within the set time, then return to step 214 and enter the normal working mode. If the abnormal event has not been repaired within the set time, then jump to step 204 and perform low power configuration. Specifically, a timeout mechanism can be set when an abnormal event is detected. When the timeout count is completed, if the abnormal event has not been repaired, then jump to step 204 and perform low power configuration to enter the low power mode, thereby reducing system power consumption while ensuring security.

[0086] Step 224: Detect whether there is a low power consumption mode triggering event.

[0087] Specifically, when the system is not in a state where full power is not required, the chip can be controlled to enter low power mode by triggering low power events such as reducing the power supply voltage or sending software instructions. In low power mode, the chip can be controlled to turn off the enable signal of the peripheral module and set the low power enable signal; and the power module is powered off based on the preset power-off sequence, triggering the logic reset of each functional module in the corresponding power-off power domain, so that the chip can be restored to a safe state. Because of the power-off operation involved, the isolation value from the power-off power domain to the non-power-off power domain can also be determined based on the signal interaction requirements (such as the signals of the digital and analog interaction parts), so as to ensure that the working circuit of the non-power-off power domain can work reasonably and normally. The clock structure of the chip can also be clock-gated, the high-speed clock source is turned off, and the low-speed clock is flipped when a wake-up event is detected.

[0088] Therefore, whether in normal working mode or safe mode, the chip can detect whether there is a low power mode triggering event, and if a low power mode triggering event is detected, it triggers entry into low power mode. If no low power mode triggering event is detected, the current mode is maintained. For example, if the chip detects a low power mode triggering event in normal working mode, it jumps to step 204 to perform low power configuration to enter low power mode; if the chip does not detect a low power mode triggering event in normal working mode, it continues to run in normal working mode. If the chip detects a low power mode triggering event in safe mode, it jumps to step 204 to perform low power configuration to enter low power mode; if the chip does not detect a low power mode triggering event in safe mode, it continues to run in safe mode.

[0089] The above-mentioned embodiments respond to the requirements of different application scenarios and monitor various status indicators of the chip in real time, thereby effectively reducing power consumption and completing the processing of abnormal events, thereby providing strong protection for the chip and improving the stability and security of the system.

[0090] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0091] Based on the same inventive concept, the embodiment of the present application also provides a chip design device for implementing the chip design method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more chip design device embodiments provided below can refer to the limitations on the chip design method above, and will not be repeated here.

[0092] In an exemplary embodiment, Figure 3 As shown, a chip design device is provided, the chip is applied to a vehicle, the device comprises: a wake-up module 302, a mode configuration module 304 and an abnormality detection module 306, wherein:

[0093] A wake-up module 302 is used to wake up the low power consumption mode of the chip based on a preset wake-up event when the chip is in the low power consumption mode and detects that a vehicle is started, and control the chip to enter the transition mode;

[0094] A mode configuration module 304 is used to configure the clock frequency of the chip based on the working requirements of the chip when it is detected that the power supply voltage is greater than a preset undervoltage threshold, enable each power module in the chip to power on and pull up the reset pin, and control the chip to enter a normal working mode;

[0095] The abnormality detection module 306 is used to trigger the chip to enter a safe mode when an abnormal event is detected according to a preset detection logic.

[0096] In an exemplary embodiment, it also includes an abnormality repair module, which is used to repair the abnormal event after triggering the chip to enter the safe mode. When it is determined that the abnormal event has been repaired, each power module in the chip is powered on to make the chip enter the normal working mode.

[0097] In an exemplary embodiment, a mode switching module is also included, which is used to control the chip to enter a low power consumption mode after triggering the chip to enter a safe mode when it is detected that the power supply voltage is less than or equal to a preset sleep voltage threshold; or, when a clear instruction for a wake-up flag is detected, control the chip to enter a low power consumption mode, and the wake-up flag is generated when it is detected that the power supply voltage is greater than a preset undervoltage threshold; or, when it is detected that the abnormal event has timed out and has not been handled, control the chip to enter a low power consumption mode.

[0098] In an exemplary embodiment, the mode switching module is also used to control the chip to enter a normal working mode after entering the normal working mode, and when it is detected that the power supply voltage is less than or equal to a preset sleep voltage threshold, the chip is controlled to enter a low power consumption mode; or, when a clear instruction for a wake-up flag is detected, the chip is controlled to enter a low power consumption mode, and the wake-up flag is generated when it is detected that the power supply voltage is greater than a preset undervoltage threshold.

[0099] In an exemplary embodiment, the mode switching module is further configured to control the chip to enter a low power consumption mode after controlling the chip to enter a transition mode, if it is detected that the supply voltage is less than or equal to a preset undervoltage threshold.

[0100] In an exemplary embodiment, the chip is divided into different power domains according to different power modules; in the low power mode, the chip is controlled to turn off the enable signal of the peripheral module and set the low power enable signal; the power module is powered off based on a preset power-off sequence, and each functional module in the corresponding power-off power domain is triggered to perform a logical reset; the isolation value from the power-off power domain to the non-power-off power domain is determined based on signal interaction requirements; the clock structure of the chip is clock-gated, the high-speed clock source is turned off, and the low-speed clock is flipped when the wake-up event is detected.

[0101] In an exemplary embodiment, the detection logic includes at least one of the following: detecting the clock frequency of the chip according to the frequency requirement when the chip is working normally; detecting the voltage of each power module of the chip according to the voltage requirement when the chip is working normally; detecting the temperature at different positions of the chip according to the temperature requirement when the chip is working normally; detecting the working state of the chip according to the working state of the chip when it is working normally.

[0102] Each module in the above chip design device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0103] Based on the same inventive concept, the embodiment of the present application also provides a chip, which is obtained by using the design method provided by any of the above method embodiments. Therefore, the implementation solution provided by the chip to solve the problem is similar to the implementation solution recorded in the above method, so it will not be repeated here.

[0104] In an exemplary embodiment, an electronic device is provided. The electronic device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 4As shown. The electronic device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC) or other technologies. When the computer program is executed by the processor, a chip design method is implemented. The display unit of the electronic device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the electronic device casing, or an external keyboard, touchpad or mouse.

[0105] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0106] In an exemplary embodiment, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0107] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0108] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0109] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0110] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0111] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0112] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the present application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip design method, characterized in that: The chip is applied to a vehicle, and the method comprises: When the chip is in a low power consumption mode and a vehicle is detected to be started, waking up the low power consumption mode of the chip based on a preset wake-up event, and controlling the chip to enter a transition mode; When it is detected that the power supply voltage is greater than a preset undervoltage threshold, the clock frequency of the chip is configured based on the working requirements of the chip, each power module in the chip is powered on and the reset pin is pulled high, and the chip is controlled to enter a normal working mode; When an abnormal event is detected according to a preset detection logic, the chip is triggered to enter a safe mode.

2. The method according to claim 1, characterized in that After triggering the chip to enter the safe mode, the method further includes: Performing repair processing on the abnormal event, and when it is determined that the abnormal event has been repaired, enabling each power module in the chip to be powered on, so that the chip enters a normal working mode; or, When it is detected that the power supply voltage is less than or equal to a preset sleep voltage threshold, the chip is controlled to enter a low power consumption mode, and the preset sleep voltage threshold is less than the preset undervoltage threshold; or, When a clear instruction for a wake-up flag is detected, the chip is controlled to enter a low power consumption mode, wherein the wake-up flag is generated when a power supply voltage is detected to be greater than a preset undervoltage threshold; or When it is detected that the abnormal event has timed out and has not been processed, the chip is controlled to enter a low power consumption mode.

3. The method according to claim 1, characterized in that: After controlling the chip to enter a normal working mode, the method further includes: When it is detected that the power supply voltage is less than or equal to a preset sleep voltage threshold, the chip is controlled to enter a low power consumption mode, and the preset sleep voltage threshold is less than the preset undervoltage threshold; or, When a clear instruction for a wake-up flag is detected, the chip is controlled to enter a low power consumption mode, and the wake-up flag is generated when it is detected that the power supply voltage is greater than a preset undervoltage threshold.

4. The method according to claim 1, characterized in that After controlling the chip to enter the transition mode, the method further includes: When it is detected that the supply voltage is less than or equal to a preset undervoltage threshold, the chip is controlled to enter a low power consumption mode.

5. The method according to any one of claims 1 to 4, characterized in that: The chip is divided into different power domains according to different power modules; the method also includes: In the low power consumption mode, controlling the chip to turn off the enable signal of the peripheral module and setting the low power consumption enable signal; The power module is powered off based on a preset power-off sequence, and each functional module in the corresponding power-off power domain is triggered to perform a logical reset; an isolation value from the power-off power domain to the non-power-off power domain is determined based on signal interaction requirements; Clock gating management is performed on the clock structure of the chip, the high-speed clock source is turned off, and the low-speed clock is flipped when the wake-up event is detected.

6. A chip design device, characterized in that: The chip is applied to a vehicle, and the device comprises: A wake-up module, used for waking up the low power consumption mode of the chip based on a preset wake-up event when the chip is in the low power consumption mode and detects that the vehicle is started, and controlling the chip to enter the transition mode; A mode configuration module, configured to configure the clock frequency of the chip based on the working requirements of the chip when it is detected that the power supply voltage is greater than a preset undervoltage threshold, enable each power module in the chip to be powered on and pull up the reset pin, and control the chip to enter a normal working mode; The abnormality detection module is used to trigger the chip to enter a safe mode when an abnormal event is detected according to a preset detection logic.

7. A chip, characterized in that: The chip is applied to a vehicle, and the chip is designed by using the method described in any one of claims 1 to 5.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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