FPGA device remote updating method, system and device and storage medium

Abstract

The invention discloses a method, a system and a device for remotely updating an FPGA device and a storage medium, which are used for simplifying the updating process of the FPGA device and reducing the updating maintenance cost. The method comprises the following steps: a test instrument receives an update file and an update instruction issued by an upper computer through a network port; the ARM processor of the test instrument analyzes the update file according to the update instruction and a preset format and packages an analysis result into message information in a paging manner; the ARM processor sends the message information to an FPGA (Field Programmable Gate Array) of the test instrument through a serial communication interface; and the FPGA analyzes the received message information and generates a Flash standard instruction, and performs read-write operation on a Flash memory through the Flash standard instruction so as to update the code of the FPGA.

Description

Technical Field

[0001] The present application relates to the field of embedded technology, and in particular to a method, system, device and storage medium for remote updating of an FPGA device. Background Art

[0002] In electronic instruments and equipment, FPGA (field programmable gate array) devices are widely used in the display panel testing industry due to their high flexibility and customizability. The excellent scalability of FPGA devices can support multiple video interface standards, such as VGA, DVI, HDMI, etc., and can be customized and expanded as needed, allowing designers to quickly respond to market demands and develop display solutions that meet specific application requirements.

[0003] Currently, electronic instruments using FPGA on the market do not frequently update and iterate the FPGA code because of their single function. However, in the display panel testing industry, because the measuring instruments are non-standard customized products and there are hundreds of display products to be tested, in order to make the test instruments adapt to different display products to be tested, the FPGA code needs to be updated frequently.

[0004] In the prior art, FPGA code is usually updated through a burner and designated burning software, or through the device-specified hardware interface, such as spi, iic, etc. However, in actual use environments, test instruments are installed together with automation equipment, and each update requires disassembly and reconnection of hardware. The entire update process is very inconvenient and time-consuming. Especially in aging or OTP devices, the number of test instrument clusters assembled is large, which greatly increases the workload of FPGA code updates, resulting in low update efficiency. Summary of the invention

[0005] The present application provides a method, system, device and storage medium for remotely updating an FPGA device, which are used to simplify the update process of the FPGA device and reduce the update and maintenance costs.

[0006] The first aspect of the present application provides a method for remotely updating an FPGA device, comprising: The test instrument receives the update files and update instructions sent by the host computer through the network port; The ARM processor of the test instrument parses the update file according to the update instruction and in a preset format and encapsulates the parsing result into message information in pages; The ARM processor sends the message information to the FPGA of the test instrument through a serial communication interface; The FPGA parses the received message information and generates Flash standard instructions, and performs read and write operations on the Flash memory through the Flash standard instructions to update the code of the FPGA.

[0007] Optionally, the ARM processor of the test instrument parses the update file according to the update instruction and in a preset format and encapsulates the parsing result into message information in pages, including: The ARM processor of the test instrument unpacks the update file according to the update instruction and the preset Page size to obtain a plurality of data blocks; The ARM processor encapsulates the control instruction and the data block into message information, wherein the control instruction includes an address configuration instruction, a data write operation cache instruction and a trigger instruction.

[0008] Optionally, the FPGA parses the received message information to obtain a Flash standard instruction, and performs a read and write operation on a Flash memory through the Flash standard instruction, including: The FPGA parses the received message information to obtain the write address of the Flash memory and the data block; The FPGA generates a Flash standard instruction according to the write address of the Flash memory and the data block, and triggers a write operation of the Flash memory through the trigger instruction, wherein the write operation is used to write the data block to a target address.

[0009] Optionally, after the FPGA writes the data block to the target address, the method further includes: The FPGA fills the address configuration instruction according to the target address, and triggers a read operation of the Flash memory through the trigger instruction; The FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent; If yes, then write the next data block; If not, the update is interrupted and an error message is returned to the host computer.

[0010] Optionally, the method further includes: The test instrument returns the update progress to the host computer in real time, so that the host computer displays the update progress through a progress bar on a UI interface.

[0011] Optionally, the update progress is the percentage of the currently updated data size to the entire data size of the update file.

[0012] Optionally, the Flash memory adopts a QSPI interface.

[0013] The second aspect of the present application provides a system for remotely updating an FPGA device, comprising: a host computer, an instruction processing unit and a Flash storage unit, wherein the instruction processing unit and the Flash storage unit are arranged on a test instrument, and the instruction processing unit comprises an ARM processing module and an FPGA processing module; The host computer is used to send update files and update instructions to the instruction processing unit through the network port; The ARM processing module is used to parse the update file according to the update instruction and in a preset format and to encapsulate the parsing result into message information in pages; and to send the message information to the FPGA processing module through a serial communication interface; The FPGA processing module is used to parse the received message information and generate Flash standard instructions, and perform read and write operations on the Flash storage unit through the Flash standard instructions to update the code of the FPGA.

[0014] Optionally, the ARM processing module is further used for: According to the update instruction, the update file is unpacked according to a preset Page size to obtain a plurality of data blocks; The ARM processor encapsulates the control instruction and the data block into message information, wherein the control instruction includes an address configuration instruction, a data write operation cache instruction and a trigger instruction.

[0015] Optionally, the FPGA processing module is further used for: Parsing the received message information to obtain the write address of the Flash storage unit and the data block; A Flash standard instruction is generated according to the write address of the Flash storage unit and the data block, and a write operation of the Flash storage unit is triggered by the trigger instruction, wherein the write operation is used to write the data block to a target address.

[0016] Optionally, the FPGA processing module is further used for: Filling the address configuration instruction according to the target address, and triggering a read operation of the Flash storage unit through the trigger instruction; Compare the read data returned by the read operation with the written data to determine whether the read and written data are consistent; If yes, then write the next data block; If not, the update is interrupted and an error message is returned to the host computer.

[0017] Optionally, the instruction processing unit is used to return the update progress to the host computer in real time, so that the host computer displays the update progress through a progress bar on a UI interface.

[0018] Optionally, the update progress is the percentage of the currently updated data size to the entire data size of the update file.

[0019] Optionally, the Flash storage unit adopts a QSPI interface.

[0020] A third aspect of the present application provides a device for remotely updating an FPGA device, the device comprising: Processor, memory, input-output unit, and bus; The processor is connected to the memory, the input and output unit, and the bus; The memory stores a program, and the processor calls the program to execute the first aspect and any optional method for remotely updating an FPGA device in the first aspect.

[0021] A fourth aspect of the present application provides a computer-readable storage medium, on which a program is stored. When the program is executed on a computer, the method for remotely updating an FPGA device according to the first aspect and any optional item in the first aspect is executed.

[0022] It can be seen from the above technical solutions that this application has the following advantages: The test instrument remotely receives update files and update instructions through the network port, and the ARM processor of the test instrument automatically parses the update file and encapsulates it into a message. After receiving the message, the FPGA automatically executes the update. The entire update process does not require complex manual intervention, which reduces the difficulty of operation. It also supports remote updating of multiple test instrument FPGAs through the local area network at the same time, significantly reducing the manpower and time costs required for the update. In addition, the update method of the present application does not require the use of dedicated burning equipment and software, nor does it rely on a specific FPGA device platform. The update of the FPGA can be achieved using a universal serial interface, which reduces additional hardware and software costs and has good compatibility and scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solution in the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1A flowchart of an embodiment of a method for remotely updating an FPGA device provided in this application; Figure 2 A schematic diagram of hardware connections in the method for remotely updating an FPGA device provided in this application; Figure 3 A flowchart of another embodiment of the method for remotely updating an FPGA device provided by the present application; Figure 4 A schematic diagram of the structure of an embodiment of a system for remotely updating an FPGA device provided in the present application; Figure 5 Functional block diagram of the system for remote updating of FPGA devices provided in this application; Figure 6 A schematic diagram of the structure of an embodiment of an apparatus for remotely updating an FPGA device provided in the present application. DETAILED DESCRIPTION

[0025] The present application provides a method, system, device and storage medium for remotely updating an FPGA device, which are used to simplify the update process of the FPGA device and reduce the update and maintenance costs.

[0026] See also Figure 1 , Figure 1 An embodiment of a method for remotely updating an FPGA device provided in the present application includes: 101. The test instrument receives the update file and update command sent by the host computer through the network port; In this embodiment, the host computer serves as the control and execution unit of the update process, receives instructions from the UI software, and communicates with the test instrument (the lower computer) to complete operations such as transmission of update files and issuing instructions. The UI software is the user interface software, which is a part running on the host computer. The UI software can provide a graphical user interface to help users intuitively operate and control the entire update process.

[0027] Specifically, the host computer can communicate with multiple test instruments at the same time through the network port. The network port provides a high-speed and reliable data transmission channel, which supports the host computer to send update files to the test instruments in batches. The host computer first initiates a connection request and transfers the update file to the test instrument through the FTP protocol. After the file transfer is completed, the host computer will also send an update instruction, which is used to notify the test instrument to start processing the update file. After receiving the FTP file transfer request from the host computer, the test instrument will receive and store the update file in the specified storage area. After receiving the update file, once the test instrument receives the update instruction, it will start the update process and start executing the subsequent update steps.

[0028] 102. The ARM processor of the test instrument parses the update file according to the update instruction and the preset format and encapsulates the parsing result into message information in pages; After receiving the update command from the host computer, the ARM processor of the test instrument will trigger the update process. The ARM processor parses the received update file according to the preset format agreed in advance. The purpose of parsing is to extract the valid data in the update file, that is, the data to be written to the FPGA, to ensure that the file can be correctly divided and encapsulated into messages suitable for transmission. The update file is usually large, so the ARM processor will paging the file according to the preset page size, split the update file into multiple data blocks by unit, and each data block will represent a part of the update file. After that, the ARM processor will encapsulate each data block into message information according to the communication protocol requirements. The message information contains the content of the data block, address information, control instructions, etc. Each message information represents a part of the update file. After receiving these messages, the FPGA will gradually write the data into the Flash memory according to the content in the message information.

[0029] 103. The ARM processor sends the message information to the FPGA of the test instrument through the serial communication interface; In embedded systems, ARM processors usually work with FPGAs to achieve efficient data processing and control. In the remote update process of the FPGA device in this embodiment, the ARM processor is mainly responsible for receiving update instructions, parsing update files and generating corresponding message information, while the FPGA is responsible for updating its own firmware or configuration according to these message information. Therefore, the ARM processor needs to send the packaged message to the FPGA through the serial communication interface.

[0030] It should be noted that the ARM processor can ensure the successful transmission of each message through a confirmation mechanism during the sending process. If an error occurs, it will retransmit or terminate the update process.

[0031] 104. The FPGA parses the received message information and generates Flash standard instructions, and performs read and write operations on the Flash memory through the Flash standard instructions to update the FPGA code.

[0032] FPGA uses an external Flash memory to store firmware code. In this way, FPGA can read the code from Flash for configuration after power-on. When FPGA receives message information from the ARM processor, it must first parse the message information and generate corresponding Flash standard instructions based on the parsed results. These Flash standard instructions follow the standard protocol of the Flash memory, such as write instructions, erase instructions, read instructions, etc. FPGA converts the custom instructions passed by the ARM processor into standard Flash operation instructions. FPGA then communicates with the Flash memory to perform specific read and write operations and write the update file to the specified location of the Flash memory, thereby updating the FPGA code.

[0033] In some specific embodiments, the FPGA is connected to the Flash memory through a QSPI interface. Compared with the traditional SPI, QSPI transmits data in parallel through four data lines, which can significantly improve the speed of data writing and reading. Figure 2 , Figure 2 The hardware connection diagram between the host computer, ARM processor (embedded system), FPGA and Flash memory, in which the host computer communicates with the ARM processor through the network, and the two transmit data through Ethernet or other network protocols. The ARM processor is connected to the FPGA through a custom interface, which can be designed according to specific communication requirements. The custom interface allows the ARM processor to send instructions and data to the FPGA. The FPGA is connected to the Flash memory through the QSPI interface. QSPI is a high-speed serial communication interface that allows the FPGA to communicate with the Flash memory at a high data transfer rate, thereby achieving fast read and write operations and improving update efficiency.

[0034] In this embodiment, the test instrument remotely receives update files and update instructions through the network port, and the ARM processor of the test instrument automatically parses the update file and encapsulates it into a message. After receiving the message, the FPGA automatically executes the update. The entire update process does not require complex manual intervention, which reduces the difficulty of operation, and supports remote updating of multiple test instrument FPGAs through a local area network at the same time, significantly reducing the manpower and time costs required for the update. In addition, the update method of the present application does not require the use of dedicated burning equipment and software, nor does it rely on a specific FPGA device platform. The update of the FPGA can be achieved using a universal serial interface, which reduces additional hardware and software costs and has good compatibility and scalability.

[0035] The following is a detailed description of the FPGA device remote update method provided by this application. Figure 3 , Figure 3Another embodiment of the method for remotely updating an FPGA device provided by the present application includes: 301. The test instrument receives the update file and update command sent by the host computer through the network port; In this embodiment, step 301 is similar to step 101 in the aforementioned embodiment and will not be described in detail here.

[0036] 302. The ARM processor of the test instrument unpacks the update file according to the update instruction and the preset Page size to obtain a plurality of data blocks; In order to effectively write the update file to the Flash memory, the data must be unpacked according to the appropriate size and transmitted in batches. In this embodiment, the ARM processor needs to unpack the update file received from the host computer according to the preset Page size to obtain several data blocks. Each unpacked data block is called a Page. Each Page contains a part of the data that needs to be written to the Flash memory. The ARM processor sends the data blocks page by page to the FPGA for processing.

[0037] In some specific embodiments, for example, the size of the update file is fixed to 64MB, and the preset Page size is fixed to 256 bytes. According to these parameters, the ARM processor splits the 64MB update file into several 256-byte data blocks, that is, a total of 262,144 Pages need to be split. The corresponding ARM processor needs to initiate 262,144 write operations, each time writing the data of a Page to the specified address of the Flash memory.

[0038] 303. The ARM processor encapsulates the control instruction and the data block into message information, where the control instruction includes an address configuration instruction, a data write operation cache instruction, and a trigger instruction; When performing Flash memory write operations, the ARM processor not only needs to split the data blocks, but also needs to perform address configuration and data cache according to the Flash memory operation protocol. In order to ensure the correctness and efficiency of the data, the ARM processor will use a series of basic control instructions, such as address configuration instructions, trigger instructions, and data write operation cache instructions. These instructions can ensure accurate address positioning and data caching for each write operation, thereby achieving the correct writing of the update file in the Flash. The ARM processor specifically encapsulates the control instructions and the actual data block into a message and transmits it to the FPGA through the serial interface. Each message will contain complete address and data information to ensure that the FPGA can correctly parse and execute the Flash write operation. The encapsulation and transmission of the message simplifies the communication process between the ARM processor and the FPGA, and improves the overall update efficiency.

[0039] Specifically, these basic commands are shown in the following table:

[0040] In this embodiment, the ARM processor uses the address configuration instruction (0x20) to set the write address of the Flash memory. The address configuration instruction needs to pass four parameters: Addr0, Addr1, Addr2, Addr3, which respectively represent the specific address bits in the Flash memory. These address parameters allow the ARM processor to accurately locate the storage location of each data block in the Flash memory. Through this address configuration method, the ARM processor can ensure that each write operation starts at the correct address to avoid the occurrence of data write misalignment.

[0041] In order to improve write efficiency, the ARM processor will pre-cache the data block to be written before performing the actual write operation, that is, cache the data block to the specified cache area through the data write operation cache instruction (0x58) and wait for the final write trigger.

[0042] In addition, after the data cache is completed, the ARM processor will use the trigger instruction (0x63) to start the FPGA to write to the Flash memory. The trigger instruction tells the FPGA to perform the actual write operation and return status information after the operation is completed. The parameter of the trigger instruction is 1 or 0: when 1 is passed, the write is started; after the write is completed, 0 is passed to complete the operation.

[0043] The ARM processor combines each data block with the relevant control instructions and encapsulates them into a unified message, which is transmitted to the FPGA through the serial interface. The FPGA performs the operation of writing to the Flash according to the content of the message. By encapsulating the control instructions and data blocks, the ARM processor can simplify the communication and control process and ensure that each step of the operation can be successfully executed on the FPGA side.

[0044] 304. The ARM processor sends the message information to the FPGA of the test instrument through the serial communication interface; In this embodiment, step 304 is similar to step 103 in the above embodiment and will not be described again here.

[0045] 305. FPGA parses the received message information to obtain the write address and data block of the Flash memory; FPGA parses the received message information and extracts control instructions and data blocks. These control instructions contain specific operation codes and parameters to control the interaction between FPGA and Flash memory. Flash memory usually supports a series of standard instruction sets, which are used to perform basic operations such as reading data, writing data, and erasing data. These standard instructions are commands that Flash memory can understand and execute.

[0046] In this embodiment, the FPGA parses the received message information, obtains the write address of the Flash memory through the address configuration instruction carried in the message information, and pre-caches the data block through the data write operation cache instruction carried in the message information.

[0047] 306. The FPGA generates a Flash standard instruction according to the write address and the data block of the Flash memory, and triggers a write operation of the Flash memory through a trigger instruction, wherein the write operation is used to write the data block to the target address; FPGA parses the received message information and extracts the write address and data block. The write address specifies the location in the Flash memory where the data should be written, and the data block contains the actual data to be written. The corresponding Flash standard instructions can be generated through the write address and data block to control the Flash memory to write the data block to the target address. In actual applications, FPGA can directly convert the control instructions obtained by parsing into Flash standard instructions according to the predefined mapping rules.

[0048] The message information also includes a trigger instruction, and the FPGA starts the write operation of the Flash memory through the trigger instruction. Under the action of the trigger instruction, the Flash memory starts to perform the write operation, and the FPGA writes the data in the data block to the target address.

[0049] 307, FPGA fills the address configuration instruction according to the target address, and triggers the read operation of the Flash memory through the trigger instruction; After the write operation is completed, it is necessary to check and verify to ensure that the updated data is correctly written to the Flash memory, thereby ensuring the accuracy and reliability of the FPGA remote update. Specifically, the FPGA fills the address configuration instruction (0x20) according to the target address. This address is the location of the previously written data block, and then the FPGA starts the read operation of the Flash memory through the trigger instruction (0x63).

[0050] 308. FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent; The FPGA reads the read data returned from the target address from the Flash memory, compares the read data with the original written data block, and determines whether the read and written data are consistent. If the read and written data are consistent, step 309 is executed to continue the update. If the read and written data are inconsistent, the FPGA will execute step 310 to interrupt the update process.

[0051] 309. Perform a write operation on the next data block; If it is determined that the read and write data are consistent, the FPGA will continue to execute the update process and process the write operation of the next data block according to the message information to continue the subsequent update process.

[0052] 310. Interrupt the update and return error information to the host computer; If the read data is inconsistent with the written data, the FPGA will interrupt the update process to prevent the wrong data from being used in subsequent operations, ensuring the stability and reliability of the system. In addition, the FPGA needs to return error information to the host computer to trigger the error handling process, such as retrying the update, recording the error log, or notifying the maintenance personnel, which is not limited here.

[0053] 311. The test instrument returns the update progress to the host computer in real time, so that the host computer can display the update progress through the progress bar of the UI interface.

[0054] During the entire remote update process, each test instrument can return the update progress to the host computer in real time, and intuitively display the update progress through the progress bar on the host computer's UI interface, enhancing the user experience and making the update process more transparent and controllable. Specifically, the update progress can be the percentage of the current updated data size to the data size of the entire update file, that is, during the update process, the test instrument calculates the updated data size by tracking the amount of data written to the Flash memory, and then calculates the progress percentage, thereby achieving synchronization with the actual update progress.

[0055] In this embodiment, the control instructions and data blocks are encapsulated into message information by the ARM processor, and the received message information is parsed by the FPGA to extract the control instructions and data blocks, and then the control instructions are parsed and converted into standard instructions of the Flash memory, and the standard instruction set is used for operation, and finally the ARM processor performs read and write operations on the Flash memory device. By mapping the control instructions to the standard instructions of the Flash memory, the FPGA improves the compatibility between different devices and memories, reduces the dependence on specific hardware, reduces the development and maintenance costs, and enables the method to be more widely applied to various combinations of FPGAs and Flash memories.

[0056] The following is a detailed description of the FPGA device remote update system provided by this application. Figure 4 , Figure 4 Another embodiment of the system for remotely updating an FPGA device provided by the present application includes: A host computer 401, an instruction processing unit 402 and a Flash storage unit 403, wherein the instruction processing unit 402 and the Flash storage unit 403 are arranged on a test instrument, and the instruction processing unit 402 includes an ARM processing module 4021 and an FPGA processing module 4022; The host computer 401 is used to send update files and update instructions to the instruction processing unit 402 through the network port; The ARM processing module 4021 is used to parse the update file according to the preset format according to the update instruction and encapsulate the parsing result into message information by paging; and send the message information to the FPGA processing module 4022 through the serial communication interface; The FPGA processing module 4022 is used to parse the received message information and generate Flash standard instructions, and perform read and write operations on the Flash storage unit 403 through the Flash standard instructions to update the FPGA code.

[0057] Optionally, the ARM processing module 4021 is further used for: According to the update instruction, the update file is unpacked according to the preset Page size to obtain several data blocks; The ARM processor encapsulates control instructions and data blocks into message information. The control instructions include address configuration instructions, data write operation cache instructions and trigger instructions.

[0058] Optionally, the FPGA processing module 4022 is further used for: Parse the received message information to obtain the write address and data block of the Flash storage unit 403; A Flash standard instruction is generated according to the write address and the data block of the Flash storage unit 403, and a write operation of the Flash storage unit 403 is triggered by the trigger instruction. The write operation is used to write the data block to the target address.

[0059] Optionally, the FPGA processing module 4022 is further used for: Fill the address configuration instruction according to the target address, and trigger the read operation of the Flash storage unit 403 through the trigger instruction; Compare the read data returned by the read operation with the written data to determine whether the read and written data are consistent; If yes, then write the next data block; If not, the update is interrupted and an error message is returned to the upper computer 401 .

[0060] Optionally, the instruction processing unit 402 is used to return the update progress to the host computer 401 in real time, so that the host computer 401 displays the update progress through a progress bar on the UI interface.

[0061] Optionally, the update progress is the percentage of the currently updated data size to the data size of the entire update file.

[0062] Optionally, the Flash storage unit 403 uses a QSPI interface.

[0063] In this embodiment, the functions of each unit and module are the same as those described above. Figure 1 or Figure 3 The steps in the method embodiment shown correspond to each other and will not be repeated here. Figure 5 This is a functional block diagram of a host computer 401, an instruction processing unit 402, and a Flash storage unit 403 in the system for remote updating of FPGA devices provided in this application.

[0064] The entire update process is described below in conjunction with the host computer 401, the instruction processing unit 402 and the Flash storage unit 403: The host computer 401 sends the update file and the update instruction. In addition, the host computer 401 can further check and determine whether the update file is reasonable. If it is unreasonable, the UI software will prompt an error and interrupt the update; The instruction processing unit 402 splits the update file, fills a Page data to the 0x58 instruction, fills the write address to the 0x20 instruction, and fills the trigger 1 to the 0x63 instruction; The Flash storage unit 403 parses the write instruction and writes the data to the corresponding address; The instruction processing unit 402 fills the read address to the 0x20 instruction, and reads one Page length at a time by default; fills trigger 1 to 0x63 instructions; Flash storage unit 403 parses the read instruction and returns the corresponding address data to the FPGA cache; The instruction processing unit 402 compares whether the read and written data are consistent. If they are consistent, the next Page data is filled; if they are inconsistent, the update is interrupted and an error message is prompted.

[0065] This application also provides a device for remotely updating an FPGA device, see Figure 6 , Figure 6 An embodiment of a device for remotely updating an FPGA device provided in the present application includes: Processor 601, memory 602, input and output unit 603, bus 604; The processor 601 is connected to the memory 602, the input and output unit 603 and the bus 604; The memory 602 stores a program, and the processor 601 calls the program to execute any of the above methods for remotely updating an FPGA device.

[0066] The present application also relates to a computer-readable storage medium on which a program is stored. When the program is run on a computer, the computer executes any of the above methods for remotely updating an FPGA device.

[0067] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0068] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0069] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0070] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0071] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk, etc. Various media that can store program codes.

Claims

1. A method for remotely updating an FPGA device, characterized in that: The method comprises: The test instrument receives the update files and update instructions sent by the host computer through the network port; The ARM processor of the test instrument parses the update file according to the update instruction and in a preset format and encapsulates the parsing result into message information in pages; The ARM processor sends the message information to the FPGA of the test instrument through a serial communication interface; The FPGA parses the received message information and generates Flash standard instructions, and performs read and write operations on the Flash memory through the Flash standard instructions to update the code of the FPGA.

2. The method according to claim 1, characterized in that The ARM processor of the test instrument parses the update file according to the update instruction and in a preset format and encapsulates the parsing result into message information in pages, including: The ARM processor of the test instrument unpacks the update file according to the update instruction and the preset Page size to obtain a plurality of data blocks; The ARM processor encapsulates the control instruction and the data block into message information, wherein the control instruction includes an address configuration instruction, a data write operation cache instruction and a trigger instruction.

3. The method according to claim 2, characterized in that The FPGA parses the received message information to obtain a Flash standard instruction, and performs a read and write operation on the Flash memory through the Flash standard instruction, including: The FPGA parses the received message information to obtain the write address of the Flash memory and the data block; The FPGA generates a Flash standard instruction according to the write address of the Flash memory and the data block, and triggers a write operation of the Flash memory through the trigger instruction, wherein the write operation is used to write the data block to a target address.

4. The method according to claim 3, characterized in that After the FPGA writes the data block to the target address, the method further includes: The FPGA fills the address configuration instruction according to the target address, and triggers a read operation of the Flash memory through the trigger instruction; The FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent; If yes, then write the next data block; If not, the update is interrupted and an error message is returned to the host computer.

5. The method according to claim 1, characterized in that The method further comprises: The test instrument returns the update progress to the host computer in real time, so that the host computer displays the update progress through a progress bar on a UI interface.

6. The method according to claim 5, characterized in that The update progress is the percentage of the currently updated data size to the entire data size of the update file.

7. The method according to any one of claims 1 to 6, characterized in that The Flash memory uses a QSPI interface.

8. A system for remotely updating an FPGA device, characterized in that: The system comprises: a host computer, an instruction processing unit and a Flash storage unit, wherein the instruction processing unit and the Flash storage unit are arranged on a test instrument, and the instruction processing unit comprises an ARM processing module and an FPGA processing module; The host computer is used to send update files and update instructions to the instruction processing unit through the network port; The ARM processing module is used to parse the update file according to the update instruction and in a preset format and to encapsulate the parsing result into message information in pages; and to send the message information to the FPGA processing module through a serial communication interface; The FPGA processing module is used to parse the received message information and generate Flash standard instructions, and perform read and write operations on the Flash storage unit through the Flash standard instructions to update the code of the FPGA.

9. A device for remotely updating an FPGA device, characterized in that: The device comprises: Processor, memory, input-output unit, and bus; The processor is connected to the memory, the input and output unit, and the bus; The memory stores a program, and the processor calls the program to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program, and when the program is executed on a computer, the method according to any one of claims 1 to 7 is performed.

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