A GPGPU-based instruction execution acceleration method and GPGPU architecture

Abstract

The present application discloses a GPGPU-based instruction execution acceleration method and GPGPU architecture, which relates to the field of high-performance computing. The method includes: receiving a thread execution task output by a host compiler, and scheduling the thread execution task according to the current idle state of a computing unit; capturing instruction data output by the host compiler, and performing concurrent instruction decoding according to the corresponding instruction type to obtain a machine code corresponding to the instruction data; obtaining operands corresponding to the instruction data, and generating a to-be-launched instruction based on the machine code corresponding to the instruction data and the operands after secondary verification; determining the optimal computing unit according to the computational complexity, and sending the to-be-launched instruction to the optimal computing unit; receiving the execution result of the to-be-launched instruction, and returning the execution result to the terminal. By dynamically scheduling the thread execution task according to the idle state of the computing unit, it is possible to ensure that computing resources are fully utilized, thereby improving operating efficiency.

Description

Technical Field

[0001] The present application relates to the field of high performance computing, and in particular to a GPGPU-based instruction execution acceleration method and a GPGPU architecture. Background Art

[0002] A general-purpose graphics processing unit (GPGPU) is a massively parallel processor used to process operations of non-graphics-related programs and repetitive tasks with massive data. It can currently handle tasks such as large-scale data encryption, decryption, data calculation, and AI computing acceleration.

[0003] As the amount of data continues to grow, the amount of computing required to be processed by GPGPU is also increasing significantly. The existing method of accelerating instruction execution through GPGPU adds a scalar data processing path to perform scalar arithmetic and logic operations, so that scalar data can be processed in parallel with regular data, thereby maximizing the GPGPU computing efficiency.

[0004] However, this method usually requires the use of a software compiler to disassemble and analyze user instructions in advance, and to provide a detailed scalar calculation / SMIT calculation combination plan, and then the GPGPU performs corresponding processing on the operands. In the process of compiler disassembly and analysis, it is often difficult to consider all possible control flow paths, and can only identify scalar opportunities in thread blocks or coarser structures, which can easily lead to the omission of scalar calculations in dynamic thread bundles, affecting the calculation accuracy. In addition, in the GPGPU architecture adopted by this method, its hardware acceleration unit is usually a single scheduling unit scheduling structure. When faced with complex concurrent scalar instructions and SIMT instructions, it is easy to generate large instruction allocation delays, thereby affecting the calculation efficiency. At the same time, this method does not consider the scalar / SIMT resource requirements in GPGPU workloads, cannot monitor the usage of scalar / SIMT computing units well, and cannot do a good job of load balancing in terms of performance, resulting in low computing unit utilization and excessive GPGPU power overhead. Summary of the invention

[0005] In order to solve the above problems, this application proposes a GPGPU-based instruction execution acceleration method, including:

[0006] receiving a thread execution task output by a host compiler, and scheduling the thread execution task according to a current idle state of a computing unit;

[0007] Based on the scheduled thread execution task, the instruction data output by the host compiler is captured, and according to the instruction type corresponding to the instruction data, concurrent instruction decoding is performed to obtain the machine code corresponding to the instruction data;

[0008] Obtaining an operand corresponding to the instruction data, and generating a to-be-issued instruction based on a machine code corresponding to the instruction data and the operand after secondary verification;

[0009] Determine an optimal computing unit according to the instruction execution quantity of the instruction data and the computational complexity of the instruction to be issued, and send the instruction to be issued to the optimal computing unit;

[0010] Receive the execution result of the instruction to be transmitted, and return the execution result to the terminal.

[0011] On the other hand, the present application also provides a GPGPU architecture, including a warp control scheduling unit, a plurality of computing units, and an on-chip L2 cache;

[0012] The thread warp control scheduling unit is used to receive the thread execution task output by the host compiler, and schedule the thread execution task according to the current idle state of the computing unit;

[0013] The plurality of computing units are used to execute tasks based on the scheduled threads, capture the instruction data output by the host compiler, perform concurrent instruction decoding according to the instruction type corresponding to the instruction data, and obtain the machine code corresponding to the instruction data; obtain the operands corresponding to the instruction data, and generate the to-be-issued instruction based on the machine code corresponding to the instruction data and the operands after secondary verification; determine the optimal computing unit according to the current number of thread executions in the GPGPU and the computational complexity of the to-be-issued instruction, and send the to-be-issued instruction to the optimal computing unit;

[0014] The on-chip L2 cache is used to receive the execution result of the instruction to be issued and return the execution result to the terminal.

[0015] The present application proposes a GPGPU-based instruction execution acceleration method that can bring the following beneficial effects:

[0016] By dynamically scheduling threads to execute tasks based on the idle state of computing units, it is possible to ensure that computing resources are fully utilized, avoid computing units being unused when idle, or tasks being blocked while waiting for computing resources, thereby improving operating efficiency.

[0017] By re-verifying the instruction data and the corresponding operands, we can effectively eliminate the omission of scalar calculations in dynamic thread bundles caused by compiler errors, improve the calculation accuracy, and dynamically allocate resources according to the needs of instructions and the load of the computing unit, and send instructions to the optimal computing unit for execution, effectively improving the utilization of the computing unit and reducing waiting time and response time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 A flowchart of a GPGPU-based instruction execution acceleration method in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the overall application architecture of GPGPU in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a GPGPU computing unit architecture in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of an operand secondary verification unit architecture in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a task sending secondary arbitration unit architecture in an embodiment of the present application;

[0024] Figure 6 This is a schematic diagram of a GPGPU-based architecture in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0026] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0027] like Figure 1 As shown, the embodiment of the present application provides an instruction execution acceleration method based on GPGPU, including:

[0028] S101: receiving a thread execution task output by a host compiler, and scheduling the thread execution task according to a current idle state of a computing unit.

[0029] Specifically, the host compiler converts source code written in a high-level programming language (such as C++, Fortran, etc.) into machine code, generates a thread execution task based on the machine code, and sends it to the GPGPU. The thread bundle control scheduling unit in the GPGPU receives the thread execution task, determines the best computing unit that is currently idle or has the least amount of tasks to be calculated based on the current idle state of each computing unit in the GPGPU, and schedules the thread execution task to the best computing unit, so that the thread execution task is completed through the best computing unit.

[0030] It should be noted that if Figure 2 As shown, it is a diagram of the overall GPGPU application architecture in an embodiment of the present application, which is composed of a thread warp control scheduling unit, a number of GPGPU computing units (the specific deployment number can be determined according to the total amount of GPGPU on-chip resources), an on-chip L2 cache and other parts.

[0031] Among them, the thread warp control scheduling unit is responsible for receiving the thread execution tasks output by the host compiler, and allocating the instructions in the thread execution tasks from the L2 scheduler to each GPGPU computing unit in units of thread warps; several computing units are the computing cores of GPGPU, which complete the calculation of the received data according to the instruction requirements and send the results back to the on-chip cache in a timely manner; the on-chip L2 cache is responsible for receiving and caching the data to be processed and the instruction data sent by the host, and finally feeding back to the user host terminal.

[0032] S102: based on the scheduled thread execution task, the instruction data output by the host compiler is captured, and according to the instruction type corresponding to the instruction data, concurrent instruction decoding is performed to obtain the machine code corresponding to the instruction data.

[0033] Specifically, the optimal computing unit receives the scheduled thread execution task and starts to execute it, and through the instruction capture unit in the computing unit, based on the scheduled thread execution task, captures the instruction data output by the host compiler. The instruction data includes the execution instruction and the instruction information corresponding to the execution instruction, and the instruction information includes the data type, operand register address, calculation method and calculation category of the data operated by the execution instruction. The instruction types of the execution instruction include scalar instructions and SIMT instructions. Scalar instructions are instructions that act on a single data element. SIMT instructions allow one instruction to be executed by multiple threads simultaneously, and each thread follows the same instruction path but operates on different data.

[0034] Furthermore, through the instruction cache in the computing unit, based on the output order of the host compiler, the instruction data is divided into several groups in the order of output in units of thread warps, with a maximum of 8 thread warps in a single group, and sent to the corresponding thread warp temporary storage pool. In the embodiment of the present application, it is divided into four groups: A, B, C, and D.

[0035] like Figure 3 As shown, the detailed computing unit architecture of GPGPU in the embodiment of the present application, the computing unit includes an instruction capture unit, an instruction cache, a thread warp temporary pool, a scalar thread warp scheduling unit, a SIMT thread warp scheduling unit, a decoding unit, an operand capture unit, an operand secondary verification unit, a register control unit (including 128 32-bit vector registers and 2 32-bit scalar registers), an instruction emission unit, a task sending secondary arbitration unit, a data storage read-write unit, a number of arithmetic logic units (including two scalar arithmetic logic calculation units, four vector arithmetic logic calculation units, four floating-point calculation units), a disk memory, a scalar data write back unit, and a SIMT data write back unit.

[0036] Among them, the instruction capture unit is responsible for capturing the instruction data output by the host compiler, and supports the simultaneous capture of instructions and related data of up to 32 thread bundles; the instruction cache is responsible for temporarily storing the instruction data received by the instruction capture unit in units of thread bundles, and divides the thread bundle data into four groups A, B, C, and D in the order of reception. A single group can cache up to 8 thread bundles, and the thread bundle temporary pool temporarily stores the thread bundle groups; the scalar thread bundle scheduling unit and the SIMT thread bundle scheduling unit receive the scalar instructions and SIMT instructions of a thread bundle cached in the thread bundle temporary pool at a time, and schedule and allocate the execution order of the thread bundle instructions. The scalar thread bundle scheduling unit only receives and schedules scalar instructions, S The IMT thread bundle scheduling unit is responsible for processing vector instructions, floating-point instructions, data storage and reading instructions, etc. The decoding unit performs decoding operations on the instruction data in the thread bundle and compiles it into machine code that can be recognized by subsequent computing units. The operand capture unit reads the operands corresponding to the instruction data from the vector registers and scalar registers of the register control unit according to the instructions, and packages them in a specific format. The operand secondary verification unit performs secondary verification on the decoding results of the highest priority thread bundle and the operands of the thread to confirm that the scalar / SIMT instructions set by the compiler are correctly matched with the actual computing capture data. If not, the corresponding data is marked as the correct instruction type in time, and the result is The instruction and related operands are sent to the instruction emission unit through the operand capture unit; the detailed operand secondary verification unit architecture and operation mechanism will be given in the next section; the instruction emission unit is responsible for receiving scalar / SIMT instructions and their corresponding operands for calculation, and packing them and sending them to the corresponding target computing unit and data storage read-write unit after completing the task sending secondary arbitration; the task sending secondary arbitration unit estimates the on-chip resources and power required for the current calculation based on information such as the number and complexity of threads, and allocates the optimal computing unit for the calculation under the calculation of the algorithm; the detailed task sending secondary arbitration unit architecture and operation mechanism will be given in the next section; data storage read-write The unit is responsible for executing SIMT read instructions on the LDS memory; 2 scalar arithmetic logic calculation units support parallel execution of 2 groups of scalar arithmetic logic calculations; 4 vector arithmetic logic calculation units are responsible for performing calculation operations on the received SIMT vector arithmetic logic instructions and data; the vector arithmetic logic calculation unit can also perform scalar arithmetic logic calculations required by users, and supports core multiplexing in specific cases to save resources; 4 floating-point calculation units are responsible for performing corresponding calculation operations on the received SIMT vector FPU instructions and data; the scalar data write back unit is responsible for writing the calculation results of the 2 groups of scalar arithmetic logic calculation units back to the 2 groups of scalar registers of the register control unit.The SIMT data write-back unit is responsible for writing the calculation results of 4 groups of vector arithmetic logic calculation units and 4 groups of floating-point calculation units back to the 128 groups of scalar registers of the register control unit (not necessarily 128 groups are actually needed); the register control unit is responsible for reading and writing 128 32-bit vector registers and 2 32-bit scalar registers to complete the data exchange between the calculation unit and the outside world; the data stored in the vector register only supports SIMT instruction reading and writing, while the data stored in the scalar register not only supports scalar instruction reading and writing, but also supports SIMT instruction reading and writing; if the scalar instruction needs to access the relevant storage unit of the vector register, a specific register data migration instruction is required to move the corresponding data of the vector register to the relevant storage unit of the scalar register.

[0037] Furthermore, through the thread warp temporary pool, according to the instruction type corresponding to the instruction data contained in the highest priority thread warp, the corresponding thread warp scheduling unit is determined, and the thread warp scheduling unit includes a scalar thread warp scheduling unit and a SIMT thread warp scheduling unit. The highest priority thread warp is sent to the corresponding thread warp scheduling unit in a queue format, and the current instruction data in the highest priority thread warp is sorted through different thread warp scheduling units, and the current instruction data is sent to the decoding unit based on the concurrent mode, and the current instruction data is decoded by the decoding unit.

[0038] The scalar warp scheduling unit processes the corresponding scalar instructions, and the SIMT warp scheduling unit processes vector instructions, floating-point instructions, data storage and reading instructions, etc. The scalar warp scheduling unit and the SIMT warp scheduling unit reasonably schedule and allocate the execution order of the warp instructions, and send the scalar instructions and SIMT instructions to the decoding unit in concurrent mode; the control register address of the warp is also sent to the register control unit.

[0039] S103: Obtain operands corresponding to the instruction data, and generate instructions to be issued based on the machine code corresponding to the instruction data and the operands after secondary verification.

[0040] Specifically, the operand corresponding to the current instruction data is extracted from the register control unit according to the operand register address through the operand capture unit, and the machine code after decoding the current instruction data and the operand corresponding to the current instruction data are packaged based on a preset format to obtain a packaged file, and the packaged file is secondary verified through the operand secondary verification unit.

[0041] In the embodiment of the present application, it is also necessary to perform a secondary verification on the obtained operands through an operand secondary verification unit. Figure 4As shown, it is a detailed architecture diagram of the operand secondary verification unit, which specifically includes an operand cache unit, a thread extraction unit, an instruction extraction unit, a thread operand detection and comparison state machine, an instruction setting unit, a priority arrangement unit and an output cache unit.

[0042] Specifically, the packaged file contains the current instruction data, the machine code corresponding to the current instruction data, and the operand corresponding to the current instruction data. The thread extraction unit is used to extract the instruction data volume and instruction sequence of the current instruction data in the packaged file. The instruction identification extraction unit is used to send the current instruction data to the thread operand detection and comparison state machine based on the instruction sequence. The operand in the packaged file is extracted through the operand cache unit. Based on the instruction sequence, the operand corresponding to the current instruction data is sent to the operand detection and comparison state machine.

[0043] Furthermore, the operand detection and comparison state machine is used to determine whether the current instruction data and the corresponding operands all match. When the instruction type of the current instruction data is a scalar instruction, it is determined whether the number of operands is 1, and when the instruction type of the current instruction data is a SIMT instruction, it is determined whether the number of operands is consistent with the instruction data amount.

[0044] If so, the current instruction data and the corresponding operands are sent to the output cache unit; if not, the abnormal instruction data and the corresponding abnormal operands are sent to the instruction setting unit; the abnormal instruction data are modified through the instruction setting unit, and the operands corresponding to the abnormal instruction data are re-extracted; and the modified abnormal instruction data and abnormal operands are sent to the corresponding address of the output cache unit based on the instruction execution priority through the priority arrangement unit.

[0045] It should be noted that the input signals of the operand secondary verification unit are operand data and decoding result data; the thread bundle thread identification extraction unit extracts the total number and order of threads contained in the highest priority thread bundle from the decoding result, and the instruction identification extraction unit extracts all current instructions contained in the thread bundle from the decoding result data in sequence, including scalar instructions and SIMT instructions, and then the total number of threads and all instructions contained in the thread bundle are sent to the thread operand detection and comparison state machine in sequence; at the same time, the operand cache unit sends the cached calculation operands to the thread operand detection and comparison state machine one by one in the order corresponding to the current instructions; in the thread operand detection and comparison state machine, one by one verification is performed according to the input current instructions and corresponding operands.

[0046] It should be noted that a scalar instruction indicates that all threads of the thread bundle need to perform the same calculation at this time, and only one set of operands is needed for this purpose; a SIMT instruction indicates that all threads of the thread bundle need to perform different calculations at this moment, and an operand corresponding to the number of threads is required; if the compiler does not allocate the instruction that should have been a scalar operation as a SIMT instruction in the early stage, the SIMT instruction will correspond to operands with the same number of threads and the same value, which will waste a lot of storage space and SIMT computing resources. At this time, it should be defined as a compiler allocation error, and the SIMT instruction needs to be converted to a scalar instruction; similarly, if the compiler allocates it as a scalar instruction in the early stage, but there are more than one set of operands at this time, it should also be defined as a compiler allocation error, and the scalar instruction needs to be converted to a SIMT instruction; thread operands The detection and comparison state machine determines whether the disassembly and allocation of the previous compiler is incorrect by comparing the received instruction type and operand data. If there is an error, the incorrect instruction will be adjusted to the correct instruction in time, and equipped with the correct number and value of operands; if the current instruction verification result is correct, the thread operand detection and comparison state machine directly sends the current instruction and the corresponding operand data to the output cache; if the current instruction verification result is incorrect, the thread operand detection and comparison state machine sends the current instruction and the corresponding operand data to the instruction setting unit, and the module modifies the incorrect instruction and operand; and through the priority arrangement unit, the modified instructions and operands are stored in the corresponding address of the output cache according to the instruction execution priority, and finally all the instructions and operands of the highest priority thread bundle are output by the operand secondary verification unit.

[0047] S104: Determine an optimal computing unit according to the instruction execution quantity of the instruction data and the computational complexity of the instruction to be issued, and send the instruction to be issued to the optimal computing unit.

[0048] Specifically, the task is sent through the secondary arbitration unit, and the on-chip resources required to execute the instruction to be issued are determined according to the current instruction data amount in the highest priority thread bundle and the computational complexity of the instruction to be issued. The optimal computing unit is determined based on the on-chip resources, and the instruction to be issued is sent to the optimal computing unit through the instruction issuance unit.

[0049] Among them, the task sending secondary arbitration unit includes a proposed processing thread information extraction unit, a thread bundle concurrency extraction unit, an on-chip resource estimation comparison state machine, an execution marking unit, an on-chip resource comparison table, etc.

[0050] The proposed instruction information of the proposed instruction is extracted through the proposed processing thread information extraction unit, and the proposed instruction information is sent to the on-chip resource estimation comparison state machine. The usage status of each arithmetic logic unit is obtained in real time through the on-chip resource estimation comparison state machine. According to the proposed instruction information and the usage status, the required number of units corresponding to each arithmetic logic unit is determined. According to the total number of available computing units and the required number of units in the on-chip resource comparison table, the proposed instruction is allocated to the corresponding arithmetic logic unit, and the allocation result is adjusted in real time.

[0051] like Figure 5 As shown, it is a detailed architecture diagram of the task sending secondary arbitration unit in the embodiment of the present application. The input signal of the task sending secondary arbitration unit is the instruction emission unit data; the proposed processing thread information extraction unit extracts the processing information involved in the current process from the emission unit data, including the type of scalar / SIMT instruction, the operation code required to be executed by the subsequent computing unit, etc., and sends it to the on-chip resource estimation comparison state machine; the thread bundle concurrency extraction unit extracts the scalar / SIMT instructions involved in the highest priority thread bundle and the total number of computing threads thereof. The on-chip resource estimation comparison state machine is responsible for monitoring the usage of the scalar / SIMT computing unit, and calculates the number of scalar arithmetic logic computing units, vector arithmetic logic computing units, and floating-point computing units required for the current computing execution according to the received current progress information, and then reads the specific partition of the on-chip resource comparison table, and compares it with the existing available The total number of various types of computing unit resources is calculated, and the allocation of the target computing units of the process is adjusted at any time according to the actual situation. If the number of scalar arithmetic logic computing units required for the current process calculation is less than the number of idle vector arithmetic logic computing units, in order to improve the utilization of computing units and reduce the total power consumption of GPGPU computing, the on-chip resource estimation control state machine tells the scalar / SIMT execution marking unit to mark the thread that originally needs the scalar arithmetic logic computing unit as a vector arithmetic logic computing unit (that is, the calculation of the unit is sent to the corresponding idle vector arithmetic logic computing unit for execution, reducing the total resource loss); conversely, if the number of idle vector arithmetic logic computing units is not enough to meet the number of scalar arithmetic logic computing units, the on-chip resource estimation control state machine tells the scalar / SIMT execution marking unit to mark according to the original plan, and there is no need to adjust the computing unit allocation plan.

[0052] S105: receiving the execution result of the instruction to be transmitted, and returning the execution result to the terminal.

[0053] Specifically, the on-chip L2 cache is responsible for receiving and caching the data to be processed and instruction data sent by the host, and finally feeding back to the user host terminal.

[0054] The design is equipped with a scalar thread warp scheduling unit and a SIMT thread warp scheduling unit to collaboratively complete the real-time instruction allocation of thread warps, significantly reducing the delay of multi-thread warp instruction allocation; an operand secondary verification unit is developed using hardware to perform secondary verification on the scalar / SIMT computing combination scheme configured by the compiler, fundamentally eliminating the omission of scalar calculations in dynamic thread warps caused by compiler errors and improving calculation accuracy; in addition, a corresponding task sending secondary arbitration unit is added to the computing unit, which can monitor the usage of scalar / SIMT computing units in real time, improve the utilization of computing units, and reduce the total power consumption of GPGPU computing.

[0055] By dynamically scheduling threads to execute tasks based on the idle state of computing units, it is possible to ensure that computing resources are fully utilized, avoid computing units being unused when idle, or tasks being blocked while waiting for computing resources, thereby improving operating efficiency.

[0056] By re-verifying the instruction data and the corresponding operands, we can effectively eliminate the omission of scalar calculations in dynamic thread bundles caused by compiler errors, improve the calculation accuracy, and dynamically allocate resources according to the needs of instructions and the load of the computing unit, and send instructions to the optimal computing unit for execution, effectively improving the utilization of the computing unit and reducing waiting time and response time.

[0057] like Figure 6 As shown, the embodiment of the present application also proposes a GPGPU-based architecture, including: a thread warp control scheduling unit, a plurality of computing units, and an on-chip L2 cache;

[0058] A thread warp control scheduling unit, used to receive thread execution tasks output by the host compiler, and schedule the thread execution tasks according to the current idle state of the computing unit;

[0059] Several computing units are used to execute tasks based on the scheduled threads, capture the instruction data output by the host compiler, perform concurrent instruction decoding according to the instruction type corresponding to the instruction data, and obtain the machine code corresponding to the instruction data; obtain the operands corresponding to the instruction data, and generate the instructions to be issued based on the machine code corresponding to the instruction data and the operands after secondary verification; determine the optimal computing unit according to the number of instructions executed in the instruction data and the computational complexity of the instructions to be issued, and send the instructions to be issued to the optimal computing unit;

[0060] The on-chip L2 cache is used to receive the execution results of the instructions to be issued and return the execution results to the terminal.

[0061] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0062] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0063] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0064] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0065] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0066] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0067] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0068] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0069] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0070] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0071] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A GPGPU-based instruction execution acceleration method, characterized in that: Applications in GPGPU include: Receive the thread execution task output by the host compiler, and schedule the thread execution task according to the current idle state of the computing unit; the computing unit includes an instruction capture unit, an instruction cache, a thread warp temporary storage pool, a thread warp scheduling unit, a decoding unit, an operand capture unit, an operand secondary verification unit, a register control unit, an instruction emission unit, a task sending secondary arbitration unit, a data storage read-write unit, a plurality of arithmetic logic units, a floating point calculation unit, a disk memory, and a data write-back unit; Based on the scheduled thread execution task, the instruction data output by the host compiler is captured, specifically comprising: using the instruction capture unit, based on the scheduled thread execution task, the instruction data output by the host compiler is captured; using the instruction cache, based on the output order of the host compiler, the instruction data is divided into a plurality of groups of thread warps, and sent to the thread warp temporary storage pool; According to the instruction type corresponding to the instruction data, concurrent instruction decoding is performed to obtain a machine code corresponding to the instruction data; the instruction type includes a scalar instruction and a SIMT instruction, and the thread warp scheduling unit includes a scalar thread warp scheduling unit and a SIMT thread warp scheduling unit; the instruction data includes an execution instruction and instruction information corresponding to the execution instruction; the instruction information includes a data type, an operand register address, a calculation method and a calculation category of the data operated by the execution instruction; The performing concurrent instruction decoding according to the instruction type corresponding to the instruction data specifically includes: Obtaining a highest priority thread warp from the plurality of thread warp groups, and determining a corresponding thread warp scheduling unit according to an instruction type corresponding to current instruction data in the highest priority thread warp; Based on the queue format, sending the current instruction data to the corresponding thread warp scheduling unit once; sorting the current instruction data through the thread warp scheduling unit, sending the current instruction data to the decoding unit based on a concurrent mode, and decoding the current instruction data through the decoding unit; Obtaining the operand corresponding to the instruction data specifically includes: extracting the operand corresponding to the current instruction data from the register control unit according to the operand register address through the operand capture unit; packaging the machine code decoded from the current instruction data and the operand corresponding to the current instruction data based on a preset format to obtain a packaged file; and performing secondary verification on the packaged file through the operand secondary verification unit; The operand secondary verification unit includes an operand cache unit, a thread extraction unit, an instruction identification extraction unit, a thread operand detection and comparison state machine, an instruction setting unit, a priority arrangement unit and an output cache unit; The secondary verification of the packaged file by the operand secondary verification unit specifically includes: extracting the instruction data amount and instruction sequence in the packaged file by the thread extraction unit; sending the current instruction data to the thread operand detection and comparison state machine based on the instruction sequence by the instruction identification and extraction unit; extracting the operands in the packaged file by the operand cache unit, and sending the operands corresponding to the current instruction data to the operand detection and comparison state machine based on the instruction sequence; judging in turn by the operand detection and comparison state machine whether the current instruction data and the corresponding operands all match; Generate an instruction to be issued based on the machine code corresponding to the instruction data and the operand after secondary verification; Determine an optimal computing unit according to the instruction execution quantity of the instruction data and the computational complexity of the instruction to be issued, and send the instruction to be issued to the optimal computing unit; Receive the execution result of the instruction to be transmitted, and return the execution result to the terminal.

2. The GPGPU-based instruction execution acceleration method according to claim 1, characterized in that: By using the operand detection and comparison state machine, it is determined in turn whether the current instruction data and the corresponding operands all match, specifically including: When the instruction type of the current instruction data is a scalar instruction, determining whether the number of operands is 1; When the instruction type of the current instruction data is a SIMT instruction, it is determined whether the quantity of the operands is consistent with the instruction data quantity.

3. The GPGPU-based instruction execution acceleration method according to claim 2, characterized in that: After determining in sequence whether the current instruction data and the corresponding operands all match each other through the operand detection and comparison state machine, the method further includes: If yes, the current instruction data and the corresponding operands are sent to the output cache unit; If not, the abnormal instruction data and the corresponding abnormal operand are sent to the instruction setting unit; Modifying the abnormal instruction data through the instruction setting unit, and re-extracting the operand corresponding to the abnormal instruction data; The priority arrangement unit sends the modified abnormal instruction data and abnormal operand to the corresponding address of the output cache unit based on the instruction execution priority.

4. The method for accelerating instruction execution based on GPGPU according to claim 1, characterized in that: The determining an optimal computing unit according to the instruction of the instruction data and the computational complexity of the instruction to be issued, and sending the instruction to be issued to the optimal computing unit specifically includes: Determining, by the task sending secondary arbitration unit, on-chip resources required to execute the instruction to be issued according to the current instruction data amount in the highest priority thread warp and the computational complexity of the instruction to be issued; Determining an optimal computing unit according to the on-chip resources; The instruction to be transmitted is sent to the optimal computing unit through the instruction transmitting unit.

5. The method for accelerating instruction execution based on GPGPU according to claim 4, characterized in that: The task sending secondary arbitration unit includes a proposed processing thread information extraction unit, a thread bundle concurrency extraction unit, an on-chip resource estimation comparison state machine, an execution marking unit, and an on-chip resource comparison table; The determining, according to the current instruction data amount in the highest priority thread warp and the computational complexity of the instruction to be issued, the on-chip resources required to execute the instruction to be issued specifically includes: Extracting the to-be-issued instruction information of the to-be-issued instruction through the to-be-processed thread information extraction unit, and sending the to-be-issued instruction information to the on-chip resource estimation comparison state machine; Acquire the usage status of each arithmetic logic unit in real time through the on-chip resource estimation control state machine, and determine the required number of units corresponding to each arithmetic logic unit according to the instruction information to be issued and the usage status; According to the total number of available computing units and the required number of units in the on-chip resource comparison table, the instructions to be issued are allocated to corresponding arithmetic logic units, and the allocation results are adjusted in real time.

6. A GPGPU architecture, characterized in that: It includes a thread warp control scheduling unit, several computing units, and an on-chip L2 cache; The thread warp control scheduling unit is used to receive the thread execution task output by the host compiler, and schedule the thread execution task according to the current idle state of the computing unit; the computing unit includes an instruction capture unit, an instruction cache, a thread warp temporary storage pool, a thread warp scheduling unit, a decoding unit, an operand capture unit, an operand secondary verification unit, a register control unit, an instruction emission unit, a task sending secondary arbitration unit, a data storage read-write unit, a plurality of arithmetic logic units, a floating point calculation unit, a disk memory, and a data write-back unit; The plurality of computing units are used to capture instruction data output by the host compiler based on the scheduled thread execution task, specifically including: capturing instruction data output by the host compiler based on the scheduled thread execution task by the instruction capture unit; dividing the instruction data into a plurality of thread warps based on the output order of the host compiler by the instruction cache, and sending the instruction data to the thread warp temporary storage pool; According to the instruction type corresponding to the instruction data, concurrent instruction decoding is performed to obtain a machine code corresponding to the instruction data; the instruction type includes a scalar instruction and a SIMT instruction, and the thread warp scheduling unit includes a scalar thread warp scheduling unit and a SIMT thread warp scheduling unit; the instruction data includes an execution instruction and instruction information corresponding to the execution instruction; the instruction information includes a data type, an operand register address, a calculation method and a calculation category of the data operated by the execution instruction; The performing concurrent instruction decoding according to the instruction type corresponding to the instruction data specifically includes: obtaining the highest priority thread bundle among the plurality of thread bundles, and determining the corresponding thread bundle scheduling unit according to the instruction type corresponding to the current instruction data in the highest priority thread bundle; sending the current instruction data to the corresponding thread bundle scheduling unit once based on the queue format; sorting the current instruction data through the thread bundle scheduling unit, and sending the current instruction data to the decoding unit based on the concurrent mode, and decoding the current instruction data through the decoding unit; Obtaining the operand corresponding to the instruction data specifically includes: extracting the operand corresponding to the current instruction data from the register control unit according to the operand register address through the operand capture unit; packaging the machine code decoded from the current instruction data and the operand corresponding to the current instruction data based on a preset format to obtain a packaged file; and performing secondary verification on the packaged file through the operand secondary verification unit; The operand secondary verification unit includes an operand cache unit, a thread extraction unit, an instruction identification extraction unit, a thread operand detection and comparison state machine, an instruction setting unit, a priority arrangement unit and an output cache unit; The secondary verification of the packaged file by the operand secondary verification unit specifically includes: extracting the instruction data amount and instruction sequence in the packaged file by the thread extraction unit; sending the current instruction data to the thread operand detection and comparison state machine based on the instruction sequence by the instruction identification and extraction unit; extracting the operands in the packaged file by the operand cache unit, and sending the operands corresponding to the current instruction data to the operand detection and comparison state machine based on the instruction sequence; judging in turn by the operand detection and comparison state machine whether the current instruction data and the corresponding operands all match; Generate an instruction to be issued based on the machine code corresponding to the instruction data and the operand after secondary verification; determine the optimal computing unit according to the instruction execution quantity of the instruction data and the computational complexity of the instruction to be issued, and send the instruction to be issued to the optimal computing unit; The on-chip L2 cache is used to receive the execution result of the instruction to be issued and return the execution result to the terminal.

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