Control method of memory device and related flash memory controller and memory device

Abstract

The invention discloses a control method of a memory device, a related flash memory controller and the memory device. The control method comprises the following steps: reading first data from a first section and decoding the first data, the first section being located at a first data page in a super data page, and the super data page comprising a plurality of data pages respectively located at the plurality of data planes; if the decoding of the first section fails, obtaining data of a plurality of corresponding sections of the first section, the plurality of corresponding sections being respectively located in other data pages in the super data page; and if not all of the data of the plurality of corresponding sections can be successfully decoded, determining whether to give up decoding operation on the first section according to a symptom weight of the first section and at least one symptom weight of at least one corresponding section which cannot be successfully decoded in the plurality of corresponding sections.

Description

Technical Field

[0001] The invention relates to a flash memory controller. Background Art

[0002] In order to better protect the data in the flash memory module, the encoder in the flash memory controller uses a redundant array of independent disks (RAID) encoding method to encode the data written to the flash memory module to generate multiple parity codes. However, as the flash memory process is miniaturized and moves towards 3-dimention, the probability that the flash memory cannot be successfully decoded using the low-density parity check code (LDPC code) when being read has also increased significantly, resulting in a significant increase in the number of times RAID is needed for decoding. In addition, the time required for decoding using RAID in the prior art is very long, which leads to low decoding efficiency. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a flash memory controller having a high-efficiency RAID decoding method to solve the problems described in the prior art.

[0004] In one embodiment of the present invention, a control method for a memory device is disclosed, wherein the memory device includes a flash memory module, the flash memory module includes a plurality of data planes, each data plane includes a plurality of blocks, each block includes a plurality of data pages, each data page includes a plurality of segments, and the control method includes: reading a first data from a first segment and decoding it, wherein the first segment is located in a first data page in a super data page, and the super data page includes a plurality of data pages respectively located in the plurality of data planes; if the decoding of the first segment fails, obtaining data of a plurality of corresponding segments of the first segment, wherein the plurality of corresponding segments are respectively located in other data pages in the super data page except the first data page; if the data of the plurality of corresponding segments can all be successfully decoded, generating decoded data of the specific segment according to a plurality of decoded data of the plurality of corresponding segments; and if not all the data of the plurality of corresponding segments can be successfully decoded, determining whether to abandon the decoding operation of the first segment according to a syndrome weight of the first segment and at least one syndrome weight of at least one corresponding segment of the plurality of corresponding segments that cannot be successfully decoded.

[0005] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes multiple data planes, each data plane includes multiple blocks, each block includes multiple data pages, each data page includes multiple segments. The flash memory controller includes a read-only memory, a buffer memory and a microprocessor, wherein the read-only memory is used to store a program code, and the microprocessor is used to execute the program code to control access to the flash memory module. The microprocessor is used to perform the following operations: read a first data from a first segment and decode it, wherein the first segment is located in a first data page in a super data page, and the super data page includes a plurality of data pages respectively located in the plurality of data planes; if the decoding of the first segment fails, obtain data of a plurality of corresponding segments of the first segment, wherein the plurality of corresponding segments are respectively located in other data pages in the super data page except the first data page; if the data of the plurality of corresponding segments can all be successfully decoded, generate decoded data of the specific segment according to a plurality of decoded data of the plurality of corresponding segments; and if not all the data of the plurality of corresponding segments can be successfully decoded, determine whether to abandon the decoding operation of the first segment according to a symptom weight of the first segment and at least one symptom weight of at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments.

[0006] In one embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory module includes multiple data planes, each data plane includes multiple blocks, each block includes multiple data pages, and each data page includes multiple segments. The flash memory controller is used to access the flash memory module, and the flash memory controller performs the following operations: reading a first data from a first segment and decoding it, wherein the first segment is located in a first data page in a super data page, and the super data page includes a plurality of data pages respectively located in the plurality of data planes; if the decoding of the first segment fails, obtaining data of a plurality of corresponding segments of the first segment, wherein the plurality of corresponding segments are respectively located in other data pages in the super data page except the first data page; if the data of the plurality of corresponding segments can all be successfully decoded, generating decoded data of the specific segment according to a plurality of decoded data of the plurality of corresponding segments; and if not all of the data of the plurality of corresponding segments can be successfully decoded, determining whether to abandon the decoding operation of the first segment according to a syndrome weight of the first segment and at least one syndrome weight of at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0008] Figure 2 A schematic diagram of configuring blocks belonging to different data planes within a flash memory module into a super block.

[0009] Figure 3 A schematic diagram for configuring a super data page.

[0010] Figure 4 FIG. 4 is a schematic diagram of a RAID encoding method according to an embodiment of the present invention.

[0011] Figure 5 , Figure 6 , Figure 7 FIG. 4 is a flow chart of a method for accessing a flash memory module according to an embodiment of the present invention.

[0012] Figure 8 FIG. 4 is a schematic diagram of generating hard information and soft information according to an embodiment of the present invention.

[0013] Fig. 9 FIG. 4 is a schematic diagram of generating a specific pattern according to an embodiment of the present invention.

[0014]

Explanation of symbols

[0015] 100: Memory Device

[0016] 110: Flash memory controller

[0017] 112: Microprocessor

[0018] 112M: Read-only memory

[0019] 112C: Program code

[0020] 114: Control Logic

[0021] 116: Buffer memory

[0022] 118: Interface Logic

[0023] 120: Flash memory module

[0024] 130: Main device

[0025] 132: Encoder

[0026] 134:Decoder

[0027] 136: Randomizer

[0028] 138:De-Randomizer

[0029] 210_1~210_A: Grain

[0030] 212_1~212_2A: Data plane

[0031] 230_1,230_2:Super Block

[0032] 310_1~310_B

[0033] 330_1,330_2: Super data page

[0034] 500-552: Step 910: Specific pattern

[0035] B0~BN: Block

[0036] D0, D1, D2: data

[0037] P1, P2, P3: Data pages

[0038] S0,S1: Status

[0039] Vr, (Vr-Δ), (Vr+Δ), (Vr-2Δ), (Vr+2Δ): read voltage DETAILED DESCRIPTION

[0040] Figure 1 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a de-randomizer 138, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code, ECC), the decoder 134 is used to decode the data read from the flash memory module 120, the randomizer 136 is used to perform a randomization operation on the data written into the flash memory module 120, and the de-randomizer 138 is used to perform a de-randomization operation on the data read from the flash memory module 120.

[0041] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller 110 performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 110 performs operations such as writing data to the flash memory module 120 in units of data pages. In other words, a block is a minimum erase unit in the flash memory module 120, and a data page is a minimum write unit in the flash memory module 120.

[0042] In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform a variety of control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130.

[0043] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the memory device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a watch, a portable medical detection device (e.g., a medical bracelet), a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0044] In the present embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, no further explanation is given in the specification.

[0045] In the implementation of the flash memory module 120, the flash memory controller 110 configures the blocks belonging to different data planes within the flash memory module 120 as a super block to facilitate the management of data access. Figure 2 The schematic diagram of the flash memory module 120 shown includes a plurality of flash memory dies 210_1-210_A, wherein A can be any suitable positive integer, for example, A can be equal to 2, 4, 6, 8, etc., and each flash memory die includes two data planes, for example, the flash memory die 210_1 includes two data planes 212_1, 212_2, the flash memory die 210_2 includes two data planes 212_3, 212_4, ..., and the flash memory die 210_A includes two data planes 212_(2A-1), 212_2A. In addition, each data plane includes a plurality of blocks B0-BN, wherein N can be any suitable positive integer, for example, N can be equal to 64, 128, etc. During the process of initializing the flash memory module 120, the flash memory controller 110 configures the first block B0 of each data plane as a super block 230_1, the second block B1 of each data plane as a super block 230_2, and so on. Figure 2 As shown, the super block 230_1 includes (2*A) physical blocks, and the flash memory controller 110 is similar to a general block when accessing the super block 230_1. For example, the super block 230_1 itself is an erase unit, that is, although the (2*A) blocks B0 of the super block 230_1 can be erased separately, the flash memory controller 110 will definitely erase the (2*A) blocks B0 together.

[0046] In addition, when writing data to the super block 230_1, data can be written sequentially from the first data page of the data plane 212_1, the first data page of the data plane 212_2, the first data page of the data plane 212_3, the first data page of the data plane 212_4, ..., the first data page of the data plane 212_(2A-1) and the first data page of the data plane 212_2A. After the data writing to the first data page of the data plane 212_2A is completed, the data is then written sequentially to the second data page of the data plane 212_1, the second data page of the data plane 212_2, ..., and so on. Figure 3 For example, the flash memory controller 110 configures the blocks belonging to different data planes in each super block as a super data page to facilitate the management of data access. Figure 3In the embodiment, the flash memory controller 110 configures the first data page P1 of block B0 of data plane 212_1, the first data page P1 of block B0 of data plane 212_2, ..., and the first data page P1 of block B0 of data plane 212_2A in the super block 230_1 as a super data page 330_1; and the flash memory controller 110 configures the second data page P2 of block B0 of data plane 212_1, the second data page P2 of block B0 of data plane 212_2, ..., and the second data page P2 of block B0 of data plane 212_2A in the super block 230_1 as a super data page 330_2, ... and so on. In addition, each data page may include a plurality of chunks (or sectors) 310_1-310_B, wherein each of the chunks 310_1-310_B may be considered as a coding unit, that is, the encoder 132 will encode a piece of data to be written into the flash memory module 120 to generate a coded data and then write it into a chunk, wherein the coded data includes the piece of data and a corresponding error correction code; and the decoder 134 may read the data in a chunk from the flash memory module 120 and decode the chunk to generate a decoded data. In an example, the size of a data page may be 16 kilobytes (KB) or 32KB, and the size of a chunk may be 4KB, but the present invention is not limited thereto.

[0047] In order to better protect the data in the flash memory module 120, the flash memory controller 110 will simultaneously use RAID encoding when writing data to the flash memory module 120. Taking the embodiments of Figures 2 and 3 as an example, in the super block 230_1, block B0 of one data plane can be used exclusively to store the checksums of other data planes. For example, data page P1 of block B0 of data plane 212_2A is used to store the result of exclusive OR (XOR) operation on data page P1 of block B0 of data planes 212_1 to 210_(2A-1), data page P2 of block B0 of data plane 212_2A is used to store the result of exclusive OR (XOR) operation on data page P2 of block B0 of data planes 212_1 to 210_(2A-1), and so on. Figure 4For example, each data page includes a plurality of data D0, D1, D3, ..., wherein each data may be one bit, and the encoder 132 may sequentially perform an XOR operation on the data D0 of the data page P1 of the block B0 of the data plane 212_1, the data D0 of the data page P1 of the block B0 of the data plane 212_2, ..., and the data D0 of the data page P1 of the block B0 of the data plane 212_(2A-1) to generate an operation result and then write it into the block B0 of the data plane 212_2A. The encoder 132 can sequentially perform an XOR operation on the data D1 of the data page P1 of block B0 of the data plane 212_1, the data D1 of the data page P1 of block B0 of the data plane 212_2, ..., the data D1 of the data page P1 of block B0 of the data plane 212_(2A-1) to generate an operation result and then write it into the data page P1 of block B0 of the data plane 212_2A as its data D1, ..., and so on. Figure 4 In the RAID encoding method shown, no matter which data page P1 in the super data page 330_1 is unable to read data, the data of all other data pages in the super data page 330_1 can be restored by performing an XOR operation on the data.

[0048] Figures 5 to 7 FIG. 1 is a flow chart of a method for accessing the flash memory module 120 according to an embodiment of the present invention. Figures 5 to 7 , at step 500, the process starts, and the memory device 100 has been powered on and completed the initialization operation. At step 502, the microprocessor 112 in the flash memory controller 110 receives a read instruction, such as a read instruction from the host device 130, to start reading a super data page, wherein in the following embodiments, the reading of the super data page 330_1 in Figures 3 and 4 is used as an example for explanation. At step 504, the flash memory controller 110 sequentially reads each segment of each data page in the super data page 330_1 and performs decoding. In this embodiment, the flash memory controller 110 can decode each segment by a hard decoding or a soft decoding, wherein the hard decoding can be a decoding method of a BCH code (Bose-Chaudhuri-Hocquenghem code) or a low-density parity-check code (low-density parity-check code, LDPC), and the soft decoding can be a decoding method of an LDPC.

[0049] refer to Figure 8 The example shown is used for illustration, where Figure 8In the description, each memory cell of each segment is used to store only one bit, that is, the super data page 330_1 is a single-level cell (SLC) data page, but the present invention is not limited thereto. Figure 8, the memory cell is used to store one bit and has one of two states S0 and S1, wherein state S0 corresponds to a logic value "0" and state S1 corresponds to a logic value "1". The control circuit in the flash memory module 120 can use a read voltage Vr to read each memory cell to determine the logic value of the memory cell, wherein if the memory cell is turned on when the read voltage Vr is applied, the memory cell is judged to correspond to a logic value "1"; and if the memory cell is not turned on when the read voltage Vr is applied, the control circuit 320 judges that the memory cell corresponds to a logic value "0". The logic value of each memory cell judged above can be called a sign bit, and a plurality of sign bits corresponding to all memory cells of a segment can be called hard information. It should be noted that due to the voltage distribution of states S0 and S1, the sign bit of the memory cell judged by the flash memory module 120 may not be the actual logic value. In addition, the decoder 134 in the flash memory controller 110 can perform hard decoding on the hard information of a segment to try to obtain a decoded data, and if the decoder 134 cannot successfully decode the adaptive information, the flash memory controller 110 will control the flash memory module 120 to generate soft information for soft decoding. For example, the flash memory module 120 can use the read voltage (Vr+Δ) and (Vr-Δ) again to read each memory cell of the segment to determine a first soft bit of the memory cell. For example, if the memory cell is turned on when the read voltage (Vr+Δ) is applied, or the memory cell is not turned on when the read voltage (Vr-Δ) is applied, the flash memory module 120 determines that the memory cell corresponds to a strong region, and the first soft bit of the memory cell is a strong bit "1". If the memory cell is conductive when the read voltage (Vr-Δ) is applied, and the memory cell is not conductive when the read voltage (Vr+Δ) is applied, the flash memory module 120 determines that the memory cell corresponds to a weak region, and the first soft bit of the memory cell is a weak bit "0". In addition, the flash memory module 120 can use another read voltage, such as read voltages (Vr+2*Δ) and (Vr-2*Δ), to read each memory cell of the segment to determine the second soft bit of the memory cell. For example, if the memory cell is conductive when the read voltage (Vr+2*Δ) is applied, or the memory cell is not conductive when the read voltage (Vr-2*Δ) is applied, the flash memory module 120 determines that the memory cell corresponds to a strong region, and the second soft bit of the memory cell is a strong bit "1".If the memory cell is conductive when the read voltage (Vr-2*Δ) is applied, and the memory cell is not conductive when the read voltage (Vr+2*Δ) is applied, the flash memory module 120 determines that the memory cell corresponds to a weak region, and the second soft bit of the memory cell is a weak bit "0". The plurality of first soft bits and the plurality of second soft bits corresponding to all memory cells of the segment may be referred to as soft information. After obtaining the soft information of the segment, the decoder 134 may perform soft decoding using the hard information and the soft information of the segment to attempt to obtain decoded data.

[0050] In step 506, the decoder 134 in the flash memory controller 110 determines whether the currently decoded segment is decoded successfully. If so, the process proceeds to step 512; if not, the process proceeds to step 508. In this embodiment, "whether the segment is decoded successfully" refers to whether the decoder 134 can use the hard information and soft information of the segment to perform soft decoding to successfully generate decoded data.

[0051] In step 508 , the decoder 134 determines whether the last segment of the super data page 330_1 has been decoded. If so, the process proceeds to step 510 and the decoder 134 completes the decoding operation of the super data page 330_1 . If not, the process returns to step 504 to continue decoding the next segment.

[0052] In step 512, the decoder 134 in the flash memory controller 110 determines whether a syndrome or a syndrome weight of the segment where decoding fails is greater than a syndrome threshold value. If so, the process proceeds to step 514; if not, the process proceeds to step 534. It should be noted that the syndrome weight mentioned above is the number of parity check equations that are not satisfied during the decoding process, and the syndrome weight can be used to reflect the quality of data, wherein the smaller the value of the syndrome weight represents the better the quality of the data (the fewer the number of error bits of the data in the segment), and the higher the value of the syndrome weight represents the worse the quality of the data (the more the number of error bits of the data in the segment). In this embodiment, if the syndrome weight of the segment is greater than the syndrome threshold value, it means that the data in the segment has serious errors and cannot be decoded through the LDPC decoding method. In addition, since the meaning and calculation method of the above-mentioned symptoms and symptom weights are well known to those with ordinary knowledge in the art, such as U.S. Patent Application Publication No. US20190158115 and Taiwan Patent Publication No. TWI718060, the relevant calculation details are not repeated here.

[0053] For the convenience of the following description, the above-mentioned decoding failed segment is described as an Uncorrectable Error Correction Code (UECC) segment.

[0054] In step 514, the decoder 134 sequentially obtains data of the corresponding segments of the above UECC segments located on other data planes. For example, assuming that the UECC segments mentioned in steps 506 and 512 are Figure 3 The flash memory controller 110 needs to obtain the segment 310_1 of the data page P1 of the block B0 of the data plane 212_1 of the data plane 212_2 to 212_2A; and if the UECC segment mentioned in steps 506 and 512 is Figure 3 In step 514, if the control logic 114 or the buffer memory 116 already has the relevant data, the decoder 134 can directly read the data of the corresponding segment of the UECC segment located on the other data planes; if the control logic 114 or the buffer memory 116 does not have the relevant data, it needs to be read and decoded through the self-flash memory module 120.

[0055] In step 516 , the decoder 134 determines whether data of corresponding segments of the UECC segment on other data planes can be decoded successfully, that is, only the UECC segment in the super data page 330_1 cannot be decoded successfully. If so, the process proceeds to step 518 ; otherwise, the process proceeds to step 520 .

[0056] In step 518, the decoder 134 uses RAID decoding to perform decoding, that is, to perform an XOR operation on the data of the corresponding segment of the UECC segment located on other data planes, and the result of the XOR operation can be used as the decoded data of the UECC segment. Figure 4 For example, if the segment 310_1 of the data page P1 of the block B0 of the data plane 212_1 is a UECC segment, the decoder 134 may perform an XOR operation on the segment 310_1 of the data page P1 of the block B0 of each data plane in the data planes 212_2 to 212_2A to generate decoded data of the segment 310_1 of the data page P1 of the block B0 of the data plane 212_1.

[0057] In step 520 , the decoder 134 determines whether there is another segment in the data of the corresponding segment of the UECC segment on other data planes in step 514 that is also a UECC segment, and its syndrome or syndrome weight is greater than the syndrome threshold value. If so, the process enters step 522 ; if not, the process enters step 524 .

[0058] In step 522 , the decoder 134 determines that the data in the UECC segment cannot be successfully decoded by the RAID decoding method, and abandons decoding of the UECC segment.

[0059] In step 524, the microprocessor 112 or the decoder 134 determines whether the number of UECC sections of the super data page 330_1 in the operations of steps 506 and 514 is greater than a threshold value. If so, the process proceeds to step 522; if not, the process proceeds to step 526. In this embodiment, the threshold value can be any suitable positive integer less than "2A".

[0060] In step 526, the microprocessor 112 or the decoder 134 generates a specific pattern according to the contents of all the segments of the super data page 330_1 in the operations of steps 506 and 514, such as the contents of the segment 310_1 of the data page P1 of the block B0 of each data plane in the data planes 212_1 to 212_2A, wherein the specific pattern is a possible error pattern, and the specific pattern is used to indicate which bit value in the above UECC segment is likely to be erroneous. Specifically, referring to Fig. 9 , the microprocessor 112 or the decoder 134 may perform XOR operations on the contents of the segment 310_1 of the data page P1 of the block B0 of each data plane in the data planes 212_1 to 212_2A in sequence to generate a specific pattern 910, that is, the microprocessor 112 or the decoder 134 performs XOR operations on the data D0 of the data page P1 of the block B0 of each data plane in the data planes 212_1 to 212_2A in sequence to generate data D0 of the specific pattern 910, and performs XOR operations on the data D1 of the data page P1 of the block B0 of each data plane in the data planes 212_1 to 212_2A in sequence to generate data D1 of the specific pattern 910, and so on. It should be noted that in Fig. 9 For each segment in the embodiment, if the segment can be successfully decoded by the decoder 134, the content of the segment used to calculate the specific pattern 910 can be the decoded data (i.e., correct data) or the data before decoding (i.e., data containing a small number of error bits); and if the segment is a UECC segment, the content of the segment used to calculate the specific pattern 910 is the data before decoding.

[0061] In step 528, the microprocessor 112 or the decoder 134 determines the possible error bits in the UECC segment according to the specific pattern 910. Fig. 9 In the embodiments, reference is also made to Figure 4 , since the data page P1 of block B0 of each data plane in the data plane 212_2A is used to store the result of XOR operation of the data page P1 of block B0 of the data plane 212_1~210_(2A-1), if the segment 310_1 can be successfully decoded, each data in the specific pattern 910 will be "0". Therefore, if "1" appears in the specific pattern 910, it means that the corresponding data in the above segment may be wrong. Specifically, assuming that the data D0 of the specific pattern 910 is "1", it means that the value of at least one data D0 in the data page P1 of block B0 of the data plane 212_1~212_2A is wrong. Therefore, the microprocessor 112 or the decoder 134 can determine multiple specific data in the above-mentioned UECC segment that may be erroneous bits based on the data with "1" in the specific pattern 910, that is, if the data D0 in the specific pattern 910 is "1", then the values ​​of the data D0 of the UECC segment determined by steps 506 and 512, and the UECC segment determined by steps 514 to 524 may be erroneous.

[0062] In step 530, the decoder 134 adjusts the soft information of at least a plurality of specific data of the UECC segment to generate adjusted soft information, wherein the adjusted soft information can selectively and significantly reduce the reliability of the hard information of each specific data compared to the original soft information. Figure 8 And its related content, assuming that the hard information, the first soft bit and the second soft bit of a specific data of the UECC segment are (1,1,1) respectively, then the adjusted first soft bit and the adjusted second soft bit included in the hard information and the adjusted soft information can be (1,0,0) respectively.

[0063] In one embodiment, since the data corresponding to the specific pattern 910 in the UECC segment is "0" and has a low probability of being erroneous, the decoder 134 can also adjust the soft information of other data in the UECC segment except for the multiple specific data (that is, the data corresponding to the specific pattern 910 is "0") to generate an adjusted soft information, wherein the adjusted soft information can selectively slightly reduce the reliability of the hard information of each piece of data compared to the original soft information. For example, while referring to Figure 8And its related content, assuming that the hard information, the first soft bit and the second soft bit of a data in the UECC segment are (1, 1, 1) respectively, then the adjusted first soft bit and the adjusted second soft bit included in the hard information and the adjusted soft information can be (1, 1, 0) respectively.

[0064] In step 532 , the decoder 134 uses the adjusted soft information of the UECC segment to decode the UECC segment again to obtain decoded data.

[0065] about Figure 7 In the process shown, the operations of steps 534, 536, and 538 are the same as those of steps 514, 516, and 518, so they are not repeated here. In step 540, it is determined whether there are two other segments in the process of the data of the corresponding segment of the UECC segment located on other data planes in step 514, and their symptoms or symptom weights are greater than the symptom threshold value. If so, the process enters step 542; if not, the process enters step 544. In addition, the operations of steps 542 to 552 are the same as those of steps 522 to 532, so they are not repeated here.

[0066] In the above embodiments of FIGS. 5 to 7, the operations of steps 528 to 532 and steps 518 to 552 are performed on the UECC segments determined in steps 506 and 512, but the present invention is not limited thereto. In other embodiments, since other UECC segments may be determined in steps 514 to 524 or steps 534 to 544, the operations of steps 528 to 532 and steps 518 to 552 may also be performed on these other UECC segments at the same time to speed up the overall execution efficiency.

[0067] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A control method for a memory device, wherein the memory device comprises a flash memory module, the flash memory module comprises a plurality of data planes, each data plane comprises a plurality of blocks, each block comprises a plurality of data pages, each data page comprises a plurality of segments, and the control method comprises: Reading a first data from a first section and decoding the first data, wherein the first section is located in a first data page in a super data page, and the super data page includes a plurality of data pages respectively located in the plurality of data planes; If the decoding of the first segment fails, obtaining data of a plurality of corresponding segments of the first segment, wherein the plurality of corresponding segments are respectively located in other data pages of the super data page except the first data page; If the data of the plurality of corresponding segments can be successfully decoded, generating decoded data of the specific segment according to the plurality of decoded data of the plurality of corresponding segments; and If not all of the data of the plurality of corresponding segments can be successfully decoded, it is determined whether to abandon the decoding operation of the first segment according to a syndrome weight of the first segment and at least one syndrome weight of at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments.

2. The control method according to claim 1, characterized in that: If not all of the data of the plurality of corresponding segments can be successfully decoded, the step of determining whether to abandon the decoding operation of the first segment according to the syndrome weight of the first segment and the at least one syndrome weight of the at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments comprises: If the syndrome weight of at least two of the first segment and the plurality of corresponding segments is greater than a syndrome threshold, abandoning the decoding operation of the first segment; and If the first segment and the number of segments whose syndrome weight is greater than the syndrome threshold value among the plurality of corresponding segments are less than two, the content of the first data is adjusted to generate an adjusted first data, and the adjusted first data is decoded.

3. The control method according to claim 2, characterized in that: The steps of adjusting the content of the first data to generate the adjusted first data and decoding the adjusted first data include: Generating a specific pattern according to the first data of the first segment and the data of the plurality of corresponding segments, wherein the specific pattern indicates which bit of the first data of the first segment is likely to be erroneous; as well as The content of the first data is adjusted according to the specific pattern.

4. The control method according to claim 3, characterized in that: The step of generating the specific pattern according to the first data of the first segment and the data of the plurality of corresponding segments comprises: An exclusive OR (XOR) operation is performed on the first data of the first segment and the data of the plurality of corresponding segments to generate the specific pattern.

5. The control method according to claim 3, characterized in that: The first data includes a plurality of hard information and a plurality of soft information respectively corresponding to a plurality of memory units, and the step of adjusting the content of the first data according to the specific pattern includes: The specific pattern is used to adjust at least a portion of the soft information in the first data to reduce the reliability of the corresponding hard information represented by the at least a portion of the soft information.

6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprises a plurality of data planes, each data plane comprises a plurality of blocks, each block comprises a plurality of data pages, each data page comprises a plurality of segments, and the flash memory controller comprises: A read-only memory for storing a program code; a buffer memory; and a microprocessor for executing the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: Reading a first data from a first section and decoding the first data, wherein the first section is located in a first data page in a super data page, and the super data page includes a plurality of data pages respectively located in the plurality of data planes; If the decoding of the first segment fails, obtaining data of a plurality of corresponding segments of the first segment, wherein the plurality of corresponding segments are respectively located in other data pages of the super data page except the first data page; If the data of the plurality of corresponding segments can be successfully decoded, generating decoded data of the specific segment according to the plurality of decoded data of the plurality of corresponding segments; and If not all of the data of the plurality of corresponding segments can be successfully decoded, it is determined whether to abandon the decoding operation of the first segment according to a syndrome weight of the first segment and at least one syndrome weight of at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments.

7. The flash memory controller according to claim 6, wherein: If not all of the data of the plurality of corresponding segments can be successfully decoded, the step of determining whether to abandon the decoding operation of the first segment according to the syndrome weight of the first segment and the at least one syndrome weight of the at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments comprises: If the syndrome weight of at least two of the first segment and the plurality of corresponding segments is greater than a syndrome threshold, abandoning the decoding operation of the first segment; and If the first segment and the number of segments whose syndrome weight is greater than the syndrome threshold value among the plurality of corresponding segments are less than two, the content of the first data is adjusted to generate an adjusted first data, and the adjusted first data is decoded.

8. The flash memory controller according to claim 7, wherein: The steps of adjusting the content of the first data to generate the adjusted first data and decoding the adjusted first data include: Generating a specific pattern according to the first data of the first segment and the data of the plurality of corresponding segments, wherein the specific pattern indicates which bit of the first data of the first segment is likely to be erroneous; as well as The content of the first data is adjusted according to the specific pattern.

9. The flash memory controller according to claim 8, wherein: The step of generating the specific pattern according to the first data of the first segment and the data of the plurality of corresponding segments comprises: An exclusive OR (XOR) operation is performed on the first data of the first segment and the data of the plurality of corresponding segments to generate the specific pattern.

10. The flash memory controller according to claim 8, wherein: The first data includes a plurality of hard information and a plurality of soft information respectively corresponding to a plurality of memory units, and the step of adjusting the content of the first data according to the specific pattern includes: The specific pattern is used to adjust at least a portion of the soft information in the first data to reduce the reliability of the corresponding hard information represented by the at least a portion of the soft information.

11. A memory device comprising: A flash memory module, wherein the flash memory module comprises a plurality of data planes, each data plane comprises a plurality of blocks, each block comprises a plurality of data pages, each data page comprises a plurality of sectors; and a flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: Reading a first data from a first section and decoding the first data, wherein the first section is located in a first data page in a super data page, and the super data page includes a plurality of data pages respectively located in the plurality of data planes; If the decoding of the first segment fails, obtaining data of a plurality of corresponding segments of the first segment, wherein the plurality of corresponding segments are respectively located in other data pages of the super data page except the first data page; If the data of the plurality of corresponding segments can be successfully decoded, generating decoded data of the specific segment according to the plurality of decoded data of the plurality of corresponding segments; and If not all of the data of the plurality of corresponding segments can be successfully decoded, it is determined whether to abandon the decoding operation of the first segment according to a syndrome weight of the first segment and at least one syndrome weight of at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments.

12. The memory device according to claim 11, characterized in that If not all of the data of the plurality of corresponding segments can be successfully decoded, the step of determining whether to abandon the decoding operation of the first segment according to the syndrome weight of the first segment and the at least one syndrome weight of the at least one corresponding segment that cannot be successfully decoded among the plurality of corresponding segments comprises: If the syndrome weight of at least two of the first segment and the plurality of corresponding segments is greater than a syndrome threshold, abandoning the decoding operation of the first segment; and If the first segment and the number of segments whose syndrome weight is greater than the syndrome threshold value among the plurality of corresponding segments are less than two, the content of the first data is adjusted to generate an adjusted first data, and the adjusted first data is decoded.

13. The memory device according to claim 12, characterized in that The steps of adjusting the content of the first data to generate the adjusted first data and decoding the adjusted first data include: Generating a specific pattern according to the first data of the first segment and the data of the plurality of corresponding segments, wherein the specific pattern indicates which bit of the first data of the first segment is likely to be erroneous; as well as The content of the first data is adjusted according to the specific pattern.

14. The memory device according to claim 13, characterized in that The step of generating the specific pattern according to the first data of the first segment and the data of the plurality of corresponding segments comprises: An exclusive OR (XOR) operation is performed on the first data of the first segment and the data of the plurality of corresponding segments to generate the specific pattern.

15. The memory device according to claim 13, characterized in that The first data includes a plurality of hard information and a plurality of soft information respectively corresponding to a plurality of memory units, and the step of adjusting the content of the first data according to the specific pattern includes: The specific pattern is used to adjust at least a portion of the soft information in the first data to reduce the reliability of the corresponding hard information represented by the at least a portion of the soft information.

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