Data transmission method between chip and chip core particles and electronic equipment

Abstract

The invention relates to a data transmission method between a chip and chip core particles and electronic equipment, and belongs to the field of integrated circuits. The chip comprises a plurality of core particles and interconnection links, the plurality of core particles are connected through the interconnection links, each core particle is connected with at least two interconnection links, and each interconnection link in the at least two interconnection links is connected to different core particles; each core particle is used for transmitting data to a destination through a transmission path where a first interconnection link in the at least two interconnection links is located in advance, and when the first interconnection link is abnormal, a second interconnection link in the at least two interconnection links is automatically selected, and the second interconnection link is used for replacing the first interconnection link to carry out data transmission, the second interconnection link is a normal link, and a transmission path exists between the second interconnection link and the destination. According to the invention, the problems of high cost and low utilization rate of the fault-tolerant design of the existing standby redundant link can be improved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuits, and specifically relates to a data transmission method between a chip and chip core particles and an electronic device. Background Art

[0002] By integrating multiple functional modules DIE (chiplets) in one package, not only the performance and integration of the chip are improved, but also the design cycle and manufacturing cost are shortened. However, as the scale of chip systems continues to expand, the number of integrated DIEs is increasing, and the interconnection links between DIEs are becoming more and more complex. This complexity increases the probability of failure of the inter-DIE links, which directly affects the startup of the system and the stability of business operations. The inter-DIE interconnection links refer to the data transmission channels between each chiplet (DIE). They are responsible for transmitting various control signals and data information and are the key to ensuring the normal operation of the entire chip system. However, these links are easily affected by various factors in a complex working environment, resulting in link failures. In order to improve the reliability and stability of the system, an effective fault-tolerant processing method must be adopted to ensure that the system can quickly resume normal operation when a link failure occurs.

[0003] The current solution is to add redundant backup links to each key link in the chip system. These redundant backup links can realize automatic switching functions through hardware multiplexing and switching switches; for example, each main link has one or more redundant backup links. If the main link fails, the system can automatically switch to the redundant backup link to maintain the continuity of data transmission. Although the above solution improves the reliability of the system to a certain extent, it still has the following disadvantages: the design of redundant backup links requires additional hardware resources, thereby increasing the cost of chip design and manufacturing; at the same time, the redundant backup links are idle under normal circumstances, with low utilization, resulting in resource waste. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a data transmission method and electronic device between chips and chip cores, so as to improve the problems of high cost and low utilization rate existing in the fault-tolerant design of existing backup redundant links.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a chip, comprising: a plurality of core particles and interconnection links, the plurality of core particles being connected through the interconnection links, each of the core particles being connected to at least two interconnection links, each of the at least two interconnection links being connected to a different core particle; each of the core particles being used to transmit data to a destination through a transmission path where a first interconnection link of the at least two interconnection links is located, and when the first interconnection link is abnormal, automatically select a second interconnection link of the at least two interconnection links, and use the second interconnection link to replace the first interconnection link for data transmission, wherein the second interconnection link is a normal link, and there is a transmission path between the second interconnection link and the destination.

[0007] In the above embodiment, since each core particle is connected to at least two interconnection links, and each interconnection link is connected to a different core particle, the core particle can automatically select and switch the interconnection link when an interconnection link fails. For example, when data is transmitted to the destination through the transmission path where the first interconnection link of at least two interconnection links is located, and the first interconnection link is abnormal, the second interconnection link (which is a normal link and there is a transmission path between the first interconnection link and the destination) is used to replace the first interconnection link for data transmission to ensure that the chip can still operate correctly. By using the mutual backup method of at least two interconnection links, through the fast fault switching mechanism, optimized resource use, automated fault handling and other measures, the problems of high cost, waste of resources, large delay, complex system and so on in the prior art are effectively solved, and the reliability and stability of the chip system are improved.

[0008] In combination with a possible implementation manner of the embodiment of the first aspect, an adaptive routing control module is provided in each of the core particles, and the adaptive routing control module is used to obtain a cross-core backup routing table in a preset routing table when a first interconnected link among the at least two interconnected links is abnormal, and automatically select a transmission path where a second interconnected link among the at least two interconnected links is located according to the cross-core backup routing table for data transmission, wherein the cross-core backup routing table is used to determine a transmission path including the second interconnected link that bypasses the abnormal interconnected link, and a destination of the transmission path where the second interconnected link is located is the same as a destination of the transmission path where the first interconnected link is located.

[0009] In the above embodiment, an adaptive routing control module is added inside the chiplet (DIE). Through this module, when a failure occurs in the interconnection link, the chiplet can quickly and automatically select and switch the transmission path according to a pre-configured cross-chiplet backup routing table (also called a cross-DIE backup routing table), thereby ensuring that the chip can still operate correctly. This effectively solves the problems of high cost, waste of resources, large delay, and complex system in the prior art, and improves the reliability and stability of the chip system.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, the adaptive routing control module includes: a routing table lookup unit and a path switching control unit; the routing table lookup unit is used to search for a routing table built into the chip, the routing table including the cross-chip backup routing table; the path switching control unit is connected to the routing table lookup unit; the path switching control unit is used to search for the cross-chip backup routing table through the routing table lookup unit when the first interconnection link is abnormal, and automatically select the transmission path where the second interconnection link is located for data transmission according to the found cross-chip backup routing table.

[0011] In the above embodiment, the routing table lookup unit is combined with the path switching control unit to ensure that the chip can still operate normally in the case of partial link failure. For example, when the first interconnection link is abnormal, the path switching control unit searches the routing table built into the chip through the routing table lookup unit, and automatically selects the second interconnection link according to the cross-chip backup routing table found, and replaces the first interconnection link for data transmission. Splitting complex modules into different small units is conducive to reducing design complexity and design flexibility.

[0012] In combination with a possible implementation manner of the embodiment of the first aspect, the adaptive routing control module further includes: a link status monitoring unit connected to the path switching control unit; the link status monitoring unit is used to monitor the status of the interconnection link, and when it is detected that the first interconnection link is abnormal, the abnormal first interconnection link is recorded in an abnormal link table; the path switching control unit is further used to access the abnormal link table to obtain the abnormal interconnection link.

[0013] In the above embodiment, a link status monitoring unit is added to monitor the status of the interconnection link, and when an abnormality is monitored, the abnormal first interconnection link is recorded in the abnormal link table, ensuring that the path switching control unit can be informed of the abnormal interconnection link in time, so as to switch to other paths in time and quickly, ensuring that the chip can still operate normally in the case of partial link failure.

[0014] In combination with a possible implementation manner of the embodiment of the first aspect, the preset routing table further includes a cross-chip main routing table, and the cross-chip main routing table is used to determine an optimal transmission path for data transmission when the interconnection link is normal.

[0015] In the above embodiment, by combining the cross-chip main routing table + the cross-chip backup routing table, data can be transmitted based on the optimal transmission path when the interconnection link is normal, and data can be transmitted based on the alternative path when the interconnection link is abnormal, which is beneficial to improving the performance of the chip system.

[0016] In combination with a possible implementation manner of the embodiment of the first aspect, the multiple core particles include M*N core particles, M and N are both integers greater than or equal to 2; the at least two interconnection links include a horizontal interconnection link and a vertical interconnection link; the cross-core particle main routing table follows the configuration rule of the vertical interconnection link first and the horizontal interconnection link later or the horizontal interconnection link first and the vertical interconnection link later; the cross-core particle backup routing table follows the configuration rule of the horizontal interconnection link and the vertical interconnection link backing up each other.

[0017] In the above embodiment, the above configuration rules are followed when configuring the cross-chip main routing table and the cross-chip backup routing table to ensure that when the interconnection link is normal, the transmission path determined based on the cross-chip main routing table is the optimal transmission path, and when the interconnection link is abnormal, the transmission path determined based on the cross-chip backup routing table can bypass the abnormal interconnection link, thereby ensuring the reliability and stability of the chip.

[0018] In combination with a possible implementation manner of the embodiment of the first aspect, the core particle further includes: a cache queue, used to temporarily cache data transmitted externally by the core particle; the adaptive routing control module is also used to use the second interconnection link to transmit the data transmitted externally by the core particle in the cache queue.

[0019] In the above embodiment, by setting a cache queue to temporarily cache the data transmitted externally by the chip, it is beneficial to improve the concurrent processing capability of the chip, reduce network transmission delay, and improve the efficiency of data transmission and reception.

[0020] In combination with a possible implementation manner of the embodiment of the first aspect, the core particle further includes: a main module, a slave module, a routing node and at least two interconnect modules, and the at least two interconnect modules, the main module and the slave module are all connected to the routing node; each of the interconnect modules, the main module and the slave module in the core particle is provided with the adaptive routing control module; the adaptive routing control module in the interconnect module is further used to report abnormal link information to the adaptive routing control modules in other modules in the core particle when an abnormality is detected in the first interconnect link.

[0021] In the above embodiment, since each interconnection module, the master module, and the slave module are provided with an adaptive routing control module, each module can transmit data in parallel, which can improve the efficiency of data transmission. At the same time, the adaptive routing control module in the interconnection module is also used to report abnormal link information to the adaptive routing control modules in other modules in the core particle when the first interconnection link is detected to be abnormal, so that the adaptive routing control modules in other modules can learn the abnormal link information.

[0022] In combination with a possible implementation manner of the embodiment of the first aspect, the chip is a server chip.

[0023] In the above embodiment, an adaptive routing control module is added to the server chip to ensure that the chip can still operate normally in the event of partial link failure, so as to meet the requirements of high performance computing and data centers for high reliability and high stability.

[0024] In a second aspect, an embodiment of the present application further provides an electronic device, comprising: a chip provided in the embodiment of the first aspect described above and / or in any possible implementation manner in combination with the embodiment of the first aspect.

[0025] In a third aspect, an embodiment of the present application also provides a method for data transmission between chip cores, wherein the chip comprises multiple cores and interconnection links, the multiple cores are connected via interconnection links, each core is connected to at least two interconnection links, and each of the at least two interconnection links is connected to a different core; the method comprises: the core transmits data to a destination through a transmission path where a first interconnection link of the at least two interconnection links is located, and when an abnormality occurs in the first interconnection link, the core automatically selects a second interconnection link of the at least two interconnection links; the core uses the second interconnection link to replace the first interconnection link for data transmission; wherein the second interconnection link is a normal link, and there is a transmission path between the second interconnection link and the destination.

[0026] In combination with a possible implementation manner of the embodiment of the third aspect, an adaptive routing control module is provided in each chiplet to automatically select a second interconnection link among the at least two interconnection links, including: the adaptive routing control module obtains a cross-chiplet backup routing table preset in the chiplet, wherein the cross-chiplet backup routing table is used to determine a transmission path including the second interconnection link that bypasses the abnormal interconnection link; and the adaptive routing control module automatically selects the second interconnection link among the at least two interconnection links according to the cross-chiplet backup routing table.

[0027] In combination with a possible implementation manner of the third aspect, the method further includes: the adaptive routing control module monitors the state of the interconnection link, and when detecting that the first interconnection link is abnormal, records the abnormal first interconnection link in an abnormal link table.

[0028] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0030] Figure 1 A schematic structural diagram of a chip provided in an embodiment of the present application is shown.

[0031] Figure 2a A schematic diagram showing the principle of data transmission according to a cross-chip master routing table in a chip provided by an embodiment of the present application is shown.

[0032] Figure 2b A schematic diagram showing the principle of a chip provided by an embodiment of the present application performing data transmission according to a cross-chip backup routing table is shown.

[0033] Figure 3 A schematic structural diagram of a core particle provided in an embodiment of the present application is shown.

[0034] Figure 4a A schematic diagram of the structure of an adaptive routing control module provided in an embodiment of the present application is shown.

[0035] Figure 4b A schematic diagram of the structure of another adaptive routing control module provided in an embodiment of the present application is shown.

[0036] Figure 5 A schematic diagram of data transmission before and after an interconnection module enters a backup routing mode is shown in an embodiment of the present application.

[0037] Figure 6 A schematic diagram showing the principle of a fault tolerance processing method for routing between chip dies provided in an embodiment of the present application is shown.

[0038] Figure 7 A schematic flow chart of a data transmission method between chip cores provided in an embodiment of the present application is shown.

[0039] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0041] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0042] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0043] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0044] With the increase of interconnection links between core particles (DIE) in chips (such as server chips), the frequency of interconnection link failures has increased significantly. In view of the deficiencies in the design of backup redundant links in the prior art, for example, although the backup redundant link design can provide fault tolerance, its high cost and waste of resources still exist. The embodiment of the present application provides a fault-tolerant processing method for routing between core particles. When a certain interconnection link between core particles fails, the chip system can quickly switch to other paths to ensure that the chip can still operate normally in the event of partial link failure. Through measures such as fast fault switching mechanism, optimized resource utilization, and automated fault handling, the problems of high cost, waste of resources, large delay, and complex system in the prior art are effectively solved, the reliability and stability of the chip system are improved, and the requirements of high-performance computing and data centers for high reliability and high stability are met.

[0045] Combine the following Figure 1 , the chip provided in the embodiment of the present application is described, such as Figure 1 As shown, the chip includes multiple core particles and interconnection links (Link), multiple core particles are connected by interconnection links, each core particle is connected to at least two interconnection links (including a first interconnection link and a second interconnection link), and each interconnection link in the at least two interconnection links is connected to a different core particle. For example, multiple core particles are connected by interconnection links to form a MESH or a fully interconnected network. It can be understood that Figure 1 Only a schematic diagram of a MESH network formed by connecting multiple particles through interconnected links is shown.

[0046] Each core particle is used to transmit data to the destination through the transmission path where the first interconnection link of at least two interconnection links is located (or is planned to be passed, or is ready to be passed), and when the first interconnection link is abnormal, automatically select the second interconnection link of at least two interconnection links, and use the second interconnection link to replace the first interconnection link for data transmission, wherein the second interconnection link is a normal link, and there is a transmission path between the second interconnection link and the destination (the destination of the transmission path where the first interconnection link is located). When transmitting data, when transmitting data using the transmission path including the second interconnection link, the destination of the transmission path needs to be the same as the destination of data transmitted using the transmission path including the first interconnection link to ensure that the data is transmitted to the same destination.

[0047] Since there is a transmission path between the second interconnection link and the destination, when the first interconnection link is abnormal, the core particle can transmit the data to be transmitted (that is, the data pre-transmitted through the transmission path where the first interconnection link is located) to the destination through the second interconnection link. For example, the data to be transmitted is transmitted to the next core particle through the second interconnection link, and the next core particle continues to transmit it to the next core particle according to the destination in the data to be transmitted, and so on, it can be transmitted to the destination.

[0048] It should be noted that the second interconnection link and the first interconnection link in the present application back up each other, and the second interconnection link in the present application is not a spare redundant link specially designed for the first interconnection link. Under normal circumstances, the second interconnection link is not in an idle state, but is used as a link for data transmission with other core particles. The reason why the second interconnection link and the first interconnection link in the present application back up each other is determined by the connection method of the core particles. Because multiple core particles are connected through interconnection links to form a MESH or fully interconnected network, each of the at least two interconnection links connected to each core particle is connected to a different core particle, and can back up each other.

[0049] Among them, for the MESH network: the nodes in the MESH are only connected to the adjacent nodes, which is suitable for large-scale networks and easy to expand. For the fully interconnected network: each node in the fully interconnected network is directly connected to all other nodes, which is suitable for small-scale networks with a large number of connections.

[0050] In a possible implementation, the chip includes M*N core particles, for example, the above-mentioned multiple core particles include M*N core particles, M and N are both integers greater than or equal to 2, and each core particle is connected with a horizontal interconnection link and a vertical interconnection link, that is, at least two interconnection links of each core particle include a horizontal interconnection link and a vertical interconnection link, wherein the first interconnection link (or the second interconnection link) can be a horizontal interconnection link or a vertical interconnection link. Figure 1 In the example shown, the chip includes 3*2 core particles, each of which is connected with a horizontal interconnection link and a vertical interconnection link.

[0051] In a possible implementation manner, an adaptive routing control module (ARCM) is provided in each chiplet, and the adaptive routing control module is used to obtain a cross-chiplet backup routing table in a preset routing table when a first interconnection link among at least two interconnection links of the chiplet is abnormal, and automatically select a transmission path where a second interconnection link among the at least two interconnection links is located for data transmission according to the cross-chiplet backup routing table, wherein a destination of the transmission path where the second interconnection link is located is the same as a destination of the transmission path where the first interconnection link is located, so as to ensure that the chiplet can still operate normally in the case of partial link failure, thereby ensuring that the chip can still operate normally in the case of partial link failure.

[0052] It can be understood that there may be multiple transmission paths including the second interconnected link, and the destinations of these multiple transmission paths may be different. When selecting the transmission path including the second interconnected link, it is necessary to select a transmission path whose destination is the same as the destination of the transmission path where the first interconnected link is located and which includes the second interconnected link. Then, the transmission path including the second interconnected link is the transmission path where the second interconnected link is located.

[0053] The embodiment of the present application provides a new chip. By adding an adaptive routing control module inside the chip, the chip can monitor the status of the interconnection link in real time through this module. When a failure occurs in the interconnection link, the chip can quickly and automatically select and switch the transmission path according to the information in the pre-configured routing table (such as the cross-chip backup routing table, also called the cross-DIE backup routing table) to ensure that the chip can still operate correctly.

[0054] Among them, the cross-chip backup routing table is used to determine the transmission path (alternative path) including the second interconnect link that bypasses the abnormal interconnect link. The cross-chip backup routing table needs to be pre-configured, and during the configuration, the backup transmission path for each interconnect link when it is abnormal will be configured, thereby bypassing the abnormal interconnect link. Correspondingly, the preset routing table also includes a cross-chip main routing table (also called a cross-DIE main routing table), which is used to determine the optimal transmission path for data transmission (such as the shortest transmission distance) when the interconnect link is normal. Through the combination of the cross-chip main routing table + the cross-chip backup routing table, data can be transmitted based on the optimal transmission path when the interconnect link is normal, and data can be transmitted based on the alternative path when the interconnect link is abnormal.

[0055] In some possible implementations, when the chip includes M*N core particles, each core particle is connected with a horizontal (such as X-axis) interconnection link and a vertical (such as Y-axis) interconnection link, the cross-core particle main routing table follows the configuration rule of vertical interconnection link first and then horizontal interconnection link or horizontal interconnection link first and then vertical interconnection link; the cross-core particle backup routing table follows the configuration rule of mutual backup of horizontal interconnection link and vertical interconnection link.

[0056] For ease of understanding, combined Figure 2a , Figure 2b When configuring the cross-chip master routing table, you can follow the rule of "Y-axis routing (Link) first, then X-axis routing", for example, Figure 2a As shown in the figure, when a message is sent from MasterA of DIE0 and the destination is SlaveA of DIE5, the message will first be routed along the Y axis to reach the row where the target DIE is located, and then routed along the X axis to reach the target DIE. The transmission path is as follows Figure 2a When configuring the cross-chip backup routing table, you can follow the rule of "horizontal links and vertical links backing up each other", which means that when a horizontal link fails, the system will automatically switch to the corresponding vertical backup link, and vice versa. For example, when Figure 2a When an abnormality occurs in the Link between DIE3 and DIE4, such as Figure 2b As shown in Figure 2, DIE3 will forward the message to the backup horizontal link and reach the target DIE via the path of DIE2. The transmission path is as follows: Figure 2b Shown by the dashed line.

[0057] Figure 2a The link between DIE3 and DIE4 can be regarded as the first interconnection link, and the link between DIE3 and DIE2 can be regarded as the second interconnection link. When DIE3 passes through the transmission path where the first interconnection link is located ( Figure 2aWhen the first interconnection link is abnormal, and there is a transmission path between the second interconnection link and SlaveA of DIE5, as shown in 2b, DIE3 can transmit the data to be transmitted to DIE2 via the second interconnection link, and then DIE2 transmits the data to be transmitted to SlaveA of DIE5. Figure 2b The dotted line where SlaveA of DIE3-DIE2-DIE5 is located is the transmission path where the second interconnection link is located.

[0058] The above-mentioned routing table may be built into the adaptive routing control module. In a possible implementation, the above-mentioned routing table may not be built into the adaptive routing control module, but stored in the memory of the core particle, and the adaptive routing control module obtains the routing table by accessing the memory. In this implementation, multiple adaptive routing control modules can share a routing table.

[0059] Each chiplet is a single integrated circuit chip unit, which is an independent chip cut from a wafer. Each DIE contains specific circuits and functions and can be used as an independent chip or part of a chiplet. The functions implemented by each chiplet can be different, so the internal structure of each chiplet can be different. Among them, chiplet refers to a small integrated circuit module that can be used as part of a larger system-on-chip (SoC).

[0060] In a possible implementation, the core particle further includes: a master module (Master), a slave module (Slave), a routing node (Crossbar) and at least two interconnection modules, such as Figure 3 As shown. At least two interconnect modules, a master module, and a slave module are connected to the routing node. Among them, Crossbar can be an NxN routing node used to connect Master, Slave, and interconnect modules. Master can refer to the main entity that controls data transmission in the system. Master is usually the main control unit that initiates communication and determines how data is transmitted between different modules or devices. Slave can refer to a response entity controlled by the Master. Slave usually performs specific functions as a subordinate unit and returns the operation results to the Master. Since the functions implemented by each core particle may be different, the implementation methods of Master and Slave in different core particles may be different.

[0061] In one possible implementation, Figure 3In the example shown, each interconnect module, main module, and slave module in the core particle is provided with an adaptive routing control module. Since each interconnect module, main module, and slave module is provided with an adaptive routing control module, each module can transmit data in parallel, which can improve the efficiency of data transmission. In this embodiment, the adaptive routing control module in the interconnect module is also used to report abnormal link information to the adaptive routing control modules in other modules in the core particle when the first interconnect link is detected to be abnormal, so that the adaptive routing control modules in other modules can learn the abnormal link information.

[0062] exist Figure 3 In the illustrated implementation mode, any message across DIE needs to be sent to Crossbar via the adaptive routing control module, and then routed to the specified Link via the interconnection module. During normal operation, data (including messages) are transmitted according to the main path in the routing table. When an abnormality occurs in the Link, the interconnection module will first sense it, and then the interconnection module will enter the backup routing mode. At this time, the data transmission in the interconnection module will change. The adaptive routing control module will take over the unsent messages and retrieve the information of the backup path from the routing table, quickly adjust the signal flow direction, so that the data transmission bypasses the faulty link and continues to be transmitted through the backup path. The whole process is completed within milliseconds, ensuring the real-time response of the system. After the interconnection module enters the backup routing mode, it will report the abnormal link information to all Masters, Slavers and interconnection modules in the DIE, and then the adaptive routing control module will record the abnormal link information to the abnormal link table (abnormal link table); when it is identified that the message is going to pass through the abnormal Link, the backup path in the routing table is retrieved, and the transmission path is adjusted so that the data transmission bypasses the faulty link to ensure that the data can be seamlessly transferred to the backup path. Through the above improvements, the newly added adaptive routing control module (ARCM) can more efficiently manage link status and path switching within the DIE, ensuring rapid response when anomalies occur. At the same time, ARCM realizes fast path switching through the internal cross-chip routing table, enabling the system to achieve routing fault tolerance between DIEs in a complex interconnected architecture.

[0063] In some implementations, each interconnect module, main module, and slave module in the core particle may share one adaptive routing control module. In this case, the adaptive routing control module is no longer arranged in each interconnect module, main module, and slave module in the core particle, but is connected to each interconnect module, main module, and slave module in the core particle through a routing node. Each interconnect module, main module, and slave module in the core particle will access the adaptive routing control module when sending data. When multiple modules need to access the adaptive routing control module, a serial access method may be adopted, and the module needs to wait until the previous module has completed the access before it can access the module.

[0064] In one possible implementation, the core particle further includes: a cache queue, which is used to temporarily cache data transmitted by the core particle to the outside. The adaptive routing control module is also used to use the second interconnection link to transmit the data transmitted by the core particle in the cache queue to the outside. In some implementations, the cache queue may include an output queue (Out Queue), which refers to a buffer or queue for temporarily storing data that has been processed and is ready to be transmitted. In some possible implementations, the cache queue may also include an input queue (In Queue), which refers to a buffer or queue for temporarily storing data entering the system.

[0065] In a possible implementation, each interconnection module, main module, and slave module in the core particle may be internally provided with a cache queue, for example, each may be provided with an In Queue and an Out Queue.

[0066] In one implementation, Figure 4a As shown, the adaptive routing control module includes: a routing table lookup unit and a path switching control unit. The routing table lookup unit is used to look up the routing table built into the core particle, and the routing table may include the above-mentioned cross-core backup routing table and cross-core main routing table. The path switching control unit is connected to the routing table lookup unit, and the path switching control unit is used to look up the cross-core backup routing table through the routing table lookup unit when the first interconnection link is abnormal, and automatically select the second interconnection link according to the found cross-core backup routing table, and use the second interconnection link to replace the first interconnection link for data transmission.

[0067] In the example shown in 4a, the inter-DIE main routing table and the inter-DIE backup routing table are both built into the adaptive routing control module, and the path switching control unit can search the routing table through the routing table lookup unit.

[0068] In some possible implementations, such as Figure 4b As shown, the adaptive routing control module may also include a link status monitoring unit connected to the path switching control unit. The link status monitoring unit is used to monitor the status of the interconnection link, and when the first interconnection link is detected to be abnormal, the abnormal first interconnection link is recorded in an abnormal link table (also referred to as an abnormal Link table). The path switching control unit is also used to access the abnormal link table to obtain or learn about the abnormal interconnection link.

[0069] exist Figure 4bIn the example shown, the abnormal Link table is built into the adaptive routing control module. In some possible implementations, the normal Link table may not be built into the adaptive routing control module, but stored in the memory of the core particle. The adaptive routing control module can access the abnormal Link table in the memory. In this implementation, multiple adaptive routing control modules can share an abnormal Link table. Among them, the perception and monitoring of Link anomalies are mainly carried out in two ways: 1. The link actively reports errors; 2. The timeout mechanism of the interconnection module, that is, the message is not successfully sent to the link, and the cache time occupied exceeds the threshold. If the threshold is exceeded, it is defaulted to Link abnormality. After the link status monitoring unit in the interconnection module perceives that the connected Link is abnormal, the corresponding interconnection module will enter the backup routing mode. After entering the backup routing mode, the adaptive routing control module will take over the unsent messages in the In Queue and perform routing resolution on these messages. According to the destination and the cross-DIE backup routing table, select the appropriate backup Link, send the message to Crossbar through the Out Queue, and then forward it to the backup Link. The principle is as follows Figure 5 shown.

[0070] After the interconnection module enters the backup routing mode, it will send a special message to notify all Master, Slave and interconnection modules in the DIE of the abnormal Link. After receiving the abnormal Link information, the adaptive routing control module in all Master, Slave and interconnection modules in the DIE will switch the message passing through the abnormal Link to the backup Link.

[0071] In a possible implementation manner, after the link status monitoring unit senses that a connected Link is abnormal, it may also report specific abnormal Link information to the user to remind the user of the occurrence of the Link abnormality.

[0072] In a possible implementation manner, the principle of the fault tolerance processing method for chip-to-chip routing in the present application can be as follows: Figure 6 As shown. After the interconnection module enters the backup routing mode, it will obtain the cross-chip backup routing table in the preset routing table, and automatically select the second interconnection link of at least two interconnection links according to the cross-chip backup routing table, and use the second interconnection link to replace the first interconnection link for data transmission. Among them, the cross-DIE routing table configuration can be configured once and used multiple times. For example, it can be configured at the first power-on startup, and there is no need to repeat the configuration at subsequent power-ons. The cross-DIE routing table configuration can include a cross-DIE backup routing table and a cross-DIE main routing table configuration.

[0073] The above-mentioned adaptive routing control module can be implemented in hardware or software, or a hybrid hardware and software architecture can be used. For example, the adaptive routing control module is designed as a reconfigurable hardware accelerator, rather than being limited to fixed logic circuits. Through reconfigurable logic (such as FPGA), the routing strategy and path switching logic can be dynamically adjusted in different application scenarios or fault modes, thereby achieving the effect achieved by the adaptive routing control module of the present application. A hybrid hardware and software architecture is used, in which the hardware implements the core high-performance routing switching logic, and the software is responsible for more complex fault handling and path optimization, thereby achieving the effect achieved by the adaptive routing control module of the present application.

[0074] The chip provided in the embodiment of the present application includes but is not limited to a server chip, and may also be other chips including multiple chips. The chip may be a processor.

[0075] The embodiment of the present application also provides a data transmission method between chip core particles with fault-tolerant processing capability, and the data transmission method is applied to the above-mentioned chip, that is, the chip includes multiple core particles and interconnection links, the multiple core particles are connected by interconnection links, each core particle is connected to at least two interconnection links, and each interconnection link of the at least two interconnection links is connected to a different core particle. Figure 7 The schematic diagram shown illustrates the data transmission method.

[0076] S1: When data is transmitted to a destination through a transmission path where a first interconnection link among at least two interconnection links is located and an abnormality occurs in the first interconnection link, a second interconnection link among the at least two interconnection links is automatically selected.

[0077] In a possible implementation, an adaptive routing control module is provided in each chiplet, and the implementation process of the above S1 may be: the adaptive routing control module obtains a cross-chiplet backup routing table preset in the chiplet; and the adaptive routing control module automatically selects a second interconnection link among the at least two interconnection links according to the cross-chiplet backup routing table.

[0078] By adding an adaptive routing control module and a cross-chip backup routing table in the chiplet, when an abnormality occurs in a first interconnection link of at least two interconnection links connected to the chiplet, the adaptive routing control module can obtain a cross-chip backup routing table preset in the chiplet, wherein the cross-chip backup routing table is used to determine a transmission path including a second interconnection link that bypasses the abnormal interconnection link.

[0079] S2: Use the second interconnection link to replace the first interconnection link for data transmission.

[0080] After obtaining the normal second interconnection link, the adaptive routing control module in the chiplet can use the second interconnection link to replace the first interconnection link for data transmission, so as to bypass the abnormal interconnection link and ensure that the chip can still operate normally in the case of partial link failure. There is a transmission path between the second interconnection link and the destination.

[0081] In a possible implementation manner, the data transmission method may further include: the adaptive routing control module monitors the state of the interconnection link, and when detecting that the first interconnection link is abnormal, records the abnormal first interconnection link in an abnormal link table, so that the abnormal interconnection link can be learned by accessing the abnormal link table.

[0082] The data transmission method between chip core particles provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned chip embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference can be made to the corresponding contents in the aforementioned chip embodiment.

[0083] The present application also provides an electronic device, which may include the above-mentioned chip. In a possible implementation manner, Figure 8 As shown, the electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230 and a processor 240. The above chip may be Figure 8 Processor 240 is shown.

[0084] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, wherein the computer program includes at least one software function module that can be stored in the memory 220 in the form of software or firmware (Firmware) or solidified in the operating system (Operating System, OS) of the electronic device 200. The processor 240 is used to execute the software function module or computer program stored in the memory 220. For example, the processor 240 is used to execute the above-mentioned data transmission method between chip core particles.

[0085] Among them, the memory 220 can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0086] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processor (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0087] The electronic device 200 mentioned above includes but is not limited to a tablet computer, a notebook, a server, etc.

[0088] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.

[0089] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: include: A plurality of core particles and interconnection links, wherein the plurality of core particles are connected via the interconnection links, each of the core particles is connected to at least two interconnection links, and each of the at least two interconnection links is connected to a different core particle; Each of the core particles is used to transmit data to a destination through a transmission path where a first interconnection link among the at least two interconnection links is located, and when the first interconnection link is abnormal, automatically select a second interconnection link among the at least two interconnection links, and use the second interconnection link to replace the first interconnection link for data transmission, wherein the second interconnection link is a normal link, and there is a transmission path between the second interconnection link and the destination.

2. The chip according to claim 1, characterized in that: An adaptive routing control module is provided in each of the core particles, and the adaptive routing control module is used to obtain a cross-core backup routing table in a preset routing table when a first interconnection link among the at least two interconnection links is abnormal, and automatically select a transmission path where a second interconnection link among the at least two interconnection links is located according to the cross-core backup routing table for data transmission, wherein the cross-core backup routing table is used to determine a transmission path including the second interconnection link that bypasses the abnormal interconnection link.

3. The chip according to claim 2, characterized in that: The adaptive routing control module includes: A routing table lookup unit, used for looking up a routing table built into the core particle, wherein the routing table includes the cross-core particle backup routing table; A path switching control unit is connected to the routing table lookup unit; the path switching control unit is used to search the cross-chip backup routing table through the routing table lookup unit when the first interconnection link is abnormal, and automatically select the transmission path where the second interconnection link is located for data transmission according to the found cross-chip backup routing table.

4. The chip according to claim 3, characterized in that: The adaptive routing control module further includes: a link status monitoring unit connected to the path switching control unit; The link status monitoring unit is used to monitor the status of the interconnection link, and when the first interconnection link is detected to be abnormal, record the abnormal first interconnection link in the abnormal link table; The path switching control unit is further used to access the abnormal link table to obtain abnormal interconnected links.

5. The chip according to claim 2, characterized in that: The preset routing table also includes a cross-chip master routing table, and the cross-chip master routing table is used to determine the best transmission path for data transmission when the interconnection link is normal.

6. The chip according to claim 5, characterized in that: The plurality of core particles include M*N core particles, where M and N are both integers greater than or equal to 2; the at least two interconnection links include a horizontal interconnection link and a vertical interconnection link; The cross-chip main routing table follows the configuration rule of first configuring the vertical interconnection link and then the horizontal interconnection link or first configuring the horizontal interconnection link and then the vertical interconnection link; the cross-chip backup routing table follows the configuration rule of mutual backup of the horizontal interconnection link and the vertical interconnection link.

7. The chip according to claim 2, characterized in that: The core particle also includes: A cache queue, used to temporarily cache data transmitted externally by the core particle; The adaptive routing control module is further configured to utilize the second interconnection link to transmit data transmitted externally by the core particle in the cache queue.

8. The chip according to claim 2, characterized in that: The core particle further comprises: a master module, a slave module, a routing node and at least two interconnect modules, wherein the at least two interconnect modules, the master module and the slave module are all connected to the routing node; Each of the interconnection modules, the master module, and the slave module in the core particle is provided with the adaptive routing control module; The adaptive routing control module in the interconnection module is further configured to report abnormal link information to the adaptive routing control modules in other modules in the core particle when detecting that the first interconnection link is abnormal.

9. The chip according to any one of claims 1 to 8, characterized in that: The chip is a server chip.

10. An electronic device, characterized in that: include: A chip as claimed in any one of claims 1 to 9.

11. A data transmission method between chip cores, characterized in that: The chip comprises a plurality of core particles and interconnection links, the plurality of core particles are connected via the interconnection links, each core particle is connected to at least two interconnection links, and each interconnection link of the at least two interconnection links is connected to a different core particle; the method comprises: The core particle transmits data to the destination through the transmission path where the first interconnection link of the at least two interconnection links is located, and when the first interconnection link is abnormal, automatically selects the second interconnection link of the at least two interconnection links; The core particle uses the second interconnection link to replace the first interconnection link for data transmission; wherein the second interconnection link is a normal link, and there is a transmission path between the second interconnection link and the destination.

12. The method according to claim 11, characterized in that Each core particle is provided with an adaptive routing control module, which automatically selects the second interconnection link of the at least two interconnection links, including: The adaptive routing control module acquires a cross-chip backup routing table preset in the chiplet, wherein the cross-chip backup routing table is used to determine a transmission path including a second interconnection link that bypasses the abnormal interconnection link; The adaptive routing control module automatically selects a second interconnection link among the at least two interconnection links according to the cross-chip backup routing table.

13. The method according to claim 12, characterized in that The method further comprises: The adaptive routing control module monitors the state of the interconnection link, and when detecting that the first interconnection link is abnormal, records the abnormal first interconnection link in an abnormal link table.

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